Wide bandgap semiconductor device structure and manufacturing method thereof

Abstract

The invention provides a wide bandgap semiconductor device structure and a manufacturing method thereof. In the device structure, a first P-type semiconductor layer and a first N-type epitaxial layer form a first heterogeneous PN junction; the second N-type epitaxial layer and the first P-type semiconductor layer form a second heterogeneous PN junction; the bottom of the multi-stage groove is located in the first N-type epitaxial layer, a third P-type semiconductor layer is sputtered on the bottom and the inner wall of the multi-stage groove, the groove is filled with a transparent medium, and a current gain window is constructed and formed; under the illumination effect, light is irradiated to the first N-type epitaxial layer through the current gain window, photons are absorbed, electron hole pairs are generated, the device conduction effect is triggered, and the device structure has the characteristics of high reverse breakdown voltage and low conduction resistance; the second N-type epitaxial layer is provided with a groove, and the grid electrode is arranged in the groove. The structure solves the problem that a wide bandgap semiconductor cannot form high reverse breakdown voltage and bipolar conduction due to lack of P-type doping or N-type doping, so that the working performance of the device is better.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a wide bandgap semiconductor device structure and a manufacturing method thereof. Background Art

[0002] In power switching applications, Baliga's Figure of Merit (BFOM) is widely used to measure the suitability of semiconductor materials for power electronics. This metric is calculated as: BFOM = εμE³, where ε represents the dielectric constant, μ is the mobility, and E is the breakdown field strength of the semiconductor. Research has shown that the BFOM value is roughly positively correlated with the sixth power of the semiconductor material's bandgap (Eg). Therefore, a larger bandgap means lower power loss and higher conversion efficiency, leading to better performance in power electronics applications.

[0003] In wide bandgap semiconductor materials, contrary to the ease of n-type doping, there is currently no The successful realization of p-type doping in Compared with materials that can be bipolar doped, their application in bipolar power devices is limited. There are three factors that make the p-type hole-conducting Almost impossible: First, it is difficult to find acceptor impurities with small activation energy; Secondly, theoretical calculations The dispersion of the valence band maximum is small and the effective mass is very large, which causes the free holes to be almost localized to small μ; Finally, in theory, It is predicted that due to local lattice distortion, the local self-trapping energy of free holes in the bulk is very large, which leads to the formation of small poles, which undoubtedly prohibits the conduction of effective holes.

[0004] Taking gallium oxide as an example, there is no research on coupling the switch unit of wide bandgap semiconductor material with the light control unit. The existing example is silicon-based light control device, which has two technical problems: first, silicon material is the voltage-resistant unit of the entire device. The currently developed silicon-based high-voltage devices such as IGBT (insulated gate bipolar transistor), VDMOS (vertical double diffused metal oxide semiconductor) and GTO (thyristor) have almost reached the physical limit of silicon-based materials, and it is very difficult to further improve their voltage resistance. For gallium oxide materials, its critical breakdown electric field (8 MV / cm) is 26 times that of silicon material (0.3MV / cm), which can naturally solve the problem of high-voltage resistance. Secondly, the light control units of silicon-based light-control devices all work near the surface of the electrode metal material. Since silicon material itself is not transparent, when the light control unit starts working, the depth of light entering from the surface of the silicon-based device is very thin and cannot reach the position of the silicon-based device's voltage-resistant layer. At this time, the electron-hole pairs generated by the light are instantly recombined by the existing majority carriers in the neutral zone near the surface, and no positive feedback of the electron-hole pairs is generated, so it has little effect on the current gain.

[0005] Based on this, the present invention provides a new wide bandgap semiconductor device structure and a manufacturing method thereof. Summary of the Invention

[0006] Based on the above description, the present invention provides a wide bandgap semiconductor device structure and a manufacturing method thereof, aiming to solve the technical problems that the voltage resistance of silicon-based devices is not as good as that of wide bandgap semiconductors with the same parameters, which is not conducive to their use in ultra-high voltage circuits, and that silicon is an opaque material, the transmission path of photons in silicon is very short, the generated electron-hole pairs will basically be recombined on the surface, and the current gain is relatively small.

[0007] The technical solution of the present invention to solve the above technical problems is as follows: In a first aspect, the present invention provides a wide bandgap semiconductor device structure, comprising: a substrate layer, a first N-type epitaxial layer, a first P-type semiconductor layer, a second P-type semiconductor layer, a second N-type epitaxial layer, a third P-type semiconductor layer, a cathode, an anode, and a gate; The first N-type epitaxial layer is epitaxially grown on the substrate layer; The first P-type semiconductor layer is sputtered on the upper surface of the first N-type epitaxial layer to form a first heterojunction; The second P-type semiconductor layer is sputtered on the lower surface of the substrate layer; The second N-type epitaxial layer is epitaxially grown or bonded on the first P-type semiconductor layer to form a second heterojunction; A multi-level groove is also provided, the bottom of the multi-level groove is located in the first N-type epitaxial layer, the bottom and inner wall of the multi-level groove are sputtered with the third P-type semiconductor layer, and the groove is filled with a transparent medium to form a current gain window; under the action of light, when light is irradiated to the first N-type epitaxial layer through the current gain window, photons are absorbed, generating electron-hole pairs, triggering the device to turn on; the device structure has the characteristics of high reverse breakdown voltage and low on-resistance.

[0008] The second N-type epitaxial layer is provided with a groove, and the gate is provided on the first P-type semiconductor layer located at the groove; The cathode is arranged on the second N-type epitaxial layer; the anode is arranged at the bottom of the second P-type semiconductor layer.

[0009] On the basis of the above technical solution, the present invention can also be improved as follows.

[0010] Furthermore, the multi-level trenches are formed by etching from the top of the second N-type epitaxial layer through the first P-type semiconductor layer to the first N-type epitaxial layer; Alternatively, the multi-level trench is formed by etching from the bottom of the anode through the second P-type semiconductor layer and the substrate layer to the first N-type epitaxial layer.

[0011] Furthermore, the substrate layer is N + Ga2O3 layer; And / or, the first N-type epitaxial layer and the second N-type epitaxial layer are one or more combinations of N-type doped Ga2O3, AlN, BN, SiC, GaN and diamond; And / or, the first P-type semiconductor layer and the second P-type semiconductor layer are one of P-type doped NiO, Cu2O, GaN, SiC, Si and diamond.

[0012] Furthermore, the P-type doping concentration of the second P-type semiconductor layer is 1e18~1e19cm -3 ; And / or, the P-type doping concentration of the first P-type semiconductor layer is 1e17~1e18cm -3 .

[0013] Furthermore, the doping concentration of the first N-type epitaxial layer is 5e15~1e16cm -3 ; And / or, the doping concentration of the second N-type epitaxial layer is 1e17~1e18cm -3 .

[0014] Furthermore, the P-type doping concentration of the third P-type semiconductor layer is 1e18~1e19cm -3; And / or, the third P-type semiconductor layer is one of CuI, Cu2O, V2O3 and β-TeO2.

[0015] Furthermore, the cross-sectional shape of the current gain window is a bar, a square, a circle or a hexagon.

[0016] Furthermore, the wide bandgap semiconductor device structure further includes a silicon oxide dielectric layer; The silicon oxide dielectric layer is deposited on the upper surfaces of the cathode, the gate and the second N-type epitaxial layer.

[0017] In a second aspect, the present invention further provides a method for manufacturing the wide bandgap semiconductor device structure as described in the first aspect, comprising the following steps: S1: epitaxially growing a first N-type epitaxial layer on a substrate layer, and sputtering a P-type semiconductor on a surface of the first N-type epitaxial layer and a bottom of the substrate layer, respectively, to form the first P-type semiconductor layer and the second P-type semiconductor layer; S2: etching the structure obtained in step S1 to form multi-level trenches in the structure, with the etching depth reaching the first N-type epitaxial layer; S3: sputtering a third P-type semiconductor layer on the sidewalls and bottom of the multi-level trench, and filling the trench with a transparent medium; S4: etching the second N-type semiconductor layer until the underlying first P-type semiconductor layer is exposed; S5: depositing metals on the surfaces of the first P-type semiconductor layer, the second N-type semiconductor layer, and the second P-type semiconductor layer, and patterning them to obtain a gate, a cathode, and an anode; S6: depositing a layer of dielectric on the surface and patterning it to expose the contact holes and multi-level groove holes of the electrode;

[0018] Compared with the prior art, the technical solution of this application has the following beneficial technical effects: The wide bandgap semiconductor device structure and the manufacturing method thereof provided by the present invention have the following beneficial effects compared with the prior art: First, the wide bandgap semiconductor device proposed in this invention utilizes a double heterojunction (PN) formed by an N-type epitaxial wafer and two layers of P-type semiconductor, combined with a multi-stage trench current-enhancing window. When the device operates in the forward-blocking state, the heterojunction formed by the P-type semiconductor and the N-type epitaxial layer is reverse-biased. Because the epitaxial layer has a low doping concentration and is thicker, this region exhibits a large depletion region in the forward-blocking state. When light passes through the multi-stage trench window and strikes the first N-type epitaxial layer, photons are absorbed by the epitaxial layer, generating electron-hole pairs. The photon-generated electrons and holes are rapidly separated by the high reverse electric field, accelerating under the electric field and acquiring significant kinetic energy. When carriers collide with atoms, there is a chance that new electron-hole pairs will be generated, thus entering a forward-blocking cycle and repeating the accelerated motion of the electron-hole pairs. This allows the first N-type epitaxial layer to carry a large current. The first N-type epitaxial layer serves as the base region of the PNP bipolar junction transistor and also as the collector region of the NPN bipolar junction transistor. The large current flow in this region drives the first P-type semiconductor of the NPN bipolar junction transistor to form a heterojunction with the second N-type epitaxial layer, and the PNP bipolar junction transistor. The second P-type semiconductor and the substrate layer form a heterojunction, which in turn increases the on-current of the entire device. When the device on-current exceeds the device's original holding current, the device can spontaneously maintain conduction without external illumination, thus triggering the device to turn on. Compared to traditional gate current-triggered device turn-on, photon illumination-triggered turn-on has lower delay time, power loss, and safety.

[0019] Second, when the wide bandgap semiconductor device proposed by the present invention is turned on, continued illumination increases the carrier concentration in the first N-type epitaxial layer, thereby further reducing the on-resistance and conduction loss. When the device transitions from the on state to the forward blocking state, it is only necessary to remove the illumination while applying a reverse current to the gate. When the on-current in the first P-type semiconductor is lower than the level required to maintain the spontaneous conduction of the device, the device will quickly turn off. By utilizing the different time points of photon on and current off, a pulsed operating circuit can be constructed to control the on and off of the device, thereby allowing the device to operate in a safe zone.

[0020] Third, the multi-level trenches used in the wide-bandgap semiconductor device proposed by the present invention provide better coverage of the transparent P-type semiconductor on the sidewalls and bottom of the multi-level trenches compared to single-level trenches. This covered transparent P-type semiconductor blocks the reverse electric field, preventing the electric field from leaking into the air through the multi-level trenches when the device is in the off state, causing air breakdown, sparking, and premature device breakdown.

[0021] In summary, the present invention utilizes a heterogeneous PN junction combined with multi-level trenches to construct a wide-bandgap ultra-high-voltage, high-current device. The multi-level trenches serve as the device's operating state trigger and current gain window, and the heterogeneous PN junction formed by different wide-bandgap semiconductors solves the problem of wide-bandgap semiconductors being unable to achieve high reverse breakdown voltage and bipolar conductivity due to a lack of P-type or N-type doping. The multi-level trenches serve as the device's operating state trigger and current gain window, and transparent P-type semiconductor material is deposited on the trench sidewalls and bottom as a protective layer or gain layer, resulting in improved device performance. Furthermore, the entire device fabrication process is simple and highly feasible. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic structural diagram of a wide bandgap semiconductor device structure provided in Example 1 of the present invention; Figure 2 A schematic diagram of the cross-sectional shape of a current gain window of a wide bandgap semiconductor device structure provided by an embodiment of the present invention; Figure 3 A schematic structural diagram of a wide bandgap semiconductor device structure provided in Example 2 of the present invention; Figure 4 A schematic structural diagram of a wide bandgap semiconductor device structure provided in Example 3 of the present invention; Figures 5 to 10 A schematic diagram of a method for manufacturing a wide bandgap semiconductor device structure corresponding to embodiment 1 provided in embodiment 4 of the present invention; In the accompanying drawings, the components represented by the reference numerals are as follows: 1. Substrate layer; 2. First N-type epitaxial layer; 3. First P-type semiconductor layer; 4. Second P-type semiconductor layer; 5. Second N-type epitaxial layer; 6. Third P-type semiconductor layer; 7. Transparent medium; 8. Cathode; 9. Anode; 10. Gate; 11. Silicon oxide dielectric layer. DETAILED DESCRIPTION

[0023] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0024] The embodiments of the present invention are described in further detail below with reference to the accompanying drawings and examples. The following examples are used to illustrate the present invention but are not intended to limit the scope of the present invention.

[0025] Example 1 like Figure 1As shown, the wide bandgap semiconductor device structure provided in this embodiment integrates the voltage-resistant unit and the light-controlled unit designed with gallium oxide material to form a gallium oxide-based light-controlled high-voltage and high-current power device, which is expected to realize the marketization of gallium oxide material applications. It specifically includes: a substrate layer 1, a first N-type epitaxial layer 2, a first P-type semiconductor layer 3, a second P-type semiconductor layer 4, a second N-type epitaxial layer 5, a transparent medium 7, a third P-type semiconductor layer 6, a cathode 8, an anode 9 and a gate 10.

[0026] The first N-type epitaxial layer 2 is epitaxially grown on the substrate layer 1 .

[0027] The first P-type semiconductor layer 3 is sputtered on the upper surface of the first N-type epitaxial layer 2 to form a first heterojunction.

[0028] The second P-type semiconductor layer 4 is sputtered on the lower surface of the substrate layer 1 .

[0029] The second N-type epitaxial layer 5 is epitaxially grown or bonded on the first P-type semiconductor layer 3 to form a second heterojunction.

[0030] The wide bandgap semiconductor device structure is also provided with a multi-level trench, the bottom of the multi-level trench is located in the first N-type epitaxial layer 2, the bottom and inner wall of the multi-level trench are sputtered with a third P-type semiconductor layer 6, and the trench is filled with a transparent medium 7 to form a current gain window; under the action of light, when light is irradiated through the current gain window to the first N-type epitaxial layer 2, photons are absorbed, generating electron-hole pairs, triggering the device to turn on, forming a low on-resistance. At the same time, because the device is made of a wide bandgap semiconductor material and has a low doping concentration, it forms a high reverse breakdown voltage.

[0031] The second N-type epitaxial layer 5 is provided with a groove, and the gate 10 is provided on the first P-type semiconductor layer 3 located in the groove.

[0032] The cathode 8 is disposed on the second N-type epitaxial layer 5 ; the anode 9 is disposed at the bottom of the second P-type semiconductor layer 4 .

[0033] In this embodiment, Figure 1 As shown, multi-level trenches are formed by etching from the top of the second N-type epitaxial layer 5 through the first P-type semiconductor layer 3 to the first N-type epitaxial layer 2 .

[0034] In this embodiment, the substrate layer 1 is N + Ga2O3 layer.

[0035] In an optional embodiment, the first N-type epitaxial layer 2 and the second N-type epitaxial layer 5 are one or more combinations of N-type doped Ga2O3, AlN, BN, SiC, GaN and diamond.

[0036] In this embodiment, the first N-type epitaxial layer 2 and the second N-type epitaxial layer 5 are both N-type doped Ga2O3; wherein the doping concentration of the first N-type epitaxial layer 2 is 5e15~1e16cm -3 The doping concentration of the second N-type epitaxial layer 5 is 1e17~1e18cm -3 .

[0037] In an optional embodiment, the first P-type semiconductor layer 3 and the second P-type semiconductor layer 4 are one of P-type doped NiO, Cu 2 O, GaN, SiC, Si and diamond.

[0038] In this embodiment, the first P-type semiconductor layer 3 and the second P-type semiconductor layer 4 are P-type doped NiO; wherein the P-type doping concentration of the second P-type semiconductor layer 4 is 1e18-1e19 cm -3 The P-type doping concentration of the first P-type semiconductor layer 3 is 1e17~1e18cm -3 .

[0039] The P-type doping concentration of the third P-type semiconductor layer 6 is 1e18-1e19 cm -3 In an optional embodiment, the third P-type semiconductor layer 6 is one of CuI, Cu2O, V2O3 and β-TeO2.

[0040] In this embodiment, the third P-type semiconductor layer 6 is a Cu2O layer with a doping concentration of 1e18-1e19 cm -3 .

[0041] In addition, if Figure 1 As shown, the multi-level trenches, the third P-type semiconductor layer 6 and the transparent medium 7 form a current gain window, and the cross-sectional shape of the current gain window is a strip, square, circle or hexagon (such as Figure 2 shown).

[0042] Furthermore, in an optional example, Figure 1 As shown, the wide bandgap semiconductor device structure further includes a silicon oxide dielectric layer 11 ; the silicon oxide dielectric layer 11 is deposited on the upper surfaces of the cathode 8 , the gate 10 and the second N-type epitaxial layer 5 .

[0043] It should be noted that the peripheral circuit for generating light and the highly doped transparent P-type semiconductor dielectric layer constitute a light control unit, and the substrate layer 1 and the first N-type epitaxial layer 2 constitute a voltage-resistant unit.

[0044] Due to the advantages of gallium oxide materials, such as its wide bandgap and high critical breakdown electric field, power devices manufactured using gallium oxide exhibit excellent performance, including high blocking voltage, high operating temperature, and low leakage current. Using a light control unit to control the operating state of gallium oxide high-voltage devices offers lower switching losses, higher device response speed, and greater safety compared to traditional electrical switches. Controlling the operating state transitions and reducing device on-resistance by controlling light intensity and pulse duration offers lower latency, power loss, and greater safety than traditional electrical switches. The heterojunction formed by combining different wide-bandgap semiconductors with gallium oxide combines the advantages of these different wide-bandgap semiconductors. This allows the excellent high-voltage and high-current resistance of gallium oxide materials to be fully utilized, even if p-type gallium oxide doping is unsuccessful, potentially opening up new opportunities for the commercialization of gallium oxide power devices.

[0045] At present, taking gallium oxide materials as an example, there are two technical problems with existing silicon-based light-control devices. The first is that silicon material is the voltage-resistant unit of the entire device. The currently developed silicon-based high-voltage devices have almost reached the physical limit of silicon-based materials, and it is very difficult to further improve their voltage resistance. For gallium oxide materials, its critical breakdown electric field (8MV / cm) is 26 times that of silicon materials (0.3MV / cm), which can naturally solve the problem of high-voltage resistance. Secondly, since the light control units of silicon-based light-control devices all work near the surface of the electrode metal material, and the silicon material itself is not transparent, when the light control unit starts working, the depth of light entering from the surface of the silicon-based device is very thin and cannot reach the position of the silicon-based device's voltage-resistant layer. At this time, the electron-hole pairs generated by the light are instantly recombined by the existing majority carriers in the neutral zone near the surface, and no positive feedback of the electron-hole pairs will be generated, so it has little effect on the current gain.

[0046] The embodiment of the present invention uses gallium oxide material to design a voltage-resistant unit and integrates it with a light control unit through technical means such as structural optimization, which effectively solves the problems of low voltage resistance of silicon-based devices and short transmission distance of photons in semiconductor materials. The additional light control unit can easily control the transition of the device's working state. When the device changes from a forward blocking state to an open state, it only needs photon irradiation to complete it, replacing the traditional electric switch to introduce current, and achieving faster, safer and low-loss control of high-voltage devices. At the same time, controlling the photon pulse time can make the device also work in a pulsed form, so that the device can work in a high voltage and pulsed high current environment, that is, it can perfectly solve the difficulties of voltage resistance and surface recombination encountered by the above-mentioned silicon-based light control devices, thereby further promoting the marketization of gallium oxide power device applications and providing potential possibilities.

[0047] Example 2 Based on the above embodiment, the difference of this embodiment is that the multi-level trench is etched from the bottom of the anode through the second P-type semiconductor layer and the substrate layer to the first N-type epitaxial layer, such as Figure 3 As shown, the opening direction of the multi-level trench can also be from the bottom anode to the first N-type epitaxial layer. The advantage of doing so is that the transparent P-type semiconductor on the sidewall of the trench is electrically connected to the anode, which can have a larger emitter area and a larger conduction current when forward conductive. Secondly, after etching the gallium oxide epitaxial layer on the back, the base region length becomes shorter, and the common base amplification factor of the PNP transistor becomes larger, making the device easier to turn on.

[0048] This embodiment also has the beneficial effects brought by embodiment 1, so the beneficial effects of the structure provided by this embodiment will not be described in detail here.

[0049] Example 3 Based on the above embodiment, the difference of this embodiment is that: Figure 4 As shown, the first N-type epitaxial layer and the second N-type epitaxial layer are both N-type doped Ga2O3, and the first P-type semiconductor layer and the second P-type semiconductor layer are P-type doped GaN; correspondingly, a vacuum bonding process can be used to bond the voltage-resistant layer to construct a heterogeneous PN junction structure.

[0050] This embodiment also has the beneficial effects brought by embodiment 1, so the beneficial effects of the structure provided by this embodiment will not be described in detail here.

[0051] Example 4 In order to facilitate understanding of the wide bandgap semiconductor device structure provided in Example 1, Figures 5 to 10 As shown, this embodiment provides a corresponding manufacturing method thereof: Step S1 ( Figure 5 As shown): a first N-type epitaxial layer is epitaxially grown on the substrate layer, and a P-type semiconductor is sputtered on the surface of the first N-type epitaxial layer and the bottom of the substrate layer, respectively, to form a first P-type semiconductor layer and a second P-type semiconductor layer.

[0052] Specifically, a gallium oxide epitaxial layer with a thickness of about 20~100um is grown on an N+ Ga2O3 substrate, and the substrate concentration is 1e18~1e19cm -3 , thickness is 150~650μm, epitaxial layer doping concentration is 5e15~1e16cm -3 Subsequently, the front and back sides of the gallium oxide epitaxial layer are sputtered with P-type NiO, Cu2O and other semiconductors with a thickness of 100~300nm. The side close to the gallium oxide substrate is the back side, and the side close to the epitaxial layer is the front side. The P-type doping concentration on the back side is 1e18~1e19cm -3 The P-type doping concentration on the front side is 1e17~1e18cm-3 Then, a gallium oxide epitaxial layer with a thickness of 100~300nm is grown or bonded on the front P-type semiconductor, and the doping concentration of the epitaxial layer is 1e18~1e19cm -3 .

[0053] Step S2 ( Figure 6 As shown): The structure obtained by etching step S1 forms multi-level trenches in the structure, and the etching depth reaches the first N-type epitaxial layer.

[0054] The number of the multi-stage grooves is greater than or equal to 2.

[0055] Step S3 ( Figure 7 As shown): A third P-type semiconductor layer is sputtered on the sidewalls and bottom of the multi-level trench, and a transparent medium is filled in the trench.

[0056] Specifically, a layer of P-type semiconductor with a thickness of about 100-300 nm is sputtered on the sidewalls and bottom of the etched trench. The doping concentration of the semiconductor is between 1e18 and 1e19 cm -3 The P-type semiconductor that meets this condition can be CuI, Cu2O, V2O3, β-TeO2; and the transparent medium is filled in the groove after sputtering.

[0057] Step S4 ( Figure 8 As shown): the second N-type semiconductor layer is etched until the underlying first P-type semiconductor layer is exposed.

[0058] Specifically, a layer of Ti metal with a thickness of 10-100 nm is deposited on the surface of the structure as an ohmic contact electrode and a gate electrode, and annealed in a N2 atmosphere at 470°C.

[0059] Step S5 ( Figure 9 As shown): Metals are deposited on the surfaces of the first P-type semiconductor layer, the second N-type semiconductor layer and the second P-type semiconductor layer, and patterned to obtain a gate, a cathode and an anode.

[0060] Specifically, a layer of insulating medium with a thickness of 100-1000 nm is grown on the surface of the structure as an interlayer dielectric between the gate electrode and the transmitter electrode, and a hole is opened at the previous ohmic contact electrode position to expose the electrode.

[0061] The interlayer dielectric layer may be Al2O3, SiO2, Si3N4 or a stacked dielectric thereof.

[0062] Step S6 ( Figure 10 As shown): A layer of dielectric is deposited on the surface and patterned to expose the contact holes and multi-level trench holes of the electrode.

[0063] The beneficial effects of this manufacturing method embodiment are the same as those of the wide bandgap semiconductor device structure provided in Example 1, and will not be described in detail here.

[0064] Throughout this specification, reference to terms such as "specific examples" or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and integrate different embodiments or examples, and features of different embodiments or examples, described in this specification, unless otherwise mutually incompatible.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A wide bandgap semiconductor device structure, characterized in that: include: A substrate layer, a first N-type epitaxial layer, a first P-type semiconductor layer, a second P-type semiconductor layer, a second N-type epitaxial layer, a third P-type semiconductor layer, a cathode, an anode, and a gate; The first N-type epitaxial layer is epitaxially grown on the substrate layer; The first P-type semiconductor layer is sputtered on the upper surface of the first N-type epitaxial layer to form a first heterojunction; The second P-type semiconductor layer is sputtered on the lower surface of the substrate layer; The second N-type epitaxial layer is epitaxially grown or bonded on the first P-type semiconductor layer to form a second heterojunction; A multi-level trench is also provided, the bottom of the multi-level trench is located in the first N-type epitaxial layer, the bottom and inner wall of the multi-level trench are sputtered with the third P-type semiconductor layer, and the trench is filled with a transparent medium to form a current gain window. Under the action of light, when light is irradiated through the current gain window to the first N-type epitaxial layer, photons are absorbed, generating electron-hole pairs, triggering the device to turn on; the device structure has the characteristics of high reverse breakdown voltage and low on-resistance; The second N-type epitaxial layer is provided with a groove, and the gate is provided on the first P-type semiconductor layer located at the groove; The cathode is arranged on the second N-type epitaxial layer; the anode is arranged at the bottom of the second P-type semiconductor layer.

2. The wide bandgap semiconductor device structure according to claim 1, characterized in that: The multi-level trenches are formed by etching from the top of the second N-type epitaxial layer through the first P-type semiconductor layer to the first N-type epitaxial layer; Alternatively, the multi-level trench is formed by etching from the bottom of the anode through the second P-type semiconductor layer and the substrate layer to the first N-type epitaxial layer.

3. The wide bandgap semiconductor device structure according to claim 1, characterized in that: The substrate layer is N + Ga2O3 layer; And / or, the first N-type epitaxial layer and the second N-type epitaxial layer are one or more combinations of N-type doped Ga2O3, AlN, BN, SiC, GaN and diamond; And / or, the first P-type semiconductor layer and the second P-type semiconductor layer are one of P-type doped NiO, Cu2O, GaN, SiC, Si and diamond.

4. The wide bandgap semiconductor device structure according to claim 3, characterized in that: The P-type doping concentration of the second P-type semiconductor layer is 1e18~1e19cm -3 ; And / or, the P-type doping concentration of the first P-type semiconductor layer is 1e17~1e18cm -3 .

5. The wide bandgap semiconductor device structure according to claim 3, characterized in that: The doping concentration of the first N-type epitaxial layer is 5e15~1e16cm -3 ; And / or, the doping concentration of the second N-type epitaxial layer is 1e17~1e18cm -3 .

6. The wide bandgap semiconductor device structure according to claim 1, characterized in that: The P-type doping concentration of the third P-type semiconductor layer is 1e18-1e19 cm -3 ; And / or, the third P-type semiconductor layer is one of CuI, Cu2O, V2O3 and β-TeO2.

7. The wide bandgap semiconductor device structure according to claim 1, characterized in that: The cross-sectional shape of the current gain window is a bar, square, circle or hexagon.

8. The wide bandgap semiconductor device structure according to claim 1, characterized in that: The wide bandgap semiconductor device structure further includes a silicon oxide dielectric layer; The silicon oxide dielectric layer is deposited on the upper surfaces of the cathode, the gate and the second N-type epitaxial layer.

9. A method for manufacturing a wide bandgap semiconductor device structure according to any one of claims 1 to 8, characterized in that: The following steps are involved: S1: epitaxially growing a first N-type epitaxial layer on a substrate layer, and sputtering a P-type semiconductor on a surface of the first N-type epitaxial layer and a bottom of the substrate layer, respectively, to form the first P-type semiconductor layer and the second P-type semiconductor layer; S2: etching the structure obtained in step S1 to form multi-level trenches in the structure, with the etching depth reaching the first N-type epitaxial layer; S3: sputtering a third P-type semiconductor layer on the sidewalls and bottom of the multi-level trench, and filling the trench with a transparent medium; S4: etching the second N-type semiconductor layer until the first P-type semiconductor layer underneath is exposed; S5: depositing metals on the surfaces of the first P-type semiconductor layer, the second N-type semiconductor layer, and the second P-type semiconductor layer, and patterning them to obtain a gate, a cathode, and an anode; S6: depositing a layer of dielectric on the surface and patterning it to expose the contact holes and multi-level groove holes of the electrode.

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