Crystal growth method, wafer manufacturing method and crystal growth control device
By increasing the equal-diameter growth pulling speed and removing the P-band area during the growth of single-crystal silicon crystals, combined with water-cooled screen cooling, the problem of poor BMD uniformity was solved, and the quality and yield of the wafers were improved.
Patent Information
- Application Number
- CN202510858615.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-25
- Publication Date
- 2025-09-16
AI Technical Summary
In the prior art, the BMD uniformity is poor during the growth of single-crystal silicon crystals, resulting in uneven BMD at the wafer edge, which affects the device yield and mechanical properties.
The Czochralski method is used to grow single-crystal silicon ingots. By increasing the crystal pulling speed during the equal-diameter growth stage, the entire ingot is located in the V-rich region, and the P-band region is removed at the radial edge. Combined with a water-cooling screen, the crystal cooling efficiency is improved to ensure BMD uniformity.
It improves the uniformity of BMD at the wafer edge, enhances the wafer's impurity absorption capability and stress distribution uniformity, and improves the yield of high-end process products.
Smart Images
Figure CN120649138A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor product manufacturing, and in particular to a crystal growth method, a wafer manufacturing method and a crystal growth control device. Background Art
[0002] Electronic-grade single-crystal silicon is a semiconductor material generally used in the manufacture of integrated circuits and other electronic components. The most common method for growing single-crystal silicon is the Czochralski method, also known as the Czochralski method. In a single crystal furnace, a seed crystal is immersed in molten silicon in a crucible. The seed crystal and the crucible are rotated while the seed crystal is pulled. The seed crystal is then seeded, shouldered, rotated, and then calibrated and finished at the end of the seed crystal to obtain a single-crystal silicon crystal. The calibrated stage is an extremely important process in the growth of single-crystal silicon crystals and is also a key process in ensuring the quality of single-crystal silicon crystals.
[0003] When manufacturing silicon single crystals using the CZ method, the main reason for the low yield of the crystal rod is that the BMD (Bulk Microdefect Density) concentration is unqualified, and uniform BMD cannot be generated well. BMD has a significant impact on the properties of single crystal silicon wafers and the yield of device wafers. In the existing technology, LTA (Low Temperature Annealing) treatment is required to nucleate BMD and thus increase the BMD density. In this process, a cleaning machine is first required to pre-clean it before the LTA treatment, and then the LTA treatment is performed. This undoubtedly adds two more steps, which is not only time-consuming but also increases costs.
[0004] Appropriately sized oxygen precipitates improve the mechanical properties of silicon wafers, thereby suppressing warpage during high-temperature processing. Furthermore, oxygen precipitates and the defects they induce within the silicon wafer body can serve as gettering sites, effectively absorbing metal contaminants from the wafer surface. This is known as internal gettering. Controlling and utilizing oxygen precipitates in device fabrication processes is a core issue in silicon wafer defect engineering. Typically, a clean zone free of crystal defects and metal impurities is created near the surface of the silicon wafer. To achieve this clean zone, BMDs (Bonding Moisture Detectors) must be formed within the crystal body for gettering. However, prior art techniques suffer from poor BMD uniformity within the ingot, reducing yield. Summary of the Invention
[0005] In order to solve the above technical problems, the present invention provides a crystal growth method, a wafer manufacturing method and a crystal growth control device to solve the problem of low BMD uniformity.
[0006] To achieve the above-mentioned object, the technical solution adopted in the embodiment of the present invention is: a crystal growth method for growing a single crystal silicon ingot using the Czochralski method, comprising:
[0007] During the isodiametric growth stage, the crystal pulling speed is set to 0.95 mm / min to 1.1 mm / min, so that the entire crystal rod is a V-rich area; during the isodiametric growth stage, the target diameter of the crystal growth is 310 mm to 320 mm.
[0008] Optionally, a seeding stage and a shoulder release stage are included before the equal diameter growth stage.
[0009] Optionally, a material adding and melting stage is included before the seeding stage, wherein the concentration of doped nitrogen is greater than 2.1E13 atoms / cc.
[0010] Optionally, a finishing stage is further included after the equal diameter growth stage.
[0011] Optionally, the crystal growth method further comprises:
[0012] After the ingot is formed, it is tested for minority carrier lifetime to confirm the crystal area of the ingot;
[0013] When the crystal region of the crystal ingot includes a P-band region, the crystal ingot is tumbled to remove the P-band region at a radial edge of the crystal ingot.
[0014] An embodiment of the present invention further provides a wafer manufacturing method, wherein the wafer is manufactured using a crystal rod grown by the above-mentioned crystal growth method as a raw material.
[0015] Optionally, the wafer manufacturing method includes sequentially cutting, polishing and cleaning the crystal rod to form a wafer, wherein the low-temperature annealing process is omitted.
[0016] An embodiment of the present invention further provides a crystal growth control device for implementing the above-mentioned crystal growth method, wherein the crystal growth control device comprises:
[0017] a furnace body, wherein a chamber is defined within the furnace body;
[0018] A crucible assembly is disposed in the chamber of the furnace body, the crucible assembly comprising a quartz crucible and a graphite crucible that are nested, and the quartz crucible contains a silicon solution;
[0019] A water cooling jacket is provided above the crucible assembly and is used to cool the crystal rod;
[0020] a guide tube for guiding the inert gas to above the silicon melt, wherein the guide tube is arranged on the periphery of the water-cooling jacket, and in the axial direction of the furnace body, the guide tube and the water-cooling jacket partially overlap;
[0021] A water cooling screen is provided on the inner side of the guide tube, and the water cooling screen is located between the guide tube and the water cooling jacket, so as to cool the crystal rod.
[0022] Optionally, a cooling medium channel is provided in the water-cooling screen.
[0023] The present invention has the following beneficial effects: Because radially distributed regions of a crystal ingot may be V-rich in some areas and P-band in others, the BMD (Body Modulation) (BMD) varies depending on the region, causing fluctuations in the radial BMD of the crystal ingot and failing to ensure radial BMD uniformity. The crystal growth method provided by the present invention increases the crystal growth rate during the constant-diameter growth stage, placing the crystal ingot in the V-rich region, thereby improving BMD uniformity at the wafer edge. This improved BMD uniformity at the radial edge of the crystal ingot allows the BMD density of wafers obtained after slicing the crystal ingot to be kept at the same level throughout the radial direction. This not only enhances the impurity gettering ability at the wafer edge but also provides a more uniform stress distribution across the wafer, effectively improving the product yield of high-end processes and providing effective protection for silicon semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 A schematic diagram showing the uniformity of the BMD of a crystal rod formed by crystal growth in the related art;
[0025] Figure 2 A schematic diagram showing the BMD uniformity of a crystal ingot formed by the crystal growth method according to an embodiment of the present invention;
[0026] Figure 3 A schematic diagram showing the BMD uniformity of a crystal ingot formed by the crystal growth method according to an embodiment of the present invention;
[0027] Figure 4 A schematic diagram showing the BMD uniformity of a crystal ingot formed by the crystal growth method according to an embodiment of the present invention;
[0028] Figure 5 A schematic diagram showing the BMD uniformity of a crystal ingot formed by the crystal growth method according to an embodiment of the present invention;
[0029] Figure 6 Schematic diagram showing wafer defects;
[0030] Figure 7 Schematic diagram showing the G value simulation calculation after the cooling efficiency is improved;
[0031] Figure 8 A schematic diagram showing a portion of the structure of a crystal growth control device;
[0032] Figure 9 Schematic diagram showing the flow of the crystal growth method in an embodiment of the present invention. DETAILED DESCRIPTION
[0033] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.
[0034] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "an" or "the" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.
[0035] In addition, in this document, unless otherwise defined, the terms "substantially," "essentially," "approximately," and "about" are used to describe and explain small variations. When used in connection with an event or circumstance, these terms can encompass situations where the event or circumstance occurs exactly, as well as situations where the event or circumstance occurs approximately. For example, when used in connection with a numerical value, these terms can include a range of variation of less than or equal to 10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, less than or equal to ±0.05%. The term "substantially coplanar" can refer to two surfaces being aligned along the same plane within the micrometer range, for example, within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm.
[0036] In the Czochralski single crystal silicon manufacturing process, polycrystalline silicon raw material is loaded into a quartz crucible and heated to melt into a silicon solution. A seed crystal is then immersed in the silicon melt and then pulled upward by rotation, causing the silicon at the interface between the seed crystal and the silicon melt to solidify and crystallize. As the seed crystal is pulled upward, a single crystal silicon ingot is formed. The native defects in single crystal silicon grown using the Czochralski method are affected by the pulling speed and thermal field distribution during crystal growth. Depending on the crystallization pulling conditions, the native defect distribution is arranged in the order of V-rich region, OISF region, Pv region, Pi region, and I-rich region, starting from the high-speed side. The V-rich region is a region with a high number of voids due to a lack of silicon atoms at high pulling speeds. The I-rich region is a region with a high number of dislocations and excess silicon atom blocks due to excess self-interstitial silicon atoms at low pulling speeds. The OISF region is a region where defects called OISF (Oxidation Induced Stacking Fault) are distributed in a ring shape when observed in a cross section (within the wafer plane) in a direction perpendicular to the crystal growth axis.
[0037] In the prior art, nitrogen is often added during crystal growth to achieve high BMD. However, the higher the nitrogen doping concentration, the more likely it is to form P-bands and OISF regions, resulting in fluctuating BMD at the wafer edge and affecting BMD uniformity at the wafer edge. To avoid the formation of P-bands and OISF regions, the crystal growth method provided in embodiments of the present invention increases the pulling speed during the isodiametric growth phase. This ensures that the resulting ingot is entirely in the V-rich region, avoiding a situation where the region near the radial center of the ingot is V-rich and the region near the radial edge is P-band. Because radially, a portion of the ingot is V-rich and another portion is P-band, BMD can vary depending on the region, causing BMD fluctuations in the radial direction of the ingot. This makes it impossible to ensure radial BMD uniformity within the ingot and, consequently, improve BMD uniformity at the radial edge of the ingot. Therefore, in embodiments of the present invention, by increasing the pulling speed during the isodiametric growth phase, the ingot is placed in the V-rich region, thereby improving BMD uniformity at the radial edge of the ingot.
[0038] refer to Figure 9 In a specific implementation manner, this embodiment provides a crystal growth method for growing a single crystal silicon ingot using a Czochralski method, comprising:
[0039] During the isodiameter growth stage, the crystal pulling speed is set to 0.95 mm / min to 1.1 mm / min, so that the entire crystal rod is in the V-rich region.
[0040] Figure 1Schematic diagram of the uniformity of the BMD of a crystal rod formed by crystal growth in the related art. Figure 2 Schematic diagram of the BMD uniformity of the crystal rod formed by the crystal growth method in an embodiment of the present invention, wherein Figure 1 , the pulling speed in the isodiameter growth stage is increased. In the related art, crystal growth is carried out. In the isodiameter growth stage, the growth pulling speed is 0.7mm / min to 0.8mm / min, and the target crystal diameter is 306mm to 308mm. It should be noted that, Figure 1 and Figure 2 The horizontal axis is the radial position of the crystal rod (which can be the distance from the center point of the crystal rod), and the vertical axis is the BMD density value. Figure 1 and Figure 2 The curve in the figure represents the BMD density at different positions in the radial direction of the crystal rod. Figure 1 and Figure 2 The bar graph in the figure shows the BMD uniformity of the edges of different wafers after the crystal rod is cut into wafers. Figure 1 and Figure 2 Clearly, the crystal growth method provided in this embodiment improves the radial BMD uniformity of the crystal ingot. This improved BMD uniformity at the radial edge of the crystal ingot allows the BMD density of wafers obtained after slicing the crystal ingot to remain constant throughout the entire radial direction. This not only improves the impurity gettering capability at the wafer edge but also provides a more uniform stress distribution across the wafer, effectively improving the yield of high-end process products and providing effective protection for silicon semiconductor devices.
[0041] It should be noted that, during the isodiametric growth stage, the target pulling rate is 0.95 mm / min to 1.1 mm / min, that is, during the entire isodiametric growth stage, the growth pulling rates corresponding to different positions in the axial direction of the crystal rod are all the target pulling rates.
[0042] During crystal growth, nitrogen doping can form a high BMD. In an exemplary embodiment, the crystal growth method includes a feeding and melting stage, wherein the concentration of nitrogen doping is greater than 2.1E13 atoms / cc, but the present invention is not limited thereto.
[0043] In an exemplary embodiment, during the isodiameter growth stage, the target diameter of the crystal growth is 310 mm to 320 mm.
[0044] In order to ensure that the BMD uniformity is improved, in this embodiment, the target diameter of crystal growth is increased in the equal-diameter growth stage. In the related art, the target diameter of crystal growth is 306mm~308mm. In this embodiment, the target diameter of crystal growth is increased in the equal-diameter growth stage, and then after the crystal rod is formed, the crystal rod is subjected to minority carrier testing. If a P-ban region appears at the radial edge of the crystal rod, the P-band region at the radial edge of the crystal rod can be removed by rolling, so that the BMD uniformity of the radial edge of the crystal rod is effectively improved.
[0045] For example, during the constant diameter growth stage, an Automatic Diameter Control (ADC) device is used to automatically control the growth diameter of the crystal. The ADC device mainly uses an optical pyrometer sensor and a charge coupled device (CCD) camera to monitor the growth diameter of the single crystal silicon crystal: it assumes that the liquid level of the silicon melt does not change at a certain position. During the crystal growth process, the optical pyrometer sensor receives the thermal radiation at the solid-liquid interface of the silicon melt and outputs a corresponding brightness value. The brightness value can be used to obtain the growth diameter of the single crystal silicon crystal.
[0046] Figure 3 Schematic diagram of the BMD uniformity of the crystal rod formed by the crystal growth method in an embodiment of the present invention, wherein Figure 1 , the target diameter is increased during the isodiametric growth stage. Figure 1 The target diameter of the crystal is 306mm~308mm, Figure 2 The target diameter in the isodiameter growth stage is 310mm to 320mm. Figure 3 The curve in the figure represents the BMD density at different positions in the radial direction of the crystal rod. Figure 3 The bar graph in the figure shows the BMD uniformity of the edges of different silicon wafers after the crystal ingot is cut into silicon wafers.
[0047] Figure 3 The lower values 138, 140…148, 150 represent the distances from the different positions of the edge of the silicon wafer in the radial direction to the center of the silicon wafer, in mm. Figure 3 The numerical value on the right side of the middle represents the value of BMD homogeneity. Figure 3 The broken line in the figure represents the BMD density at different positions (139-148mm from center, 10 point) along the radial direction of the silicon wafer after the ingot is cut into silicon wafers. The bar graph represents the BMD uniformity of the edges of different silicon wafers. Figure 1It can be seen that the BMD uniformity of the edges of different silicon wafers is as low as 0.6 and as high as 1.5. Figure 3 The BMD uniformity values for different wafer edges range from a minimum of 0.18 to a maximum of 0.35. Smaller BMD edge uniformity values indicate more uniform wafer edges. Figure 3 The maximum value of the middle histogram is 0.35, which is less than Figure 1 The minimum value is 0.6, that is Figure 3 The BMD uniformity values of different silicon wafers are all less than Figure 1 The BMD uniformity values of different silicon wafers in the figure indicate that the BMD uniformity of the edge of the silicon wafer is improved after increasing the diameter.
[0048] Specifically, in some embodiments, the crystal growth method further includes: performing a minority carrier lifetime test on the crystal rod after the crystal rod is formed. If the test results show that a P-band region exists on the radial edge of the crystal rod, the crystal rod is subjected to a rolling process to remove the P-band region.
[0049] Specifically, the crystal growth method includes:
[0050] After the seeding stage, shoulder release stage, equal diameter growth stage and finishing stage, a crystal rod is formed;
[0051] Cutting the crystal rod to obtain test samples;
[0052] The samples were cleaned with a cleaning solution consisting of HF+H2O;
[0053] After cleaning, you can use a rotary hair dryer to dry or blow dry with nitrogen;
[0054] heat treating the sample;
[0055] Performing a minority carrier lifetime test on the heat-treated samples to obtain an MCLT map (minority carrier lifetime test result map);
[0056] Analyze the results of minority carrier lifetime test to determine the crystal region of the sample;
[0057] When the edge of the sample has a P-band region, the crystal ingot is subjected to a rolling process to remove the P-band region at the radial edge of the crystal ingot.
[0058] Exemplarily, the sample is subjected to heat treatment, including a first heat treatment stage and a second heat treatment stage, specifically comprising:
[0059] In the first heat treatment stage: in an oxygen atmosphere, the temperature is raised to 800°C and maintained at 800°C for 4 hours;
[0060] In the second heat treatment stage: in a nitrogen atmosphere, the temperature was raised to 1000° C. and maintained at 1000° C. for 16 hours.
[0061] In an exemplary embodiment, a seeding stage and a shoulder releasing stage are further included before the isodiameter growth stage.
[0062] In an exemplary embodiment, a finishing stage is further included after the isodiametric growth stage.
[0063] In a specific embodiment, the crystal growth method comprises:
[0064] S1: Adding materials: Polycrystalline silicon raw materials are placed in a quartz crucible and heated to melt, and nitrogen, boron, phosphorus, antimony, and arsenic are added and mixed to improve the production quality of the silicon raw materials. The concentration of nitrogen doping is greater than 2.1E13 atoms / cc. In some specific embodiments, the concentration of nitrogen doping is 2.1E13 atoms / cc, 3.8E13 atoms / cc, 4.7E13 atoms / cc, 5.9E13 atoms / cc, 7E13 atoms / cc, or 2.1E13 atoms / cc, but is not limited thereto.
[0065] It should be noted that excessively high or low nitrogen doping concentrations will lead to increased defects in the crystal structure, affecting the quality of the crystal rod. For example, the nitrogen doping concentration is less than or equal to 3E14 atoms / cc to avoid excessively high nitrogen doping concentrations, which will lead to increased defects in the crystal structure, such as dislocations or vacancies, which will affect the quality and integrity of the crystal.
[0066] S2: Melting: The polysilicon raw material and the added nitrogen, boron, phosphorus, antimony and arsenic are heated in a crystal furnace to raise the heating temperature to 1450°C, which is higher than the melting point of polysilicon, to quickly obtain the polysilicon melt raw material;
[0067] S3: Seeding stage: After the temperature of the polysilicon melt stabilizes, the seed crystal is slowly immersed in the silicon melt. When the seed crystal contacts the silicon solution, it is lifted upward, causing the silicon melt to climb upward and pull out the crystal at the top of the crystal rod;
[0068] S4: Shoulder release stage: Control the speed and temperature at the neck to control the crystal to form a specified diameter, adjust the crystal diameter, and continue to stretch the crystal;
[0069] S5: Constant diameter growth stage: Control the pulling speed of the crystal. At the same time, the crystal will be moved in the thermal field to control the temperature. The stability of the crystal when it is removed is constant to ensure that the diameter of the crystal rod is stably locked. At this time, the diameter of the crystal rod will be determined, forming constant diameter growth, which will act on the subsequent silicon wafer cutting;
[0070] During the isodiameter growth process, the target pulling speed for the crystal rod growth is 0.95 mm / min to 1.1 mm / min, and the target diameter for the crystal rod growth is 310-320 mm.
[0071] In some specific embodiments, during the isodiametric growth process, the target pulling rate for the crystal ingot growth may be 0.95 mm / min, 0.97 mm / min, 0.99 mm / min, 1 mm / min, or 1.1 mm / min.
[0072] In an exemplary embodiment, the target diameter of the crystal ingot growth may be 310 mm, 312 mm, 313 mm, 315 mm, 317 mm, or 320 mm.
[0073] S6: Finishing stage: When the crystal rod separates from the liquid surface, the overall pulling speed is reduced, and the crystal rod and the silicon melt are controlled to separate slowly until a sharp point is formed at the tail of the crystal rod, and then it can be separated from the liquid surface to ensure the production quality of the crystal rod.
[0074] S7: Conduct minority carrier lifetime test on the crystal ingot; specifically including:
[0075] S71: cutting the crystal rod to obtain a test sample;
[0076] S72: Cleaning the sample with a cleaning solution consisting of HF+H2O;
[0077] S73: After cleaning, the surface can be dried using a rotary blower or nitrogen gas.
[0078] S74: heat treating the sample;
[0079] S75: Perform minority carrier lifetime test on the heat-treated sample to obtain MCLT map (minority carrier lifetime test result map, refer to Figure 6 );
[0080] S76: Analyze the results of the minority carrier lifetime test to determine the crystal region of the sample;
[0081] S8: When a P-band region exists at the radial edge of the crystal rod in the test results of the minority carrier lifetime test, the crystal rod is subjected to a rolling process to remove the P-band region.
[0082] An embodiment of the present invention further provides a wafer manufacturing method, wherein the wafer is manufactured using a crystal rod grown by the above-mentioned crystal growth method as a raw material.
[0083] In an exemplary embodiment, the wafer manufacturing method includes sequentially cutting, polishing, and cleaning the crystal rod to form a wafer, wherein the low-temperature annealing process is omitted.
[0084] Specifically, the wafer manufacturing method includes:
[0085] Providing a crystal rod formed by the above crystal growth method;
[0086] Cutting the crystal rod into thin slices;
[0087] Polishing is performed on the cut wafers to reduce the defects and roughness on the wafer surface. The wafers need to be chamfered and ground first, and then polished with polishing fluid and polishing equipment to make the wafer surface smooth.
[0088] Cleaning the surface of the wafer;
[0089] Related art wafer fabrication methods also include an LTA (Low Temperature Annealing) process to increase BMD density. However, during this annealing process, the wafer is heated unevenly in the radial direction of the furnace, resulting in uneven BMD core distribution along the wafer's radial direction, impacting BMD uniformity. Because the crystal ingot in this embodiment is doped with a high concentration of nitrogen, the required BMD density is achieved, eliminating the need for a low-temperature annealing process to increase BMD density. Therefore, this low-temperature annealing process is omitted in this embodiment, improving BMD uniformity at the wafer edge while also reducing costs.
[0090] Figure 5 Schematic diagram of the uniformity of BMD of a wafer formed by the wafer manufacturing method in this embodiment. Figure 5 The curve in the figure represents the BMD density at different positions in the radial direction of the crystal rod. Figure 5 The bar graph in the figure shows the BMD uniformity of the edges of different silicon wafers after the crystal rod is cut into silicon wafers. Figure 1 ,get Figure 5 The silicon wafers shown in the results were not subjected to low temperature annealing process. Figure 1 The resulting silicon wafer underwent a low-temperature annealing process.
[0091] Figure 5 The lower values 138, 140…148, 150 represent the distances from the different positions of the edge of the silicon wafer in the radial direction to the center of the silicon wafer, in mm. Figure 5 The numerical value on the right side of the middle represents the value of BMD homogeneity. Figure 5 The broken line in the figure represents the BMD density at different positions (139-148mm from center, 10 point) along the radial direction of the silicon wafer after the ingot is cut into silicon wafers. The bar graph represents the BMD uniformity of the edges of different silicon wafers. Figure 1It can be seen that the BMD uniformity of the edges of different silicon wafers is as low as 0.6 and as high as 1.5. Figure 5 The BMD uniformity values for different wafer edges range from a minimum of 0.28 to a maximum of 0.58. Smaller BMD edge uniformity values indicate more uniform wafer edges. Figure 5 The maximum value of the middle histogram is 0.58, which is less than Figure 1 The minimum value is 0.6, that is Figure 5 The BMD uniformity values of different silicon wafers are all less than Figure 1 The BMD uniformity values of different silicon wafers indicate that the BMD uniformity of the silicon wafer edge has been improved after the low-temperature annealing process.
[0092] refer to Figure 8 The embodiment of the present invention further provides a crystal growth control device for implementing the above-mentioned crystal growth method, wherein the crystal growth control device comprises:
[0093] a furnace body, wherein a chamber is defined within the furnace body;
[0094] A crucible assembly is disposed in the chamber of the furnace body, the crucible assembly comprising a quartz crucible and a graphite crucible that are nested, and the quartz crucible contains a silicon solution;
[0095] A water cooling jacket is provided above the crucible assembly and is used to cool the crystal ingot 10;
[0096] A guide tube 1, which is used to guide the inert gas to the top of the silicon melt, wherein the guide tube is arranged on the periphery of the water cooling jacket, and in the axial direction of the furnace body, the guide tube and the water cooling jacket partially overlap;
[0097] The water-cooling screen 2 is disposed on the inner side of the guide tube 1 , and the water-cooling screen 2 is located between the guide tube 1 and the water-cooling jacket, so as to cool the crystal rod 10 .
[0098] The defects in crystal growth are determined by the V / G theory proposed by Voronkov in 1982, where V is the pulling speed in the isodiameter stage of the MCZ process section, G is the temperature gradient of the growth interface, V is implemented by the control system of the crystal pulling furnace, and G is determined by the shape of the heat shield, the core component of the thermal field. There is a critical region for the V / G ratio. When the V / G ratio is greater than the critical region, mainly vacancy defects are generated; when the V / G ratio is less than the critical region, mainly gap defects are generated. In this embodiment, the setting of the water-cooled shield improves the crystal cooling efficiency and improves the G value during crystal pulling (refer to Figure 7 , Figure 7(Case 1 curve shows the G value without a water cooling screen, while case 2 shows the G value with a water cooling screen.) According to the V / G theory (V / G = ζ), the smaller the ζ, the smaller the COP (crystal-derived particle) size. Furthermore, the smaller the ζ, the smaller the difference in COP size in the radial direction of the wafer, and from the wafer center to the wafer edge. Therefore, the overall radial vacancy concentration is more uniform, making BMD uniform in the radial direction of the wafer and improving BMD uniformity at the wafer edge.
[0099] Figure 4 This is a schematic diagram of the BMD uniformity of the wafer after improving the G value. Figure 4 The curve in the figure represents the BMD density at different positions in the radial direction of the crystal rod. Figure 4 The bar graph in the figure shows the BMD uniformity of the edges of different wafers after the crystal ingot is cut into wafers.
[0100] In an exemplary embodiment, a cooling medium channel is provided in the water-cooling panel 2. The water-cooling panel 2 is an annular structure, and the cooling medium channel is provided in a surrounding manner in the side wall of the water-cooling panel 2.
[0101] In an exemplary embodiment, the cooling medium channel includes a liquid inlet channel, a liquid outlet channel, and a main body channel disposed between the liquid inlet channel and the liquid outlet channel;
[0102] One end of the liquid inlet channel (liquid inlet 21) is exposed on the side wall of the water-cooling screen, and the other end of the liquid inlet channel extends along the axial direction of the water-cooling screen to the bottom of the water-cooling screen and is connected to the main channel;
[0103] The main channel is spirally arranged around the water-cooling screen, one end of the main channel is connected to the liquid inlet channel, and the other end of the main channel is arranged around the top of the water-cooling screen;
[0104] One end of the liquid outlet channel is communicated with the main channel, and the other end of the liquid outlet channel (liquid outlet 22) is exposed to the side wall of the water-cooling screen.
[0105] In an exemplary embodiment, the water cooling shield is fixed to the top of the furnace body.
[0106] In an exemplary embodiment, the water-cooling shield is fixed on the water-cooling jacket.
[0107] There are a few points to note:
[0108] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.
[0109] (2) For the sake of clarity, the thickness of layers or regions in the drawings used to describe the embodiments of the present disclosure are exaggerated or reduced, i.e., these drawings are not drawn to scale. It is understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or intervening elements may be present.
[0110] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.
[0111] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.
Claims
1. A crystal growth method for growing a single crystal silicon ingot using a Czochralski method, characterized in that: include: During the isodiameter growth stage, the crystal pulling speed is set to 0.95 mm / min to 1.1 mm / min, so that the entire crystal rod is in the V-rich region; In the isodiameter growth stage, the target diameter of the crystal growth is 310mm to 320mm.
2. The crystal growth method according to claim 1, wherein The isodiameter growth stage includes a seeding stage, and the seeding stage includes a material adding and melting stage, wherein the concentration of doped nitrogen is greater than 2.1E13 atoms / cc.
3. The crystal growth method according to claim 1, wherein A finishing stage is included after the isodiametric growth stage.
4. The crystal growth method according to claim 1, wherein Also includes: After the ingot is formed, it is tested for minority carrier lifetime to confirm the crystal area of the ingot; When the crystal region of the crystal ingot includes a P-band region, the crystal ingot is tumbled to remove the P-band region at a radial edge of the crystal ingot.
5. A wafer manufacturing method, characterized in that: The wafer is produced by using a crystal rod grown by the crystal growth method according to any one of claims 1 to 4 as a raw material.
6. The wafer manufacturing method according to claim 5, characterized in that: The method comprises cutting, polishing and cleaning the crystal rod in sequence to form a wafer, wherein the low-temperature annealing process is omitted.
7. A crystal growth control device, characterized in that: For implementing the crystal growth method according to any one of claims 1 to 4, the crystal growth control device comprises: a furnace body, wherein a chamber is defined within the furnace body; A crucible assembly is disposed in the chamber of the furnace body, the crucible assembly comprising a quartz crucible and a graphite crucible that are nested, and the quartz crucible contains a silicon solution; A water cooling jacket is provided above the crucible assembly and is used to cool the crystal rod; A flow guide tube, the flow guide tube being used to guide the inert gas to above the silicon solution, wherein the flow guide tube is arranged on the periphery of the water cooling jacket, and in the axial direction of the furnace body, the flow guide tube and the water cooling jacket partially overlap; A water cooling screen is provided on the inner side of the guide tube, and the water cooling screen is located between the guide tube and the water cooling jacket, so as to cool the crystal rod.
8. The crystal growth control device according to claim 7, characterized in that A cooling medium channel is provided in the water cooling panel.