Zero-current detection circuit optimization method based on combination of double-cycle prediction and nA-level dynamic adjustment

Abstract

The invention relates to a zero-current detection circuit optimization method combining double-cycle prediction with nA-level dynamic adjustment, which is particularly suitable for a power conversion circuit of a micro-energy acquisition system. According to the method, the ideal conduction time of a PMOS power tube is predicted through two power conversion periods, nA-level pulse current is adopted in subsequent ZCD modulation to charge and discharge a capacitor, digital logic signal overturning is abandoned, the precision-power consumption contradiction caused by logic scale enlargement in a traditional digital technology is avoided, and the reliability of the device is improved. And meanwhile, high power consumption caused by realizing high-precision ZCD in a traditional simulation technology is avoided, the high-precision ZCD is realized with extremely low power consumption, the efficiency of a micro-energy system is effectively improved, and the micro-energy acquisition circuit is particularly suitable for micro-energy acquisition circuits of heat energy, radio frequency and the like.

Description

Technical Field

[0001] The present invention relates to a zero current detection circuit technology for power conversion in a micro energy collection system, and in particular to a zero current detection circuit optimization method combining dual-cycle prediction with nA-level dynamic regulation. Background Art

[0002] In ambient micro-energy harvesting systems, boost converters are widely used to convert low-voltage micro-energy sources (such as thermal energy and radio frequency) into high voltages for subsequent circuitry. To improve energy harvesting efficiency, precise control of the power switch's on-time is crucial. Zero current detection (ZCD) technology, used to detect the moment a power switch (such as a PMOS power transistor) turns off, is a key technology for ensuring efficient energy conversion. However, traditional ZCD methods suffer from the following issues: 1. The traditional analog ZCD method detects the SW node and the output voltage (V OUT ), but a major drawback of this approach is the charge backflow caused by the comparator's response delay. To reduce this delay, the comparator typically consumes a large current, which directly leads to a significant increase in power consumption. Therefore, while traditional analog ZCD methods improve response speed, they also come with higher power consumption.

[0003] 2. Traditional digital ZCD methods typically track the approximate initial on-time of a PMOS power transistor. This initial tracking requires a long cycle (usually more than ten cycles). Subsequently, the system modulates the signal based on the flag bit immediately after the PMOS power transistor turns off. The accuracy of each cycle depends on the number of bits in the digital register. More bits improve accuracy, but this also significantly increases power consumption. Signal inversion itself consumes significant power, and the increase in power consumption becomes even more pronounced as the number of register bits increases. Although the adjustment accuracy improves in subsequent cycles, the increased number of register bits required for higher accuracy still poses a significant power consumption issue.

[0004] 3. The trade-off between power consumption and accuracy. Both analog and digital ZCD face a trade-off between power consumption and accuracy. For analog ZCD, increasing the comparator response speed improves accuracy but also results in higher power consumption. For digital ZCD, increasing the number of register bits improves modulation accuracy but also increases power consumption. This conflict between power consumption and accuracy makes existing ZCD technology difficult to meet practical requirements in low-power applications, especially in applications with extremely high energy efficiency requirements, such as micro-energy harvesting systems.

[0005] In summary, both traditional digital and analog ZCD methods have inherent limitations, especially in terms of the trade-offs between power consumption, response latency, and accuracy. These issues need to be addressed urgently to improve system efficiency and meet more stringent low-power requirements. Summary of the Invention

[0006] This invention provides a zero-current detection circuit optimization method that combines dual-cycle prediction with nA-level dynamic regulation. This method aims to address the limitations of existing ZCD technology in low-power applications, particularly the high power consumption and response delay issues of traditional analog and digital ZCD methods. It is particularly suitable for micro-energy harvesting systems in the environment. Through ingenious circuit design, this invention achieves high-precision ZCD with extremely low power consumption, further improving the efficiency of micro-energy harvesting systems.

[0007] The present invention adopts the following technical solution: a zero current detection circuit optimization method combining dual-cycle prediction with nA-level dynamic adjustment, in which the ideal on-time T0 is obtained by comparing the on-time difference of the PMOS power tube in two adjacent power conversion cycles; wherein the on-time length T0 of the NMOS power tube in the first cycle is N1 The NMOS power tube conduction time T in the second cycle N2 From the third cycle onwards, the initial on-time is set based on the ideal on-time T0, and the on-time of the next cycle is dynamically adjusted according to the SW node voltage value at the moment the PMOS power tube is turned off in the current cycle.

[0008] Compared with the prior art, the present invention has the following beneficial effects: 1. Extremely low power consumption: Through clever circuit design, this invention avoids the high-speed comparators and numerous flip-flop digital logic circuits required in traditional ZCD methods, significantly reducing system power consumption. Especially in micro-energy harvesting systems, this invention can achieve high-precision ZCD with extremely low power consumption.

[0009] 2. High-precision ZCD: The present invention is based on dual-cycle prediction combined with nA-level dynamic adjustment technology to accurately adjust the conduction time of the PMOS power tube. From the third cycle onwards, dynamic adjustment is performed based on the results of the previous cycle. In this way, the system can quickly adjust the optimal conduction time of the PMOS power tube in each cycle, thereby improving the response speed of the system and being able to quickly adapt to changes in input and output voltages. It overcomes the accuracy loss caused by comparator delay and digital modulation in traditional ZCD technology, ensures the accurate modulation of the ZCD circuit, and at the same time, the high precision of ZCD further improves the efficiency of the entire system.

[0010] 3. Rapid prediction of ideal on-time: The present invention can predict the ideal on-time of the PMOS in just two cycles, improving the system's response speed and enabling the system to adapt to rapidly changing environments.

[0011] 4. Simplified Circuit Design: This invention avoids the reliance on complex digital logic such as registers and counters in traditional ZCD methods by using simple current sources, fF-level capacitors, and control logic. This not only reduces circuit complexity but also reduces excess power consumption, thereby improving overall system efficiency.

[0012] 5. Wide range of application scenarios: The present invention can be widely used in low-power, high-precision micro-energy collection systems, especially in micro-energy collection circuits such as thermal energy and radio frequency, which greatly improves the energy conversion efficiency and system reliability of the micro-energy collection system. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A structural diagram of a micro energy harvesting system according to an embodiment of the present invention; Figure 2 is a flow chart of a method according to an embodiment of the present invention; Figure 3 is a working waveform diagram according to an embodiment of the present invention; Figure 4 1 is a waveform diagram of modulation of the on-time of a PMOS power tube according to an embodiment of the present invention, wherein (a) is a waveform diagram for shortening the on-time of the PMOS power tube, and (b) is a waveform diagram for extending the on-time of the PMOS power tube. DETAILED DESCRIPTION

[0014] The present invention will be further described below in conjunction with Examples and accompanying drawings. It should be understood that the examples are only intended to illustrate the present invention and are not intended to limit the scope of the present invention. Without departing from the spirit and scope of the present invention, variations and advantages that those skilled in the art can imagine are included in the present invention and are protected by the appended claims and their equivalents.

[0015] It should be understood that the term "a" should be understood as "at least one" or "one or more." That is, in one embodiment, the number of an element may be one, while in another embodiment, the number of the element may be multiple, and the term "a" should not be understood as limiting the quantity. In the present invention, except for names and terms that have been explicitly defined by the inventors, other names and terms are commonly used in the art.

[0016] In one embodiment of the present invention, a method for optimizing a zero current detection circuit by combining dual-cycle prediction with nA-level dynamic regulation includes: obtaining an ideal on-time T0 by comparing the on-time difference of a PMOS power tube in two adjacent power conversion cycles; wherein, the on-time length T0 of the NMOS power tube in the first cycle is N1 The NMOS power tube conduction time T in the second cycle N2From the third cycle onwards, the initial on-time is set based on the ideal on-time T0, and the on-time of the next cycle is dynamically adjusted according to the SW node voltage value at the moment the PMOS power tube is turned off in the current cycle.

[0017] Preferably, the NMOS power tube conduction time length T of the first cycle N1 is the conduction time of the NMOS power tube in the second cycle T N2 twice as much.

[0018] The micro energy collection system of the present invention is as follows Figure 1 As shown, the important components of the ZCD circuit include the following key components: 1. NMOS power tube and control logic: Based on MPPT technology, the on and off of the NMOS power tube is controlled to control the inductor energy storage.

[0019] 2. PMOS power tube: controls the energy release of inductor L.

[0020] 3. Two comparators CMP1 and CMP2: CMP1 is used to predict the ideal on-time of PMOS and generate a reference capacitor C REF The charge and discharge control signal CMP2 is used to determine when the PMOS power tube is disconnected starting from the third cycle.

[0021] 4. Reference capacitor C REF : The ideal on-time is predicted for the charge and discharge in the first two cycles, and from the third cycle onwards, the ideal on-time is modulated for the charge and discharge.

[0022] 5. Comparison capacitor C C : Starting from the third cycle, the comparison capacitor voltage V C and the voltage on the reference capacitor V REF The comparison determines whether to disconnect the PMOS.

[0023] 6. nA level current source: used to control the charging and discharging of the reference capacitor and the comparison capacitor, reduce power consumption, and improve the modulation accuracy of the PMOS power tube conduction time.

[0024] 7. Control logic: Some other control logic to ensure the orderly operation of the system.

[0025] In yet another embodiment of the present invention, obtaining the ideal on-time T0 includes: In the first cycle, a nA current source is used to connect the reference capacitor C REF Constant current charging; In the second cycle, the reference capacitor C is connected to the nA current source. REF Constant current discharge; According to the reference capacitor voltage V after discharge is completed REFCalculate T0.

[0026] Dynamically adjusting the on-time of the next cycle according to the SW node voltage value at the moment the PMOS power tube is turned off in the current cycle includes: When the PMOS power tube is turned off and the SW node is high, the reference capacitor C REF Charge the current of a pulse duration to extend the conduction time of the next cycle; When the PMOS power tube is turned off and the SW node is low, the reference capacitor C REF Discharge the current of a pulse duration to shorten the conduction time of the next cycle.

[0027] Preferably, the method includes a reference capacitor C REF and comparison capacitor C C .

[0028] Preferably, the comparison capacitor C C is the reference capacitor C REF twice as much.

[0029] Preferably, the method does not rely on digital logic signal inversion to achieve regulation.

[0030] Preferably, in the method, the operating current of all comparators is less than 100 nA.

[0031] Specific implementation steps, such as Figure 2 As shown in Figure 2, the prediction of the ideal on-time T0 for the first two cycles includes: 1. In the first cycle, the NMOS power tube is turned on T N1 time. Then after the switch is switched, the PMOS conduction time T P1 = Ideal on-time T0 + comparator delay T CMP At the same time, the constant current source charges the reference capacitor, and the voltage V REF Rise at a constant speed.

[0032] 2. In the second cycle, the NMOS power tube is turned on T N2 time, then after the switch is switched, the PMOS conduction time T P2 =0.5×ideal on-time T0+comparator delay T CMP At the same time, the voltage on the reference capacitor is discharged at a constant current, and the voltage on the reference capacitor V REF Descending at a constant speed.

[0033] 3. At this time, the reference voltage V REF = (0.5×ideal on-time T0) / C REF To obtain the ideal on-time, you only need to: 1) use the same current and capacitance value C REF The comparison capacitor is charged to 0.5×VREF ; or, 2) use the same current for a capacitance of 2×C REF The comparison capacitor is charged to V REF The time spent by the two is the ideal conduction time T0. In this embodiment, the latter is selected.

[0034] In the third cycle, the conduction time of the PMOS power tube is T0. The subsequent cycles are dynamically adjusted based on the conduction time of the PMOS power tube in the previous cycle, including: 1. In the third and subsequent cycles, the same current is used to give a capacitance value of approximately 2×C REF The comparison capacitor is charged, and when the voltage on the comparison capacitor is close to the reference voltage V REF When , CMP2 flips over and disconnects the PMOS power tube.

[0035] 2. In the third and subsequent cycles, when the PMOS power tube is just turned off and the SW node is high, it means that the PMOS power tube conduction time in the current cycle is too short and the energy in the inductor is not fully released. At this time, the reference capacitor C REF The current of one pulse time is charged to extend the PMOS conduction time of the next cycle.

[0036] 3. In the third and subsequent cycles, when the PMOS power tube is just disconnected and the SW node is low, it means that the PMOS power tube is on for too long in the current cycle, and current flows from the output through the PMOS power tube and the inductor to the input. At this time, the reference capacitor C REF Discharge the current of one pulse time and shorten the conduction time of the PMOS power tube in the next cycle.

[0037] The working waveform diagram of the embodiment of the present invention is as follows: Figure 3 As shown in the figure, it shows how to accurately predict the ideal on-time of PMOS in two cycles, and then how the next cycle is modulated according to the SW node voltage. The embodiment of the present invention can be divided into two processes: prediction and modulation. The prediction: in the first two cycles, the on-time of NMOS power tube in the first cycle is T N1 , after the NMOS power tube is disconnected, the PMOS conduction time is T P1 , while the current source to the reference capacitor C REF Charging T P1 Time. The NMOS power tube conduction time of the second cycle is T N1 / 2, after the NMOS power tube is disconnected, the PMOS conduction time is T P2 , while the reference capacitor C REF Discharge T P2 Time, at which the voltage on the reference capacitor V REFIt is exactly half of the conduction time of the PMOS power management. Modulation: Starting from the third cycle, based on the voltage on the reference capacitor and the SW node voltage value at the moment the PMOS power tube is turned off in the current cycle, the conduction time of the next cycle is dynamically adjusted. When the PMOS power tube is turned off and the SW node is high, the reference capacitor C REF Charge a pulse duration current to extend the next cycle on time; when the PMOS power tube is turned off and the SW node is low, the reference capacitor C REF Discharge the current of a pulse duration to shorten the conduction time of the next cycle.

[0038] The system adjusts the on-time by charging and discharging a reference capacitor through a current source. Through this method, the reference voltage is precisely adjusted during the charging and discharging process, allowing the PMOS power transistor to achieve the ideal on-time. This adjustment is more precise and consumes less power than traditional digital ZCD.

[0039] In this embodiment, the current source current is selected to be in the nA level to ensure low power consumption while achieving sufficient accuracy in on-time regulation. REF The capacitance value is usually half of the comparison capacitance, but can be fine-tuned according to the specific application. Figure 4 As shown in (a), when the PMOS power tube is disconnected and the SW node is at a low level, it means that the PMOS power tube is on for a slightly longer time. In order to make the PMOS power tube on time more accurate, the reference capacitor C REF Discharge the current of a pulse duration to shorten the conduction time of the next cycle. This process eliminates parasitic effects and the power supply does not need to supply the reference capacitor C REF To replenish energy, the power supply only needs to charge the comparison capacitor with a current of several nA (charging time is usually less than 1μs). Figure 4 As shown in (b), when the PMOS power tube is disconnected and the SW node is high, it means that the PMOS power tube conduction time is slightly shorter. In order to make the PMOS power tube conduction time more accurate, the reference capacitor C REF A current of the duration of a pulse is charged to extend the on-time of the next cycle. This process eliminates parasitic effects. The power supply charges the reference capacitor with a current of several nanoamperes for a pulse duration, and the power supply charges the comparison capacitor with a current of several nanoamperes (the charging time is typically less than 1 μs). Therefore, in this embodiment, high-precision ZCD can be achieved with a current consumption of nanoamperes.

[0040] Through the above circuit design, the present invention can achieve high-precision ZCD under low power consumption conditions, avoiding the efficiency loss caused by high-power comparators and complex digital logic circuits in traditional methods. REF The precise charge and discharge control ensures the system's fast response and high-precision regulation, while significantly reducing the system's power consumption.

[0041] This paper proposes a zero-current detection (ZCD) circuit optimization method that combines dual-cycle prediction with nA-level dynamic adjustment. This method aims to address the high power consumption and response delay issues of traditional analog and digital ZCD methods. This method predicts the ideal on-time during the first two cycles and fine-tunes it based on the SW node voltage during subsequent cycles, thereby precisely controlling the on-time of the PMOS power transistor while maintaining low power consumption. This method avoids the reliance on high-speed comparators and complex digital circuits found in traditional methods, significantly reducing power consumption and improving system response speed and accuracy.

[0042] The innovative point of the present invention is:By simple current source, reference capacitor and control logic, high-precision ZCD technology is realized in a low-power mode. The method only needs two cycles to accurately predict the ideal on-time of PMOS power tube, and accurately adjusts its on-time in subsequent cycles, breaks through the limitations of traditional ZCD methods, and provides a kind of efficient, low-power and high-precision ZCD control mechanism. Compared with prior art, the present invention not only improves system energy conversion efficiency, but also reduces design complexity, with significant technological advancement and practical application value.

[0043] Therefore, the present invention has broad application prospects in micro-energy collection systems, and is particularly suitable for micro-energy collection systems such as thermal energy and radio frequency. It can meet the requirements of low power consumption and high precision, and greatly improves the working efficiency and reliability of the system.

[0044] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0045] The above-mentioned specific implementation methods are used to illustrate the present invention and are only preferred embodiments of the present invention, rather than limiting the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit of the present invention and the scope of protection of the claims shall fall within the scope of protection of the present invention.

Claims

1. A zero current detection circuit optimization method combining dual-cycle prediction with nA-level dynamic adjustment, characterized in that: In two adjacent power conversion cycles, the ideal on-time T0 is obtained by comparing the on-time difference of the PMOS power tube; among them, the on-time of the NMOS power tube in the first cycle is T N1 The NMOS power tube conduction time T in the second cycle N2 It is a multiple relationship; From the third cycle onwards, the initial on-time is set based on the ideal on-time T0, and the on-time of the next cycle is dynamically adjusted according to the SW node voltage value at the moment the PMOS power tube is turned off in the current cycle.

2. The method according to claim 1, characterized in that The NMOS power tube conduction time of the first cycle is T N1 is the conduction time of the NMOS power tube in the second cycle T N2 twice as much.

3. The method according to claim 1, characterized in that Obtaining the ideal on-time T0 includes: In the first cycle, a nA current source is used to connect the reference capacitor C REF Constant current charging; In the second cycle, the reference capacitor C is connected to the nA current source. REF Constant current discharge; According to the reference capacitor voltage V after discharge is completed REF Calculate T0.

4. The method according to claim 1, wherein The dynamic adjustment includes: When the PMOS power tube is turned off and the SW node is high, the reference capacitor C REF Charge the current of a pulse duration to extend the conduction time of the next cycle; When the PMOS power tube is turned off and the SW node is low, the reference capacitor C REF Discharge the current of a pulse duration to shorten the conduction time of the next cycle.

5. The method according to claim 1, characterized in that Including reference capacitor C REF and comparison capacitor C C .

6. The method according to claim 5, characterized in that The comparison capacitor C C is the reference capacitor C REF twice as much.

7. The method according to claim 1, characterized in that The method does not rely on digital logic signal inversion to achieve regulation.

8. The method according to claim 1, characterized in that The operating current of all comparators in the method is less than 100 nA.

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