Multi-channel real-time data acquisition unit based on FPGA (Field Programmable Gate Array)

Abstract

The invention relates to a multi-channel real-time data acquisition unit based on an FPGA. The invention discloses a design method of a multi-channel data real-time acquisition and edge calculation processor for data acquisition. Data output by the processor comprises multi-channel signals and characteristic values such as mean values, variances and mean square values of the channel signals. The system has the characteristics of multi-channel synchronous real-time acquisition, random customization of the number of sampling channels and sampling frequency and the like. Compared with the prior art, the method has the characteristics of multiple synchronous sampling channels, customizable acquisition channel number and sampling rate, real-time calculation of signal characteristic values and the like.

Description

Technical Field

[0001] The invention discloses a method for designing FPGA data collection and real-time output, and belongs to the field of data collection. Background Art

[0002] In today's rapidly developing information society, multi-channel data acquisition systems are widely used in various fields. Successfully acquiring sensor data and processing such large amounts of data in real time are among their most important functions. Using programmable logic gates within an FPGA to replace the DSP core within the FPGA for calculating eigenvalues ​​can effectively reduce the FPGA's computational burden and lower its cost.

[0003] Currently, the front-end of data acquisition systems primarily utilizes a DSP+FPGA-based hardware architecture. In this DSP+FPGA-based solution, the DSP is primarily responsible for calculating the characteristic values ​​of the acquired signals. However, this approach has the disadvantage that when a multi-channel acquisition system collects large amounts of data or a high number of bits, the DSP may be limited by its own computing power, resulting in the system being unable to achieve real-time calculations. This is one of the factors that limits the overall sampling rate of the data acquisition system. Summary of the Invention

[0004] The problem to be solved by the present invention is to provide a real-time eigenvalue calculation system based on FPGA, which can realize the real-time calculation of eigenvalues ​​of a large amount of high-bit, multi-channel data. Moreover, the system has the characteristics of small size, light weight, and low power consumption.

[0005] This system provides a storage strategy that prioritizes appending 8 bits of data as a channel number to the data collected from all channels. After appending the channel number, the data is stored in the corresponding storage location in the input data buffer. For example, if channel 5 has 24 bits of data to be stored in the data storage area, the channel number will be prepended to the data before it is stored in the data buffer, i.e., "0000 0101" (in binary display). The final data bits stored in the data buffer are "05XX XX XX" (in hexadecimal display, where XX represents the collected data). Figure 2 This is a detailed logic block diagram of the input data buffer area.

[0006] This system provides a high degree of freedom to modify the sampling frequency modification strategy, this function is mainly realized by the channel data acquisition unit. Its logic block diagram is as follows Figure 2As shown in the figure, the specific implementation process is as follows: the channel acquisition power supply receives the sampling rate command for each channel from the main control module, sets the sampling counter threshold for each channel, reads the data of the corresponding channel from the A / D, and counts the data read by each channel through the counter. When the count value reaches the counter threshold, the data is sent to the input data buffer and the count value is reset to zero. Through this method of modifying the sampling frequency controlled by the main control module, any channel can be modified to any value less than the maximum sampling frequency of the A / D.

[0007] When the master module issues a channel sampling rate instruction of 0x0002, the table sets the counter threshold of this channel to 2. At this time, the sampling frequency of this channel is 1 / 2 of the maximum sampling frequency. When the master module issues a channel sampling rate of 0xFFFF, it means that the channel is closed and the data of this channel is no longer read.

[0008] The parallel-to-serial conversion unit performs high-speed scanning of data from the channel acquisition area, combining the data from 128 channels into a single data stream and sending this data to the FIFO_1 and FIFO_2 storage areas in a rotating manner according to a rotation cycle. The high-speed scanning clock frequency is no less than 200 times the maximum A / D sampling frequency. For example, when the maximum A / D sampling rate is 256K, the high-speed scanning clock frequency can be set to 50MHz. During operation, the data parallel-to-serial conversion unit scans to read the values ​​of the channel flag bits in the channel acquisition area. When the flag bit corresponding to a channel is found to be 1, the parallel-to-serial conversion unit writes the data for that channel to the front-end storage area in a rotating manner, setting the flag bit to 0.

[0009] Figure 3 The data selection area scans and reads the data in the channel acquisition area, combining the data from 128 channels into a single data stream. This data is then sent to the FIFO_1 and FIFO_2 storage areas in a rotating manner according to a specific time period. Specifically, the data selection area scans and reads the values ​​of each flag bit in the channel acquisition area. When a flag bit corresponding to a channel is 1, the data for that channel is written to the FIFO storage area according to a specific time period (data is written to the FIFO_1 storage area in odd cycles, as indicated by a solid arrow, and to the FIFO_2 storage area in even cycles, as indicated by a dashed arrow). The flag bit for that channel is set to 0, and scanning is restarted. For example, in the first rotation cycle, the parallel-serial conversion unit writes the scanned data to the FIFO_1 storage area. In the second rotation cycle, the parallel-serial conversion unit writes the read data to the FIFO_2 storage area.

[0010] Figure 3The internal structure of the mean calculation module and its corresponding FIFO storage area. The function of this module is to receive data from the data selection area in rotation according to the rotation cycle. While receiving the data, the mean calculation module starts to calculate the mean of the data within this time period, and finally sends the stored data and the calculated mean to the next level FIFO storage area and variance & mean square value calculation module in rotation. Figure 3 As you can see, after data is input into this area, it is not only entered into the FIFO storage area but also sent to the corresponding counter and adder based on its channel number. These counters and adders count the amount of data and the total data in the corresponding channel within that cycle. At the end of that cycle, the data in all counters and adders is sent to the divider, which calculates the average value of all channels during that cycle. After the divider completes the calculation, it outputs the data in the register and the average value.

[0011] Figure 4 This is the internal structure of the variance & mean square value calculation module. The function of this area is to receive data from the FIFO storage area in a certain period of time, calculate the mean and variance of these data within this period through the logic circuit, and finally output the calculated mean and variance to the output module. In specific operation, the variance & mean square value calculation module will send the received channel raw data stream and mean to the designated module ( Figure 4 The solid line in the middle is the original data flow of the channel, and the dotted line is the mean. After the data is input, the mean will be stored in a specific register so that it can be called at any time. The data flow will be calculated through a multiplier to calculate its corresponding square value x i 2 , and according to the channel number corresponding to the data in the data stream, add all the data with the same channel number to obtain the mean square value ∑x of each channel i 2 At the same time, the data stream will pass through a subtractor and subtract the mean value with the same channel number (x ij -μ i ), and then the square of this value is calculated by the multiplier (x ij -μ i ) 2 Finally, the square values ​​of the same channel number are added together by the adder to obtain the variance ∑(x ij -μ i ) 2 .

[0012] FIFO_3 and FIFO_4 are primarily used to receive raw data from FIFO_1 and FIFO_2, and output it to the output module at regular intervals. In the first interval, FIFO_1 inputs raw data into Data Storage Area 1, and Data Storage Area 2 outputs the existing data to the output module. In the second interval, FIFO_2 inputs raw data into Data Storage Area 2, and Data Storage Area 1 outputs the data stored in the previous interval to the output module.

[0013] The output module is primarily used to alternately output the FIFO storage area and the calculated eigenvalue data. Specifically, in the first cycle, the output module first selects data from FIFO_3 and, after completing the data from FIFO_3, outputs the eigenvalue data from Variance & RMS Calculation Module_1. In the second cycle, the output module first selects data from FIFO_4 and, after completing the data output, selects the eigenvalue data from Variance & RMS Calculation Module_2. The output data flow should be: data from FIFO_3 + data from Variance & RMS Calculation Module_1 + data from FIFO_4 + data from Variance & RMS Calculation Module_2. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 It is a system structure diagram of the present invention; Figure 2 It is the internal structure of the channel data acquisition unit and input data buffer area of ​​the present invention; Figure 3 Schematic diagram of the internal structure of the mean value calculation module of the present invention; Figure 4 Schematic diagram of the internal structure of the variance & mean calculation module of the present invention.

Claims

1. A multi-channel FPGA real-time signal processing method, characterized in that: include: Main control module, serial communication module, channel data acquisition unit, input data buffer, parallel-serial conversion unit, FIFO storage area (including FIFO_1 to FIFO_4), eigenvalue calculation module (mean calculation module and variance & mean square value calculation module) and output module. The main control module is used to control and coordinate the working sequence of each logic unit and receive instructions from the host computer through the serial port module. The channel data acquisition unit is used to receive the sampling rate instructions of each channel issued by the main control module, and collect A / D output data according to the set sampling rate of each channel. The input data buffer is used to receive and store the data output by the channel data acquisition unit and to add the channel number before each channel data. The data parallel-to-serial conversion unit is used to scan and read the data in the input data buffer, combine the data of 128 channels into a single data stream, and send it to the FIFO 1 storage area and FIFO 2 storage area in a rotating manner according to the rotation cycle. The FIFO storage area consists of four storage areas, FIFO_1-FIFO_4, among which FIFO_1 and FIFO_2 are front-end storage areas, which receive data from the parallel-serial conversion unit in a round-robin manner. FIFO_3 and FIFO_4 are back-end storage areas, which receive data from the front-end storage area in a round-robin manner. The eigenvalue calculation module includes a mean calculation unit, a variance and mean square value calculation unit, which is used to receive the data stream and calculate the eigenvalues ​​such as the mean, variance and mean square value of each channel according to the channel number. The output module is used to continuously send the data and characteristic values ​​stored in the back-end storage area to the host computer.

2. The channel data acquisition unit according to claim 1, wherein: The channel data acquisition unit sets a sampling counter for each channel. This unit receives sampling rate commands for each channel from the main control module and sets the threshold for the corresponding channel sampling counter based on the sampling rate. The data for the corresponding channel is read from the A / D converter and counted. When the count reaches the counter threshold, the data is sent to the input data buffer and the counter is reset. The sampling rate for each channel issued by the main control module can be any value less than the maximum sampling rate of the A / D converter, so the sampling rate for each channel can be any frequency division less than the maximum sampling rate of the A / D converter. If a sampling channel needs to be closed, the sampling rate of the channel sent by the main control module is 0xFFFF, and the data of the channel is no longer read.

3. The input data buffer according to claim 1, wherein: The input data buffer receives and stores data output by the channel data acquisition unit and sets a flag for each channel to indicate whether the channel's data has been updated. When data is stored in the buffer, a one-byte channel number is prepended to the data. For example, if channel 5 inputs a 24-bit data, "05" is prepended to the data, resulting in a 4-byte data buffer of "05 XX XX XX" (in hexadecimal notation, where XX represents the channel data). When the data is successfully stored in the input data buffer, the corresponding channel flag, Flag_N, is set to 1.

4. The data parallel-to-serial conversion unit according to claim 1 is configured to scan and read the channel acquisition area at high speed, combine the data from 128 channels into a single data stream, and transmit the data to the FIFO_1 storage area and the FIFO_2 storage area in a rotating manner according to a rotation cycle. The high-speed scanning clock frequency is not less than 200 times the maximum sampling rate of the A / D. For example, when the maximum sampling rate of the A / D is 256 kHz, the high-speed scanning clock frequency can be set to 50 MHz. Specifically, under the control of the main control module, the data parallel-to-serial conversion unit scans and reads the values ​​of the flag bits of each channel in the channel acquisition area. When a flag bit corresponding to a channel is 1, the data of the channel is rotated and written to the front-end storage area FIFO_1 or FIFO_2 according to the rotation cycle, and the flag bit is set to 0. For example, if the data scanned and read in the data selection area in the first rotation cycle is written to the FIFO_1 storage area, the data scanned and read in the data selection area in the next rotation cycle will be written to the FIFO_2 storage area.

5. The detailed working process of the rotation cycle as claimed in claim 1 is as follows: Odd rotation period: (1) Send the data in the string conversion unit to the FIFO_1 storage area and the mean calculation module_1; (2) Send the data in the FIFO_2 storage area to the FIFO_4 storage area and the variance & mean square value calculation module_2; (3) Send the data in FIFO_3 and the mean, variance & mean square value and other data in variance & mean square value calculation module_1 to the output module respectively; Even rotation period: (1) Send the data in the string conversion unit to the FIFO_2 storage area and the mean calculation module_2; (2) Send the data in the FIFO_1 storage area to the FIFO_3 storage area and the variance & mean square value calculation module_1; (3) The data in FIFO_4 and the mean, variance & mean square value and other data in variance & mean square value calculation module_2 are sent to the output module respectively.

6. The mean calculation module of claim 1, wherein the module is configured to calculate the mean of data from each channel using a pipeline operation. When data is written to the FIFO_1 or FIFO_2 storage area, the data also flows into the corresponding mean calculation module. The mean calculation module transmits the incoming data to the counter and adder corresponding to the channel number according to its channel number. These counters and adders count and calculate the number and sum of data in the corresponding channel in the input data. After the rotation cycle, the data in all counters and adders are transmitted to the divider. The divider calculates the mean μi (where i is the channel number) of all channels and outputs the calculated result to the variance and mean square value calculation module.

7. The variance & mean square value calculation module as described in claim 1, wherein the function of this area is to receive data from the FIFO_1 storage area or the FIFO_2 storage area in rotation according to the rotation cycle, and calculate and store the variance and mean square value of this data. The specific working process is as follows: the variance & mean square value calculation module receives the data stream input from the front-end storage area and the mean value of each channel output by the mean calculation module. The data stream is passed through a multiplier to calculate the corresponding square value. And calculate the mean square value of the corresponding channel through the adder (where i is the channel number and j is the jth data of the channel). At the same time, the data stream is calculated by the subtractor, multiplier and adder respectively (x ij -μ i )、(x ij -μ i ) 2 ,∑(x ij -μ i ) 2 Get the variance ∑(x ij -μ i ) 2 Finally, the mean, variance and mean square value of all channels are stored in registers.

8. The output module of claim 1, wherein the region is configured to receive data from the backend storage area (FIFO_3 or FIFO_4) and the variance & mean square calculation module. The specific operation process is as follows: during odd cycles, the output module sequentially reads data from FIFO_3 and eigenvalue data from variance & mean square calculation module_1; during even cycles, the output module sequentially reads data from FIFO_4 and eigenvalue data from variance & mean square calculation module_2.

Images