Memory fault processing method and device, memory controller, chip and equipment

Abstract

The invention provides a memory fault processing method and device, a memory controller, a chip and equipment, and relates to the technical field of memorys.The method comprises the steps that correctable error CE fault sampling is conducted on a memory according to a first sampling time strategy, CE fault data are obtained, and the CE fault data comprise address information of CE faults in the memory; performing fault processing on the memory according to the CE fault data; and performing CE fault sampling on the memory according to a second sampling time strategy, the first sampling time strategy being different from the second sampling time strategy. According to the invention, the influence of the UCE fault of the memory on the computing equipment can be avoided as far as possible.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a method, apparatus, memory controller, chip, and device for handling memory faults. Background Art

[0002] Memory, as a crucial component of computing devices, plays a crucial role. However, uncorrectable memory errors (UCEs) have become a common hardware failure in computing devices. These UCEs cannot be recovered through self-recovery strategies and can significantly impact the normal operation of computing devices.

[0003] Therefore, how to predict memory failures in a timely manner to minimize the serious impact of memory UCE failures on computing devices has become an urgent problem that needs to be solved. Summary of the Invention

[0004] This application provides a method, apparatus, memory controller, chip, and device for handling memory failures, which can minimize the impact of memory UCE failures on computing devices. The corresponding technical solutions are as follows:

[0005] In a first aspect, a method for handling a memory failure is provided, the method comprising:

[0006] According to a first sampling time strategy, correctable error (CE) fault sampling is performed on the memory to obtain CE fault data, where the CE fault data includes address information of the CE fault in the memory. Fault processing is performed on the memory based on the CE fault data. According to a second sampling time strategy, CE fault sampling is performed on the memory, where the first sampling time strategy and the second sampling time strategy are different.

[0007] In the technical solution provided in this application, the address information of a CE fault in memory can be the address of the cell in the memory where the CE fault occurred. The sampling strategy can include a sampling window length and a sampling interval. Accordingly, the difference between the first sampling time strategy and the second sampling time strategy may include: the sampling window length in the first sampling time strategy and the sampling window length in the second sampling time strategy are different; or the sampling interval in the first sampling time strategy and the sampling interval in the second sampling time strategy are different; or, the sampling window length in the first sampling time strategy and the sampling window length in the second sampling time strategy are different and the sampling interval in the first sampling time strategy and the sampling interval in the second sampling time strategy are different. In this solution, by collecting CE fault data from the memory, fault prediction is performed on the memory, thereby implementing appropriate fault handling measures for the memory to minimize the serious impact of memory UCE faults on the computing device. In addition, in this solution, the sampling interval and sampling window length to be used next are dynamically adjusted based on the CE fault data collected within the current sampling window, thereby adjusting the amount of data to be sampled next and optimizing the computing resources used for sampling.

[0008] In a possible implementation, before performing CE fault sampling on the memory according to the second sampling time strategy, the method further includes:

[0009] According to the CE fault data, the second sampling time strategy is determined.

[0010] In the technical solution provided in this application, at the end of the previous sampling window, the sampling window length and sampling interval can be dynamically adjusted based on the CE fault data in the memory collected in the previous sampling window, and the adjusted sampling window length and sampling interval can be used as the second sampling time strategy.

[0011] In a possible implementation, determining the second sampling time strategy according to the CE fault data includes:

[0012] According to the address information of the CE fault in the memory, the spatial distribution characteristics of the CE fault data are determined. According to the spatial distribution characteristics of the CE fault data, a second sampling time strategy is determined.

[0013] In the technical solution provided by this application, after collecting address information of CE faults in memory, further statistics can be performed to obtain spatial distribution characteristics of the CE fault data. The spatial distribution characteristics can characterize the spatial distribution of cells in memory where CE faults have occurred. Furthermore, a second sampling time strategy can be determined based on the spatial distribution characteristics of the CE fault data.

[0014] In a possible implementation, determining the second sampling time strategy according to the spatial distribution characteristics of the CE fault data includes:

[0015] In the correspondence between the spatial distribution characteristics and the sampling time strategy, the second sampling time strategy corresponding to the spatial distribution characteristics of the CE fault data is queried.

[0016] In the technical solution provided by this application, a correspondence between spatial distribution characteristics and sampling time strategies can be pre-established. This correspondence can be established by technical personnel based on experiments and experience. After the spatial distribution characteristics of CE fault data are statistically obtained, the corresponding second sampling time strategy can be queried from this correspondence.

[0017] In a possible implementation, performing fault processing on the memory according to the CE fault data includes:

[0018] Based on the address information of CE faults in the memory, the temporal distribution characteristics of the CE fault data are determined. Based on the temporal and spatial distribution characteristics of the CE fault data and the fault level prediction model, the fault level of each memory cell in the memory is predicted to obtain the predicted fault level of each memory cell. For each cell, fault handling is performed based on the predicted fault level.

[0019] In the technical solution provided by this application, after collecting CE fault data from the memory, the temporal distribution characteristics of the CE faults can also be calculated. These temporal distribution characteristics can characterize the temporal distribution of CE faults occurring in the memory within the first sampling window. To improve the accuracy of fault prediction, this method simultaneously considers both the spatial and temporal distribution characteristics of CE faults, performs cell-level fault prediction on the memory, and obtains the predicted fault level for each cell. This allows for targeted fault handling for each cell.

[0020] In one possible implementation, to improve fault prediction efficiency, before inputting the spatial and temporal distribution features of CE faults into the fault level prediction model, the spatial and temporal distribution features of CE faults may be reduced in dimension. Accordingly, the processing may be as follows:

[0021] Performing dimensionality reduction on the spatial distribution features of the CE fault data and the temporal distribution features of the CE fault data to obtain reduced spatial distribution features and reduced temporal distribution features. Inputting the reduced spatial distribution features and reduced temporal distribution features into a fault level prediction model to obtain a predicted fault level for each cell.

[0022] In a possible implementation, dimensionality reduction is performed on the spatial distribution features and the temporal distribution features of the CE fault data to obtain the reduced spatial distribution features and the reduced temporal distribution features, including:

[0023] The spatial distribution characteristics of CE fault data and the temporal distribution characteristics of CE fault data are input into the feature dimensionality reduction model to obtain the spatial distribution characteristics and the temporal distribution characteristics after dimensionality reduction.

[0024] In the technical solution provided in the embodiment of the present application, a feature dimensionality reduction model may be used to reduce the dimensionality of the spatial distribution features and the temporal distribution features of the CE fault data, for example, a gradient boosting algorithm (Catboost) model.

[0025] In one possible implementation, cell fault handling is performed based on the predicted fault level of the cell, including:

[0026] If the cell's predicted fault level corresponds to an uncorrectable error (UCE), the data stored in the cell is migrated to an idle cell with the lowest predicted fault level. If the cell's predicted fault level corresponds to a CE, the self-recovery policy corresponding to the cell's predicted fault level is invoked in the recovery policy library to recover the cell.

[0027] In the technical solution provided in this application, a lower predicted fault level indicates a less severe possible fault in the corresponding cell. Conversely, a higher predicted fault level indicates a more severe possible fault. The highest predicted fault level indicates that the cell's predicted fault is a UCE fault. Based on this, for each cell, if the predicted fault level corresponds to a UCE fault, the data stored in the cell is migrated to an idle cell with the lowest predicted fault level to prevent a UCE fault in the cell from seriously impacting the computing device.

[0028] In one possible implementation, the address information of the CE fault in the memory is the address of the cell where the CE fault occurs in the memory, and the spatial distribution characteristics of the first CE fault data include at least one of the sum of the number of target memory rows (row) where CE faults occur and the number of target memory columns (column) where CE faults occur collected under the first sampling time strategy, the average number of cells where CE faults occur in the target row and target column, and the maximum number of cells where CE faults occur in the target row and target column.

[0029] In the technical solution provided in the present application, the sum of the number of target rows where CE faults occur and the number of target columns where CE faults occur collected within the first sampling window: the target row is the row where the cell where the CE fault occurs is located, and the target column is the column where the cell where the CE fault occurs is located. The sum of the number of target rows and the number of target columns is the spatial distribution feature.

[0030] Average number of cells with CE failures in the target row and target column: The number of cells with CE failures in the target row is a first number, and the number of cells with CE failures in the target column is a second number. The first number and the second number are added together to obtain a first value. The number of cells in the target row and the number of cells in the target column are added together to obtain a second value. The first value is divided by the second value to obtain this spatial distribution feature.

[0031] Maximum number of cells with CE failures in the target row and target column: Count the number of cells with CE failures in each target row and each target column, and determine the maximum number among these counts as the spatial distribution feature.

[0032] In one possible implementation, the address information of the CE fault in the memory is the address of the cell where the CE fault occurs in the memory, and the time distribution characteristics include at least one of the standard deviation of the number of cells where the CE fault occurs in each target row where the CE fault occurs collected under the first sampling time strategy, the standard deviation of the number of cells where the CE fault occurs in each target column where the CE fault occurs collected under the first sampling time strategy, the kurtosis and skew of the number of cells where the CE fault occurs in each target row, the kurtosis and skew of the number of cells where the CE fault occurs in each target column, the error between the number of cells where the CE fault occurs in each target row and the predicted number of cells where the CE fault occurs, and the error between the number of cells where the CE fault occurs in each target column and the predicted number of cells where the CE fault occurs.

[0033] In a second aspect, a device for handling memory failure is provided, the device comprising:

[0034] a data acquisition module, configured to perform correctable error CE fault sampling on the memory according to a first sampling time strategy to obtain CE fault data, wherein the CE fault data includes address information of the CE fault in the memory;

[0035] a fault processing module, configured to perform fault processing on the memory according to the CE fault data;

[0036] The data acquisition module is configured to perform correctable error CE fault sampling on the memory according to the second sampling time strategy, wherein the first sampling time strategy and the second sampling time strategy are different.

[0037] In a possible implementation, the apparatus further includes a sampling strategy formulation module, configured to:

[0038] A second sampling time strategy is determined according to the address information of the CE fault in the memory.

[0039] In a possible implementation, the sampling strategy formulation module is configured to:

[0040] determining a spatial distribution feature of the CE fault data according to the address information of the CE fault in the memory;

[0041] A second sampling time strategy is determined according to the spatial distribution characteristics of the CE fault data.

[0042] In a possible implementation, the sampling strategy formulation module is configured to:

[0043] In the correspondence between the spatial distribution characteristics and the sampling time strategies, a second sampling time strategy corresponding to the spatial distribution characteristics of the CE fault data is queried.

[0044] In a possible implementation, the fault processing module is configured to:

[0045] determining a time distribution feature of the CE fault data according to the address information of the CE fault in the memory;

[0046] Predicting the fault level of each memory cell in the memory according to the temporal distribution characteristics of the CE fault data, the spatial distribution characteristics of the CE fault data, and a fault level prediction model to obtain a predicted fault level of each cell;

[0047] For each cell, fault processing is performed on the cell according to the predicted fault level of the cell.

[0048] In a possible implementation, the fault processing module is configured to:

[0049] Performing dimensionality reduction processing on the spatial distribution characteristics of the CE fault data and the temporal distribution characteristics of the CE fault data to obtain a spatial distribution characteristic after dimensionality reduction and a temporal distribution characteristic after dimensionality reduction;

[0050] The spatial distribution features after dimensionality reduction and the temporal distribution features after dimensionality reduction are input into the fault level prediction model to obtain the predicted fault level of each cell.

[0051] In a possible implementation, the fault processing module is configured to:

[0052] The spatial distribution features of the CE fault data and the temporal distribution features of the CE fault data are input into a feature dimensionality reduction model to obtain the spatial distribution features and the temporal distribution features after dimensionality reduction.

[0053] In a possible implementation, the fault processing module is configured to:

[0054] If the fault corresponding to the predicted fault level of the cell is an uncorrectable error (UCE) fault, the data stored in the cell is migrated to an idle cell with the lowest predicted fault level;

[0055] If the fault corresponding to the predicted fault level of the cell is a CE fault, a self-recovery policy corresponding to the predicted fault level of the cell is called in a recovery policy library to perform fault recovery processing on the cell.

[0056] In one possible implementation, the address information of the CE fault in the memory is the address of the cell where the CE fault occurs in the memory, and the spatial distribution characteristics of the first CE fault data include at least one of the sum of the number of target memory rows (row) where CE faults occur and the number of target memory columns (column) where CE faults occur collected under the first sampling time strategy, the average number of cells where CE faults occur in the target row and target column, and the maximum number of cells where CE faults occur in the target row and target column.

[0057] In one possible implementation, the address information of the CE fault in the memory is the address of the cell where the CE fault occurs in the memory, and the time distribution characteristics include at least one of the standard deviation of the number of cells where the CE fault occurs in each target row where the CE fault occurs collected under the first sampling time strategy, the standard deviation of the number of cells where the CE fault occurs in each target column where the CE fault occurs collected under the first sampling time strategy, the kurtosis and skew of the number of cells where the CE fault occurs in each target row, the kurtosis and skew of the number of cells where the CE fault occurs in each target column, the error between the number of cells where the CE fault occurs in each target row and the predicted number of cells where the CE fault occurs, and the error between the number of cells where the CE fault occurs in each target column and the predicted number of cells where the CE fault occurs.

[0058] In a third aspect, a chip is provided, which includes a logic circuit and a power supply circuit, wherein the power supply circuit is used to power the logic circuit, and the logic circuit is used to execute the memory fault handling method as described in the first aspect and any possible implementation thereof.

[0059] In a fourth aspect, a memory controller is provided, which is connected to a memory in a computing device, and is used to execute the method for handling memory failures as described in the first aspect and any possible implementation thereof.

[0060] In a fifth aspect, a computing device is provided, comprising a processor and a memory, wherein the processor is configured to execute instructions stored in the memory of the device so that the computing device performs the method for handling memory faults as described in the first aspect above and any possible implementation thereof.

[0061] In a sixth aspect, a computer program product comprising instructions is provided, which, when executed by a computing device cluster, enables the computing device to perform the memory fault handling method as described in the first aspect and any possible implementation thereof.

[0062] In the seventh aspect, a computer-readable storage medium is provided, comprising computer program instructions. When the computer program instructions are executed by a computing device, the computing device executes the method for handling memory faults as described in the first aspect and any possible implementation thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 is a structural diagram of a computing device provided in an embodiment of the present application;

[0064] Figure 2 is a structural diagram of a computing device provided in an embodiment of the present application;

[0065] Figure 3 is a schematic diagram of a memory provided in an embodiment of the present application;

[0066] Figure 4 This is a schematic diagram of a sampling time strategy for CE faults provided in an embodiment of the present application;

[0067] Figure 5 This is a schematic diagram of a sampling time strategy for CE faults provided in an embodiment of the present application;

[0068] Figure 6 This is a flowchart of a method for handling memory failures provided by an embodiment of the present application;

[0069] Figure 7This is a flowchart of a method for handling memory failures provided by an embodiment of the present application;

[0070] Figure 8 This is a schematic diagram of the structure of a device for handling memory failures provided in an embodiment of the present application. DETAILED DESCRIPTION

[0071] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0072] An embodiment of the present application provides a method for handling memory failures, which can be implemented by a computing device, which may be a computer, a server, a mobile phone, or the like.

[0073] See also Figure 1 The schematic diagram of the structure of a computing device is shown, which includes a bus 102, a processor 104, a memory 106, a communication interface 108, a memory controller 110, and a memory 112. The processor 104, the memory 106, the communication interface 108, the memory controller 110, and the memory 112 can communicate with each other via the bus 102. It should be understood that this application does not limit the number of processors and memories in the computing device.

[0074] The bus 102 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 1 The fact that only one line is used in the figure does not mean that there is only one bus or only one type of bus. Bus 102 may include a path for transmitting information between various components of computing device 100 (eg, memory 106, processor 104, communication interface 108).

[0075] The processor 104 may include any one or more processors such as a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).

[0076] The memory 106 may include volatile memory, such as random access memory (RAM).

[0077] The memory controller 110 may control the memory 106 and be responsible for data exchange between the memory 106 and the processor 104 . Figure 1 The memory controller 110 and the processor 104 are shown to be separate. In one possible implementation, the memory controller 110 can be integrated into the processor 104, such as Figure 2 The structural relationship between the memory controller and the processor is not limited in the embodiments of the present application.

[0078] The memory 112 may include a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD), or a solid state drive (SSD).

[0079] The memory 112 stores executable program codes, and the processor 104 executes the executable program codes to implement the memory fault handling methods provided in the embodiments of the present application. That is, the memory 112 stores instructions for executing the memory fault handling methods.

[0080] In one possible implementation, the memory fault handling method provided in the embodiment of the present application may be implemented by the memory controller 110 .

[0081] In another possible implementation, the computing device may further include an out-of-band controller 114. In this implementation, the memory fault handling method provided in the embodiment of the present application may be implemented by the out-of-band controller 114. The out-of-band controller may be a baseboard management controller (BMC).

[0082] The communication interface 108 uses a transceiver module such as, but not limited to, a network interface card or a transceiver to implement communication between the computing device 100 and other devices or a communication network.

[0083] During the use of a computer device, its memory may malfunction. Memory failures are categorized as correctable errors (CE) and uncorrectable errors (ECE). CE failures can be recovered by invoking existing self-recovery strategies, while UCE failures cannot be recovered using these strategies. Memory UCE failures can severely impact the reliability and availability of a computing device. Therefore, it is crucial to promptly predict memory failures and implement appropriate strategies to minimize the impact of UCE failures on the computing device.

[0084] See also Figure 3 , shows a schematic diagram of the structure of a memory, such as Figure 3 As shown, the memory may include at least one memory chip, each memory chip includes at least one logic array (bank), each logic array is composed of multiple memory units (cells), cells arranged in the same row form a memory row (row), and cells arranged in the same column form a memory column (column). The address of each cell can be represented by the memory row and memory column in which the cell is located. Figure 3 The cells filled with shaded cells in the middle represent cells where CE faults have occurred. CE fault sampling is performed once every sampling interval at the beginning of each sampling window. At the end of each sampling window, the memory fault condition is predicted based on the CE fault data collected within the sampling window. CE faults in the memory are sampled according to a certain sampling window and sampling interval. Then, based on the collected CE fault data, the memory fault condition is predicted. Then, the corresponding fault handling strategy can be adopted to handle the memory fault.

[0085] See also Figure 4 In the related art, when sampling the CE fault of the memory, the sampling interval and the sampling window length are fixed. In this way, regardless of whether the memory fault is serious or not, sampling is performed according to the same sampling interval and sampling window length. In the case that the memory fault is very minor, the memory will basically not have a serious fault, and the amount of CE fault data required for prediction does not need to be too large. However, due to the fixed sampling interval and sampling window length, a lot of data may still be collected, which will waste more computing resources. In the case that the memory fault is more serious, the memory is likely to have a serious fault, and the amount of CE fault data required for prediction should be as large as possible to improve the accuracy of memory fault prediction. However, due to the fixed sampling interval and sampling window length, the amount of data collected may not be enough to support the accuracy of the prediction, so the prediction accuracy may be low.

[0086] See also Figure 5 Compared with the related art, in the technical solution provided in the present application, the sampling interval and sampling window length to be used next can be dynamically adjusted according to the CE fault data collected in the current sampling window, thereby adjusting the amount of data for the next sampling and making the computing resources used for sampling more reasonable.

[0087] The following describes the memory fault handling method provided by the embodiment of the present application in conjunction with the accompanying drawings. Figure 6 , the method may include the following steps:

[0088] Step 401: Perform CE fault sampling on the memory according to the first sampling time strategy to obtain CE fault data.

[0089] The first sampling time strategy includes a first sampling interval and a first sampling window length.

[0090] In implementation, the computing device collects CE fault data in the memory once every first sampling interval within the first sampling window. The CE fault data includes address information of the CE fault in the memory. The address information of the CE fault may be the address of the cell where the CE fault occurs.

[0091] Here, the first sampling window can be any sampling window in the CE fault sampling process, and the length of the first sampling window is the first sampling window length. If the first sampling window is the first sampling window in the CE fault sampling process, the first sampling window length and the first sampling interval can be pre-configured. If the first sampling window is not the first sampling window in the CE fault sampling process, the first sampling window length can be determined based on the CE fault data collected in the previous sampling window. The specific determination method can refer to the method for determining the second sampling time strategy in step 402 below.

[0092] Step 402: Determine a second sampling time strategy based on the CE fault data.

[0093] The second sampling time strategy includes a second sampling interval and a second sampling window length.

[0094] In implementation, after the first sampling window ends, the computing device may determine a second sampling time strategy based on the CE fault data of the memory collected within the first sampling window.

[0095] This step 402 can be implemented by table lookup, by a neural network model, or by a combination of table lookup and neural network model.

[0096] The above methods are described below by way of example.

[0097] 1. Table Lookup Implementation

[0098] After the first sampling window ends, statistics are collected on the CE fault data collected within the first sampling window to obtain spatial distribution characteristics of the CE fault data. The spatial distribution characteristics of the CE fault data include at least one of the sum of the number of target memory rows and columns with CE faults collected within the first sampling window, the average number of cells with CE faults in the target row and target column, and the maximum number of cells with CE faults in the target row and target column. These spatial distribution characteristics are described below:

[0099] The sum of the number of target rows and columns with CE faults collected within the first sampling window: the target row is the row where the cell with CE fault is located, and the target column is the column where the cell with CE fault is located. The sum of the number of target rows and the number of target columns is the spatial distribution feature.

[0100] Average number of cells with CE failures in the target row and target column: The number of cells with CE failures in the target row is a first number, and the number of cells with CE failures in the target column is a second number. The first number and the second number are added together to obtain a first value. The number of cells in the target row and the number of cells in the target column are added together to obtain a second value. The first value is divided by the second value to obtain this spatial distribution feature.

[0101] Maximum number of cells with CE failures in the target row and target column: Count the number of cells with CE failures in each target row and each target column, and determine the maximum number among these counts as the spatial distribution feature.

[0102] After obtaining the spatial distribution characteristics of CE fault data through statistics, the second sampling time strategy can be determined based on the spatial distribution characteristics of CE fault data. The specific processing can be as follows:

[0103] The computing device may store a correspondence between spatial distribution characteristics and sampling time strategies. Here, the spatial distribution characteristics include the sum of the number of target rows with CE faults and the number of target columns with CE faults collected within the first sampling window, the average number of cells with CE faults in the target row and target column, and the maximum number of cells with CE faults in the target row and target column as an example, as shown in Table 1 below.

[0104] For ease of description, in Table 1, the sum of the number of target memory rows and columns with CE faults collected in the first sampling window is recorded as sum, the average number of cells with CE faults in the target row and target column is avg, and the maximum number of cells with CE faults in the target row and target column is recorded as max.

[0105] Table 1

[0106]

[0107] Sum interval 1 indicates that sum is greater than or equal to sum1 and less than sum2, and sum1 is less than sum2. Sun interval 2 indicates that sum is greater than or equal to sum2 and less than sum3, and sum2 is less than sum3. The same applies to avg intervals, max intervals, and so on. The specific sum ranges represented by sum interval 1, sum interval 2, sum interval 3, etc. can be configured by technicians through experimentation and experience. Similarly, the specific avg range represented by avg intervals and the specific max range represented by max intervals can also be configured by technicians through experimentation and experience. Sampling time strategy 1, sampling time strategy 2, and sampling time strategy 3 corresponding to the spatial distribution characteristics can also be configured by technicians through experimentation and experience.

[0108] The general principle for establishing the correspondence between spatial distribution characteristics and sampling time strategies can be: the larger the sun, avg, and max are, the more serious the possible memory failure is, and more CE failure data needs to be collected. Accordingly, in this case, the longer the sampling window length is, the smaller the sampling interval is. Conversely, the smaller the sun, avg, and max are, the milder the possible memory failure is, and less CE failure data can be collected. Accordingly, in this case, the smaller the sampling window length is, the larger the sampling interval is.

[0109] After determining the spatial distribution characteristics of the CE fault data, the correspondence between the spatial distribution characteristics and the sampling time strategy can be queried to determine the second sampling time strategy corresponding to the spatial distribution characteristics of the CE fault data. For example, if sum is within sum interval 2, avg is within avg interval 2, and max is within max interval 2, then by querying Table 1, sampling time strategy 2 can be determined as the second sampling time strategy to be used.

[0110] In another implementation of the table lookup, the computing device may store a correspondence between spatial distribution characteristics and memory coarse-grained fault levels, as shown in Table 2 below. It may also store a correspondence between memory coarse-grained fault levels and sampling time strategies, as shown in Table 3 below:

[0111] Table 2

[0112] Spatial distribution characteristics Spatial distribution characteristics Spatial distribution characteristics Memory coarse-grained fault level sum interval 1 sum interval 1 sum interval 1 Memory coarse-grained fault level 1 sum interval 2 sum interval 2 sum interval 2 Memory coarse-grained fault level 2 sum interval 3 sum interval 3 sum interval 3 Memory coarse-grained fault level 3 …… …… …… ……

[0113] Table 3

[0114] Memory coarse-grained fault level Sampling time strategy Memory coarse-grained fault level 1 Sampling time strategy 1 Memory coarse-grained fault level 2 Sampling Time Strategy 2 Memory coarse-grained fault level 3 Sampling Time Strategy 3 …… ……

[0115] The memory coarse-grained fault levels may be ranked from high to low as memory coarse-grained fault level 1, memory coarse-grained fault level 2, memory coarse-grained fault level 3, and so on.

[0116] The general principle for establishing the correspondence between spatial distribution characteristics and memory coarse-grained fault levels can be: the larger the sun, avg, and max, the more serious the possible memory fault, and the higher the memory coarse-grained fault level; conversely, the smaller the sun, avg, and max, the milder the possible memory fault, and the lower the memory coarse-grained fault level.

[0117] The general principle for establishing the correspondence between the memory coarse-grained fault level and the sampling time strategy can be as follows: the higher the memory coarse-grained fault level, the more serious the possible memory fault, and more CE fault data needs to be collected. Correspondingly, in this case, the longer the sampling window length, the smaller the sampling interval. Conversely, the lower the memory coarse-grained fault level, the milder the possible memory fault, and less CE fault data can be collected. Correspondingly, in this case, the smaller the sampling window length, the larger the sampling interval.

[0118] After determining the spatial distribution characteristics of the CE fault data, the correspondence between the spatial distribution characteristics and the memory coarse-grained fault level can be queried to determine the target memory coarse-grained fault level corresponding to the spatial distribution characteristics of the CE fault data. Then, the correspondence between the memory coarse-grained fault level and the sampling time strategy is queried to determine the second sampling time strategy corresponding to the target memory coarse-grained fault level. For example, if sum is within sum interval 2, avg is within avg interval 2, and max is within max interval 2, then by querying Table 2, it can be determined that the current memory coarse-grained fault level is memory coarse-grained fault level 2. Then, by querying Table 3, sampling time strategy 2 corresponding to memory coarse-grained fault level 2 is determined as the second sampling time strategy to be used.

[0119] 2. Neural Network Model Implementation

[0120] The sampling time strategy formulation model can be pre-trained through samples, wherein the sampling time strategy formulation model can be a neural network model, and the samples can include input samples and output samples, the input samples are spatial distribution feature samples, and the output samples are sampling time strategy samples, and the input samples and output samples can be obtained by technicians through experiments.

[0121] After determining the spatial distribution characteristics of the CE fault data, the spatial distribution characteristics of the CE fault data are input into the trained sampling time strategy formulation model, and the sampling time strategy formulation model outputs a second sampling time strategy corresponding to the spatial distribution characteristics of the CE fault data.

[0122] 3. Combination of table lookup and neural network model

[0123] A coarse-grained fault level prediction model can be pre-trained through samples, wherein the sampling time strategy formulation model can be a neural network model, and the samples can include input samples and output samples, the input samples are spatial distribution feature samples, and the output samples are memory coarse-grained fault levels, and the input samples and output samples can be obtained by technicians through experiments.

[0124] After determining the spatial distribution characteristics of the CE fault data, the data is input into the trained coarse-grained fault level prediction model, which then outputs a target coarse-grained memory fault level. The correspondence between the coarse-grained memory fault level and the sampling time strategy is then queried to determine the second sampling time strategy corresponding to the target coarse-grained memory fault level.

[0125] Step 403: Perform fault processing on the memory according to the CE fault data.

[0126] In implementation, the fault level of each storage space of a specified memory granularity in the memory can be predicted based on the CE fault data. Then, fault handling can be performed on the storage space based on the fault level of the storage space of each specified memory granularity. The specified memory granularity can be cell, row, column, bank, etc.

[0127] Step 404: Perform CE fault sampling on the memory according to the second sampling time strategy.

[0128] The second sampling time strategy includes a second sampling interval and a second sampling window length.

[0129] In implementation, the computing device collects the CE fault data in the memory once every second sampling interval within the second sampling window, wherein the length of the second sampling window is the second sampling window length.

[0130] In addition, there is no temporal sequence relationship between the above-mentioned step 403 and step 404. The two steps can be executed simultaneously or one after another, and the embodiment of the present application does not limit this.

[0131] The following describes the process of step 403 by taking the memory granularity of cell as an example. Figure 7 , the processing may include the following steps:

[0132] Step 501: Determine the spatial distribution characteristics and the temporal distribution characteristics of the CE fault data according to the address information of the CE fault in the memory.

[0133] In implementation, at the end of the first sampling window, statistics are performed on the CE fault data collected in the first sampling window to obtain spatial distribution characteristics of the CE fault data and temporal distribution characteristics of the CE fault data.

[0134] Among them, the spatial distribution characteristics of CE fault data include at least one of the sum of the number of target rows with CE faults and the number of target memory columns with CE faults collected within the first sampling window, the average number of cells with CE faults in the target row and the target column, and the maximum number of cells with CE faults in the target row and the target column.

[0135] The time distribution characteristics include at least one of the standard deviation of the number of cells with CE failures in each target row within the first sampling window, the standard deviation of the number of cells with CE failures in each target column within the first sampling window, the kurtosis and skew of the number of cells with CE failures in each target row within the first sampling window, the kurtosis and skew of the number of cells with CE failures in each target column within the first sampling window, the error between the number of cells with CE failures in each target row within the first sampling window and the number of cells predicted to have CE failures in the target row, and the error between the number of cells with CE failures in each target column within the first sampling window and the number of cells predicted to have CE failures in the target column.

[0136] The number of cells predicted to have CE failures in the target row refers to the number of cells predicted to have CE failures in the target row based on the CE failure data collected in the previous sampling window. The number of columns predicted to have CE failures in each target column refers to the number of cells predicted to have CE failures in the target column based on the CE failure data collected in the previous sampling window.

[0137] Step 502: According to the temporal distribution characteristics and spatial distribution characteristics of the CE fault data, a fault level prediction is performed on each memory cell in the memory to obtain a predicted fault level of each cell.

[0138] In practice, a neural network model can be used to implement step 502. Specifically, a fault level prediction model can be pre-trained. After obtaining the temporal distribution characteristics and spatial distribution characteristics of the CE fault data, the temporal distribution characteristics and spatial distribution characteristics of the CE fault data are input into the trained fault level prediction model, which then outputs the predicted fault level for each cell.

[0139] In one possible implementation, in order to save computing resources, the temporal distribution characteristics and spatial distribution characteristics of the CE fault data can be first reduced in dimensionality, and the reduced spatial distribution characteristics and reduced temporal distribution characteristics are input into the fault level prediction model, which outputs the predicted fault level of each cell.

[0140] Dimensionality reduction of the temporal and spatial distribution features of CE fault data can be achieved using a neural network model. Specifically, a feature dimensionality reduction model can be pre-trained. After obtaining the temporal and spatial distribution features of the CE fault data, the temporal and spatial distribution features of the CE fault data are input into the trained feature dimensionality reduction model, which then outputs the reduced spatial and temporal distribution features.

[0141] The feature dimensionality reduction model can be a gradient boosting algorithm (Catboost) model. The temporal distribution features and spatial distribution features of the CE fault data are input into the feature dimensionality reduction model. The feature dimensionality reduction model ranks the features from low to high based on their impact on fault level prediction. The top N% of features are then removed to obtain the reduced spatial distribution features and reduced temporal distribution features. The number N can be configured based on actual needs, for example, N = 5.

[0142] Step 503: For each cell, if the fault corresponding to the predicted fault level of the cell is a UCE fault, the data stored in the cell is migrated to an idle cell with the lowest predicted fault level.

[0143] In practice, the lower the predicted fault level, the less severe the fault that may occur in the corresponding cell. Conversely, the higher the predicted fault level, the more severe the fault that may occur in the corresponding cell. The highest predicted fault level indicates that the predicted fault of the cell is a UCE fault. Based on this, for each cell, if the fault corresponding to the predicted fault level of the cell is a UCE fault, the data stored in the cell is migrated to an idle cell with the lowest predicted fault level.

[0144] Step 504: If the fault corresponding to the predicted fault level of the cell is a CE fault, the self-recovery policy corresponding to the predicted fault level of the cell is called in the recovery policy library to perform fault recovery processing on the cell.

[0145] In practice, the recovery strategy library includes the corresponding relationship between fault levels and self-recovery strategies, as shown in Table 4 below:

[0146] Table 4

[0147] Fault level Self-recovery strategy Fault level 1 Self-recovery strategy 1 Fault Level 2 Self-recovery strategy 2 Fault level 3 Self-recovery strategy 3 …… ……

[0148] If the fault corresponding to the predicted fault level of the cell is determined to be a CE fault, the self-recovery strategy corresponding to the predicted fault level of the cell can be determined from the correspondence between the fault level and the self-recovery strategy, and the self-recovery strategy can be called to perform fault recovery processing on the cell.

[0149] In addition, the specified memory granularity can also be a variety of granularities such as cell, row, column, bank, etc. When the specified memory granularity is one or more of the granularities such as row, column, bank, etc., the processing of the above step 403 is basically the same as the processing when the specified memory granularity is cell. The difference is that for different memory granularities, corresponding samples need to be used to train the fault level prediction model.

[0150] The embodiment of the present application also provides a device for processing memory failures, such as Figure 8 As shown, the device includes a data acquisition module 610 and a fault processing module 620, wherein:

[0151] The data acquisition module 610 is configured to perform correctable error CE fault sampling on the memory according to a first sampling time strategy to obtain CE fault data, wherein the CE fault data includes address information of the CE fault in the memory;

[0152] a fault processing module 620, configured to perform fault processing on the memory according to the CE fault data;

[0153] The data collection module 610 is configured to perform correctable error CE fault sampling on the memory according to the second sampling time strategy, wherein the first sampling time strategy and the second sampling time strategy are different.

[0154] In a possible implementation, the apparatus further includes a sampling strategy formulation module, configured to:

[0155] A second sampling time strategy is determined according to the address information of the CE fault in the memory.

[0156] In a possible implementation, the sampling strategy formulation module is configured to:

[0157] determining a spatial distribution feature of the CE fault data according to the address information of the CE fault in the memory;

[0158] A second sampling time strategy is determined according to the spatial distribution characteristics of the CE fault data.

[0159] In a possible implementation, the sampling strategy formulation module is configured to:

[0160] In the correspondence between the spatial distribution characteristics and the sampling time strategies, a second sampling time strategy corresponding to the spatial distribution characteristics of the CE fault data is queried.

[0161] In a possible implementation, the fault processing module 620 is configured to:

[0162] determining a time distribution feature of the CE fault data according to the address information of the CE fault in the memory;

[0163] Predicting the fault level of each memory cell in the memory according to the temporal distribution characteristics of the CE fault data, the spatial distribution characteristics of the CE fault data, and a fault level prediction model to obtain a predicted fault level of each cell;

[0164] For each cell, fault processing is performed on the cell according to the predicted fault level of the cell.

[0165] In a possible implementation, the fault processing module 620 is configured to:

[0166] Performing dimensionality reduction processing on the spatial distribution characteristics of the CE fault data and the temporal distribution characteristics of the CE fault data to obtain a spatial distribution characteristic after dimensionality reduction and a temporal distribution characteristic after dimensionality reduction;

[0167] The spatial distribution features after dimensionality reduction and the temporal distribution features after dimensionality reduction are input into the fault level prediction model to obtain the predicted fault level of each cell.

[0168] In a possible implementation, the fault processing module 620 is configured to:

[0169] The spatial distribution features of the CE fault data and the temporal distribution features of the CE fault data are input into a feature dimensionality reduction model to obtain the spatial distribution features and the temporal distribution features after dimensionality reduction.

[0170] In a possible implementation, the fault processing module 620 is configured to:

[0171] If the fault corresponding to the predicted fault level of the cell is an uncorrectable error (UCE) fault, the data stored in the cell is migrated to an idle cell with the lowest predicted fault level;

[0172] If the fault corresponding to the predicted fault level of the cell is a CE fault, a self-recovery policy corresponding to the predicted fault level of the cell is called in a recovery policy library to perform fault recovery processing on the cell.

[0173] In one possible implementation, the address information of the CE fault in the memory is the address of the cell where the CE fault occurs in the memory, and the spatial distribution characteristics of the first CE fault data include the sum of the number of target memory rows (row) where CE faults occur and the number of target memory columns (column) where CE faults occur collected under the first sampling time strategy, the average number of cells where CE faults occur in the target row and the target column, and at least one of the maximum number of cells where CE faults occur in the target row and the target column.

[0174] In a possible implementation, the address information of the CE fault in the memory is the address of the cell where the CE fault occurs in the memory, and the time distribution characteristics include at least one of the standard deviation of the number of cells where the CE fault occurs in each target row where the CE fault occurs collected under the first sampling time strategy, the standard deviation of the number of cells where the CE fault occurs in each target column where the CE fault occurs collected under the first sampling time strategy, the kurtosis and skew of the number of cells where the CE fault occurs in each target row, the kurtosis and skew of the number of cells where the CE fault occurs in each target column, the error between the number of cells where the CE fault occurs in each target row and the predicted number of cells where the CE fault occurs, and the error between the number of cells where the CE fault occurs in each target column and the predicted number of cells where the CE fault occurs.

[0175] It should be noted that the memory fault handling apparatus provided in the above embodiment only uses the division of the above functional modules as an example to illustrate memory fault handling. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the computing device can be divided into different functional modules to complete all or part of the functions described above. In addition, the memory fault handling apparatus provided in the above embodiment and the memory fault handling method embodiment are based on the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0176] An embodiment of the present application also provides a chip, which includes a logic circuit and a power supply circuit. The power supply circuit is used to supply power to the logic circuit, and the logic circuit is used to execute the memory fault processing method provided in the embodiment of the present application.

[0177] An embodiment of the present application also provides a memory controller, which can be deployed in a computing device. The memory controller is connected to the memory in the computing device and is used to execute the memory fault handling method provided in the embodiment of the present application.

[0178] The present application also provides a computer program product including instructions. The computer program product may be software or a program product including instructions that can be executed on a computing device or stored in any available medium. When the computer program product is executed on at least one computing device, the computer program product causes the at least one computing device to perform a memory fault handling method.

[0179] The present application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that can be stored by a computing device, or a data storage device such as a data center that contains one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive). The computer-readable storage medium includes instructions that instruct the computing device to execute a method for handling memory failures.

[0180] In the embodiments of the present application, "multiple" refers to two or more than two. "At least one of" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can mean: a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0181] In addition, in order to facilitate a clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art will understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit differences. At the same time, in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way for easy understanding.

[0182] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the protection scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for handling memory failure, characterized in that: The method comprises: According to the first sampling time strategy, correctable error CE fault sampling is performed on the memory to obtain CE fault data, wherein the CE fault data includes address information of the CE fault in the memory; Performing fault processing on the memory according to the CE fault data; CE fault sampling is performed on the memory according to a second sampling time strategy, wherein the first sampling time strategy and the second sampling time strategy are different.

2. The method according to claim 1, characterized in that Before performing CE fault sampling on the memory according to the second sampling time strategy, the method further includes: A second sampling time strategy is determined according to the CE fault data.

3. The method according to claim 2, characterized in that Determining a second sampling time strategy according to the CE fault data includes: determining a spatial distribution feature of the CE fault data according to the address information of the CE fault in the memory; A second sampling time strategy is determined according to the spatial distribution characteristics of the CE fault data.

4. The method according to claim 3, characterized in that The determining of the second sampling time strategy according to the spatial distribution characteristics of the CE fault data includes: In the correspondence between the spatial distribution characteristics and the sampling time strategies, a second sampling time strategy corresponding to the spatial distribution characteristics of the CE fault data is queried.

5. The method according to claim 3 or 4, characterized in that The performing fault processing on the memory according to the CE fault data includes: determining a time distribution feature of the CE fault data according to the address information of the CE fault in the memory; Predicting the fault level of each memory cell in the memory according to the temporal distribution characteristics of the CE fault data, the spatial distribution characteristics of the CE fault data, and a fault level prediction model to obtain a predicted fault level of each cell; For each cell, fault processing is performed on the cell according to the predicted fault level of the cell.

6. The method according to claim 5, characterized in that The method of performing a fault level prediction on each memory cell in the memory according to the temporal distribution characteristics of the CE fault data, the spatial distribution characteristics of the CE fault data, and the fault level prediction model to obtain a predicted fault level of each cell includes: Performing dimensionality reduction processing on the spatial distribution characteristics of the CE fault data and the temporal distribution characteristics of the CE fault data to obtain a spatial distribution characteristic after dimensionality reduction and a temporal distribution characteristic after dimensionality reduction; The spatial distribution features after dimensionality reduction and the temporal distribution features after dimensionality reduction are input into the fault level prediction model to obtain the predicted fault level of each cell.

7. The method according to claim 6, characterized in that The performing dimensionality reduction processing on the spatial distribution characteristics of the CE fault data and the temporal distribution characteristics of the CE fault data to obtain the spatial distribution characteristics and the temporal distribution characteristics after dimensionality reduction includes: The spatial distribution features of the CE fault data and the temporal distribution features of the CE fault data are input into a feature dimensionality reduction model to obtain the spatial distribution features and the temporal distribution features after dimensionality reduction.

8. The method according to any one of claims 5 to 7, characterized in that The performing fault processing on the cell according to the predicted fault level of the cell includes: If the fault corresponding to the predicted fault level of the cell is an uncorrectable error (UCE) fault, the data stored in the cell is migrated to an idle cell with the lowest predicted fault level; If the fault corresponding to the predicted fault level of the cell is a CE fault, a self-recovery policy corresponding to the predicted fault level of the cell is called in a recovery policy library to perform fault recovery processing on the cell.

9. A device for handling memory failure, characterized in that: The device comprises: a data acquisition module, configured to perform correctable error CE fault sampling on the memory according to a first sampling time strategy to obtain CE fault data, wherein the CE fault data includes address information of the CE fault in the memory; a fault processing module, configured to perform fault processing on the memory according to the CE fault data; The data acquisition module is configured to perform correctable error CE fault sampling on the memory according to the second sampling time strategy, wherein the first sampling time strategy and the second sampling time strategy are different.

10. A chip, characterized in that: The chip includes a logic circuit and a power supply circuit, wherein the power supply circuit is used to supply power to the logic circuit, and the logic circuit is used to execute the memory fault processing method according to any one of claims 1 to 8.

11. A memory controller, characterized in that: The memory controller is connected to a memory in a computing device, and is configured to execute the memory failure processing method according to any one of claims 1 to 8.

12. A computing device, characterized in that The computing device includes a processor and a memory; The processor is configured to execute instructions stored in a memory of the device, so that the computing device executes the memory failure processing method according to any one of claims 1 to 8.

13. A computer program product comprising instructions, characterized in that When the instruction is executed by a computing device cluster, the computing devices are caused to execute the memory fault handling method according to any one of claims 1 to 8.

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