High-performance real-time range migration correction processor FPGA design system and method

Abstract

The invention discloses a high-performance real-time range migration correction processor FPGA (Field Programmable Gate Array) design system and method, and solves the problem that in the prior art, when a range migration correction engineering implementation scheme based on a CPU (Central Processing Unit), a GPU (Graphic Processing Unit) and a DSP (Digital Signal Processor) is used for processing high-resolution and large-scale data; the problems of performance bottleneck, data transmission limitation, high power consumption, insufficient computing power and flexibility limitation generally exist; the system comprises a control state machine used for reading preset parameters in a data packet header and inputting the preset parameters to a Keystone parameter configuration module; the Keystone parameter configuration module is used for calculating four groups of effective values according to preset parameters and storing the four groups of effective values; the correction module is used for performing calculation according to the input ISAR echo data and the four groups of effective values to obtain echo data after migration correction; according to the system, high-parallelization acceleration of the migration correction module is realized, and the processing speed and efficiency are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of radar signal processing technology, and in particular to a high-performance real-time range migration correction processor FPGA design system and method. Background Art

[0002] The azimuth resolution of ISAR imaging is inversely proportional to the effective cumulative rotation angle of the target. Therefore, increasing the observation angle is a key means of improving resolution and acquiring high-definition images. However, the target's translational and rotational motions are typically coupled, and this coupling effect becomes increasingly pronounced with increasing rotation angle. When the cumulative rotation angle reaches a certain threshold, the enhanced coupling effect causes the range history of a single scattering point to span more than one range resolution unit, triggering the phenomenon of range unit migration (MTRC). Without effective MTRC correction, the advantages of large-angle imaging will be severely limited, resulting in image blur and defocus. Therefore, implementing accurate MTRC compensation is a prerequisite for achieving high-resolution ISAR imaging at large rotation angles.

[0003] There are two main methods for MTRC correction. One is the non-parametric correction based on the Keystone transform. This method can effectively correct linear range migration and does not require prior motion parameters. However, it cannot effectively correct quadratic and higher-order range migration terms introduced by complex rotations. The other is the correction method based on the Polar Format Algorithm (PFA), which can completely correct high-order range migration and azimuth high-order phase errors caused by rotation. However, the application of PFA depends on the precise knowledge of the target's rotation parameters, which is difficult to meet in actual ISAR scenarios.

[0004] In order to solve the problem that the range units between ISAR target pulses move and are not conducive to long-term accumulation, most existing studies use the Keystone transform technology to correct it. The core mechanism of the Keystone transform is to implement a coordinate transformation in the range frequency-slow time domain, that is, to adjust the slow time dimension according to the range frequency, thereby decoupling the range and Doppler information. This process makes it possible to accumulate coherent data for a longer time, which is crucial for obtaining high-resolution and high signal-to-noise ratio ISAR images. In actual engineering applications, there are two main technical approaches to implement the Keystone transform for discrete slow-time sampling data: the DFT+IFFT-based method and the SINC interpolation-based method [7]. When the number of range frequency units and the number of azimuth pulses are large, the DFT+IFFT method has the highest computational complexity, followed by the SINC interpolation method. The specific implementation process is as follows: Cross-range unit migration correction based on DFT+IFFT: This method primarily implements the Keystone transform based on the Discrete Fourier Transform (DFT). First, a Fast Fourier Transform (FFT) is performed on the ISAR echo data along the fast time dimension, mapping the data into the range-frequency-slow time domain. Subsequently, a second FFT is applied to the slow time series of each range-frequency channel, converting it into the joint range-frequency-Doppler frequency domain. Next, the core correction steps of the Keystone transform are implemented in the joint domain: First, the data is multiplied by a precisely calculated complex phase factor that depends on both the range frequency and the Doppler frequency to achieve a scaled coordinate system. The data is then reconstructed in the rescaled coordinate plane to eliminate the coupling term between range migration and Doppler frequency. Finally, an Inverse Fast Fourier Transform (IFFT) is performed along the Doppler frequency dimension to transform the data back into the range-frequency domain. This process effectively corrects the slow-time axis of the data, thereby compensating for linear range migration. GPUs, based on parallel programming frameworks like CUDA, can efficiently handle large-scale parallel computing tasks, significantly improving the computational speed of range-correction algorithms and significantly reducing computation time. However, in practical applications, the limited bandwidth of the data path between the CPU and GPU reduces the GPU's acceleration effect. Furthermore, the GPU's high-performance computing comes at the cost of high energy consumption and heat generation, posing a significant challenge for platforms with extremely limited power budgets and cooling space, such as airborne and onboard systems.

[0005] Cross-range bin migration correction based on SINC interpolation: This method also first performs a fast Fourier transform on the radar echo pulse train along the fast time dimension, transforming the data into the range-frequency-slow time domain. Unlike strategies based on DFT+IFFT, the core mechanism of the SINC interpolation method lies in directly performing frequency-dependent resampling of the slow time dimension. In practice, this resampling process is accomplished by applying a SINC interpolation kernel function. For each discrete range-frequency bin, the algorithm accurately calculates the signal sample value at the correspondingly scaled slow time coordinate based on the bin's frequency value. This targeted, range-frequency-dependent rescaling of the slow time axis effectively compensates for the target's linear range migration error.

[0006] The implementation strategy and performance of the Keystone transform for range migration correction are highly dependent on the selected hardware platform, commonly including the central processing unit (CPU), graphics processing unit (GPU), and digital signal processor (DSP). However, these solutions have their own limitations when faced with large-scale echo data, high real-time requirements, and low cost and power consumption. CPU-based engineering technology for range migration correction: CPU design focuses on general-purpose computing and serial task processing. Its limited core count and architectural characteristics make it difficult to efficiently handle the massively parallel computing requirements inherent in range migration correction algorithms. Especially in high-resolution, high-data-volume scenarios, CPUs struggle to process massive amounts of data concurrently, resulting in excessively long execution times for range migration correction algorithms, making them unable to meet the real-time requirements of many ISAR applications.

[0007] Existing technologies use multi-core DSPs to implement the Keystone transform. By increasing the number of processor cores, this approach improves parallel processing capabilities to a certain extent, speeding up the numerous interpolation and data rearrangement operations involved in the Keystone transform. However, each DSP core is still essentially a processor that executes instructions sequentially. Even with multiple cores, the number of data streams it can process simultaneously and the flexibility of concurrent operations are far inferior to hardware-level parallel architectures.

[0008] In summary, existing CPU, GPU, and DSP-based range motion correction engineering implementations generally suffer from performance bottlenecks, data transmission limitations, high power consumption, insufficient computing power, and limited flexibility when processing high-resolution, large-scale data. Summary of the Invention

[0009] The present invention provides a high-performance real-time range motion correction processor FPGA design system and method, which solves the problems of performance bottlenecks, data transmission limitations, high power consumption, insufficient computing power, and limited flexibility commonly encountered in existing CPU, GPU, and DSP-based range motion correction engineering implementation solutions when processing high-resolution and large-scale data. It achieves highly parallelized acceleration of the motion correction module and significantly improves processing speed and efficiency.

[0010] In a first aspect, the present invention provides a high-performance real-time range migration correction processor FPGA design system, the system comprising: A control state machine is used to read the preset parameters in the data packet header and input the preset parameters into the Keystone parameter configuration module; A Keystone parameter configuration module, configured to calculate four sets of valid values ​​according to the preset parameters and save the four sets of valid values; The correction module is used to perform calculations based on the input ISAR echo data and the four groups of effective values ​​to obtain the echo data after migration correction.

[0011] In conjunction with the first aspect, in one possible implementation, the Keystone parameter configuration module includes: a level 1 computing core, a level 2 computing core, and a cache core; The step of calculating four sets of valid values ​​according to the preset parameters and saving the four sets of valid values ​​includes: The level 1 computing core calculates the preset parameters through five built-in computing cores to obtain multiple configuration parameters; The level 2 computing core calculates the multiple configuration parameters through four built-in computing cores to obtain four sets of valid values; The cache core caches the four groups of valid values ​​respectively through four groups of cache areas.

[0012] In conjunction with the first aspect, in one possible implementation, the level 1 computing core calculates the preset parameters using five built-in computing cores to obtain multiple configuration parameters, including: According to the number of azimuth pulses in the preset parameters and the number of sampling points in the distance direction Calculate the CZT transformation length ; Among them, CZT transformation length To satisfy A minimum integer that satisfies the condition and is an integer power of 2; According to the number of azimuth pulses in the preset parameters and radar signal bandwidth , calculate the distance-to-frequency coordinates ; According to the radar signal carrier frequency in the preset parameters and the number of sampling points in the distance direction , calculate the unit circle non-conformal sampling coordinates ; According to the preset parameters Determine the coordinates of the first constant system ; According to the preset parameters and Determine the coordinates of the second constant system ; The CZT conversion length , distance-direction equal-frequency coordinates , unit circle non-conformal sampling coordinates , the first constant system coordinates and the second constant system coordinates As multiple configuration parameters.

[0013] In conjunction with the first aspect, in one possible implementation, the level 2 computing core calculates the multiple configuration parameters using four built-in computing cores to obtain four sets of valid values, including: According to the first constant coordinate system among the multiple configuration parameters and the second constant system coordinates , calculate and obtain the first effective value, the second effective value and the third effective value; Non-conformal sampling of unit circle coordinates in multiple configuration parameters Perform complex exponential operation to obtain the fourth effective value; The first effective value, the second effective value, the third effective value and the fourth effective value are taken as four groups of effective values.

[0014] In conjunction with the first aspect, in one possible implementation, the correction module includes: an input buffer core, a complex exponential calculation core, a complex multiplication operation core, a zero-padding operation core, an FFT operation core, an IFFT operation core, an H matrix cache core, and a Y matrix cache core; The calculation is performed based on the input ISAR echo data and the four groups of effective values ​​to obtain the echo data after migration correction, including: The input buffer core is used to extract valid data segments from the input ISAR echo data to obtain valid radar data, and simultaneously read four groups of valid values ​​in the Keystone parameter configuration module; The complex exponential calculation core is configured to perform a complex exponential operation on the four groups of effective values ​​according to three identical CORDIC IP cores to obtain a first complex exponential operation result, a second complex exponential operation result, and a third complex exponential operation result; and to concatenate the first complex exponential operation result and the third complex exponential operation result to obtain a concatenated sequence; The Y matrix cache core is used to cache the spliced ​​sequence; The complex multiplication operation core is used to perform a complex multiplication operation on the effective radar data and the second complex exponential operation result to obtain a complex multiplication result; The zero-padding operation core is used to add zero values ​​to both ends of the complex multiplication result to obtain a complex multiplication sequence; The H matrix cache core is used to cache the complex multiplication sequence; The FFT operation core is used to use the FFT IP core integrated in the FPGA to perform the complex multiplication sequence and the splicing sequence. FFT of the points to obtain the first operation result; The IFFT operation core is used to use the read first complex exponential operation result as a weight, perform migration correction on the first operation result, and obtain echo data after migration correction.

[0015] With reference to the first aspect, in a possible implementation manner, the complex multiplied sequence and the concatenated sequence are equal in length.

[0016] In a second aspect, the present invention provides a high-performance real-time range migration correction processor FPGA design method, the method comprising: Analyze the preset parameters of input ISAR echo data; Calculate and cache four sets of valid values ​​according to the preset parameters; The input ISAR echo data is processed by range unit, and the migration correction of the input ISAR echo data is implemented by using the four groups of effective values ​​through complex exponential calculation, zero padding, FFT, and IFFT to obtain the migration-corrected echo data.

[0017] In conjunction with the second aspect, in one possible implementation, processing the input ISAR echo data by range unit, using the four sets of effective values ​​to perform migration correction on the input ISAR echo data through complex exponential calculation, zero padding, FFT, and IFFT to obtain the migration-corrected echo data, includes: Extract valid data segments from the input ISAR echo data to obtain valid radar data; Performing a complex exponential operation on the four groups of effective values ​​to obtain a first complex exponential operation result, a second complex exponential operation result, and a third complex exponential operation result; splicing the first complex exponential operation result and the third complex exponential operation result to obtain a spliced ​​sequence, and caching the spliced ​​sequence; performing a complex multiplication operation on the valid radar data and the second complex exponential operation result to obtain a complex multiplication result; adding zero values ​​to both ends of the complex multiplication result to obtain a complex multiplication sequence, and caching the complex multiplication sequence; The FFT IP core integrated in FPGA is used to perform the multiplication and concatenation of the complex sequence and the concatenation sequence. FFT of the points to obtain the first operation result; The first complex exponential operation result is used as a weight, and migration correction is performed on the first operation result to obtain echo data after migration correction.

[0018] One or more technical solutions provided in the present invention have at least the following technical effects or advantages: The present invention realizes the automatic reading and transmission of data packet header parameters by adopting a state machine control module, avoiding the inefficiency and error risks of traditional manual configuration, and significantly improving the system response speed and processing consistency; the Keystone parameter configuration module pre-calculates and saves four sets of effective values, completing complex calculations (such as interpolation or phase compensation parameters required for range migration correction) in advance, reducing the computational burden during real-time processing; the correction module directly uses pre-calculated optimized parameters to process ISAR echo data, reducing approximate errors in real-time calculations, and making the migration correction more accurate, especially for high-speed targets or scenes with large accumulation angles. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Module diagram of the FPGA design system for a high-performance real-time range migration correction processor provided by an embodiment of the present invention; Figure 2 This is an image of the imaging result before migration correction provided by an embodiment of the present invention; Figure 3 MATLAB migration correction operation result diagram provided by an embodiment of the present invention; Figure 4 FPGA migration calibration operation result diagram provided by an embodiment of the present invention; Figure 5 A one-dimensional range image comparison diagram provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0021] In the first aspect, the present invention provides a high-performance real-time range migration correction processor FPGA design system, see Figure 1 ,The system includes: a control state machine, a Keystone parameter ,configuration module and a correction module.

[0022] The control state machine is used to read the preset parameters in the data packet header and input the preset parameters into the Keystone parameter configuration module; For example, in step 1, the ISAR echo data is transmitted to the FPGA development board, and the control state machine first reads the number of azimuth pulses in the data packet header. , number of sampling points in distance direction , radar signal bandwidth and radar signal carrier frequency Four preset parameters are passed to the Keystone parameter configuration module.

[0023] The Keystone parameter configuration module is used to calculate four sets of valid values ​​based on preset parameters and save the four sets of valid values; Specifically, the Keystone parameter configuration module includes: level 1 computing core, level 2 computing core, and cache core; In the Keystone parameter configuration module, four sets of valid values ​​are calculated based on the preset parameters and saved, including: (1) The level 1 computing core calculates the preset parameters through five built-in computing cores to obtain multiple configuration parameters; Here, the Level 1 computing core calculates the preset parameters through five built-in computing cores to obtain multiple configuration parameters, including: (1.1) According to the number of azimuth pulses in the preset parameters and the number of sampling points in the distance direction Calculate the CZT transformation length ; Among them, CZT transformation length To satisfy A minimum integer that satisfies the condition and is an integer power of 2; (1.2) According to the number of azimuth pulses in the preset parameters and radar signal bandwidth , use the interval calculation formula to calculate the distance-to-frequency coordinates ; Among them, the interval calculation formula is expressed as: ; (1.3) According to the radar signal carrier frequency in the preset parameters and the number of sampling points in the distance direction , the non-conformal sampling coordinates of the unit circle are calculated using the sampling interval coordinate calculation formula ; Among them, the sampling interval coordinate calculation formula is expressed as: ; (1.4) According to the preset parameters Determine the coordinates of the first constant system ; (1.5) According to the preset parameters and Determine the coordinates of the second constant system ; (1.6) Convert CZT to length , distance-direction equal-frequency coordinates , unit circle non-conformal sampling coordinates , the first constant system coordinates and the second constant system coordinates As multiple configuration parameters.

[0024] (2) The Level 2 computing core calculates multiple configuration parameters through four built-in computing cores to obtain four sets of effective values; Here, the Level 2 computing core calculates multiple configuration parameters through four built-in computing cores to obtain four sets of valid values, including: (2.1) According to the first constant system coordinates among multiple configuration parameters and the second constant system coordinates , calculate and obtain the first effective value, the second effective value and the third effective value; (2.2) Non-conformal sampling coordinates of the unit circle in multiple configuration parameters Perform complex exponential operation to obtain the fourth effective value; (2.3) The first effective value, the second effective value, the third effective value and the fourth effective value are taken as four groups of effective values.

[0025] (3) The cache core caches four groups of valid values ​​through four groups of cache areas.

[0026] (4) a correction module, which is used to calculate the input ISAR echo data and four sets of effective values ​​to obtain the echo data after migration correction; Here, the correction module includes: an input buffer core, a complex exponential calculation core, a complex multiplication operation core, a zero-filling operation core, an FFT operation core, an IFFT operation core, an H matrix cache core, and a Y matrix cache core; In the correction module, calculations are performed based on the input ISAR echo data and four sets of effective values ​​to obtain the echo data after migration correction, including: (4.1) Input buffer core, used to extract valid data segments from the input ISAR echo data to obtain valid radar data, and at the same time read the four sets of valid values ​​in the Keystone parameter configuration module; (4.2) A complex exponential calculation core, configured to perform complex exponential calculations on the four sets of effective values ​​using three identical CORDIC IP cores, obtaining a first complex exponential calculation result, a second complex exponential calculation result, and a third complex exponential calculation result; and concatenating the first complex exponential calculation result and the third complex exponential calculation result to obtain a concatenated sequence; (4.3) Y matrix cache core, used to cache the spliced ​​sequence; (4.4) a complex multiplication operation core, configured to perform a complex multiplication operation based on the valid radar data and the second complex exponential operation result to obtain a complex multiplication result; (4.5) The zero-padding operation core is used to add zero values ​​to both ends of the complex multiplication result to obtain a complex multiplication sequence; here, the length of the complex multiplication sequence is equal to the length of the splicing sequence.

[0027] (4.6) H matrix cache core, used to cache the complex multiplication sequence; (4.7) FFT operation core, used to use the FFT IP core integrated in FPGA to perform complex multiplication sequence and splicing sequence FFT of the points to obtain the first operation result; (4.8) An IFFT operation core is used to use the read first complex exponential operation result as a weight, perform migration correction on the first operation result, and obtain echo data after migration correction.

[0028] For example, the Keystone parameter configuration module consists of three parts: the level 1 computing core, the level 2 computing core, and the cache core. After the preset parameters enter the module, the preset parameters will first enter the level 1 computing core, and the five computing cores built into the level 1 computing core will calculate the CZT transformation length in parallel. , distance-direction equal-frequency coordinates , unit circle non-conformal sampling coordinates , the first constant system coordinates and the second constant system coordinates Five configuration parameters. Among them, To satisfy The smallest positive integer that satisfies the condition and is an integer power of 2; is equally spaced Point span distance unit frequency coordinate value, interval is ; is a non-uniformly spaced distribution on the unit circle The point sampling interval coordinate value is defined as ; is a constant coefficient coordinate, defined as ; Also a constant coefficient coordinate, defined as After the calculation is completed, the calculation result enters the level 2 calculation core and proceeds to step 3.

[0029] Step 3: The 2nd level computing core has 4 built-in computing cores, which use the output of the 1st level computing core as input and calculate in parallel. Four groups of valid values. They are defined as the first valid value , second effective value and the third effective value . Output for level 1 computing core The corresponding fourth effective value (complex exponential value) is defined as The four sets of values ​​in the Level 2 calculation core only need to be calculated once, before the ISAR echo data arrives. When the calculation results are valid, they are stored in the cache core and transferred to step 4. It should be noted that the term "valid" mentioned here and in the following article refers to the ability to be calculated.

[0030] Step 4: The cache core pre-allocates 4 groups of cache areas. When the output results of the 4 computing cores built into the 2nd level computing core are valid, they are accessed to these 4 groups of cache areas respectively. At this point, the Keystone parameter configuration module is complete, ISAR echo data is allowed to enter, and the system enters a waiting state. When the ISAR echo data input is valid, the correction module is executed and the process proceeds to step 5.

[0031] Step 5: The correction module includes: input buffer core, complex exponential calculation core, complex multiplication operation core, zero padding operation core, FFT operation core, IFFT operation core, H matrix cache core and Y matrix cache core. When the ISAR echo data input valid time arrives, the input data is first connected to the input buffer core for buffering. The buffer core is FIFO. At the same time, the first distance unit corresponding to the pre-calculated first distance unit in the buffer core of the parameter calculation module is read. Value and Sequence. Read The value is a complex number, denoted by , Three fixed groups Point coefficient sequence, connect the read value to the complex exponential calculation core, and go to step 6.

[0032] Step 6: The complex exponential calculation core integrates three identical CORDIC IP cores to perform three different sets of complex exponential operations: .exist When the operation result output is valid, the two are spliced ​​into a spliced ​​sequence. In the first half, In the second half, the splicing result is directly connected to the Y matrix cache core. When the operation result is output, the first ISAR echo data in the input buffer core of step 5 is synchronously read out, and the two are connected to the complex multiplication operation core to enter step 7.

[0033] Step 7: Enter the ISAR echo data of the complex multiplication core and For complex exponential sequences, use the FPGA's internal multiplier and adder resources to perform complex multiplication. Connect the complex multiplication result to the zero-padding core and proceed to step 8.

[0034] Step 8: Add zero padding to both ends of the data entering the zero padding core. The number of zero values ​​makes the length of the sequence reach . Connect the zero-padded complex multiplication sequence to the H matrix cache core. Go to step 9.

[0035] Step 9: When the data lengths in the Y matrix cache core and the H matrix cache core both reach When , the concatenation operation in step 6 and the zero-padding operation in step 7 for the first ISAR echo data are completed. At this point, two sequences are read from the two matrix buffer cores, named Y sequence and H sequence respectively. These two sequences are connected to the FFT operation core, and the process proceeds to step 10.

[0036] Step 10: After the Y sequence and H sequence enter the FFT operation core, the FFT IP core integrated in the FPGA is used to perform The corresponding frequency domain data is obtained by performing FFT of the number of points, and then connected to the complex multiplication operation core. After obtaining the complex multiplication operation results of the two sets of frequency domain data, the operation results are connected to the IFFT operation core, and then go to step 11.

[0037] Step 11: After the results of the two sets of frequency domain data multiplication enter the IFFT operation core, the IFFT IP core integrated in the FPGA is used to perform IFFT of the number of points, The cache data read signal is triggered synchronously with the effective reading of the IFFT output result, and the read As weight (length is ) and the IFFT result The data are multiplied to obtain the echo data after migration correction with the same dimension as the initial input data. This data is the first correction result of the range migration correction module.

[0038] Step 12: The ISAR echo data of each range unit performs the above steps 5-11 in sequence until All the range frequency units complete the range migration correction, the iteration is terminated, and the correction is completed.

[0039] In a specific embodiment provided by the present invention, the above-designed system is designed based on the following algorithm.

[0040] Assume that the baseband signal transmitted by the radar is A series of pulse signals: (1) in, For full time, is an integer, , is the number of sampling points in the range direction (the total number of pulses emitted during one scan), is the pulse repetition period, is an imaginary unit, is the center frequency of the transmitted signal, is a linear frequency modulated pulse, defined as follows: (2) in, is the pulse width, To adjust the frequency, is a rectangular window function.

[0041] Assume the target radial velocity is , the instantaneous distance of the target at this time , then the radar receives the The baseband echo signal of a pulse is: (3) in, represents the slope distance at time zero, is the radial velocity of the target relative to the radar. When the target approaches the radar, is a negative value; otherwise, Is a positive value. For quick time, For slow time, is a constant that depends on the scattering intensity, is the receiver noise, which is assumed to be Gaussian white noise.

[0042] Performing Fourier transform on the baseband echo signal in the fast time domain yields: (4) Use a signal with the same initial frequency as the transmitted signal Modulation frequency The linear frequency modulation signal of is used as the reference signal, and the difference frequency processing is performed between this signal and the received signal described in formula 4 to realize range pulse compression. The spectrum of the obtained range compression signal is expressed as: (5) It can be seen from Equation 5 that the fast time frequency and slow time variables There is coupling in the second exponential phase term. This coupling is manifested in the time domain as: different slow times After range compression, the peak positions of the corresponding pulse echoes shift relative to each other. Consequently, the energy of each pulse echo is distributed within different range resolution bins, a phenomenon known as range bin migration. Over long coherent integration times, this range migration effect can become significant, causing the target energy to span multiple range resolution bins, thereby affecting ISAR imaging. Therefore, effective range migration correction is essential.

[0043] The Keystone transform can effectively remove fast time frequencies by remapping the coordinates in the frequency domain. and slow time variables The linear coupling relationship between them is achieved, so that the target energy corresponding to different slow times is focused into the same distance unit, realizing range migration correction. The specific principle is as follows. First, the following variable substitution is introduced: (6) in, is the transformation coefficient, is the constructed virtual slow time coordinate.

[0044] After transformation, the original The rectangular area of ​​the plane becomes The trapezoidal area of ​​the inverted plane. Substituting Equation 6 into Equation 5, we get: (7) Obviously, after the variable substitution, in the new coordinate plane, the fast time frequency and slow time variables There is no longer a linear coupling relationship, which indicates that the range cell migration has been effectively corrected.

[0045] Theoretically, the Keystone transform is a scale transformation of slow time in the continuous domain. However, in digital signal processing, after the signal is discretized, the discrete slow time required by Keystone is To virtual slow time The coordinate transformation of is a nonlinear mapping relationship. This leads to non-uniform resampling of the spectrum, and thus the efficient FFT algorithm cannot be directly applied. If this non-uniform resampling is achieved by DFT point-by-point calculation, its The computational complexity is too high to meet the requirements of real-time engineering applications.

[0046] To solve the above computational efficiency issues, this paper uses the CZT-RCMC algorithm to implement the spectrum resampling required by the Keystone transform. The specific derivation process of the algorithm is detailed as follows: against point signal ,That Transform Provides frequency domain information, which Transformed into: (8) Unlike DFT’s uniform sampling on the unit circle, CZT-RCMC can calculate Point discrete signal Z transform A series of specific sampling points on the Z plane The value at that point, that is, CZT-RCMC allows the sampling points to be distributed on a more general contour, and each sampling point The definition is as follows: (9) in, is the number of sampling points in the distance direction, is the starting point of CZT, Is the starting sampling point The length of the vector radius, Is the starting sampling point The phase angle; is the sampling path, is the stretch rate of the sampling curve, is the angle difference between two adjacent sampling points. When, with The increase in value, will be To fix the length of the outward spiral, when When, with The increase in value, will be It is a fixed long inward spiral.

[0047] The sampling point Substitution Transform the formula to obtain The CZT-RCMC results of the points are: (10) When the conditions in the following formula 11 are met, each sampling point in the CZT-RCMC algorithm Will be evenly spaced on the unit circle: (11) Substituting Equation 11 into Equation 10, we get The CZT-RCMC transformation result is: (12) in, represents convolution, , , .

[0048] From the above expression, we can see that its core contains a convolution operation. According to the convolution theorem, the CZT-RCMC operation can be efficiently implemented by FFT. Therefore, CZT-RCMC under the above specific conditions can be used instead of DFT to efficiently complete the spectrum non-uniform resampling required by Keystone transform to correct range migration. The computational complexity of CZT-RCMC is dominated by FFT, and its complexity is close to (in is the length of the FFT to be performed), which is much shorter than that required to directly compute the non-uniform DFT Therefore, the Keystone implementation based on CZT-RCMC significantly improves the computational efficiency of the range migration correction algorithm.

[0049] In a second aspect, the present invention provides a high-performance real-time range migration correction processor FPGA design method, which includes the following steps S101 to S103.

[0050] S101 analyzes preset parameters of input ISAR echo data; S102, calculating and caching four sets of valid values ​​according to preset parameters; S103 , processing the input ISAR echo data range-by-range unit, and implementing migration correction on the input ISAR echo data by using four groups of effective values ​​through complex exponential calculation, zero padding, FFT, and IFFT to obtain migration-corrected echo data.

[0051] Specifically, in step S103, the input ISAR echo data is processed range-by-range unit, and the input ISAR echo data is subjected to migration correction using four sets of effective values ​​through complex exponential calculation, zero padding, FFT, and IFFT to obtain the migration-corrected echo data, including: S1031, extracting valid data segments from the input ISAR echo data to obtain valid radar data; S1032, performing a complex exponential operation on the four groups of effective values ​​to obtain a first complex exponential operation result, a second complex exponential operation result, and a third complex exponential operation result; S1033, concatenating the first complex exponential operation result and the third complex exponential operation result to obtain a concatenated sequence, and caching the concatenated sequence; S1034, performing a complex multiplication operation on the valid radar data and the second complex exponential operation result to obtain a complex multiplication result; S1035, adding zero values ​​to both ends of the complex multiplication result to obtain a complex multiplication sequence, and caching the complex multiplication sequence; S1036, using the FFT IP core integrated in the FPGA to perform complex multiplication sequence and splicing sequence FFT of the points to obtain the first operation result; S1037 , using the first complex exponential operation result as a weight, performing migration correction on the first operation result to obtain echo data after migration correction.

[0052] For example, to verify the correctness of the system designed in the present invention, the ISAR echo data of the aircraft target was first generated by MATLAB simulation. For specific ISAR echo data, please refer to Figure 2 , set the number of distance units , pulse number Then, the FPGA distance migration correction processing results are compared with the reference processing results of MATLAB. Figure 3 and Figure 4 As shown, the range unit migration phenomenon is effectively corrected. Figure 5 The one-dimensional range images obtained after processing by the two strategies were compared. The results showed that the processing effect of FPGA was highly consistent with the MATLAB benchmark, indicating that the accuracy error introduced by FPGA implementation was extremely small, verifying that the processing accuracy of the architecture met the design requirements.

[0053] As shown in Table 1, when processing 512 frequency points, the FPGA acceleration architecture customized for the CZT-RCMC algorithm in this paper only requires 10.128ms at a single degree of parallelism, compared to approximately 65.583ms required by a CPU, achieving a nearly 6x speedup. Furthermore, this FPGA architecture supports adjustable parallelism. Increasing the degree of parallelism effectively reduces processing time while increasing resource consumption. As shown in Table 1, when the degree of parallelism is increased to 8, the speedup reaches nearly 80x. This parallel acceleration significantly improves computational efficiency, and its advantages are particularly prominent when processing large-scale datasets.

[0054] Table 1 Summary of CZT-RCMC performance on different hardware platforms

[0055] The system provided by the present invention can effectively correct cross-distance unit migration errors while maintaining low computational complexity. The present invention achieves highly parallelized and low-latency processing of the cross-distance unit migration algorithm. Results show that compared with CPU platforms, the system achieves higher parallelism and faster processing speeds, while compared with GPU platforms, it achieves greater throughput and improved energy efficiency. The system designed by the present invention is highly flexible and scalable, and can be easily configured into different test modes. In addition to being used to verify the cross-distance unit migration function of the present invention, it can also be widely used for hardware acceleration and performance evaluation of other digital signal processing algorithms.

[0056] The various embodiments in this specification are described in a progressive manner. References to the same or similar parts between the various embodiments are sufficient. Each embodiment focuses on the differences from other embodiments. All or part of the present invention can be used in a variety of general or specialized computer system environments or configurations. For example, personal computers, server computers, handheld or portable devices, tablet devices, mobile communication terminals, multiprocessor systems, microprocessor-based systems, programmable electronic devices, network PCs, minicomputers, mainframe computers, and distributed computing environments that include any of the above systems or devices.

[0057] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it should be understood by those skilled in the art that the technical solutions described in the aforementioned embodiments may still be modified, or some or all of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the present invention.

Claims

1. A high-performance real-time range migration correction processor FPGA design system, characterized by: include: A control state machine is used to read the preset parameters in the data packet header and input the preset parameters into the Keystone parameter configuration module; A Keystone parameter configuration module, configured to calculate four sets of valid values ​​according to the preset parameters and save the four sets of valid values; The correction module is used to perform calculations based on the input ISAR echo data and the four groups of effective values ​​to obtain the echo data after migration correction.

2. The high-performance real-time range migration correction processor FPGA design system according to claim 1, characterized in that: The Keystone parameter configuration module includes: a level 1 computing core, a level 2 computing core, and a cache core; The step of calculating four sets of valid values ​​according to the preset parameters and saving the four sets of valid values ​​includes: The level 1 computing core calculates the preset parameters through five built-in computing cores to obtain multiple configuration parameters; The level 2 computing core calculates the multiple configuration parameters through four built-in computing cores to obtain four sets of valid values; The cache core caches the four groups of valid values ​​respectively through four groups of cache areas.

3. The high-performance real-time range migration correction processor FPGA design system according to claim 2, characterized in that: The level 1 computing core calculates the preset parameters using five built-in computing cores to obtain multiple configuration parameters, including: According to the number of azimuth pulses in the preset parameters and the number of sampling points in the distance direction Calculate the CZT transformation length ; Among them, CZT transformation length To satisfy A minimum integer that satisfies the condition and is an integer power of 2; According to the number of azimuth pulses in the preset parameters and radar signal bandwidth , calculate the distance-to-frequency coordinates ; According to the radar signal carrier frequency in the preset parameters and the number of sampling points in the distance direction , calculate the unit circle non-conformal sampling coordinates ; According to the preset parameters Determine the coordinates of the first constant system ; According to the preset parameters and Determine the coordinates of the second constant system ; The CZT conversion length , distance-direction equal-frequency coordinates , unit circle non-conformal sampling coordinates , the first constant system coordinates and the second constant system coordinates As multiple configuration parameters.

4. The high-performance real-time range migration correction processor FPGA design system according to claim 2, characterized in that: The Level 2 computing core calculates the multiple configuration parameters using four built-in computing cores to obtain four sets of valid values, including: According to the first constant coordinate system among the multiple configuration parameters and the second constant system coordinates , calculate and obtain the first effective value, the second effective value and the third effective value; Non-conformal sampling of unit circle coordinates in multiple configuration parameters Perform complex exponential operation to obtain the fourth effective value; The first effective value, the second effective value, the third effective value and the fourth effective value are taken as four groups of effective values.

5. The high-performance real-time range migration correction processor FPGA design system according to claim 1, characterized in that: The correction module includes: an input buffer core, a complex exponential calculation core, a complex multiplication operation core, a zero-filling operation core, an FFT operation core, an IFFT operation core, an H matrix cache core, and a Y matrix cache core; The calculation is performed based on the input ISAR echo data and the four groups of effective values ​​to obtain the echo data after migration correction, including: The input buffer core is used to extract valid data segments from the input ISAR echo data to obtain valid radar data, and simultaneously read four groups of valid values ​​in the Keystone parameter configuration module; The complex exponential calculation core is configured to perform a complex exponential operation on the four groups of effective values ​​according to three identical CORDIC IP cores to obtain a first complex exponential operation result, a second complex exponential operation result, and a third complex exponential operation result; and to concatenate the first complex exponential operation result and the third complex exponential operation result to obtain a concatenated sequence; The Y matrix cache core is used to cache the spliced ​​sequence; The complex multiplication operation core is used to perform a complex multiplication operation on the effective radar data and the second complex exponential operation result to obtain a complex multiplication result; The zero-padding operation core is used to add zero values ​​to both ends of the complex multiplication result to obtain a complex multiplication sequence; The H matrix cache core is used to cache the complex multiplication sequence; The FFT operation core is used to use the FFT IP core integrated in the FPGA to perform the complex multiplication sequence and the splicing sequence. FFT of the points to obtain the first operation result; The IFFT operation core is used to use the read first complex exponential operation result as a weight, perform migration correction on the first operation result, and obtain echo data after migration correction.

6. The high-performance real-time range migration correction processor FPGA design system according to claim 3, characterized in that: The length of the complex multiplied sequence is equal to that of the concatenated sequence.

7. A high-performance real-time range migration correction processor FPGA design method, characterized in that: include: Analyze the preset parameters of input ISAR echo data; Calculate and cache four sets of valid values ​​according to the preset parameters; The input ISAR echo data is processed by range unit, and the migration correction of the input ISAR echo data is implemented by using the four groups of effective values ​​through complex exponential calculation, zero padding, FFT, and IFFT to obtain the migration-corrected echo data.

8. The high-performance real-time range migration correction processor FPGA design method according to claim 7, characterized in that: The range-by-range unit processes the input ISAR echo data, and uses the four groups of effective values ​​to perform migration correction on the input ISAR echo data through complex exponential calculation, zero padding, FFT, and IFFT to obtain the migration-corrected echo data, including: Extract valid data segments from the input ISAR echo data to obtain valid radar data; Performing a complex exponential operation on the four groups of effective values ​​to obtain a first complex exponential operation result, a second complex exponential operation result, and a third complex exponential operation result; splicing the first complex exponential operation result and the third complex exponential operation result to obtain a spliced ​​sequence, and caching the spliced ​​sequence; performing a complex multiplication operation on the valid radar data and the second complex exponential operation result to obtain a complex multiplication result; adding zero values ​​to both ends of the complex multiplication result to obtain a complex multiplication sequence, and caching the complex multiplication sequence; The FFT IP core integrated in FPGA is used to perform the multiplication and concatenation of the complex sequence and the concatenation sequence. FFT of the points to obtain the first operation result; The first complex exponential operation result is used as a weight, and migration correction is performed on the first operation result to obtain echo data after migration correction.

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