Physical design method suitable for high-performance atomic-scale computing chip

Abstract

The invention relates to the field of integrated circuit design, and discloses a physical design method suitable for a high-performance atomic-scale computing chip. The method comprises the following steps: firstly, analyzing an RTL code, performing module segmentation and generating a required memory; performing logic synthesis, setting different path groups for paths from the memory to the register, and endowing the paths with different weights; in the layout and wiring stage, top layer layout planning, module layout planning, power supply ground planning, layout, clock tree synthesis, wiring and design rule inspection are realized according to the algorithm function of each module and the trend of a data stream; and then physical verification, time sequence analysis and power consumption and voltage drop analysis are carried out, and sufficient iterative optimization is carried out to ensure that the final design meets the requirements of time sequence, power consumption and voltage drop. The method focuses on the physical design of a high-performance atomic-scale computing chip, effectively deals with challenges such as dense computation, high design complexity, large chip scale and high power consumption, and improves the reliability of the chip on the basis of ensuring high performance.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a physical design method suitable for high-performance atomic-level computing chips. Background Art

[0002] Atomic-level computing is widely used in numerous fields, including physics, chemistry, biology, materials science, energy, and geology. Its core applications include molecular dynamics simulations and first-principles calculations based on density functional theory. Currently, atomic-level computing primarily relies on central processing units (CPUs) and graphics processing units (GPUs). However, mainstream CPUs and GPUs generally utilize the von Neumann (vN) architecture. This architecture separates the storage unit from the compute unit, resulting in a significant portion of computing time and power consumed by the frequent data transfer between the two units. This creates significant bottlenecks, both in terms of storage and power consumption, severely restricting improvements in computing efficiency.

[0003] To overcome this bottleneck, designing application-specific integrated circuits (ASICs) using a non-von Neumann (NvN) architecture has become an effective solution. However, due to the extremely high requirements of atomic-level computing algorithms for data capacity, computational accuracy, and speed, ASIC chip design faces challenges such as computational intensity, high design complexity, large chip size, and high power consumption. During the physical design phase, timing closure, physical verification, and power management present numerous challenges. Furthermore, atomic-level computing is typically pipelined, and even the slightest error in any step of the computational process can lead to a decrease in the accuracy of the final result. Therefore, higher requirements are placed on the reliability and robustness of the physical design. Summary of the Invention

[0004] In response to the technical difficulties in the physical design of the atomic-level computing chip mentioned above, the present invention proposes a physical design method suitable for high-performance atomic-level computing chips. The present invention provides a stable and efficient physical design process that improves the reliability of the chip while ensuring high chip performance. The technical solution to achieve the purpose of the present invention is:

[0005] A physical design method for high-performance atomic-scale computing chips, including the following steps:

[0006] S1, RTL code analysis, determine the partitioning scheme of each sub-module in the hierarchical design, count the ports of each module and their data interaction relationship, organize them into a module interaction relationship diagram, and determine the type, bit width and depth of the memory required by each sub-module based on storage requirements; at the same time, classify the memory according to the type of stored data and the read and write cycle of the memory.

[0007] S2, logic synthesis. Given the large number of high-bitwidth memories in atomic-level computing chips, optimizing the timing of memory-to-register paths can easily become a bottleneck. Therefore, based on the memory read and write cycle sizes obtained in step S1, different path groups are established for each memory-to-register path and assigned different weights. Logic synthesis is then performed, allowing the tool to optimize each path group to varying degrees.

[0008] S3: Placement and routing. Using an automated placement and routing tool such as INNOVUS / ICC2, combined with the module port and data interaction information obtained in step S1 and the netlist obtained in step S2, the top-level layout is completed, ensuring precise alignment of the submodule ports. When planning the internal layout of each submodule, a reasonable layout plan is developed based on the algorithm functions and data flow of each module. Memories with the same or related computational data sources are placed in close proximity, and memories that interact with module ports are placed close to the ports. Simultaneously, a reasonable power and ground network plan is implemented, setting appropriate power line width and spacing rules for different modules, regions, and layers. During the layout phase, placement blockage is set based on the characteristics of each module. For compute-intensive modules, local density must be controlled to avoid congestion. If significant congestion occurs, the layout is re-created. During the clock tree synthesis phase, clock networks are constructed using cells with appropriate voltage thresholds. While ensuring that clock skew meets the target, high-voltage threshold cells are prioritized to reduce clock network power consumption. Different insertion delays are set based on the memory read and write cycle sizes obtained in step S1. If the generated clock tree does not meet the requirements, it is regenerated. During the routing phase, enable OCV (on-chip variation) settings, perform a rough timing analysis, and review the timing report. If significant violations are detected, perform timing repairs. Simultaneously, perform a design rule check (DRC) to check for errors such as shorts and opens. If errors are found, repair them and reroute the circuit. During the first iteration, complete each step of step S3. Subsequent iterations will iterate through the corresponding substeps of step S3 based on the type of errors or violations detected in steps S4 through S6.

[0009] S4, physical verification, uses the Calibre tool to perform DRC, LVS, ANT, and ERC checks on each module and the top layer of the atomic-level computing chip. If errors are found, the report is imported into the automatic place and route tool and categorized according to the error type. If the error is caused by routing, the error is corrected in the routing stage in step S3; if the error is caused by the device, the error is avoided in the layout stage in step S3.

[0010] S5, Timing Analysis: Use timing analysis tools such as Prime Time to perform setup and hold timing checks at multiple process corners to ensure that the timing results for multiple process corners meet requirements simultaneously. If the timing violation exceeds the repairable range, classify the violating paths and return to step S3 to set specific path groups, assigning different weights for optimization. If the timing violation is within the repairable range, use tools such as Prime Time and ICExplorer-XTop for timing optimization. The optimization results are imported into the automatic place and route tool, and ECO methods are used for iteration.

[0011] S6: Power consumption and voltage drop analysis. Use tools such as Redhawk, Voltus, and PTPX to analyze power consumption and understand its composition. This helps identify key areas for power reduction and allows for targeted optimization. The system also checks whether voltage drop is within a reasonable range, identifies areas with severe voltage drop, and performs targeted optimization. If the corresponding indicators are not met, the system returns to the corresponding sub-steps of S3 and iterates.

[0012] Compared with the existing technology, the advantages of the present invention mainly lie in: fully leveraging the capabilities of electronic design automation (EDA) tools such as automatic layout and routing, effectively circumventing problems such as high-bit-width memory path bottlenecks and computationally intensive pipeline structures that may be encountered in atomic-level computing chips in the early stages of physical design, and ensuring the high performance and high stability of atomic-level computing chips through a complete verification system including physical verification, multi-process corner timing sign-off, and power consumption and power integrity analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is an operational flow chart of the present invention;

[0014] Figure 2 is a schematic diagram of the interaction of chip modules in an embodiment of the present invention;

[0015] Figure 3 is a flow chart of step S3 in an embodiment of the present invention;

[0016] Figure 4 Schematic diagram of chip layout planning in an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0018] The present invention relates to a physical design method suitable for high-performance atomic-level computing chips, such as Figure 1 As shown, the method first analyzes the RTL code to clarify the hierarchical division and memory selection; then enters logic synthesis to obtain a timing-closed netlist; then completes layout and routing; finally, the design that has completed layout and routing is physically verified, timing analyzed, and power consumption and voltage drop analyzed. If it is found that the indicators do not meet the standards, it returns to the layout and routing stage for iteration. This embodiment is specifically explained using an atomic-level computing chip that implements molecular dynamics simulation as an example:

[0019] 1. Analyze the RTL code to clarify the hierarchical division of the molecular dynamics chip. The functional modules are mainly classified into computing modules and communication modules. The design frequency of the computing module is 1 GHz. Count the ports of each module and organize the module interaction diagram (such as Figure 2 (as shown). Based on the SMIC 28nm HKCP process, the required SRAM memory was generated using ARM Memory Compiler. The required SRAM width and depth for each submodule were determined to meet storage requirements. Memory was categorized: For example, the SRAM in module ③ was divided into three types based on the type of storage: interpolation parameters for forward calculations, interpolation parameters for backward calculations, and intermediate results. Furthermore, the memory was divided into three ranges based on read and write cycle times: 400 ps to 500 ps, ​​500 ps to 600 ps, ​​and 600 ps to 700 ps.

[0020] 2. Perform logic synthesis. Calculate the ratio of the memory read / write cycle to the target clock cycle based on the memory read / write cycle intervals divided in step 1. Use the group_path command in the Design Compiler synthesis tool to create path groups for memory-to-register paths in different read / write cycle intervals (representing different criticalities) and assign them different weights, with higher criticality receiving higher weights. Perform logic synthesis.

[0021] 3. Layout and routing, such as Figure 3 As shown, using the automatic layout and routing tool INNOVUS, according to the module port and data interaction obtained in step 1, and combined with the netlist obtained in step 2, the top-level Floorplan is designed to accurately align the sub-module ports according to the data flow direction (schematic diagram as shown in Figure 4As shown); Combined with the storage data type classification in step 1 (such as the three types of SRAM in module ③) and the algorithm functions and data flow direction of each module, place memories with the same or related computing data sources in similar locations, and place memories that interact with module ports close to the ports; Plan the power ground network, set differentiated rules, use high-level metal wiring power networks in computing-intensive modules (such as matrix multiplication units), reserve standard unit wiring resources, and increase the top metal density to suppress voltage drop; During layout, set different placement blockages based on the different characteristics of each module, such as setting dense small-area placement for high-pin density modules (such as serial-to-parallel conversion modules). For blockage arrays, for compute-intensive modules, set the local density cap to 70% and instance_padding to 1.5 to control local density. If congestion occurs, continue adjusting these settings and re-layout until the congestion is eliminated. During clock tree synthesis, use cells with appropriate voltage thresholds to build the clock network. While ensuring that clock skew meets requirements, prioritize cells with high voltage thresholds to reduce clock network power consumption. Differentiated insertion delays are set based on the memory read and write cycle ranges: for example, the insertion delays for memories in the 600 ps-700 ps, ​​500 ps-600 ps, ​​and 400 ps-500 ps ranges are set to 100 ps, ​​80 ps, ​​and 60 ps, ​​respectively. During routing, enable OCV settings and perform rough timing analysis to check setup / hold timing. If violations exceed the threshold (for example, setup violations greater than 300 ps or hold violations greater than 200 ps), perform timing repair and check and repair DRC errors such as shorts and opens.

[0022] 4. Physical verification: Use Calibre to perform DRC, LVS, ANT, and ERC checks on the module and top layer. If errors are found, the report is imported into INNOVUS for analysis. If the errors are due to routing errors such as metal spacing, return to the routing stage in step S3 to correct them. If the errors are due to device-related rule errors, return to the layout stage in step 3 to circumvent them.

[0023] 5. Timing Analysis: Use the Primetime tool to perform static timing analysis, checking setup and hold timing at various process corners, such as ffg_v0p99_125c and ssg_v0p81_-40c. If Setup / Hold violations are greater than 100 ps, ​​analyze the characteristics of the violating paths, return to step 3, assign high-weight path groups to these paths, and re-optimize. If the violations are less than 100 ps, ​​use the IC Explorer-XTop tool for timing optimization. Fix setup by changing the threshold voltage and device size, and fix hold by inserting delay cells. Then return to the routing phase in step 3, import the corresponding script into INNOVUS, and re-route using the ecoRoute command.

[0024] 6. Power consumption and voltage drop analysis: Use Voltus to analyze power consumption and understand its composition. For example, if the clock network in a molecular dynamics chip accounts for up to 70% of power consumption in many modules due to its high toggle rate, it is necessary to return to the clock tree synthesis stage in step 3 to improve the clock network structure, reduce the number of clock levels, and reduce the number of clock units. Check whether the voltage drop exceeds the threshold (set to 5% here). If so, return to the power ground planning stage in step 3, replan the power ground network, and insert decap units in areas with severe voltage drops.

[0025] Repeat steps 3 to 6 iteratively until all physical verifications pass, all target process corner timings converge, power consumption and voltage drop meet the standards, and the physical design is completed.

[0026] Finally, it should be noted that the above embodiments are intended only to illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention. With reference to the description of these embodiments, those skilled in the art should be able to understand and make relevant modifications or substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention.

Claims

1. A physical design method for high-performance atomic-level computing chips, characterized in that: The following steps are involved: S1: Determine the partitioning scheme for each submodule in the hierarchical design of the atomic-level computing chip, count the ports of each module and their data interaction relationships, organize them into a module interaction relationship diagram, and determine the type, bit width, and depth of the memory required by each submodule based on storage requirements; at the same time, classify the memory according to the type of stored data and the read and write cycle of the memory; S2, logic synthesis: Based on the memory read and write cycle sizes obtained in step S1, different path groups are established for each memory to register and assigned different weights. Then, the Design Compiler synthesis tool is used to perform logic synthesis, allowing the tool to optimize each path group to different degrees. S3: Placement and routing. Using but not limited to the INNOVUS automatic place and routing tool, combined with the module port and data interaction information obtained in step S1 and the netlist obtained in step S2, complete top-level layout planning, module layout planning, power and ground planning, layout, clock tree synthesis, routing, and design rule checking (DRC). S4, physical verification, uses the Calibre tool to perform DRC, LVS, ANT, and ERC checks on each module and the top layer of the atomic-level computing chip; S5, timing analysis, uses the Prime Time timing analysis tool to perform setup and hold timing checks under multiple process corners to ensure that the timing results of multiple process corners meet the requirements simultaneously; S6, power consumption and voltage drop analysis, uses tools such as, but not limited to, Redhawk to analyze power consumption components, identify entry points for power reduction, and perform targeted optimization. It also checks whether voltage drop is within a reasonable range and performs targeted optimization in areas with severe voltage drop.

2. The physical design method for a high-performance atomic-level computing chip according to claim 1, wherein: In step S3, when performing top-level layout planning, accurate alignment of the sub-module ports is achieved based on the module port and data interaction information obtained in step S1; When planning the module layout, based on the algorithm functions and data flow directions of each module, memories with the same or related computing data sources should be placed in similar locations, and memories that interact with module ports should be placed close to the ports.

3. The physical design method for a high-performance atomic-level computing chip according to claim 1, wherein: In step S3, when planning the power ground, corresponding power line width and spacing rules are set according to different modules, areas, and levels. When performing layout, placement blockage is set according to different module characteristics. In particular, for compute-intensive modules, local density needs to be controlled to avoid congestion. If a large amount of congestion occurs, the layout is re-established.

4. The physical design method for a high-performance atomic-level computing chip according to claim 1, wherein: In step S3, when performing clock tree synthesis, cells with appropriate voltage thresholds are used to construct a clock network. Under the premise of ensuring that the clock offset meets the target, high voltage threshold cells are preferentially used to reduce the power consumption of the clock network. Different insertion delays are set according to the memory read and write cycle size obtained in step S1. If the generated clock tree does not meet the requirements, the clock tree is regenerated.

5. The physical design method for a high-performance atomic-level computing chip according to claim 1, wherein: In step S3, when performing routing, OCV (on chip variation) related settings are turned on, a rough timing analysis is performed, and a timing report is checked; If a large timing violation is found, perform timing repairs; when performing DRC checks, check whether there are errors such as short circuits and open circuits. If errors are found, repair them and rewire.

6. The physical design method for a high-performance atomic-level computing chip according to claim 1, wherein: When performing the first round of placement and routing iteration, the entire process of step S3 needs to be fully executed. Subsequent iterations will enter the corresponding stage of step S3 for iteration according to the error or violation type found in steps S4 to S6.

7. The physical design method for a high-performance atomic-level computing chip according to claim 1, wherein: In step S4, when performing DRC, LVS, ANT, and ERC checks, if an error is found, the report is imported into, but not limited to, the INNOVUS automatic layout and routing tool, and classified and processed according to the error type; if the error is caused by routing, return to the routing stage in step S3 for repair; if the error is caused by the device, return to the layout stage in step S3 for avoidance.

8. The physical design method for a high-performance atomic-level computing chip according to claim 1, wherein: In step S5, if the timing violation exceeds the repairable range, the violating paths are classified, and the process returns to step S3 to set a specific path group and assign different weights for optimization; if the timing violation is within the repairable range, timing optimization is performed using Prime time and ICExplorer-XTop tools, the optimization results are imported into the automatic layout and routing tool, and iteration is performed using ECO means.

9. The physical design method for a high-performance atomic-level computing chip according to claim 1, wherein: In step S6, the power consumption composition is analyzed and divided into combinational logic, sequential logic, clock network, and memory according to the source of power consumption, and divided into leakage power consumption, short-circuit power consumption, and flip power consumption according to the type of power consumption. The two power consumption categories are analyzed, and targeted optimization is performed on modules with a larger power consumption ratio. The areas with severe voltage drops are optimized by encrypting the power ground network, reducing the density of local standard cells, and adding decap cells.

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