Overvoltage protection circuit and method

Abstract

The invention discloses an overvoltage protection circuit and method. The circuit comprises a sampling circuit, a current mirror circuit, a charging circuit and a comparator circuit, the sampling circuit is used for sampling the voltage of the voltage detection end to obtain a sampled voltage; the current mirror circuit is used for scaling down the sampling voltage and charging the charging circuit; and the comparator circuit is used for detecting the voltage of the charging circuit and sending an overvoltage protection signal when determining that the charging voltage is greater than a preset overvoltage protection threshold value. According to the overvoltage protection circuit, the current flowing through the first capacitor is scaled down through the current mirror by the current mirror circuit, then the second capacitor is charged by the scaled-down current, and when the voltage on the capacitor reaches the threshold value, overvoltage protection is triggered. The voltage sampling network is a capacitor and has no static power consumption. And the capacitor can be integrated into the chip, so that the system integration level can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to an overvoltage protection circuit and method. Background Art

[0002] In the field of switching power supplies, overvoltage protection is a crucial feature for ensuring the safe operation of both the power supply and load devices. Overvoltage protection prevents damage to components within the power supply system. When a switching power supply outputs an overvoltage, the excessive voltage can cause components such as capacitors, inductors, and power transistors to exceed their rated specifications, potentially damaging them. Furthermore, various electronic devices connected to the switching power supply, such as mobile phone chargers and laptop chargers, have specific operating voltage ranges. Overvoltage can damage the device's power supply, causing it to malfunction.

[0003] In commonly used converter circuits, such as Boost circuits (step-up converter circuits), the output voltage is generally scaled down by a voltage divider resistor network and other circuits, and the scaled-down voltage is sent to a comparator to be compared with an internally set reference voltage. When the comparator input voltage exceeds the reference voltage, the comparator output signal changes, indicating that overvoltage protection is triggered. Traditional Boost circuits such as Figure 1 As shown, resistors R1 and R2 form a voltage divider network that divides the VOUT voltage to FB. Comparing the FB voltage with an internal reference implements output overvoltage protection. However, if R2 is short-circuited, the FB voltage will not truly reflect the VOUT voltage, causing output overvoltage and damage to the system and internal devices. Furthermore, due to the static power consumption and high voltage resistance of resistors, they cannot be integrated into the chip, preventing the system from being reduced in size. Summary of the Invention

[0004] In order to overcome the static power consumption and the problem of being unable to be integrated into a chip in the existing overvoltage protection circuit, the present invention proposes an overvoltage protection circuit and method.

[0005] The specific technical solutions adopted in the present invention are as follows:

[0006] In a first aspect, an embodiment of the present invention provides an overvoltage protection circuit, wherein the overvoltage protection circuit includes a sampling circuit, a current mirror circuit, a charging circuit, and a comparator circuit;

[0007] The sampling circuit is used to sample the voltage at the voltage detection terminal to obtain a sampled voltage;

[0008] The current mirror circuit is used to reduce the sampling voltage ratio and charge the charging circuit;

[0009] The comparator circuit is used to detect the voltage of the charging circuit and send an overvoltage protection signal when it is determined that the charging voltage is greater than a preset overvoltage protection threshold.

[0010] Optionally, the overvoltage protection circuit further includes a discharge circuit, and the discharge circuit is used to discharge the charging circuit.

[0011] Optionally, the sampling circuit includes a first capacitor, a first end of the first capacitor is connected to the voltage detection end, and a second end of the first capacitor is connected to the input end of the current mirror circuit.

[0012] Optionally, the charging circuit includes a second capacitor, and a first end of the second capacitor is respectively connected to the output end of the current mirror circuit and the first input end of the comparator circuit.

[0013] Optionally, the current mirror circuit includes a first switch tube, a second switch tube, a third switch tube and a fourth switch tube, the first end of the first switch tube is respectively connected to the output end of the sampling circuit, the control end of the first switch tube and the control end of the second switch tube, the first end of the second switch tube is respectively connected to the first end, the control end and the control end of the fourth switch tube, the first end of the fourth switch tube is connected to the input end of the charging circuit, the second end of the third switch tube and the second end of the fourth switch tube are both connected to the power supply end, and the second end of the first switch tube and the second end of the second switch tube are both connected to ground.

[0014] Optionally, the discharge circuit includes a first switch, which is connected in parallel with the charging circuit.

[0015] In second aspect, an embodiment of the present invention also provides an overvoltage protection circuit, which includes a first capacitor, a current mirror circuit, a second capacitor and a comparator circuit, wherein the first end of the first capacitor is connected to the voltage detection end, the second end of the first capacitor is connected to the first end of the second capacitor through the current mirror circuit, the first end of the second capacitor is connected to the first input end of the comparator circuit, and the second input end of the comparator circuit is connected to the reference voltage.

[0016] Optionally, the capacitance of the second capacitor is greater than the capacitance of the first capacitor.

[0017] In a third aspect, an embodiment of the present invention further provides an overvoltage protection method, the overvoltage protection method comprising:

[0018] Sampling the voltage at the voltage detection terminal to obtain a sampled voltage;

[0019] reducing the sampling voltage ratio and charging the charging circuit;

[0020] The voltage of the charging circuit is detected, and an overvoltage protection signal is issued when it is determined that the charging voltage is greater than a preset overvoltage protection threshold.

[0021] The beneficial effects of the present invention are:

[0022] The present invention uses a current mirror circuit to reduce the current flowing through a first capacitor through a current mirror ratio, then uses the reduced current to charge a second capacitor. When the voltage on the capacitor reaches a threshold, overvoltage protection is triggered. The voltage sampling network in the present invention is a capacitor, eliminating static power consumption. Furthermore, the capacitors in the present invention can be integrated into a chip, effectively improving system integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Traditional Boost circuit schematic diagram;

[0024] Figure 2 A circuit schematic diagram of an overvoltage protection circuit of the present invention;

[0025] Figure 3 A circuit diagram of a Boost converter according to a first embodiment of the present invention;

[0026] Figure 4 A timing diagram of an overvoltage protection circuit according to a first embodiment of the present invention;

[0027] Figure 5 Working waveform of the overvoltage protection circuit of embodiment 1 of the present invention;

[0028] Figure 6 A flyback converter circuit diagram according to a second embodiment of the present invention;

[0029] Figure 7 A timing diagram of an overvoltage protection circuit according to a second embodiment of the present invention;

[0030] Figure 8 Working waveform of the overvoltage protection circuit according to the second embodiment of the present invention. DETAILED DESCRIPTION

[0031] The present invention and its beneficial effects will be further described in detail below with reference to specific implementations and the accompanying drawings. However, the specific implementations of the present invention are not limited thereto.

[0032] refer to Figure 2 , an embodiment of the present invention provides an overvoltage protection circuit, the overvoltage protection circuit includes a sampling circuit, a current mirror circuit, a charging circuit and a comparator circuit;

[0033] A sampling circuit is used to sample the voltage at the voltage detection terminal to obtain a sampled voltage;

[0034] A current mirror circuit is used to reduce the sampling voltage ratio and charge the charging circuit;

[0035] The comparator circuit is used to detect the voltage of the charging circuit and send an overvoltage protection signal when it is determined that the charging voltage is greater than a preset overvoltage protection threshold.

[0036] In one embodiment, the overvoltage protection circuit further includes a discharge circuit, and the discharge circuit is used to discharge the charging circuit.

[0037] In one embodiment, the sampling circuit includes a first capacitor C1 , a first terminal of the first capacitor C1 is connected to the voltage detection terminal, and a second terminal of the first capacitor C1 is connected to the input terminal of the current mirror circuit.

[0038] In one embodiment, the comparator circuit includes a comparator.

[0039] In one embodiment, the charging circuit includes a second capacitor C2 , and a first terminal of the second capacitor C2 is respectively connected to the output terminal of the current mirror circuit and the first input terminal of the comparator circuit.

[0040] In one embodiment, the current mirror circuit includes a first switch transistor M1, a second switch transistor M2, a third switch transistor M3, and a fourth switch transistor M4. The first end of the first switch transistor M1 is respectively connected to the output end of the sampling circuit, the control end of the first switch transistor M1, and the control end of the second switch transistor M2. The first end of the second switch transistor M2 is respectively connected to the first end and the control end of the third switch transistor M3, and the control end of the fourth switch transistor M4. The first end of the fourth switch transistor M4 is connected to the input end of the charging circuit. The second ends of the third switch transistor M3 and the fourth switch transistor M4 are both connected to the power supply end. The second ends of the first switch transistor M1 and the second ends of the second switch transistor M2 are both connected to ground. The first switch transistor M1, the second switch transistor M2, the third switch transistor M3, and the fourth switch transistor M4 can all be switching devices such as triodes or MOS transistors.

[0041] In one embodiment, the discharge circuit includes a first switch S1 , and the first switch S1 is connected in parallel with the charging circuit.

[0042] It should be noted that the principle of the circuit of the embodiment of the present invention is specifically as follows: the current-voltage relationship of the capacitor is as shown in formula (1):

[0043]

[0044] where i C is the current on the capacitor, C is the capacitance value, dU C is the voltage change on the capacitor, and dt is the time change.

[0045] In this embodiment, the first switch tube and the second switch tube are NMOS tubes, and the third switch tube and the fourth switch tube are PMOS tubes. Figure 1When the Boost circuit switch S2 is turned on, the current of the inductor L1 increases, the voltage at the SW point is zero, and at the same time the first switch S1 of the overvoltage protection circuit of the present invention is turned on to discharge the second capacitor C2 to zero. Figure 1 When the Boost circuit switch S2 is closed, the first switch S1 is also closed. Since the current of the inductor L1 cannot change suddenly, the voltage at the SW point will rise to VOUT+VD1. During this period, the voltage change of the first capacitor C1 is approximately ΔVOUT, where the current flowing through the first capacitor C1 is The current flowing through the NMOS tube M1 is IC1. The current IC1 is proportionally reduced by the current mirrors M1 and M2, M3 and M4. The voltage change of the capacitor C2 is a multiple of ΔVOUT. Therefore, by selecting a suitable VREF, the overvoltage protection of the SW point voltage can be achieved.

[0046] In addition, an embodiment of the present invention further provides an overvoltage protection circuit, the overvoltage protection circuit including a first capacitor, a current mirror circuit, a second capacitor, and a comparator circuit, wherein the first end of the first capacitor is connected to the voltage detection end, the second end of the first capacitor is connected to the first end of the second capacitor via the current mirror circuit, the first end of the second capacitor is connected to the first input end of the comparator circuit, and the second input end of the comparator circuit is connected to a reference voltage. The capacitance of the second capacitor is greater than that of the first capacitor.

[0047] In addition, an embodiment of the present invention further provides an overvoltage protection method, which includes:

[0048] Sampling the voltage at the voltage detection terminal to obtain a sampled voltage;

[0049] Scaling down the sampled voltage and charging the charging circuit;

[0050] Detect the voltage of the charging circuit and send an overvoltage protection signal when it is determined that the charging voltage is greater than a preset overvoltage protection threshold.

[0051] First embodiment

[0052] Figure 3 FIG. 1 is a circuit diagram of a Boost converter according to a first embodiment of the present invention.

[0053] Figure 2 The application of the present invention in the first embodiment is as follows. Figure 2 Middle SW termination Figure 3The connection point of inductor L1, switch S2, and diode D1. One end of the first capacitor C1 is connected to point SW, and one end is connected to the gate and drain of NMOS transistor M1 and the gate of NMOS transistor M2. The source of NMOS transistor M1 is grounded, and its gate and drain are connected to the gate of NMOS transistor M2. The gate of NMOS transistor M2 is connected to the gate and drain of transistor M1, its source is grounded, and its drain is connected to the gate and drain of PMOS transistor M3. The source of PMOS transistor M3 is connected to power supply VCC, and its gate and drain are connected to the drain of transistor M2 and the gate of transistor M4. The gate of PMOS transistor M4 is connected to the gate of M3, its source is connected to power supply VCC, and its drain is connected to the second capacitor C2, one end of the first switch S1, and the non-inverting input of the comparator. One end of switch S1 is connected to the second capacitor C2 and the non-inverting input of the comparator, and one end is grounded. One end of the second capacitor C2 is connected to the drain of M4, switch S1, and the non-inverting input of the comparator, and one end is grounded. The non-inverting input terminal of the comparator is connected to the second capacitor C2, the inverting input terminal is connected to the reference voltage, the reference voltage is the overvoltage protection threshold, and the output terminal is the overvoltage protection signal.

[0054] The specific working sequence of the overvoltage protection circuit of the present invention in the first embodiment is as follows: Figure 4 shown.

[0055] Phase 1: When the power tube S2 is turned on, the SW point is connected to the ground potential, and the voltage across the first capacitor C1 is zero. Figure 2 The switch S1 in the circuit is closed, discharging the second capacitor C2 to the ground potential, and the voltage across the second capacitor C2 is zero.

[0056] Phase 2: When the power tube S2 is turned off, the first switch S1 is turned off, and the current mirror circuit charges the second capacitor C2. Assume that the width-to-length ratio of the current mirror M1 and M2 is The aspect ratio of the current mirrors M3 and M4 is Then the relationship between the current flowing through the first capacitor C1 and the current flowing through the second capacitor C2 is I C2 =m1·m2·I C1 Assuming that the capacitance relationship between capacitors C1 and C2 is C2 = k·C1, the change in voltage on the second capacitor C2 is the change in voltage on the first capacitor C1. If the range of m1 and m2 is selected to be less than 1 and greater than 0, and the range of k is greater than 1, the voltage change on the first capacitor C1 can be reduced to a detectable range.

[0057] Phase 3: When the voltage on the second capacitor C2 exceeds the set overvoltage protection threshold, the comparator switches to high, indicating that the SW point triggers overvoltage protection. When the voltage on the second capacitor C2 falls below the set overvoltage protection threshold, the comparator remains low, indicating that the SW point does not trigger overvoltage protection.

[0058] Therefore, through this patent, by setting the appropriate current mirror width-to-length ratio, capacitor capacitance ratio, and overvoltage protection threshold, overvoltage protection of the SW point can be achieved.

[0059] The working waveform of the overvoltage protection circuit of embodiment 1 is as follows: Figure 5 shown.

[0060] When S2 is on, the SW point is connected to ground, and the voltage on capacitor C1, VC1, is also at ground. When S1 is on, the voltage on capacitor C2, VC2, is also at ground. At this point, the comparator output is low, indicating that OVP has not been triggered. When S2 is closed, S1 is also closed, causing the SW point voltage to rise, thereby increasing the voltage on VC1 and VC2. During the first two cycles, the change in VC2 does not reach the overvoltage protection threshold, VREF, and the comparator does not flip. During the next two cycles, the change in VC2 exceeds VREF, and the comparator flips high when S1 and S2 are closed, indicating that the overvoltage protection has been triggered.

[0061] Second embodiment

[0062] Figure 6 FIG. 1 is a circuit diagram of a flyback converter according to a first embodiment of the present invention.

[0063] The present invention is applied in the second embodiment as follows: Figure 2 Middle SW termination Figure 6 The transformer connects to the power supply M5 at point VD. One end of the first capacitor C1 is connected to point VD, and one end is connected to the gate and drain of NMOS transistor M1 and the gate of NMOS transistor M2. The source of NMOS transistor M1 is grounded, while its gate and drain are connected to the gate of NMOS transistor M2. The gate of NMOS transistor M2 is connected to the gate and drain of transistor M1, its source is grounded, and its drain is connected to the gate and drain of PMOS transistor M3. The source of PMOS transistor M3 is connected to power supply VCC, while its gate and drain are connected to the drain of transistor M2 and the gate of transistor M4. The gate of PMOS transistor M4 is connected to the gate of M3, its source is connected to power supply VCC, and its drain is connected to the second capacitor C2, one end of the first switch S1, and the non-inverting input of the comparator. One end of the first switch S1 is connected to the second capacitor C2 and the non-inverting input of the comparator, while one end is grounded. One end of capacitor C2 is connected to the drain of M4, switch S1, and the non-inverting input of the comparator, while one end is grounded. The non-inverting input terminal of the comparator is connected to the second capacitor C2, the inverting input terminal is connected to the reference voltage, the reference voltage is the overvoltage protection threshold, and the output terminal is the overvoltage protection signal.

[0064] Phase 1: When the power tube M5 is turned on, the VD point is connected to the ground potential, and the voltage across the first capacitor C1 is zero. Figure 2 The switch S1 in the circuit is closed, discharging the second capacitor C2 to the ground potential, and the voltage across the second capacitor C2 is zero.

[0065] Phase 2: When the power tube M5 is turned off, the first switch S1 is turned off, and the current mirror circuit charges the second capacitor C2. Assume that the width-to-length ratio of the current mirror M1 and M2 is The aspect ratio of the current mirrors M3 and M4 is Then the relationship between the current flowing through the first capacitor C1 and the current flowing through the second capacitor C2 is I C2 =m1·m2·I C1 Assuming that the capacitance relationship between capacitors C1 and C2 is C2 = k·C1, the change in voltage on the second capacitor C2 is the change in voltage on the first capacitor C1. If the range of m1 and m2 is selected to be less than 1 and greater than 0, and the range of k is greater than 1, the voltage change on the first capacitor C1 can be reduced to a detectable range.

[0066] Phase 3: When the voltage on the second capacitor C2 is greater than the set overvoltage protection threshold, the comparator flips to high, indicating that the VD point triggers overvoltage protection. When the voltage on the second capacitor C2 is less than the set overvoltage protection threshold, the comparator remains low, indicating that the VD point does not trigger overvoltage protection.

[0067] Therefore, through this patent, by setting the appropriate current mirror width-to-length ratio, capacitor capacitance ratio, and overvoltage protection threshold, overvoltage protection of the VD point can be achieved.

[0068] The working waveform of the overvoltage protection circuit of the second embodiment is as follows: Figure 8 shown.

[0069] When M5 is on, point VD is connected to ground, and the voltage on capacitor C1, VC1, is also at ground. When S1 is on, the voltage on capacitor C2, VC2, is also at ground. At this point, the comparator output is low, indicating that OVP has not been triggered. When M5 is off, S1 is also closed, causing the voltage on point VD to rise, thereby increasing the voltage on VC1 and, consequently, the voltage on VC2. During the first two cycles, the change in VC2 does not reach the overvoltage protection threshold, VREF, and the comparator does not flip. During the next two cycles, the change in VC2 exceeds VREF, and the comparator flips high when S1 and M5 are off, indicating that the overvoltage protection has been triggered.

[0070] The above are only preferred embodiments of the present invention. It should be pointed out that the above preferred embodiments should not be regarded as limitations of the present invention. For ordinary technicians in this technical field, several equivalent substitutions, improvements and modifications can be made without departing from the spirit and scope of the present invention. These equivalent substitutions, improvements and modifications should also be regarded as the scope of protection of the present invention. No further examples will be used here. The scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. An overvoltage protection circuit, characterized in that: The overvoltage protection circuit includes a sampling circuit, a current mirror circuit, a charging circuit and a comparator circuit; The sampling circuit is used to sample the voltage at the voltage detection terminal to obtain a sampled voltage; The current mirror circuit is used to reduce the sampling voltage ratio and charge the charging circuit; the comparator circuit is used to detect the voltage of the charging circuit and issue an overvoltage protection signal when it is determined that the charging voltage is greater than a preset overvoltage protection threshold.

2. The overvoltage protection circuit according to claim 1, wherein: The overvoltage protection circuit further includes a discharge circuit, and the discharge circuit is used to discharge the charging circuit.

3. The overvoltage protection circuit according to claim 1, wherein: The sampling circuit includes a first capacitor, a first end of the first capacitor is connected to the voltage detection end, and a second end of the first capacitor is connected to the input end of the current mirror circuit.

4. The overvoltage protection circuit according to claim 1, wherein: The charging circuit includes a second capacitor, wherein a first terminal of the second capacitor is connected to an output terminal of the current mirror circuit and a first input terminal of the comparator circuit respectively.

5. The overvoltage protection circuit according to claim 1, wherein: The current mirror circuit includes a first switch tube, a second switch tube, a third switch tube and a fourth switch tube. The first end of the first switch tube is respectively connected to the output end of the sampling circuit, the control end of the first switch tube and the control end of the second switch tube. The first end of the second switch tube is respectively connected to the first end and the control end of the third switch tube and the control end of the fourth switch tube. The first end of the fourth switch tube is connected to the input end of the charging circuit. The second ends of the third switch tube and the fourth switch tube are both connected to the power supply end. The second ends of the first switch tube and the second ends of the second switch tube are both connected to ground.

6. The overvoltage protection circuit according to claim 2, wherein: The discharge circuit includes a first switch connected in parallel with the charging circuit.

7. An overvoltage protection circuit, characterized in that: The overvoltage protection circuit includes a first capacitor, a current mirror circuit, a second capacitor and a comparator circuit, wherein the first end of the first capacitor is connected to the voltage detection end, the second end of the first capacitor is connected to the first end of the second capacitor through the current mirror circuit, the first end of the second capacitor is connected to the first input end of the comparator circuit, and the second input end of the comparator circuit is connected to the reference voltage.

8. The overvoltage protection circuit according to claim 7, wherein: The capacitance of the second capacitor is greater than the capacitance of the first capacitor.

9. An overvoltage protection method, characterized in that: The overvoltage protection method comprises: Sampling the voltage at the voltage detection terminal to obtain a sampled voltage; reducing the sampling voltage ratio and charging the charging circuit; The voltage of the charging circuit is detected, and an overvoltage protection signal is issued when it is determined that the charging voltage is greater than a preset overvoltage protection threshold.

Images