Mainboard dual-path power supply input source control circuit and chip

Abstract

Embodiments of the present disclosure provide a mainboard dual power supply input source control circuit and a chip, the circuit comprising: a logic judgment module, a level conversion module and a switch module, the logic judgment module comprising a first AND gate and a second AND gate, the first AND gate being used for judging the current working state according to SLP_S3 signal and SLP_S5 signal, and the second AND gate being used for outputting a level control signal according to a main power signal; the level conversion module comprising a first MOS tube and a second MOS tube, and being used for isolating the level control signal output by the logic judgment module, and converting the level control signal into a first voltage signal and a second voltage signal used for controlling the switch module; and the switch module comprising a first power MOS tube and a second power MOS tube, the first voltage signal and the second voltage signal being respectively used for controlling the switching of the second power MOS tube and the first power MOS tube, and by controlling the switching time of the first power MOS tube and the second power MOS tube, the input source of P5V_DUAL is maintained at a high level when the system state is switched.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of power control technology for electronic devices, and more specifically, to a dual-channel power input source control circuit and chip for a motherboard. Background Technology

[0002] In modern computer systems, with the continuous enhancement of electronic device functions and the increasing demand for low power consumption, power management technology has become increasingly important. Electronic circuits increasingly require immediate functionality upon power-up. For example, USB OTG (which allows USB devices to connect and exchange data directly) needs to provide power to peripherals in all system states (S5 off, S3 sleep, and S0 active). In S3 and S0 states, data in memory needs to be kept powered to support rapid system recovery.

[0003] In traditional ATX power supply designs, the P5V_STBY (standby power) circuit continues to provide 5V even when the system is off (S5 state) to support functions such as motherboard standby mode and USB port power supply. However, the 5V_STBY current of traditional ATX power supplies is relatively low (typically a maximum of 2A), which may be insufficient to support some high-power peripherals or components. Many motherboard designs employ more efficient power control to improve power delivery capabilities under different operating conditions. For example, PWR_OK is used to control the input source of P5V_DUAL (dual power supply). PWR_OK is a signal from the ATX power supply indicating that the power supply output has stabilized and can begin supplying power to the motherboard. Typically, the PWR_OK signal is sent to the motherboard after the 12V voltage stabilizes to trigger the motherboard power system to enter normal operating mode. However, the PWR_OK signal has a delay of approximately 360ms. This delay can cause the PWR_OK signal to fail to trigger the P5V_DUAL input source voltage supply in time between S3 and S0 states, resulting in the system failing to boot successfully or enter S3 state. If P5V_DUAL does not have enough input sources, the motherboard will fail to boot, affecting the normal operation of the device.

[0004] While controlling the P5V_DUAL input source using the uP7501M8 logic integrated chip allows for more precise power switching management and avoids issues caused by PWR_OK signal delay, integrated chips like the uP7501M8 are expensive. There is a lack of comparable alternatives on the market, which increases costs for mass-produced motherboards and impacts their market competitiveness. Summary of the Invention

[0005] To ensure stable power switching of the system under various operating conditions and to reduce circuit costs, the embodiments described herein provide a motherboard dual-channel power input source control circuit and chip.

[0006] According to a first aspect of this disclosure, a motherboard dual-power input source control circuit is provided, comprising: a logic judgment module, a level conversion module, and a switching module. The logic judgment module includes a first AND gate and a second AND gate. The first AND gate is used to determine the current operating state based on the SLP_S3 signal and the SLP_S5 signal, and the second AND gate is used to output a level control signal based on the main power signal. The level conversion module includes a first MOSFET and a second MOSFET, used to isolate the level control signal output by the logic judgment module and convert the level control signal into a first voltage signal and a second voltage signal for controlling the switching module. The switching module includes a first power MOSFET and a second power MOSFET, and by controlling the switching time of the first power MOSFET and the second power MOSFET, the input source of P5V_DUAL is maintained at a high level during system state switching.

[0007] In some embodiments of this disclosure, the level control signal is used to control the input source switching of P5V_DUAL. When the main power supply signal is present, the second power MOSFET is turned on, and the input source of P5V_DUAL comes from the 5V main power supply. When the main power supply signal is absent, the first power MOSFET is turned on, and the input source of P5V_DUAL comes from the 5V standby voltage.

[0008] In some embodiments of this disclosure, the logic judgment module further includes a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor. The first and second input terminals of the first AND gate are respectively connected to the SLP_S3 and SLP_S5 signals of the system, which are both controlled by the CPU. One end of the first resistor is connected to the first input terminal of the first AND gate, and the other end is grounded. One end of the second resistor is connected to the second input terminal of the first AND gate, and the other end is grounded. The power supply terminal of the first AND gate is connected to a 3.3V power supply voltage, and the output terminal of the first AND gate is connected to the second input terminal of the second AND gate via the third resistor. The first input terminal of the second AND gate is connected to a 5V power supply voltage via the fourth resistor, and the first input terminal of the second AND gate is grounded via the fifth resistor. The power supply terminal of the second AND gate is connected to a 3.3V power supply voltage.

[0009] In some embodiments of this disclosure, the first and second resistors are pull-down resistors used to fix the states of the SLP_S3 and SLP_S5 signals of the system during CPU initialization; the third resistor is used to suppress signal reflection and ringing in the logic judgment module; the fourth and fifth resistors are used to divide the 5V power supply voltage into a 3.3V voltage as the input signal of the first input terminal of the second AND gate.

[0010] In some embodiments of this disclosure, the level conversion module further includes a sixth resistor and a seventh resistor. The source of the first MOSFET and the source of the second MOSFET are both connected to the output of the second AND gate. The gate of the first MOSFET is connected to a 3.3V power supply voltage through the sixth resistor, and the gate of the second MOSFET is connected to a 3.3V power supply voltage through the seventh resistor.

[0011] In some embodiments of this disclosure, when the second AND gate outputs a high level, the first MOSFET and the second MOSFET are in a turned-off state, the drain voltage of the first MOSFET is pulled up to 5V, and the drain voltage of the second MOSFET is pulled up to 12V.

[0012] In some embodiments of this disclosure, the switching module further includes an eighth resistor, a ninth resistor, a tenth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, and a tenth capacitor;

[0013] The drain voltage of the second MOSFET is connected to the drain of the first power MOSFET via the first capacitor, and then to the source and gate of the first power MOSFET via the second capacitor. The drain of the first power MOSFET is connected to P5V_DUAL. One end of the eighth resistor is grounded, and the other end is connected to P5V_DUAL. One end of the ninth resistor is connected to the gate of the first power MOSFET, and the other end is connected to the 5V standby voltage. The source of the first power MOSFET is connected to the third, fourth, and fifth capacitors. One end of the third, fourth, and fifth capacitors is grounded, and the other end is connected to the 5V standby voltage.

[0014] The drain voltage of the first power MOSFET is connected to the source of the second power MOSFET via the eighth capacitor, and is also connected to the gate of the second power MOSFET; the drain of the second power MOSFET is connected to P5V_DUAL, and grounded through the sixth and seventh capacitors; one end of the tenth resistor is connected to the gate of the second power MOSFET, and the other end is connected to the 12V power supply voltage; the source of the second power MOSFET and the common terminal of the ninth and tenth capacitors are connected to the 5V power supply voltage, and the other ends of the ninth and tenth capacitors are grounded.

[0015] In some embodiments of this disclosure, the first power MOSFET is a WMS16P03T1, and the second power MOSFET is a WMS032N04LG2. When the system state changes from SLP_S3=0, SLP_S5=1 to SLP_S3=1, SLP_S5=1, the on-time of the second power MOSFET is controlled to be 15ns, and the off-time of the first power MOSFET is controlled to be 105ns, so that P5V_DUAL remains high when the gate levels of the first and second power MOSFETs change from 0 to 1. When the system state changes from SLP_S3=1, SLP_S5=1 to SLP_S3=0, SLP_S5=1, the on-time of the first power MOSFET is controlled to be 33.5ns, and the off-time of the second power MOSFET is controlled to be 38.6ns, so that P5V_DUAL remains high when the gate levels of the first and second power MOSFETs change from 1 to 0.

[0016] In some embodiments of this disclosure, the first, second, and eighth capacitors have a capacitance of 0.01 μF, the fifth and seventh capacitors have a capacitance of 0.1 μF, and are used for signal filtering; the third, fourth, sixth, ninth, and tenth capacitors have a capacitance of 10 μF, and are used to stabilize the power supply voltage; the eighth resistor is used to quickly discharge P5V_DUAL when the power is off; and the ninth and tenth resistors are used to limit the current passing through the 5V and 12V lines.

[0017] According to a second aspect of this disclosure, a chip is provided that includes a motherboard dual-power input source control circuit according to a first aspect of this disclosure.

[0018] According to the motherboard dual-power input source control circuit chip provided in this embodiment, the system's operating state is determined based on the SLP_S3 and SLP_S5 signals. Combined with the main power signal, the input source switching is controlled, ensuring that the system receives the required stable power supply under different operating states, preventing system failures due to insufficient power supply or untimely switching. Level conversion not only effectively avoids interference between different signal sources but also converts the control signal into a voltage signal suitable for controlling the switching module, improving circuit stability and reliability. By precisely controlling the switching time of the power MOSFET in the switching module, the system can provide a smooth transition during state switching, avoiding system instability or restarts caused by power fluctuations or instantaneous voltage changes, while reducing circuit costs and improving the stability of long-term system operation. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0020] Figure 1 This is a schematic diagram of the structure of the motherboard dual power input source control circuit according to an embodiment of the present disclosure;

[0021] Figure 2 This is a system timing logic control truth table according to an embodiment of the present disclosure;

[0022] Figure 3 This is a circuit schematic diagram of the logic judgment module according to an embodiment of the present disclosure;

[0023] Figure 4 This is a circuit schematic diagram of a level conversion module according to an embodiment of the present disclosure;

[0024] Figure 5 This is a circuit schematic diagram of a switching module according to an embodiment of the present disclosure.

[0025] It should be noted that the elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0027] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0028] To ensure a stable power supply for electronic devices in various operating states (such as S5, S3, S0) and to guarantee rapid system startup and stable operation, this disclosure provides a motherboard dual-power input source control circuit. Through the coordinated operation of modules such as logic judgment, level conversion, and MOS switch control, it ensures stability during power switching and avoids power failure and restart issues caused by dead time.

[0029] Figure 1 This is a schematic diagram of the structure of a motherboard dual-channel power input source control circuit according to an embodiment of this disclosure. (Refer to...) Figure 1 As shown, the motherboard's dual-power input source control circuit includes a logic judgment module, a level conversion module, and a switching module. The logic judgment module includes a first AND gate and a second AND gate. The first AND gate determines the current operating state based on the SLP_S3 and SLP_S5 signals, while the second AND gate outputs a level control signal VCC_ON based on the main power signal P5V. The level conversion module includes a first MOSFET and a second MOSFET, used to isolate the level control signal output from the logic judgment module and convert the level control signal VCC_ON into a first voltage signal 5VCC_DRV and a second voltage signal 5VSB_DRV for controlling the switching module. The switching module includes a first power MOSFET and a second power MOSFET. The first voltage signal 5VCC_DRV and the second voltage signal 5VSB_DRV are used to control the switching of the second power MOSFET and the first power MOSFET, respectively. By controlling the switching time of the first power MOSFET and the second power MOSFET, the input source P5V_DUAL is maintained at a high level during system state switching.

[0030] In some embodiments of this disclosure, a level control signal is used to control the input source switching of P5V_DUAL, a first voltage signal is used to control the switching of the first power MOSFET, and a second voltage signal is used to control the switching of the second power MOSFET. When the main power signal is absent, the first power MOSFET is turned on, and the input source of P5V_DUAL comes from the 5V standby voltage, indicating that the system is in standby or off state at this time, with low power consumption. The current of P5V_STBY of the ATX circuit is sufficient to meet the power consumption requirements of P5V_DUAL under this system condition. When the main power signal is present, the second power MOSFET is turned on, and the input source of P5V_DUAL comes from the 5V main power supply, indicating that the system is in operating state at this time.

[0031] Figure 2 This is a truth table for system timing logic control according to embodiments of this disclosure. (Refer to...) Figure 2As shown, the output P5V_DUAL status is determined by different combinations of four input signals: SLP_S5, SLP_S3, 5VCC, and 5VSB. Here, 5VCC is the 5V main power supply signal, 5VSB is the 5V standby voltage signal, and P5V_DUAL is the final power output.

[0032] When SLP_S3 = 1 and SLP_S5 = 1, the system is in the power-on state (S0). At this time, when the main power supply signal is present (5VCC = 1), the input source of P5V_DUAL comes from the 5V main power supply. When the main power supply signal is absent (5VCC = 0), the input source of P5V_DUAL comes from the 5V standby voltage.

[0033] When SLP_S5 = 1 and SLP_S3 = 0, the system is in sleep state (S3). At this time, regardless of whether the main power signal is present, the input source of P5V_DUAL comes from the 5V standby voltage.

[0034] When SLP_S5 = 0 and SLP_S3 = X (X = 0 or 1), the system is in the off state (S5). At this time, when the standby power signal 5VSB is high (5VSB = 1), the input source of P5V_DUAL comes from the 5V standby voltage; otherwise, there is no voltage input.

[0035] Figure 3 This is a circuit schematic diagram of a logic judgment module according to an embodiment of this disclosure. (Refer to...) Figure 3 As shown, the logic judgment module includes a first AND gate U44, a second AND gate U45, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The first and second input terminals of the first AND gate U44 are connected to the system's SLP_S3 and SLP_S5 signals, respectively, both of which are controlled by the CPU. One end of the first resistor R1 is connected to the first input terminal of the first AND gate U44, and the other end is grounded. One end of the second resistor R2 is connected to the second input terminal of the first AND gate U44, and the other end is grounded. The power supply terminal of the first AND gate U44 is connected to a 3.3V power supply voltage P3V3_STBY. Since the voltages of SLP_S3 and SLP_S5 are 3.3V, the logic AND gate U44 needs to operate in the S5 state, so the voltage of U44 is selected as P3V3_STBY.

[0036] The output of the first AND gate U44 is connected to the second input of the second AND gate U45 via the third resistor R3; the first input of the second AND gate U45 is connected to a 5V power supply voltage P5V via the fourth resistor R4, and the first input of the second AND gate U45 is grounded via the fifth resistor R5; the power supply terminal of the second AND gate U45 is connected to a 3.3V power supply voltage P3V3_STBY.

[0037] According to one embodiment of this disclosure, the first AND gate U44 and the second AND gate U45 employ the Aip74LVC1G08GA logic chip. The first resistor R1 and the second resistor R2 are pull-down resistors with a Z-value set to 10KΩ, used to fix the states of the SLP_S3 and SLP_S5 signals during CPU initialization to prevent signal fluctuations. The third resistor R3 is used to suppress signal reflection and ringing in the logic judgment module, with a resistance value set to 22Ω; the fourth resistor R4 and the fifth resistor R5 are used to divide the 5V power supply voltage to 3.3V as the input signal to the first input terminal of the second AND gate U45.

[0038] The level conversion module is used to convert the input 3.3V signal into different voltage outputs (5V and 12V) to drive switching modules with different voltage requirements and to provide electrical isolation. Figure 4 This is a circuit schematic diagram of a level conversion module according to an embodiment of the present disclosure. (Refer to...) Figure 4 As shown, the level conversion module includes a first MOSFET Q44, a second MOSFET Q45, a sixth resistor R6, and a seventh resistor R7. The first MOSFET Q44 and the second MOSFET Q45 are WM05N02M. The WM05N02M is an N-channel MOSFET, suitable for use in power control circuits.

[0039] The source (S) of the first MOSFET Q44 and the source (S) of the second MOSFET Q45 are both connected to the output of the second AND gate U45. The gates (G) of the first MOSFET Q44 and the second MOSFET Q45 are connected to the 3.3V power supply voltage P3V3_STBY via resistors 6 and 7, respectively. When the second AND gate U45 outputs a high level (VCC_ON outputs 3.3V), since the gates of both Q44 and Q45 are pulled high to 3.3V, the voltage difference between their gates and sources is 0V. Therefore, the first MOSFET Q44 and the second MOSFET Q45 are not conducting. At this time, the drain voltages of Q44 and Q45 determine the voltage of the output signal. That is, when these MOSFETs are turned off, their drain voltages are affected by the pull-up voltage on their drains. The drain voltage of the first MOSFET Q44 is pulled up to 5V (5VSB_DRV), and the drain voltage of the second MOSFET Q45 is pulled up to 12V (5VCC_DRV). These converted voltage signals are then further transmitted to the switching module to drive the circuits that require the corresponding voltage.

[0040] Furthermore, this level conversion module achieves electrical isolation through the design of MOSFETs and pull-up resistors, ensuring that the 5VSB_DRV and 5VCC_DRV voltages do not interfere with each other. Although the 5VSB_DRV and 5VCC_DRV voltages are different, they can operate independently without affecting each other due to electrical isolation.

[0041] In this system, the P5V_DUAL power supply must always remain high. If there is a dead time during MOSFET switching (i.e., both MOSFETs are turned off simultaneously), P5V_DUAL may briefly drop to 0V, causing the system to mistakenly interpret this as a power outage and restart, which is unacceptable in practical applications. The design focus of the switching module is to ensure the stability of the P5V_DUAL power supply, avoiding system restarts due to dead time during MOSFET switching when the state changes. This is achieved by appropriately selecting MOSFET specifications and adjusting the MOSFET switching time to ensure that P5V_DUAL remains high at all times.

[0042] Figure 5 This is a circuit schematic diagram of a switching module according to an embodiment of the present disclosure. (Refer to...) Figure 5 As shown, the switching module includes a first power MOSFET PQ29, a second power MOSFET PQ30, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, and a tenth capacitor C10.

[0043] Figure 4 The drain voltage 5VSB_DRV of the second MOSFET Q45 is connected to the drain D (pins 5, 6, 7, 8) of the first power MOSFET PQ29 via the first capacitor C1, and to the source S (pins 1, 2, 3) of the first power MOSFET PQ29 via the second capacitor C2, and is also connected to the gate G (pin 4) of the first power MOSFET PQ29. The drain D (pins 5, 6, 7, 8) of the first power MOSFET PQ29 is connected to P5V_DUAL. One end of the eighth resistor R8 is grounded, and the other end is connected to P5V_DUAL. One end of the ninth resistor is connected to the gate G (pin 4) of the first power MOSFET PQ29, and the other end is connected to the 5V standby voltage P5V_STBY. The source S (pins 1, 2, 3) of the first power MOSFET PQ29 is connected to the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5; one end of the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 is grounded, and the other end is connected to the 5V standby voltage P5V_STBY.

[0044] Figure 4The drain voltage 5VCC_DRV of the first MOSFET Q44 is connected to the source S (pins 1, 2, 3) of the second power MOSFET PQ30 via the eighth capacitor C8, and is also connected to the gate G (pin 4) of the second power MOSFET PQ30. The drain D (pins 5, 6, 7, 8) of the second power MOSFET PQ30 is connected to P5V_DUAL, and grounded through the seventh capacitor C7 and the sixth capacitor C6. One end of the tenth resistor R10 is connected to the gate G (pin 4) of the second power MOSFET PQ30, and the other end is connected to the 12V power supply voltage P12V. The common terminal of the source S (pins 1, 2, 3) of the second power MOSFET PQ30 and the ninth capacitor C9 and the tenth capacitor C10 is connected to the 5V power supply voltage P5V, and the other ends of the ninth capacitor C9 and the tenth capacitor C10 are grounded.

[0045] According to one embodiment of this disclosure, the first power MOSFET PQ29 is selected as WMS16P03T1, and the second power MOSFET PQ30 is selected as WMS032N04LG2. WMS16P03T1 is a P-channel MOSFET, whose low on-resistance reduces power loss, making it suitable for applications requiring fast switching. WMS032N04LG2 is an N-channel MOSFET, providing better conductivity and response speed, suitable for high-voltage power supply applications. Their switching characteristics (turn-on time and turn-off time) are crucial to power supply stability. The first, second, and eighth capacitors have a capacitance of 0.01μF, and the fifth and seventh capacitors have a capacitance of 0.1μF, used for signal filtering to improve and stabilize switching performance. The third, fourth, sixth, ninth, and tenth capacitors have a capacitance of 10μF, used to stabilize the power supply voltage.

[0046] When power is off, P5V_DUAL may retain a certain voltage due to the presence of capacitors. If no measures are taken, the residual charge in the capacitors may prevent the circuit from completely disconnecting or generate noise. The eighth resistor provides a fast discharge path for the capacitors, ensuring that the P5V_DUAL voltage drops to zero as quickly as possible after power is off. The ninth and tenth resistors limit the current flowing through the 5V and 12V lines, preventing excessive current from damaging other components or causing overheating. The presence of these current-limiting resistors helps protect the power supply and load circuits, ensuring that the system does not malfunction due to overload during operation.

[0047] When the system state changes from SLP_S3=0, SLP_S5=1 to SLP_S3=1, SLP_S5=1, the on-time of the second power MOSFET PQ30 is controlled to be 15ns, and the off-time of the first power MOSFET PQ29 is controlled to be 105ns. This ensures that P5V_DUAL remains high when the gate levels of the first power MOSFET PQ29 and the second power MOSFET PQ30 change from 0 to 1, avoiding dead time. When the system state changes from SLP_S3=1, SLP_S5=1 to SLP_S3=0, SLP_S5=1, the turn-on time of the first power MOSFET PQ29 is controlled to be 33.5ns, and the off-time of the second power MOSFET PQ30 is controlled to be 38.6ns. This ensures that P5V_DUAL remains high when the gate levels of the first power MOSFET PQ29 and the second power MOSFET PQ30 change from 1 to 0, preventing brief power outages.

[0048] When the SLP_S3 state changes, the system will directly use the signals of SLP_S5 and SLP_S3 to control the input source of P5V_DUAL, thereby ensuring that the 5V_DUAL power supply can quickly switch to the 5VCC input source with sufficient current supply capacity at the moment of device startup, avoiding the problem of insufficient current supply caused by delay, ensuring that the system can be stably powered, and thus ensuring the normal operation of the system.

[0049] Embodiments of this disclosure also provide a chip. This chip includes a motherboard dual-power input source control circuit according to embodiments of this disclosure.

[0050] In summary, the motherboard dual-power input source control circuit chip provided in the embodiments of this disclosure determines the system's operating state based on the SLP_S3 and SLP_S5 signals, and then controls the input source switching in conjunction with the main power signal. This ensures that the system can obtain the required stable power supply under different operating states, preventing system failures due to insufficient power supply or untimely switching. Level conversion not only effectively avoids interference between different signal sources but also converts the control signal into a voltage signal suitable for controlling the switching module, improving the circuit's stability and reliability. By precisely controlling the switching time of the power MOSFET in the switching module, the system can provide a smooth transition during state switching, avoiding system instability or restarts caused by power fluctuations or instantaneous voltage changes, while reducing circuit costs and improving the system's long-term operational stability.

[0051] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0052] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0053] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A motherboard dual-channel power input source control circuit, characterized in that, include: Logic judgment module, level conversion module, and switch module; The logic judgment module includes a first AND gate and a second AND gate. The first AND gate is used to determine the current working state based on the SLP_S3 and SLP_S5 signals. When SLP_S3 = 1 and SLP_S5 = 1, the system is in the power-on state; when SLP_S5 = 1 and SLP_S3 = 0, the system is in the sleep state; when SLP_S5 = 0, SLP_S3 = X, and X = 0 or 1, the system is in the power-off state. The second AND gate is used to output a level control signal based on the main power signal. The logic judgment module also includes a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor. The first and second input terminals of the first AND gate are respectively connected to... The system's SLP_S3 and SLP_S5 signals are both controlled by the CPU; one end of the first resistor is connected to the first input of the first AND gate, and the other end is grounded; one end of the second resistor is connected to the second input of the first AND gate, and the other end is grounded; the power supply terminal of the first AND gate is connected to a 3.3V power supply voltage, and the output terminal of the first AND gate is connected to the second input of the second AND gate through the third resistor; the first input terminal of the second AND gate is connected to a 5V power supply voltage through the fourth resistor, and the first input terminal of the second AND gate is grounded through the fifth resistor; the power supply terminal of the second AND gate is connected to a 3.3V power supply voltage. The level conversion module includes a first MOSFET and a second MOSFET, which are used to isolate the level control signal output by the logic judgment module and convert the level control signal into a first voltage signal and a second voltage signal for controlling the switching module. The switching module includes a first power MOSFET and a second power MOSFET. The first voltage signal and the second voltage signal are used to control the switching of the second power MOSFET and the first power MOSFET, respectively. By controlling the switching time of the first power MOSFET and the second power MOSFET, the input source of P5V_DUAL is kept at a high level when the system state is switched.

2. The motherboard dual-channel power input source control circuit according to claim 1, characterized in that, The level control signal is used to control the input source switching of P5V_DUAL. When the main power signal is present, the second power MOSFET is turned on, and the input source of P5V_DUAL comes from the 5V main power supply. When the main power signal is absent, the first power MOSFET is turned on, and the input source of P5V_DUAL comes from the 5V standby voltage.

3. The motherboard dual-channel power input source control circuit according to claim 1, characterized in that, The first and second resistors are pull-down resistors used to fix the state of the SLP_S3 and SLP_S5 signals of the system during CPU initialization; the third resistor is used to suppress signal reflection and ringing in the logic judgment module; the fourth and fifth resistors are used to divide the 5V power supply voltage into a 3.3V voltage, which serves as the input signal to the first input terminal of the second AND gate.

4. The motherboard dual-channel power input source control circuit according to claim 1, characterized in that, The level conversion module further includes a sixth resistor and a seventh resistor. The source of the first MOSFET and the source of the second MOSFET are both connected to the output terminal of the second AND gate. The gate of the first MOSFET is connected to a 3.3V power supply voltage through the sixth resistor, and the gate of the second MOSFET is connected to a 3.3V power supply voltage through the seventh resistor.

5. The motherboard dual-channel power input source control circuit according to claim 4, characterized in that, When the second AND gate outputs a high level, the first MOSFET and the second MOSFET are in the off state, the drain voltage of the first MOSFET is pulled up to 5V, and the drain voltage of the second MOSFET is pulled up to 12V.

6. The motherboard dual-channel power input source control circuit according to claim 4, characterized in that, The switching module also includes an eighth resistor, a ninth resistor, a tenth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, and a tenth capacitor; The drain voltage of the second MOSFET is connected to the drain of the first power MOSFET via the first capacitor, and then connected to the source and gate of the first power MOSFET via the second capacitor. The drain of the first power MOSFET is connected to P5V_DUAL. One end of the eighth resistor is grounded, and the other end is connected to P5V_DUAL. One end of the ninth resistor is connected to the gate of the first power MOSFET, and the other end is connected to the 5V standby voltage. The source of the first power MOSFET is connected to the third, fourth, and fifth capacitors. One end of the third, fourth, and fifth capacitors is grounded, and the other end is connected to the 5V standby voltage. The drain voltage of the first power MOSFET is connected to the source of the second power MOSFET via the eighth capacitor, and is also connected to the gate of the second power MOSFET; the drain of the second power MOSFET is connected to P5V_DUAL, and grounded through the sixth and seventh capacitors; one end of the tenth resistor is connected to the gate of the second power MOSFET, and the other end is connected to a 12V power supply voltage; the source of the second power MOSFET and the common terminal of the ninth and tenth capacitors are connected to a 5V power supply voltage, and the other ends of the ninth and tenth capacitors are grounded.

7. The motherboard dual-channel power input source control circuit according to claim 6, characterized in that, The first power MOSFET is WMS16P03T1, and the second power MOSFET is WMS032N04LG2; When the system state changes from SLP_S3=0, SLP_S5=1 to SLP_S3=1, SLP_S5=1, the on-time of the second power MOSFET is controlled to be 15ns and the off-time of the first power MOSFET is controlled to be 105ns, so that P5V_DUAL remains high when the gate levels of the first power MOSFET and the second power MOSFET change from 0 to 1. When the system state changes from SLP_S3=1, SLP_S5=1 to SLP_S3=0, SLP_S5=1, the on-time of the first power MOSFET is controlled to be 33.5ns and the off-time of the second power MOSFET is controlled to be 38.6ns, so that P5V_DUAL remains high when the gate levels of the first and second power MOSFETs change from 1 to 0.

8. The motherboard dual-channel power input source control circuit according to claim 6, characterized in that, The capacitance values ​​of the first capacitor, the second capacitor, and the eighth capacitor are all 0.

01. The capacitance values ​​of the fifth and seventh capacitors are 0.

1. It is used for signal filtering; the capacitance values ​​of the third, fourth, sixth, ninth, and tenth capacitors are 10. The eighth resistor is used to stabilize the power supply voltage. The eighth resistor is used to quickly discharge P5V_DUAL when the power is off. The ninth and tenth resistors are used to limit the current passing through the 5V and 12V lines.

9. A chip, wherein, Includes the motherboard dual power input source control circuit as described in any one of claims 1-8.

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