Multi-channel high-speed digital phase-locked amplifier based on FPGA (Field Programmable Gate Array) and signal processing method
Patent Information
- Application Number
- CN202510697761.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-28
- Publication Date
- 2025-09-16
AI Technical Summary
Traditional FPGA-based digital lock-in amplifiers have problems in signal processing, such as design complexity, high resource consumption, slow response speed, insufficient accuracy, and difficulty in debugging. These problems are particularly prominent in high-frequency signal processing, affecting the real-time tracking accuracy and stability of the signal.
The system adopts a multi-channel high-speed digital lock-in amplifier based on FPGA. By optimizing the hardware design and parallel processing technology, it combines the analog-to-digital conversion module, DDS-Sunderland module, phase-sensitive detection multiplier module, cascaded integral comb-finite impulse response filter module, effective value detection module, coordinated rotation digital calculation square root inverse tangent module and discrete Hallett transform module to reduce system delay, improve phase-locking accuracy and simplify the debugging process.
It reduces FPGA chip resource consumption, improves response speed, enhances signal processing accuracy, enhances system adaptability, simplifies debugging and maintenance processes, and is suitable for high-performance signal processing applications.
Smart Images
Figure CN120658262A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of signal processing, and in particular relates to a multi-channel high-speed digital lock-in amplifier based on FPGA and a signal processing method. Background Art
[0002] A digital phase-locked loop (DPLL) is a technology that precisely tracks the frequency and phase changes of an input signal through a phase-locking mechanism. In the field of signal processing, DPLLs are widely used for high-precision frequency tracking, noise suppression, and signal enhancement. With the rapid development of field programmable gate array (FPGA) technology, FPGAs, as a flexible and highly customizable hardware platform, have demonstrated significant advantages in DPLL implementation. Compared to traditional hardware implementations, FPGA-based DPLLs offer not only greater flexibility and scalability, but also meet more stringent accuracy requirements and a wider range of application scenarios. They are particularly well-suited for high-frequency signal processing and dynamic response.
[0003] However, despite the numerous advantages of FPGA-implemented DPLL technology, challenges remain in terms of design complexity, resource consumption, response speed, accuracy, and debugging difficulty during signal processing. Specifically, DPLL systems typically consist of multiple modules, including phase detection, filter design, frequency control, and a phase-locked loop. This complex modular design not only increases the difficulty of hardware and software implementation but also increases the workload of subsequent system maintenance and debugging. Furthermore, as DPLL system frequency requirements increase, especially in high-frequency signal processing applications, FPGA resource consumption becomes increasingly prominent, potentially leading to reduced system efficiency and design limitations.
[0004] In some applications with high real-time requirements, the response speed of traditional DPLLs may not be sufficient, and system latency may occur, affecting the real-time tracking accuracy of the signal. Furthermore, in noisy environments, the DPLL's phase-locked accuracy is easily disturbed, resulting in waveform distortion or frequency offset in the system's output signal, which in turn affects the accuracy and stability of the signal. Finally, the debugging and verification process of DPLL systems is relatively complex, often requiring specialized testing equipment and debugging tools. This not only increases development costs but also prolongs project development cycles. Summary of the Invention
[0005] To address the aforementioned technical issues, the present invention provides an FPGA-based multi-channel high-speed digital lock-in amplifier and signal processing method. By optimizing hardware design and reducing system complexity and resource consumption, the DPLL's response speed and accuracy are improved, while also enhancing the system's adaptability and flexibility. Through precise resource scheduling and parallel processing techniques, the present invention effectively reduces DPLL system latency and achieves superior noise suppression performance. Furthermore, the system's debugging and maintenance processes are significantly simplified, improving overall development efficiency and providing a more stable and efficient solution for high-performance signal processing applications.
[0006] The present invention is achieved through the following technical solutions:
[0007] A multi-channel high-speed digital lock-in amplifier based on FPGA, comprising an analog-to-digital conversion module (ADC), a DDS-Sunderland module, a phase-sensitive detection multiplier module (PSD), a cascaded integral comb-finite impulse response filter module (CIC-FIR), an effective value detection module (RMS), a coordinated rotation digital calculation square root inverse tangent module (CORDIC) and a discrete Hallett transform module (IDHT); the ADC module is used to convert the analog signal to be measured into a digital signal through the ADC module and send it to the PSD phase-sensitive detection multiplier module, the DDS-Sunderland module is used to generate a reference sine sequence and a reference cosine sequence and send them to the PSD phase-sensitive detection multiplier module, and the PSD phase-sensitive detection multiplier module is used to respectively compare the received digital signal to be measured with the reference signal. The reference sine sequence and the reference cosine sequence are multiplied to obtain two modulated signals, and the signals are sent to the CIC-FIR cascade filter module. The CIC-FIR cascade filter module is used to perform low-pass filtering on the received signal to filter out the double frequency and noise signal. The two modulated signals can obtain in-phase components and orthogonal components after filtering, and then send them to the RMS effective value detection module; the RMS effective value detection module is used to perform an average operation on the received sine component and cosine component to obtain two mean square value signals, and then send them to the CORDIC square root inverse tangent module. The CORDIC square root inverse tangent module is used to calculate the amplitude and phase information of the signal to be measured, and send it to the discrete Hallett transform module, which is used to convert the calculated amplitude and phase information of the signal to be measured into a time domain signal through a frequency domain signal.
[0008] Furthermore, the ADC module is connected to the input signal end through a small radio frequency coaxial connector (SMA), and uses an operational amplifier and a differential circuit internally to output an analog voltage. The bias voltage is then set through an AD chip to output a 12-bit digital signal of 0 to 8192.
[0009] Furthermore, the DDS-Sunderland module generates a reference sine sequence and a reference cosine sequence, specifically including the following:
[0010] The first step is to set the input to a continuous sinusoidal signal with known frequency and phase;
[0011] The second step is to use the frequency control word (F word ) and the phase control word (P word ) storing the accumulated data in the accumulation register and the synchronization register respectively so as to output discrete points;
[0012] The third step is to input the clock (F clk ), under the control of an N-bit frequency control word and an N-bit accumulator register, repeatedly and continuously accumulate feedback data; the data output by the N-bit accumulator is truncated to M bits, and then added to the M-bit phase control word, and a discrete sine signal is output by setting the number of sampling points, and the signal is read out through a table lookup in the first memory; wherein N represents the word length of the frequency control word, and M represents the word length of the sine and cosine signals obtained after processing;
[0013] The fourth step is to shift the output discrete sine signal by 90 degrees through the phase shifter, and use the second memory to perform a table lookup to read out the discrete cosine signal;
[0014] Among them, in the third and fourth steps, the table read includes fine-ROM and coarse-ROM. First, the coarse-ROM To roughly determine the frequency phase of the reading, and then read it accurately To accurately process the frequency phase, the two parts are summed and accumulated to reduce the size of the lookup table and increase the operating speed of the system; F coarse is the frequency obtained after rough reading, F coarse is the thick part of the frequency tuning word, M coarse is the truncated word length for coarse read.
[0015] Furthermore, the CIC-FIR cascade filter module is composed of a CIC-Hogenauer decimation filter and an FIR finite length filter in a cascade form. The specific steps of the filtering process are as follows:
[0016] The first step is to change the insertion filter order of the CIC-Hogenauer decimation filter through the R divider, assuming the input data rate is f s , then the down-sampling output signal; where R represents the frequency division coefficient, which is determined by the number of comb filters and integrators;
[0017] In the second step, the signal after downsampling by the CIC-Hogenauer decimation filter is smoothed by an FIR finite-length filter.
[0018] Furthermore, the discrete Hallett transform module is used to convert the amplitude and phase information of the measured signal obtained by calculation into a time domain signal through a frequency domain signal, which specifically includes the following contents:
[0019] Among them, for a finite length sequence x (n) The N-point discrete Hallett transform is defined as follows:
[0020]
[0021] The N-point discrete inverse Hallett transform is defined as:
[0022]
[0023] Where: cosα=cosα+sinα; n is a positive integer, N is the number of sampling points, and k is the transformation of the kth point.
[0024] The implementation of IDHT consists of the following three steps:
[0025] Step 1: For a signal of length n, construct an n×n Hallett inverse transform matrix H -1 .
[0026] Step 2: Perform matrix multiplication to calculate IDHT, x(n) = H -1 ×X(k).
[0027] Step 3: Check whether the output time domain signal has been padded with zeros in the first step. If so, trim the result to remove the zeros added before; if not, output it normally to obtain a time domain signal with the original signal length.
[0028] On the other hand, the present invention also provides a signal processing method for a high-speed digital lock-in amplifier based on FPGA, which specifically includes the following steps:
[0029] B1. Generate two sinusoidal reference signals. One channel keeps the sinusoidal signal unchanged, while the other channel converts the sinusoidal reference signal into a cosine reference signal through a 90° phase shifter.
[0030] B2. The two reference signals are sent to the phase-sensitive detector (PSD), i.e., the multiplier, together with the input signal to be measured, for multiplication. The result of the multiplication includes a DC signal component and a doubled frequency signal component.
[0031] B3. Filter out the double frequency component through a low-pass filter. According to the completeness of the sinusoidal signal, other random signals have no correlation with the reference signal, so the integration result is zero.
[0032] B4. The obtained DC component is passed through an effective value detector to obtain the mean component, that is, the output sine component and cosine component, and the amplitude and phase signals of the signal to be measured are obtained by calculation.
[0033] Furthermore, in step B1, the frequency of the signal to be measured is f, and the sampling frequency is f s , according to Nyquist sampling theorem, let f s =nf, where n≥2, the sampling interval In order to eliminate spectrum leakage, full-cycle sampling is selected; the signal is sampled for N cycles, and the total number of sampling points is M.
[0034] Furthermore, in step B2, the multiplication operation is specifically as follows:
[0035] The digital lock-in amplifier reference signal generation module generates sine and cosine reference sequences through FPGA programming:
[0036] The signal to be measured can be expressed as:
[0037] X[t]=A IN sin(2πft+θ)+n 0(t)
[0038] Among them, n 0(t) is the noise signal; A IN is the amplitude of the signal to be measured.
[0039] After ADC sampling, the signal sequence to be measured is expressed as:
[0040] X[k]=A IN sin(2πfkτ+θ)=A IN sin(2πk / n+θ)
[0041] Wherein, k=0, 1, 2, ..., M-1;
[0042] The digital lock-in amplifier reference signal generation module generates sine and cosine reference sequences through FPGA programming:
[0043] The sinusoidal reference sequence is expressed as:
[0044] Z[k]=A R sin(2πk / n)
[0045] The cosine reference sequence is expressed as:
[0046] Y[k]=A R cos(2πk / n)
[0047] Wherein, k=0, 1, 2, ..., M-1;
[0048] After the full cycle sampling, the Z[k] and Y[k] sequences are multiplied with X[k] to obtain the cross-correlation signal C of the sine and cosine component outputs. XZ and C XY for:
[0049]
[0050] Its amplitude and phase are obtained by calculation:
[0051]
[0052] The number of sampling points is M, and M correlation operations are required to filter the signal by taking the arithmetic average. XZ and C XY , thereby obtaining the amplitude and phase of the signal to be measured.
[0053] Compared with the prior art, the advantages of the present invention are as follows
[0054] 1. The present invention provides a multi-channel high-speed digital lock-in amplifier and signal processing method based on FPGA, which can solve the problem of processing weak signals, reduce the resource consumption and computing burden of FPGA chips, and achieve efficient detection and accurate processing of weak signals.
[0055] 2. The present invention solves the phase truncation spurious problem of traditional DDS frequency synthesis technology through the DDS-Sunderland frequency synthesis technology algorithm, significantly reducing resource consumption;
[0056] 3. The present invention solves the problem of poor narrow-band filtering effect of traditional digital phase-locked amplifier circuit filters through the CIC-FIR cascade filter, and can achieve a smooth filtering effect. BRIEF DESCRIPTION OF THE DRAWINGS
[0057] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly describes the drawings required for the specific embodiments or the description of the prior art. Similar elements or parts are generally identified by similar reference numerals throughout the drawings. Elements or parts in the drawings are not necessarily drawn to scale.
[0058] Figure 1 Design a flow chart for a quadrature vector digital lock-in amplifier;
[0059] Figure 2 Schematic diagram of a high-speed digital lock-in amplifier based on FPGA;
[0060] Figure 3 Schematic diagram of the DDS-Sunderland algorithm structure;
[0061] Figure 4 Design the structure diagram for the CIC-FIR cascade filter;
[0062] Among them, a is the CIC-Hogenauer decimation filter design flow chart; b is the CIC-FIR downsampling flow chart;
[0063] Figure 5 This is a schematic diagram of the FPGA internal IP call structure;
[0064] Figure 6 Schematic diagram of the overall effect of the digital lock-in amplifier realized by data processing in MATLAB;
[0065] Among them, a is the amplitude waveform of the cosine component test processing of the digital lock-in amplifier; b is the amplitude waveform of the cosine component test processing of the digital lock-in amplifier;
[0066] Figure 7 Schematic diagram of the high-speed digital lock-in amplifier implemented based on FPGA. DETAILED DESCRIPTION
[0067] In order to clearly and completely describe the technical solution and specific working process of the present invention, the specific implementation methods of the present invention are as follows in conjunction with the accompanying drawings:
[0068] Example 1
[0069] like Figure 1 As shown, this embodiment provides a design flow chart of an orthogonal vector digital lock-in amplifier based on FPGA, which specifically includes the following contents:
[0070] The signal to be measured serves as the input of the digital lock-in amplifier; the reference signal is generated as a sine sequence within the FPGA, and the phase is shifted 90 degrees by the phase shifter to generate a cosine sequence; the two signals enter the phase-sensitive detection module for multiplication, and the resulting mixed signal is filtered out with a low-pass filter to remove the doubled frequency component. The resulting DC component is then passed through an effective value detector to obtain the orthogonal component and the in-phase component; the final amplitude and phase information are calculated.
[0071] like Figure 2 As shown, a high-speed digital lock-in amplifier based on FPGA in this embodiment includes: an ADC module, a DDS-Sunderland module, a PSD phase-sensitive detection multiplier module, a CIC-FIR cascade filter module, an RMS effective value detection module, a CORDIC square root inverse tangent module and an IDHT module;
[0072] The ADC module is used to convert the analog signal to be measured into a digital signal through the ADC module.
[0073] The ADC module is connected to the input signal terminal through a small RF coaxial connector (Subminiature version A, SMA). It uses an operational amplifier and differential circuit to output analog voltage. The bias voltage is then set through an AD chip to output a 12-bit digital signal of 0 to 8192.
[0074] The DDS-Sunderland module is used to generate a reference sine sequence and a reference cosine sequence. The specific method is as follows:
[0075] The first step is to set the input to a continuous sinusoidal signal with known frequency and phase;
[0076] The second step is to use the frequency control word (P word ) and the phase control word (P word ) storing the accumulated data in the accumulation register and the synchronization register respectively so as to output discrete points;
[0077] The third step is to input the clock (F clk ), under the control of an N-bit frequency control word and an N-bit accumulator register, the feedback data is repeatedly accumulated in a loop; the data output by the N-bit accumulator is truncated to M bits, and then added to the M-bit phase control word, and a discrete sine signal is output by setting the number of sampling points, and is read out through a table lookup in memory 1; wherein N represents the word length of the frequency control word, and M represents the word length of the sine and cosine signals obtained after processing;
[0078] The fourth step is to shift the output discrete sine signal by 90 degrees through the phase shifter, and use the memory 2 to read out the discrete cosine signal by table lookup;
[0079] Among them, the table reading part of the third and fourth steps is divided into two parts: fine-ROM and coarse-ROM. To roughly determine the frequency phase of the reading, and then read it accurately To accurately process the frequency phase, the two parts are summed and accumulated to reduce the size of the lookup table and increase the operating speed of the system; F coarse is the frequency obtained after rough reading, F coarse is the thick part of the frequency tuning word, M coarse is the truncated word length for coarse read.
[0080] The PSD phase-sensitive detection multiplier module is used to perform multiplication operations on the received digital signal to be measured with a reference sine sequence and a reference cosine sequence respectively to obtain two modulation signals.
[0081] The CIC-FIR cascade filter module is composed of a CIC-Hogenauer decimation filter and an FIR finite length filter in a cascade form. The specific filtering method is as follows:
[0082] The first step is to change the insertion filter order of the CIC-Hogenauer decimation filter through the R divider, assuming the input data rate is f s , then the down-sampling output signal; where R represents the frequency division coefficient, which is determined by the number of comb filters and integrators;
[0083] In the second step, the signal after downsampling by the CIC-Hogenauer decimation filter is smoothed by an FIR finite length filter;
[0084] In the third step, the two modulated signals received are low-pass filtered separately through the CIC-FIR cascade filter to filter out the double frequency and noise signals. After filtering, the in-phase component and the orthogonal component of the two modulated signals can be obtained.
[0085] like Figure 4 The b is the downsampling flow chart of the CIC-FIR cascade filter. The input sequence is downsampled by the N-stage CIC-Hogenauer decimation filter and the FIR finite length filter compensates for the passband attenuation to achieve signal filtering and acquisition. Among them: the transfer function of the N-stage CIC filter is: Where: R represents the decimation factor, (R-1)×N=D represents the delay factor. The transfer function of the FIR filter is: Where N is the tap coefficient and h(n) is the filter coefficient.
[0086] The RMS effective value detection module is used to perform an average operation on the received sine component and cosine component to obtain two mean square value signals.
[0087] The CORDIC square root inverse tangent module is used to calculate the amplitude and phase information of the signal to be measured;
[0088] The discrete Hallett transform module is used to convert the amplitude and phase information of the measured signal obtained by calculation into a time domain signal through a frequency domain signal;
[0089] For a finite length sequence x (n) The N-point DHT transformation is defined as follows:
[0090]
[0091] The N-point IDHT transform is defined as:
[0092]
[0093] Where: casα = cosα + sinα, n is a positive integer, N is the number of sampling points, and k is the transformation of the kth point.
[0094] The implementation of IDHT consists of the following three steps:
[0095] Step 1: For a signal of length n, construct an n×n Hallett inverse transform matrix H -1 .
[0096] Step 2: Perform matrix multiplication to calculate IDHT, x(n) = H -1 ×X(k).
[0097] Step 3: Check whether the output time domain signal has been padded with zeros in the first step. If so, trim the result to remove the zeros added before; if not, output it normally to obtain a time domain signal of the original signal length.
[0098] The above method can realize high-speed digital lock-in amplifier processing based on FPGA.
[0099] Example 2
[0100] This embodiment provides a signal processing method for a high-speed digital lock-in amplifier based on FPGA, which specifically includes the following steps:
[0101] B1. Generate two sinusoidal reference signals. One channel keeps the sinusoidal signal unchanged, while the other channel converts the sinusoidal reference signal into a cosine reference signal through a 90° phase shifter.
[0102] B2. The two reference signals are sent to the phase-sensitive detector (PSD), i.e., the multiplier, together with the input signal to be measured, for multiplication. The result of the multiplication includes a DC signal component and a doubled frequency signal component.
[0103] B3. Filter out the double frequency component through a low-pass filter. According to the completeness of the sinusoidal signal, other random signals have no correlation with the reference signal, so the integration result is zero.
[0104] B4. The obtained DC component is passed through an effective value detector to obtain the mean component, that is, the output sine component and cosine component, and the amplitude and phase signals of the signal to be measured are obtained by calculation.
[0105] In step B1, the frequency of the signal to be measured is f, and the sampling frequency is f s , according to Nyquist sampling theorem, let f s =nf, where n≥2, the sampling interval In order to eliminate spectrum leakage, full cycle sampling is selected; the signal is sampled for N cycles, and the total number of sampling points is M;
[0106] In step B2, the multiplication operation is specifically as follows:
[0107] The digital lock-in amplifier reference signal generation module generates sine and cosine reference sequences through FPGA programming:
[0108] The signal to be measured can be expressed as:
[0109] X[t]=A IN sin(2πft+θ)+n 0(t)
[0110] Among them, n 0(t) is the noise signal; A IN is the amplitude of the signal to be measured.
[0111] Since there is coherence between the measured signal and the reference signal, but there is basically no coherence with the noise signal, the influence of noise is ignored in the calculation process.
[0112] After ADC sampling, the signal sequence to be measured can be expressed as:
[0113] X[k]=A IN sin(2πfkτ+θ)=A IN sin(2πk / n+θ)
[0114] Where k = 0, 1, 2..., M-1.
[0115] The digital lock-in amplifier reference signal generation module generates sine and cosine reference sequences through FPGA programming:
[0116] The sinusoidal reference sequence can be expressed as:
[0117] Z[k]=A R sin(2πk / n)
[0118] The cosine reference sequence can be expressed as:
[0119] Y[k]=A R cos(2πk / n)
[0120] Wherein, k=0, 1, 2, ..., M-1.
[0121] After the full cycle sampling, the Z[k] and Y[k] sequences are multiplied with X[k] to obtain the cross-correlation signal C of the sine and cosine component outputs. XZ and C XY for:
[0122]
[0123] Its amplitude and phase can be obtained by calculation:
[0124]
[0125] The above process is the principle of cross-correlation operation, which is the core algorithm principle of digital lock-in amplifier. The algorithm is implemented by FPGA software programming. The number of sampling points is M, and M correlation operations are required. The arithmetic average is performed to filter the signal. By analyzing the above process, it can be found that only C XZ and C XY , the amplitude and phase of the signal to be measured can be obtained.
[0126] like Figure 5 The overall design flow chart of the FPGA chip shown in the figure specifically includes the following contents:
[0127] The ADC module inputs the test signal and connects it to the FPGA chip pin through the IO interface. The input signal is collected and converted into a digital signal, and the input digital signal is temporarily stored in the FIFO data buffer. The FPGA core board pin is connected to the 50Mz clock of the PL end as the input clock, and the PLL phase-locked loop module is used to realize the frequency division or multiplication operation of the clock signal to drive the ADC and the internal system of the FPGA. The DDS synthesized sine and cosine reference sequence is used by the ROM core to realize data transmission. A Booth encoding IP core is established, and multiplication operations are performed in two ways. The CIC-FIR filter IP core is used for filtering to filter out the doubled frequency signal. The DC component is then taken through the RMS IP core to achieve the mean square value operation. Finally, the DC signal after the mean square value is taken is processed by the CORDIC IP core into amplitude and phase information. After setting up multiple reference signals, the frequency domain information of the multiple amplitudes and phases is IDHT to obtain the final time domain signal, which is finally displayed on the PC.
[0128] See also Figure 6-7 The figure shows the simulation implementation content in the embodiment of the present invention, including a schematic diagram of the overall effect of the digital phase-locked amplifier implemented by MATLAB data simulation and a schematic diagram of the high-speed digital phase-locked amplifier results based on FPGA. It shows the process of multiplying the reference signal and the small signal to be measured, filtering, and taking the average operation to obtain the amplitude and phase information.
[0129] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the scope of protection of the present invention.
[0130] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any appropriate manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.
[0131] In addition, the various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.
Claims
1. A multi-channel high-speed digital lock-in amplifier based on FPGA, characterized in that: The system comprises an analog-to-digital conversion module, a DDS-Sunderland module, a phase-sensitive detection multiplier module, a cascaded integral comb-finite impulse response filter module, an effective value detection module, a coordinated rotation digital calculation square root inverse tangent module and a discrete Hallett transform module; the ADC module is used to convert the analog signal to be measured into a digital signal through the ADC module and send it to the PSD phase-sensitive detection multiplier module, the DDS-Sunderland module is used to generate a reference sine sequence and a reference cosine sequence and send them to the PSD phase-sensitive detection multiplier module, the PSD phase-sensitive detection multiplier module is used to multiply the received digital signal to be measured with the reference sine sequence and the reference cosine sequence respectively to obtain two modulation signals, and send them to the PSD phase-sensitive detection multiplier module. The signals are sent to the CIC-FIR cascade filter module, which is used to perform low-pass filtering on the received signals to filter out the double frequency and noise signals. The two modulated signals can obtain in-phase components and orthogonal components after filtering, and then send them to the RMS effective value detection module; the RMS effective value detection module is used to perform an average operation on the received sine component and cosine component to obtain two mean square value signals, and then send them to the CORDIC square root inverse tangent module. The CORDIC square root inverse tangent module is used to calculate the amplitude and phase information of the signal to be measured, and send it to the discrete Hallett transform module, which is used to convert the calculated amplitude and phase information of the signal to be measured into a time domain signal through a frequency domain signal.
2. The FPGA-based multi-channel high-speed digital lock-in amplifier according to claim 1, wherein: The ADC module is connected to the input signal end through a small RF coaxial connector, and uses an operational amplifier and a differential circuit to output an analog voltage. The bias voltage is then set through an AD chip to output a 12-bit digital signal of 0 to 8192.
3. The FPGA-based multi-channel high-speed digital lock-in amplifier according to claim 1, wherein: The DDS-Sunderland module generates a reference sine sequence and a reference cosine sequence, specifically including the following: The first step is to set the input to a continuous sinusoidal signal with known frequency and phase; The second step is to use the frequency control word F word With the phase control word P word The accumulated data are stored in the accumulation register and the synchronization register respectively so as to output discrete points; The third step is to input the clock F clk Under the control of , the N-bit frequency control word and the N-bit accumulator register repeatedly accumulate the feedback data; the data output by the N-bit accumulator is truncated to M bits, and then added to the M-bit phase control word, and a discrete sine signal is output by setting the number of sampling points, and is read out through a table lookup through the first memory; wherein N represents the word length of the frequency control word, and M represents the word length of the sine and cosine signals obtained after processing; The fourth step is to shift the output discrete sine signal by 90 degrees through the phase shifter, and use the second memory to perform a table lookup to read out the discrete cosine signal; Among them, in the third and fourth steps, the table read includes fine-ROM reading and coarse-ROM reading. First, the coarse read To roughly determine the frequency phase of the reading, and then read it accurately To accurately process the frequency phase, the two parts are summed and accumulated to reduce the size of the lookup table and increase the operating speed of the system; F coarse is the frequency obtained after rough reading, F coarse is the thick part of the frequency tuning word, M coarse is the truncated word length for coarse read.
4. The FPGA-based multi-channel high-speed digital lock-in amplifier according to claim 1, wherein: The CIC-FIR cascade filter module is composed of a CIC-Hogenauer decimation filter and an FIR finite length filter in cascade form. The specific steps of the filtering process are as follows: The first step is to change the insertion filter order of the CIC-Hogenauer decimation filter through the R divider, assuming the input data rate is f s , then the down-sampling output signal; where R represents the frequency division coefficient, which is determined by the number of comb filters and integrators; In the second step, the signal after downsampling by the CIC-Hogenauer decimation filter is smoothed by an FIR finite-length filter.
5. The FPGA-based multi-channel high-speed digital lock-in amplifier according to claim 1, wherein: The discrete Hallett transform module is used to convert the amplitude and phase information of the measured signal into a time domain signal through the frequency domain signal, which specifically includes the following contents: Among them, for a finite length sequence x (n) The N-point discrete Hallett transform is defined as follows: The N-point discrete inverse Hallett transform is defined as: Where: casα = cosα + sinα; n is a positive integer, N is the number of sampling points, and k is the transformation of the kth point.
6. The FPGA-based multi-channel high-speed digital lock-in amplifier according to claim 1, wherein: The implementation of the IDHT module specifically includes the following three steps: Step 1: For a signal of length n, construct an n×n Hallett inverse transform matrix H -1 ; Step 2: Perform matrix multiplication to calculate IDHT, x(n) = H -1 ×X(k); Step 3: Check whether the output time domain signal has been padded with zeros in the first step. If so, trim the result to remove the zeros added before; if not, output it normally to obtain a time domain signal with the original signal length.
7. The signal processing method of a multi-channel high-speed digital lock-in amplifier based on FPGA according to claim 1, characterized in that: The specific steps include: B1. Generate two sinusoidal reference signals. One channel keeps the sinusoidal signal unchanged, while the other channel converts the sinusoidal reference signal into a cosine reference signal through a 90° phase shifter. B2. The two reference signals are sent to the phase-sensitive detector PSD, i.e., the multiplier, together with the input signal to be measured, for multiplication. The result of the multiplication operation includes a DC signal component and a doubled frequency signal component. B3. Filter out the double frequency component through a low-pass filter. According to the completeness of the sinusoidal signal, other random signals have no correlation with the reference signal, so the integration result is zero. B4. The obtained DC component is passed through an effective value detector to obtain the mean component, that is, the output sine component and cosine component, and the amplitude and phase signals of the signal to be measured are obtained by calculation.
8. The signal processing method of a multi-channel high-speed digital lock-in amplifier based on FPGA as claimed in claim 7, characterized in that: In step B1, the frequency of the signal to be measured is f, and the sampling frequency is f s , according to Nyquist sampling theorem, let f s =nf, where n≥2, the sampling interval In order to eliminate spectrum leakage, full-cycle sampling is selected; the signal is sampled for N cycles, and the total number of sampling points is M.
9. The signal processing method of a multi-channel high-speed digital lock-in amplifier based on FPGA according to claim 7, characterized in that: In step B2, the multiplication operation is specifically as follows: The digital lock-in amplifier reference signal generation module generates sine and cosine reference sequences through FPGA programming: The signal to be measured can be expressed as: X[t]=A IN sin(2πft+θ)+n 0(t) Among them, n 0(t) is the noise signal; A IN is the amplitude of the signal to be measured. After ADC sampling, the signal sequence to be measured is expressed as: X[k]=A IN sin(2πfkτ+θ)=A IN sin(2πk / n+θ) Wherein, k=0, 1, 2, ..., M-1; The digital lock-in amplifier reference signal generation module generates sine and cosine reference sequences through FPGA programming: The sinusoidal reference sequence is expressed as: Z[k]=A R sin(2πk / n) The cosine reference sequence is expressed as: Y[k]=A R cos(2πk / n) Wherein, k=0, 1, 2, ..., M-1; After the full cycle sampling, the Z[k] and Y[k] sequences are multiplied with X[k] to obtain the cross-correlation signal C of the sine and cosine component outputs. XZ and C XY for: Its amplitude and phase are obtained by calculation: The number of sampling points is M, and M correlation operations are required to filter the signal by taking the arithmetic average. XZ and C XY , thereby obtaining the amplitude and phase of the signal to be measured.