ASIC circuit design method of Ethernet UDP / IP protocol stack

Abstract

The invention provides an ASIC (Application Specific Integrated Circuit) circuit design method of a gigabit Ethernet UDP / IP protocol stack aiming at the problems that the current UDP / IP protocol stack function is realized by software, the burden on a CPU (Central Processing Unit) is large, the power consumption is relatively high and the transmission speed is low, the function from a data link layer to a transmission layer is realized through hardware, the burden of the CPU is reduced, and the data transmission efficiency is improved. According to the method, a UDP / IP protocol stack is constructed on an ASIC hardware level, a state machine is used for controlling data packaging and analysis, and the ASIC is used for achieving UDP / IP protocol design of a gigabit Ethernet system. The system comprises an FPGA module, an RGMII module, an ARP top layer module, a UDP top layer module and an Ethernet control module. The verification rate of the FPGA can reach 165 Mbps; according to the ASIC design based on the SMIC 0.18 [mu] m CMOS process, layout, wiring and a clock tree are optimized by adopting a comprehensive and back-end design tool, and the power consumption is reduced; finally, the area of the ASIC is only 0.221 square millimeters, the ASIC supports a 125MHz clock, the average power consumption is 15.34 microwatts, full duplex gigabit transmission is realized, the load of a CPU (Central Processing Unit) is obviously reduced, and the network communication efficiency of Internet of Things equipment is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and in particular relates to an Ethernet UDP / IP protocol stack circuit implemented based on FPGA hardware and an ASIC design method thereof. Background Art

[0002] In recent years, the Internet of Things (IoT) technology has shown explosive growth. More and more embedded devices need to access the Internet for data transmission and remote control. The demand for embedded devices to "go to the cloud" is constantly increasing, and the importance of Ethernet in data transmission is becoming increasingly prominent.

[0003] However, many current microprocessors (MCUs) or system-on-chips (SoCs) used in IoT and industrial control devices only integrate Ethernet MAC layer hardware, while the IP protocol stack still relies on software implementation. While this software implementation approach offers a certain degree of flexibility, it also presents numerous problems. First, the software-implemented IP protocol stack requires significant CPU resources to encode and decode data packets, which undoubtedly increases the CPU burden. This can lead to system performance bottlenecks, especially in high-data-traffic scenarios, and affect overall data transmission efficiency. Second, because the CPU needs to handle other tasks while processing network protocols, this multitasking approach can easily introduce delays, which in turn affects the real-time and reliability of data transmission. Therefore, there is an urgent need for a hardware-implemented Gigabit Ethernet UDP / IP protocol stack solution to meet the needs of high-speed, low-power data transmission.

[0004] In summary, with the rapid development of the Internet of Things, the demand for high-speed, low-power and reliable network communication solutions is becoming increasingly urgent. The traditional software implementation of the IP protocol stack has gradually become difficult to meet the requirements of modern embedded devices, and the IP protocol stack based on hardware implementation, especially ASIC implementation, provides a feasible and efficient method to solve this problem. In this context, the present invention proposes an ASIC circuit design for a Gigabit Ethernet UDP / IP protocol stack, which aims to implement the functions from the data link layer to the transport layer through hardware, thereby significantly improving data transmission efficiency, reducing power consumption, and meeting the strict requirements of Internet of Things devices for real-time performance and reliability. Summary of the Invention

[0005] This application aims to provide an ASIC circuit design method for a Gigabit Ethernet UDP / IP protocol stack, which implements the functions from the data link layer to the transport layer through hardware, thereby significantly reducing the CPU burden, improving data transmission efficiency, and meeting the needs of the Internet of Things and embedded devices for high-speed, low-power data transmission.

[0006] The core content of the design is as follows:

[0007] The first aspect proposes a design method for implementing the UDP / IP protocol of the Gigabit Ethernet system using ASIC.

[0008] Step 1: First, make a top-level design for the overall system. The entire module is divided into GMII&RGMII module, UDP top-level module, ARP top-level module, and Ethernet control module. Use the state machine to design each sub-module one by one.

[0009] Step 2: The GMII & RGMII module serves as the input and output hub of the block, connecting to the external RGMII interface. It receives the RGMII RX clock signal, uses it as the system clock for the entire block, and receives the RGMII data signal. It is internally divided into two sub-modules: receiving and transmitting. It can convert the received 4-bit RGMII data into 8-bit GMI data, and can also convert the transmitted 8-bit GMII data into 4-bit RGMII data simultaneously.

[0010] Step 3: The UDP module can be designed into two submodules: the UDP receiver module and the UDP transmitter module. The UDP receiver module design includes a seven-state machine: st_idle, st_preamble, st_eth_head, st_ip_head, st_udp_head, st_rx_data, and st_rx_end. This implements layer-by-layer data parsing from the physical layer to the application layer. A four-level progressive verification mechanism ensures the integrity of protocol parsing: preamble detection (8′h55 sequence recognition), Ethernet frame header checksum (MAC address filtering + protocol type verification), IP header parsing (destination IP matching), and UDP header processing (dynamic calculation of data segment length). Similar to the UDP receiver module, the UDP transmitter module includes a seven-state machine: st_idle, st_check_sum, st_preamble, st_eth_head, st_ip_head, st_tx_data, and st_crc. This implements reverse protocol encapsulation from application layer data to physical layer frames. A progressive processing mechanism, including checksum precalculation, dynamic padding of protocol fields, and CRC post-processing, ensures the reliability of protocol encapsulation.

[0011] Step 4: The ARP module can be designed as two submodules: the ARP receiving module and the ARP sending module. The ARP receiving module uses the five states of st_idle, st_preamble, st_eth_head, st_arp_data, and st_rx_end to accurately parse the ARP data frame. It establishes a vertical verification system from the physical layer to the application layer through physical layer preamble segment verification (immediate triggering of the first byte and batch detection of the last 6 bytes), link layer two-factor verification (dual matching of the target MAC address and protocol type), and dynamic network layer address determination (preset IP address matching and ARP opcode parsing). The ARP sending module uses the five states of st_idle, st_preamble, st_eth_head, st_arp_data, and st_erc to complete the encapsulation process from the logical layer request to the physical layer frame. The reliability of network communications is significantly improved through dynamic address filling (automatically detecting the target device MAC / IP address as empty in the initial state and calling the ARP cache data to complete the intelligent filling), self-consistent generation of protocol fields (dynamically setting the ARP request / response type (OP code) according to arp_tx_type to achieve two-way protocol interaction support), and CRC delayed insertion (appending the CRC check result after the data segment is sent, in compliance with the Ethernet frame integrity specification).

[0012] Step 5: The Ethernet control module is used to control the output of GMII. That is, when the previous UDP data packet is sent and the ARP module does not receive data, it controls the UDP sending module to transmit data to the GMII & RGMII conversion module to complete the sending of the UDP data packet.

[0013] Step 6: After completing the design of the top-level module, the present invention uses FPGA to perform prototype verification for data transmission. First, the FPGA phase-locked loop resources are used to achieve a frequency multiplication effect to meet the clock requirements, and a synchronous FIFO and ROM core are established for loop testing; then, two open source software, Xcap and Wireshark, are used as the host computer for data testing; during the test process, Xcap is mainly used to select the corresponding network card and construct traffic, perform flow triggering operations, and can accurately simulate network traffic. Wireshark is responsible for capturing these data packets and performing in-depth analysis. Finally, the test results show that there are no bit errors when 3 million groups of messages are transmitted, and the packet loss rate is 0.0002%, which meets the design requirements. The feasibility of the design is proved, laying the foundation for the subsequent ASIC design of the UDP / IP protocol stack.

[0014] Step 7: After verifying the correctness of the overall UDP / IP protocol module, ASIC synthesis and back-end design were performed. First, in a Linux environment, Design Compiler reads the setup file in the current directory (which configures process libraries, link libraries, and other parameters based on a TCL script). After startup, a graphical interface is used to read the HDL file and specify the top-level module to generate the RTL schematic. During synthesis, a timing constraint script is used to set the clock period to 8ns (125MHz), clock uncertainty, signal delay, and the "don't_touch" attribute on the reset network (to prevent optimization from affecting fanout). The maximum fanout of cells is limited to 8, and the CLKINV2 driver unit is selected. Next, a netlist is generated using "compiler_ultra" synthesis. The timing report shows a maximum critical path delay of 7.51ns and a slack of 0ns, achieving a balance between timing and area. Finally, Cadence Innovus EDA software is used for floorplanning and power planning, respectively determining the location of ports and macro cells, as well as power supply stability and routing space.

[0015] The present application provides an ASIC circuit design method and verification scheme for a Gigabit Ethernet UDP / IP protocol stack. The method includes: constructing a UDP / IP protocol stack at the hardware level, and accurately controlling the data encapsulation and parsing process through a state machine. Prototype verification is performed on an FPGA platform, Verilog code is deployed, and data transmission testing is performed using related software. Subsequently, ASIC synthesis and back-end design are carried out based on the SMIC 0.18um CMOS process, and professional tools are used to complete logic synthesis, layout and routing, and clock tree optimization. At the same time, low-power strategies are adopted to reduce power consumption. Through the above steps, the present application effectively improves data transmission efficiency, reduces power consumption and CPU load, and provides an efficient solution for network communication of IoT devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is the working diagram of the main modules

[0017] Figure 2 This is a workflow diagram

[0018] Figure 3 This is the state transition diagram of the udp_rx module

[0019] Figure 4 This is the state transition diagram of the udp_tx module

[0020] Figure 5 This is the state transition diagram of the arp_rx module

[0021] Figure 6This is the state transition diagram of the arp_tx module DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0023] In one embodiment, the FPGA prototype verification, hardware architecture and functional module implementation, and ASIC implementation process include the following steps:

[0024] Step 1: FPGA Prototype Verification. First, perform RTL design, using an HDL language (such as Verilog or VHDL) to describe the digital logic to implement the functionality. Modifying the RTL design involves converting the ASIC-standard code into FPGA code. Considering the FPGA platform's resource limitations on I / O, PLLs, multi-processor modules (MMCMs), and RAM, the impact of hardware resource limitations should be minimized while maintaining equivalent ASIC design functionality. Evaluate the FPGA's performance, including processing speed, power consumption, and resource utilization. If performance issues are identified, optimize and adjust accordingly. Compile and download testing involves using EDA tools to compile and download the designed FPGA code to the FPGA development board. Verify its functional accuracy by observing waveforms or other methods. The ASIC RTL code is then modified to accommodate the FPGA's internal resources. The FPGA's system clock is typically derived from the onboard clock through frequency multiplication and division by a PLL or multi-processor module (MMCM). However, the module designed in this paper utilizes pure digital logic, so its clock must be a multiplied 125 MHz. In specific applications, clock signals of varying frequencies within the ASIC are typically generated using a PLL. For Xilinx FPGAs, the Clocking Wizard IP wizard can be used to create a clock IP core. The onboard clock on this board is 50MHz, while the system operates at 200MHz. Therefore, the IP is configured to use MMCM for quadruple clock multiplication, generating a 200MHz clock, clk_out1. RAM resources are then configured, requiring a synchronous FIFO to receive udp_rx data and transmit udp_tx data for loopback testing. Distributed RAM resources within the FPGA have a very small capacity, ranging from a few hundred to a few thousand bits, so a large-capacity block RAM is used for the synchronous FIFO. The IP is configured to generate a 32-bit block RAM with a depth of 2048. Finally, performance and resource consumption are tested using Vivado software synthesis and layout and UDP data loopback for download testing.

[0025] Step 2: Hardware architecture and functional module implementation The UDP / IP protocol stack hardware circuit of the present invention is based on ASIC design and adopts a layered architecture to implement protocol processing functions from the data link layer to the transport layer.

[0026] First, the system features a GMII / RGMII interface conversion module, configured as a bidirectional data path, enabling real-time conversion between 4-bit data from the external RGMII interface and 8-bit data from the internal GMII interface. The receiver integrates a clock recovery circuit, using a phase-locked loop (PLL) to extract the 125MHz system clock from the RGMII_RXC pin. On the transmitter side, data alignment logic ensures phase synchronization between the TXC pin and the TXD pin. Second, the system includes a protocol parsing and encapsulation module. The UDP processing unit utilizes a dual-state machine architecture. The receive state machine parses the preamble, Ethernet header, IP header, and UDP header according to the Ethernet frame structure, performing a simultaneous check for the destination MAC / IP address during the parsing process. The transmit state machine dynamically generates protocol header fields based on pre-set rules and integrates a hardware checksum generator, enabling single-cycle calculation of the IP header checksum. Furthermore, the module's ARP coprocessor features a dynamic address mapping table, utilizing a CAM (content-addressable memory) structure to rapidly query and update MAC-IP address pairs. Upon detecting an unknown destination IP address, it triggers the automatic generation and broadcast of an ARP request frame. In addition, the system is also equipped with a data buffer and control module, which integrates dual-port SRAM as a data buffer and adopts a pipeline architecture at the receiving end to achieve decoupling of protocol parsing and data storage; the sending end uses priority arbitration logic to coordinate the conflict management between UDP data transmission and ARP response.

[0027] Step 3: ASIC implementation process. In the ASIC implementation process, the UDP / IP protocol stack hardware circuit of the present invention first undergoes logic synthesis and optimization. Synopsys Design Compiler is used to perform process mapping on the RTL code, and the target process is selected as the SMIC 0.18μm CMOS library. During this process, constraints such as a 125MHz system clock and a maximum fan-out number not exceeding 8 are set, and a 10% timing margin is set for the critical path. At the same time, the RTL hierarchy is retained through topological constraints (Topographical Mode), and physical perception synthesis is implemented for the UDP receiving / transmitting module to reduce the risk of timing violations in the subsequent layout and routing stage. In its layout planning, a rectangular layout with an aspect ratio of 1:4 is adopted, and a 20μm power ring space is reserved around the core area. The IO pins are arranged in functional groups, with the receiving end signal concentrated on the left and the transmitting end signal concentrated on the right, thereby effectively reducing signal crosstalk. The clock tree synthesis phase utilizes Cadence Innovus' CCD (Concurrent Clock Data) optimization engine and inserts cascaded clock buffers (CLKBUFX8 / CLKINVX4) to precisely control clock skew to less than 50ps. Furthermore, for low-power design, power gating is applied to idle logic cells, while a dynamic voltage frequency scaling (DVFS) module is introduced to adaptively adjust clock frequency based on data traffic. Ultimately, power consumption is successfully reduced to 3.2μW in idle state.

[0028] Verification and Target Achievement: Using PrimeTime for multi-condition timing analysis, the worst negative timing slack (WNS) was 0.04ns at the SS (Slow-Slow) process corner, meeting gigabit speed requirements. IR drop analysis was performed using RedHawk, and the power network design ensured voltage fluctuations were less than 5%. The final layout area was 228.36μm × 967.68μm, with an average power consumption of 15.34μW.

[0029] Technical Effects

[0030] The present invention achieves the following core advantages through hardware protocol stack design:

[0031] By implementing the functions of the data link layer to the transport layer through hardware, this design can support full-duplex Gigabit Ethernet data transmission at a system clock frequency of 125MHz, with an average power consumption of only 15.34 microwatts. Compared with traditional software implementation methods, it not only greatly improves the data transmission rate, but also significantly reduces power consumption, meeting the needs of the Internet of Things and embedded devices for high-speed, low-power data transmission. Following the AMBAAXI bus standard, the design has good modularity. This modular design allows the protocol stack to be seamlessly integrated into the system-on-chip (SoC) through a standard interface and reused as an independent IP core. This not only improves the system's integration, but also simplifies the connection with other hardware components, enhances its applicability in a variety of application environments, and reduces development costs and time. In the key ARP address resolution function, this design achieves a low latency of ≤2 microseconds. The above embodiments fully disclose the technical details of the present invention, and those skilled in the art can implement the technical solution of the present invention based on the described content.

Claims

1. A method for designing an ASIC circuit for a Gigabit Ethernet UDP / IP protocol stack, characterized in that: It includes a GMII&RGMII module, an ARP top-level module, a UDP top-level module and an Ethernet control module; the GMII&RGMII module serves as an input and output hub, is connected to the external RGMII interface, receives the RX clock signal of RGMII as the system clock, and receives the data signal of RGMII. It is internally divided into two sub-modules, receiving and sending, for converting the received 4-bit RGMII data into 8-bit GMII data and converting the sent 8-bit GMII data into 4-bit RGMII data; the ARP top-level module is used to execute routing logic, record the MAC address corresponding to the destination IP, and encapsulate the Ethernet frame header. If there is no corresponding MAC address in the cache, it actively sends an ARP request and records the MAC address of the destination IP; the UDP top-level module contains two parts of logic, sending and receiving, corresponding to the two processes of encapsulation and unpacking; the Ethernet control module is used to control the output of GMII. When the previous frame of UDP data packet is sent and the ARP module has not received data, it controls the UDP sending module to transmit data to the GMII&RGMII conversion module to complete the sending of the UDP data packet.

2. The ASIC circuit design method for a Gigabit Ethernet UDP / IP protocol stack according to claim 1, wherein: FPGA prototype verification was adopted, the ASIC code was modified to maximize the use of FPGA hardware resources, and the high-performance Xilinx Zynq 7020 platform was adopted to achieve full-link Gigabit Ethernet test conditions.

3. The ASIC circuit design method for a Gigabit Ethernet UDP / IP protocol stack according to claim 1, wherein: The physical design of the synthesized UDP / IP protocol stack logic netlist file was carried out using Cadence Innovus EDA tools. Based on the SMIC 0.18um CMOS process, the layout and routing, timing optimization and other processes were carried out to complete the block-level physical layout design.

4. The ASIC circuit design method for a Gigabit Ethernet UDP / IP protocol stack according to claim 1, wherein: The receiving module of the UDP top-level module obtains the UDP data segment by parsing the UDP frame structure. The specific steps are as follows: (1) In the initial state, wait for the arrival of the data reception signal and detect whether the first byte of the preamble is received. If so, enter the preamble detection state. (2) In the preamble detection state, determine whether the subsequent bytes are in the correct preamble format. If so, enter the Ethernet frame header receiving state; otherwise, enter the error handling state. (3) In the state of receiving Ethernet frame header, store the destination device MAC address and network type data, detect whether the destination MAC address is the preset value or the broadcast value, and determine whether the network type is the IPv4 UDP protocol. If so, enter the state of receiving IP header, otherwise enter the error handling state. (4) In the receiving IP header state, extract the destination IP data, check whether it is the preset value, and determine whether the IP header byte number requirement is met. If so, enter the receiving UDP header state, otherwise enter the error handling state. (5) In the UDP header receiving state, obtain the total number of bytes of the UDP header and data segment, and calculate the number of bytes of the UDP data segment. (6) In the UDP data receiving state, UDP data segment data is received according to the number of bytes. (7) In the receiving end state, wait for the current frame data to be sent and then return to the initial state.

5. The ASIC circuit design method for a Gigabit Ethernet UDP / IP protocol stack according to claim 1, wherein: The sending module of the UDP top-level module sends the UDP data segment according to the UDP frame structure. The specific steps are as follows: (1) In the initial state, wait for the arrival of the data sending signal, prepare the data of the IP header and Ethernet header, and detect whether the MAC and IP of the receiving device are empty. If they are empty, use the data in the ARP module list to assign values. After completing the operation, enter the data checksum calculation state. (2) In the data checksum calculation state, calculate the checksum of the UDP header and the data segment, and fill the result into the corresponding position of the IP header. (3) In the preamble sending state, the preamble of the specified byte is sent. (4) In the Ethernet frame header sending state, the destination device MAC address, source device MAC address and network type identification number are sent in sequence. (5) In the state of sending the IP header, the data of each field of the IP header is sent in sequence. (6) In the UDP data sending state, the UDP data segment data is split into multiple bytes and sent. (7) In the state of sending CRC check result, the CRC data generated by the CRC module is sent, and after sending, it returns to the initial state.

6. The ASIC circuit design method for a Gigabit Ethernet UDP / IP protocol stack according to claim 1, wherein: The ARP receiving module is used to receive the ARP data segment, and the specific steps are as follows: (1) In the initial state, wait for the arrival of the data reception signal and detect whether the first byte of the preamble is received. If so, enter the preamble detection state. (2) In the preamble detection state, determine whether the subsequent bytes are in the correct preamble format. If so, enter the Ethernet frame header receiving state; otherwise, enter the error handling state. (3) In the state of receiving Ethernet frame header, store the destination device MAC address and network type data, detect whether the destination MAC address is the preset value or the broadcast value, and determine whether the network type is the IPv4 UDP protocol. If so, enter the state of receiving ARP data, otherwise enter the error handling state. (4) In the ARP data receiving state, receive the ARP data segment data and determine whether all the data has been received. If so, determine the ARP type based on the destination address and operation data; otherwise, continue receiving. (5) In the receiving end state, wait for the current frame data to be sent and then return to the initial state.

7. The ASIC circuit design method for a Gigabit Ethernet UDP / IP protocol stack according to claim 1, wherein: The ARP sending module is used to send the ARP data segment. The specific steps are as follows: (1) In the initial state, wait for the arrival of the data transmission signal, prepare the data of the IP header and Ethernet header, detect whether the MAC and IP of the receiving device are empty, if they are empty, use the data in the ARP module list to assign values, and determine the ARP type. After completing the operation, enter the sending preamble code state. (2) In the preamble sending state, the preamble of the specified byte is sent. (3) In the Ethernet frame header sending state, the destination device MAC address, source device MAC address and network type identification number are sent in sequence. (4) In the ARP data sending state, send ARP data segment data. (5) In the state of sending CRC check result, the CRC data generated by the CRC module is sent, and after sending, it returns to the initial state.

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