Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes an integrated circuit structure including a conductive region; a capacitor including a lower electrode structure connected to the conductive region and spaced apart on the integrated circuit structure, a dielectric layer covering the lower electrode structure, and an upper electrode structure on the dielectric layer; and a support structure interconnecting the lower electrode structures, where the support structure includes: an upper support structure interconnecting and spaced apart upper regions of the lower electrode structures; and lower support structures interconnecting and spaced apart the lower electrode structures, a side surface of the upper support pattern of the upper support structure and a side surface of the upper region of the lower electrode structure defining an upper open pattern, and a side surface of the lower support pattern of the lower support structure and a side surface of the lower electrode structure defining a lower open pattern, and the center of the upper support pattern is aligned with the center of the lower support pattern.

Description

[0001] This application claims the benefit of and priority to Korean Patent Application No. 10-2024-0036390 filed on March 15, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments of the present disclosure relate to semiconductor devices. Background Art

[0003] As the demand for high performance, high speed, and / or multifunctionality of semiconductor devices has increased, the integration density of semiconductor devices has increased. In response to the trend of integration density of semiconductor devices, when manufacturing semiconductor devices having fine patterns, it may be necessary to implement patterns having fine widths or having fine spacing distances therebetween. Summary of the Invention

[0004] Some example embodiments of the present disclosure provide semiconductor devices including a support structure having various designs according to an arrangement of a data storage structure.

[0005] According to some example embodiments, a semiconductor device includes: an integrated circuit structure including a conductive region; a capacitor including a lower electrode structure electrically connected to the conductive region of the integrated circuit structure, a dielectric layer covering the lower electrode structure, and an upper electrode structure on the dielectric layer, the lower electrode structures being spaced apart from each other on the integrated circuit structure; and a support structure interconnecting the lower electrode structures, wherein the support structure includes: an upper support structure interconnecting upper regions of the lower electrode structures, the upper support structure including upper support patterns spaced apart from each other; and a lower support structure including a lower support pattern interconnecting the lower electrode structures, the lower support pattern including a lower support pattern. The support member patterns are spaced apart from each other below the upper support member pattern, wherein the outer side surface of the upper support member pattern of the upper support member structure and the outer side surface of the upper region of the lower electrode structure connected to each other through the upper support member pattern define an upper open pattern extending in a horizontal direction, wherein the outer side surface of the lower support member pattern of the lower support member structure and the outer side surface of the lower electrode structure connected to each other through the lower support pattern define a lower open pattern extending in a horizontal direction, and wherein the first center of the upper support member pattern of the upper support member structure and the second center of the lower support pattern of the lower support structure corresponding to the first center are aligned respectively.

[0006] According to some example embodiments, a semiconductor device includes: an integrated circuit structure including a conductive region; a capacitor including a lower electrode structure electrically connected to the conductive region of the integrated circuit structure, a dielectric layer covering the lower electrode structure, and an upper electrode structure on the dielectric layer; an upper support member structure including upper support member patterns spaced apart from each other, each of the upper support member patterns surrounding at least one first lower electrode structure of the lower electrode structures, and each of the upper support member patterns contacting at least a portion of a side surface of each of a plurality of second lower electrode structures adjacent to the at least one first lower electrode structure; and a lower support member structure below the upper support member structure and including a lower support member pattern, the lower support member pattern having a center respectively aligned with the center of the upper support pattern, wherein at least a portion of the upper electrode structure of the capacitor surrounds the side surface of each of the upper support patterns and extends in a horizontal direction between the upper support patterns, and wherein at least a portion of the upper electrode structure of the capacitor surrounds the side surface of each of the lower support patterns and extends in a horizontal direction between the lower support patterns.

[0007] According to some example embodiments, a semiconductor device includes: an integrated circuit structure including a conductive region; a capacitor including a lower electrode structure electrically connected to the conductive region of the integrated circuit structure, a dielectric layer covering the lower electrode structure, and an upper electrode structure on the dielectric layer; and a support structure including a support pattern group sequentially located at different heights on the integrated circuit structure, the support pattern group surrounding at least one first lower electrode structure of the lower electrode structures at different heights and contacting at least a portion of a side surface of each of a plurality of second lower electrode structures adjacent to the at least one first lower electrode structure, wherein the support pattern group of the support structure includes: an upper support pattern in an upper region of the lower electrode structure and horizontally extending therefrom. spaced apart from each other; an intermediate support member pattern below the upper support member pattern and having a center aligned with the center of the upper support member pattern; and a lower support member pattern between the intermediate support member pattern and the integrated circuit structure and having centers aligned with the centers of the intermediate support patterns, respectively, wherein a minimum distance between outer side surfaces of mutually adjacent upper support member patterns among the upper support member patterns is greater than a minimum distance between outer side surfaces of mutually adjacent intermediate support patterns among the intermediate support patterns, and wherein a minimum distance between outer side surfaces of mutually adjacent intermediate support patterns among the intermediate support pattern is greater than a minimum distance between outer side surfaces of mutually adjacent lower support patterns among the lower support pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above aspects and other aspects, features and advantages of some example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 is a plan view illustrating a semiconductor device according to some example embodiments of the present disclosure.

[0010] Figure 2A It shows Figure 1 An enlarged view of a portion of the semiconductor device shown in FIG.

[0011] Figure 2B are cross-sectional views illustrating semiconductor devices according to some example embodiments of the present disclosure.

[0012] Figure 2C is a plan view illustrating a semiconductor device according to some example embodiments of the present disclosure.

[0013] Figure 3 is a plan view illustrating a semiconductor device according to some example embodiments of the present disclosure.

[0014] Figure 4 and Figure 5 is an enlarged view illustrating a portion of a semiconductor device according to some example embodiments of the present disclosure.

[0015] Figure 6A It shows Figure 1 An enlarged view of a portion of the semiconductor device shown in FIG.

[0016] Figure 6B are cross-sectional views illustrating semiconductor devices according to some example embodiments of the present disclosure.

[0017] Figure 6C is a plan view illustrating a semiconductor device according to some example embodiments of the present disclosure.

[0018] Figure 7 and Figure 8 is an enlarged view illustrating a portion of a semiconductor device according to some example embodiments of the present disclosure.

[0019] Figures 9 to 20 are cross-sectional views taken in a vertical direction illustrating processes of a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure. DETAILED DESCRIPTION

[0020] It will be understood that elements and / or their properties (e.g., structures, surfaces, directions, etc.) that may be referred to as being “perpendicular,” “parallel,” “coplanar,” etc., relative to other elements and / or their properties (e.g., structures, surfaces, directions, etc.) may be “perpendicular,” “parallel,” “coplanar,” etc., respectively, relative to the other elements and / or their properties, or may be “substantially perpendicular,” “substantially parallel,” “substantially coplanar,” etc., respectively, relative to the other elements and / or their properties.

[0021] Elements and / or their properties (e.g., structures, surfaces, directions, etc.) that are “substantially perpendicular,” “substantially parallel,” or “substantially coplanar” relative to other elements and / or their properties will be understood to be “perpendicular,” “parallel,” or “coplanar,” respectively, relative to other elements and / or their properties within manufacturing tolerances and / or material tolerances, and / or having a magnitude and / or angle deviation of equal to or less than 10% from being “perpendicular,” “parallel,” or “coplanar,” respectively, relative to other elements and / or their properties (e.g., a tolerance of ±10%).

[0022] Hereinafter, some example embodiments will be described with reference to the accompanying drawings as follows.

[0023] Figure 1 is a plan view illustrating a semiconductor device according to some example embodiments.

[0024] Figure 2A It shows Figure 1 FIG. 1 is an enlarged view of a region “A” of a semiconductor device shown in FIG.

[0025] Figure 2B is a diagram illustrating a method according to some example embodiments Figure 2A Lines I-I' and Figure 1 A cross-sectional view of the semiconductor device taken along line II-II' in FIG. Figure 2A It is shown along Figure 2B A plan view of the semiconductor device taken along line III-III' in FIG.

[0026] Figure 2C is a plan view illustrating a semiconductor device according to some example embodiments.

[0027] Reference Figure 1 According to some example embodiments, a semiconductor device may include a cell area CA, an interface area IA, and a peripheral circuit area PA. The peripheral circuit area PA may surround the cell area CA, and the interface area IA may be disposed between the cell area CA and the peripheral circuit area PA. The cell area CA may represent a region where memory cells of a dynamic random access memory (DRAM) device are disposed, and the peripheral circuit area PA may include word line drivers, sense amplifiers, row and column decoders, and control circuits. The interface area IA may electrically connect the cell area CA to the peripheral circuit area PA.

[0028] Reference Figures 2A to 2CThe semiconductor device 100 may include a substrate 101 including a first active area ACT1 disposed in a cell area CA, a device isolation layer 110 defining the first active area ACT1 in the substrate 101, a bit line structure BLS disposed on the substrate 101 and including a bit line BL, and a data storage structure CAP on the bit line structure BLS. The data storage structure CAP may store data and may be configured as a capacitor structure of a DRAM, for example. In the cell area CA, the semiconductor device 100 may further include a lower conductive pattern 150 on the first active area ACT1, an upper conductive pattern 160 on the lower conductive pattern 150, and an insulating pattern 165 penetrating the upper conductive pattern 160.

[0029] Although not shown, the semiconductor device 100 may include word lines disposed in the cell area CA and buried in the substrate 101 .

[0030] For example, the semiconductor device 100 may include a cell array of a dynamic random access memory (DRAM). For example, a bit line BL may be connected to the first impurity region 105 a of the first active region ACT1, and the second impurity region 105 b of the first active region ACT1 may be electrically connected to the data storage structure CAP on the upper conductive pattern 160 through the lower conductive pattern 150 and the upper conductive pattern 160.

[0031] The data storage structure CAP can be configured as a capacitor capable of storing data in a memory device such as a DRAM. The data storage structure CAP can be electrically connected to a conductive region (e.g., lower conductive pattern 150 and upper conductive pattern 160) on a lower structure including the conductive region (e.g., lower conductive pattern 150 and upper conductive pattern 160). Here, the lower structure can include a substrate 101, word line and bit line structures BLS, and can be referred to as an integrated circuit structure.

[0032] The data storage structure CAP may include a lower electrode structure 170, a dielectric layer 172 on the lower electrode structure 170, and an upper electrode structure 174 on the dielectric layer 172. The semiconductor device 100 may further include support structures SS1, SS2, and SS3 supporting the data storage structure CAP.

[0033] The substrate 101 may include a semiconductor material (such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor). For example, the Group IV semiconductor may include silicon, germanium, or silicon germanium. The substrate 101 may also include impurities. The substrate 101 may include a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer.

[0034] A first active region ACT1 may be defined in the substrate 101 by the device isolation layer 110. The first active region ACT1 may include a first impurity region 105a and a second impurity region 105b at a predetermined depth from the upper surface of the substrate 101. The first impurity region 105a and the second impurity region 105b may be spaced apart from each other. The first impurity region 105a and the second impurity region 105b may serve as source / drain regions of a transistor including a word line. The source region and the drain region may be formed from the first impurity region 105a and the second impurity region 105b by doping or ion implanting substantially the same impurities and may be referred to interchangeably depending on the circuit configuration of the transistor ultimately formed. The impurities may include impurities having a conductivity type opposite to that of the substrate 101. In some example embodiments, the depths of the first impurity region 105a and the second impurity region 105b in the source region and the drain region may be different.

[0035] The device isolation layer 110 may be formed by a shallow trench isolation (STI) process. The device isolation layer 110 may surround the first active region ACT1 and electrically isolate the first active region ACT1 from each other. The device isolation layer 110 may be formed of an insulating material (eg, silicon oxide, silicon nitride, or a combination thereof).

[0036] Although not shown, the word lines may extend across the first active region ACT1 in the first direction X. For example, a pair of word lines adjacent to each other may cross the first active region ACT1. The word lines may be included in gates of buried channel array transistors (BCAT), but example embodiments are not limited thereto.

[0037] The bit line structure BLS may extend perpendicularly to the word lines in one direction, eg, in the second direction Y. The bit line structure BLS may include a bit line BL and a bit line capping pattern BC on the bit line BL.

[0038] The bit lines BL may include a plurality of bit lines stacked in sequence (eg, in a vertical direction (eg, Figure 2BA first conductive pattern 141, a second conductive pattern 142, and a third conductive pattern 143 (sequentially stacked in the Z direction (as depicted in FIG)) are provided. A bitline capping pattern BC may be provided on the third conductive pattern 143. A buffer insulating layer 128 may be provided between the first conductive pattern 141 and the substrate 101, and a portion of the first conductive pattern 141 (hereinafter, a bitline contact pattern DC) may contact the first impurity region 105a of the first active region ACT1. The bitline BL may be electrically connected to the first impurity region 105a through the bitline contact pattern DC. The lower surface of the bitline contact pattern DC may be provided at a height lower than that of the upper surface of the substrate 101 and may be provided at a height higher than that of the upper surface of the wordline. In some example embodiments, the bitline contact pattern DC may be formed in the substrate 101 and may be partially provided in a bitline contact hole that exposes the first impurity region 105a.

[0039] The first conductive pattern 141 may include a semiconductor material (such as polysilicon). The first conductive pattern 141 may be in contact with (e.g., in direct contact with) the first impurity region 105a. The second conductive pattern 142 may include a metal-semiconductor compound. For example, the metal-semiconductor compound may be configured as a layer that silicides a portion of the first conductive pattern 141. For example, the metal-semiconductor compound may include cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides. The third conductive pattern 143 may include a metal material (such as titanium (Ti), tantalum (Ta), tungsten (W), and / or aluminum (Al)). The number of conductive patterns included in the bit line BL, the type of material of the conductive patterns, and / or the stacking order of the conductive patterns may vary in some example embodiments.

[0040] The bit line capping pattern BC may include a first capping pattern 146, a second capping pattern 147, and a third capping pattern 148 stacked in sequence on the third conductive pattern 143. Each of the first to third capping patterns 146, 147, and 148 may include an insulating material (e.g., a silicon nitride film). The first to third capping patterns 146, 147, and 148 may be formed of different materials, and even when the capping patterns include the same material, the boundaries therebetween may be distinct due to differences in physical properties. The thickness of the second capping pattern 147 may be smaller than the thickness of the first capping pattern 146 and the thickness of the third capping pattern 148. The number of capping patterns included in the bit line capping pattern BC and / or the type of material of the capping patterns may vary in example embodiments.

[0041] The spacer structures SSC may be disposed on both sidewalls of the bitline structure BLS and may extend in one direction (e.g., the Y direction). The spacer structures SSC may be disposed between the bitline structure BLS and the lower conductive pattern 150. The spacer structures SSC may extend along the sidewalls of the bitline BL and the sidewalls of the bitline capping pattern BC. The pair of spacer structures SSC disposed on either side of the bitline structure BLS may have an asymmetric shape relative to the bitline structure BLS. Each of the spacer structures SSC may include a plurality of spacer layers and, in some example embodiments, may further include air spacers.

[0042] The lower conductive pattern 150 may be connected to a region of the first active region ACT1 (e.g., the second impurity region 105b). The lower conductive pattern 150 may be disposed between the bit lines BL. The lower conductive pattern 150 may penetrate the buffer insulating layer 128 and may be connected to the second impurity region 105b of the first active region ACT1. The lower conductive pattern 150 may be in contact with (e.g., directly in contact with) the second impurity region 105b. The lower surface of the lower conductive pattern 150 may be disposed at a height lower than the upper surface of the substrate 101 and may be disposed at a height higher than the lower surface of the bit line contact pattern DC. The lower conductive pattern 150 may be disposed at a height higher than the spacer structure SSC (e.g., disposed at a height higher than the lower surface of the spacer structure SSC). The lower conductive pattern 150 may be insulated from the bit line contact pattern DC by the spacer structure SSC. The lower conductive pattern 150 may be formed of a conductive material, and the conductive material may include, for example, at least one of polysilicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and / or aluminum (Al). In some example embodiments, the lower conductive pattern 150 may include a plurality of layers.

[0043] A metal-semiconductor compound layer 155 may be provided between the lower conductive pattern 150 and the upper conductive pattern 160. For example, when the lower conductive pattern 150 includes a semiconductor material, the metal-semiconductor compound layer 155 may be configured to silicide a portion of the lower conductive pattern 150. The metal-semiconductor compound layer 155 may include, for example, cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides. In some example embodiments, the metal-semiconductor compound layer 155 may not be provided.

[0044] An upper conductive pattern 160 may be disposed on the lower conductive pattern 150. The upper conductive pattern 160 may extend to the region between the spacer structures SSC and may cover the upper surface of the metal-semiconductor compound layer 155. The upper conductive pattern 160 may include a barrier layer 162 and a conductive layer 164. The barrier layer 162 may cover the lower surface and side surfaces of the conductive layer 164. The barrier layer 162 may include at least one metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), and / or tungsten nitride (WN). The conductive layer 164 may include a conductive material, such as at least one of polycrystalline silicon (Si), titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), copper (Cu), molybdenum (Mo), platinum (Pt), nickel (Ni), cobalt (Co), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), and / or tungsten nitride (WN).

[0045] The insulating pattern 165 may penetrate the upper conductive pattern 160. The upper conductive pattern 160 may be divided into a plurality of portions by the insulating pattern 165. The insulating pattern 165 may include at least one of insulating materials (eg, silicon oxide, silicon nitride, and / or silicon oxynitride).

[0046] Etch stop layer 168 may cover insulating pattern 165 between lower electrode structures 170. Etch stop layer 168 may also further extend into interface region IA (not shown). Etch stop layer 168 may contact lower regions of side surfaces of lower electrode structure 170. Etch stop layer 168 may be disposed below support structures SS1, SS2, and SS3. For example, etch stop layer 168 may be vertically aligned with support structures SS1, SS2, and SS3. The upper surface of etch stop layer 168 may include a portion in contact with (e.g., in direct contact with) dielectric layer 172. For example, etch stop layer 168 may include at least one of silicon nitride and silicon oxynitride.

[0047] The lower electrode structure 170 may be disposed on the upper conductive pattern 160. The lower electrode structure 170 may penetrate the etch stop layer 168 and may contact the upper conductive pattern 160. The lower electrode structure 170 may include niobium nitride (NbN), niobium oxide (NbO x ), at least one of polysilicon (Si), iridium (Ir), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN) and / or aluminum (Al) or a combination thereof, metal nitride and / or metal compound.

[0048] Reference Figure 2AIn a plan view viewed from above, the lower electrode structures 170 may be regularly arranged. In some example embodiments, the lower electrode structures 170 may be spaced apart by a predetermined distance in a first horizontal direction D1 and may be arranged in a second horizontal direction D2 intersecting the first horizontal direction D1. In a different viewpoint, the lower electrode structures 170 may be arranged in a zigzag pattern in the Y direction. For example, the lower electrode structures 170 may be arranged in a honeycomb structure. However, the arrangement of the lower electrode structures 170 is not limited thereto.

[0049] Reference Figures 2A to 2C , the lower electrode structure 170 may have a pillar shape. The lower electrode structure 170 may have a cylindrical shape whose horizontal width (e.g., radius) may vary in the Z direction. For example, the radii r1, r2, and r3 of the lower electrode structure 170 may decrease (e.g., in the Z direction) toward the upper surface of the substrate 101.

[0050] The support structures SS1, SS2, and SS3 may include a lower support structure SS3, an intermediate support structure SS2 on the lower support structure SS3, and an upper support structure SS1 on the intermediate support structure SS2. The lower support structure SS3, the intermediate support structure SS2, and the upper support structure SS1 may be sequentially spaced apart from the substrate 101 in a direction perpendicular to the upper surface of the substrate 101. The support structures SS1, SS2, and SS3 may support the lower electrode structure 170 having a high aspect ratio (or "height-to-width ratio" or "depth-to-width ratio"). Each of the support structures SS1, SS2, and SS3 may include, for example, at least one of silicon nitride, silicon oxynitride, and / or similar materials.

[0051] Reference Figure 2A and Figure 2B , the upper support structure SS1 may include upper support patterns SP1 connecting the upper regions UR of the lower electrode structures 170. The upper support patterns SP1 may be spaced apart from each other in the horizontal direction. In some example embodiments, at least a portion of the upper electrode structure 174 may surround a side surface of each of the upper support patterns SP1 and may extend in the horizontal direction between the upper support patterns SP1.

[0052] Each of the upper support patterns SP1 may surround at least one first lower electrode structure 170_1 of the lower electrode structures 170 and may be in contact with side surfaces of a plurality of second lower electrode structures 170_2 adjacent to the at least one first lower electrode structure 170_1. Figure 2A , the upper support pattern SP1 may surround the first lower electrode structure 170_1 and may be disposed to contact at least a portion of side surfaces of six second lower electrode structures 170_2 that are closest to the first lower electrode structure 170_1.

[0053] The distance between the centers of horizontally adjacent upper support patterns SP1 may be defined as a first distance L1. From a different perspective, the first distance L1 may be defined as the distance (e.g., the minimum horizontal distance) between a conceptual vertical axis X1 that passes through the center of the first lower electrode structure 170_1 in the Z direction. In some embodiments, the Z direction may be perpendicular to the horizontal directions (e.g., the X and Y directions). Here, the conceptual vertical axis X1 may be defined as being arranged in a third horizontal direction D3 that intersects the first horizontal direction D1 and the second horizontal direction D2. The first distance L1 may be configured to be 76 nm or greater (e.g., 76 nm to 120 nm, or 76 nm to 110 nm, or 76 nm to 100 nm). In some embodiments, the semiconductor device 100 may include support patterns surrounding at least one first lower electrode structure 170_1 and contacting side surfaces of a plurality of second lower electrode structures 170_2 adjacent to the at least one first lower electrode structure 170_1. This allows for addressing limitations on the pitch (e.g., the minimum pitch) between the support patterns during the patterning process.

[0054] Reference Figure 2A , the outer side surfaces SP1_s of the upper support pattern SP1 may have an outwardly curved shape between the second lower electrode structures 170_2. For example, when the outer side surfaces SP1_s of the upper support pattern SP1 extend in a conceptual curve and are connected to each other, the upper support pattern SP1 may be interpreted as having a circular shape. For example, the outer side surfaces SP1_s of the upper support pattern SP1 (for example, the outer side surfaces SP1_s of the upper support pattern SP1 between the adjacent second lower electrode structures 170_2) may have a convex shape in a direction away from the center of the upper support pattern SP1.

[0055] Reference Figure 2B and Figure 2C The intermediate support structure SS2 may include an intermediate support pattern SP2 that connects the intermediate regions MR of the lower electrode structures 170 to each other. Here, the intermediate region MR may be a term indicating a region disposed below the upper region UR and may not be limited to a specific region. The intermediate support patterns SP2 may be spaced apart from each other in the horizontal direction.

[0056] The middle support pattern SP2 may be aligned with the upper support pattern SP1 in a vertical direction (eg, Z direction). Specifically, the centers of the middle support pattern SP2 may be aligned with the centers of the upper support pattern SP1 on the same vertical axis X1.

[0057] Thus, the intermediate support pattern SP2 may surround the first lower electrode structure 170_1 and may make contact with at least a portion of side surfaces of six second lower electrode structures 170_2 that are closest to the first lower electrode structure 170_1 .

[0058] Reference Figure 2C , the outer side surfaces SP2_s of the intermediate support pattern SP2 may have an outwardly curved shape between the second lower electrode structures 170_2. For example, when the outer side surfaces SP2_s of the intermediate support pattern SP2 extend in a conceptual curve and are connected to each other, the intermediate support pattern SP2 may be interpreted as having a circular shape.

[0059] Reference Figure 2B and Figure 2C , the lower support structure SS3 may include lower support patterns SP3 connecting the lower regions LR of the lower electrode structures 170 to each other. Here, the lower region LR may be a term indicating a region disposed below the middle region MR and may not be limited to a specific region. The lower support patterns SP3 may be spaced apart from each other in the horizontal direction. In some example embodiments, at least a portion of the upper electrode structure 174 may surround a side surface of each of the lower support patterns SP3 and may extend in the horizontal direction between the lower support patterns SP3.

[0060] The lower support pattern SP3 may be aligned with the middle support pattern SP2 in the vertical direction (e.g., in the Z direction). Specifically, the center of the lower support pattern SP3 may be aligned with the center of the middle support pattern SP2 on the same vertical axis X1. Therefore, the center of the lower support pattern SP3 may also be aligned with the center of the upper support pattern SP1 on the same vertical axis X1.

[0061] Thus, the lower support pattern SP3 may surround the first lower electrode structure 170_1 and may respectively make contact with at least a portion of side surfaces of the six second lower electrode structures 170_2 closest to the first lower electrode structure 170_1 .

[0062] Reference Figure 2C , the outer side surfaces SP3_s of the lower support pattern SP3 may have an outwardly curved shape between the second lower electrode structures 170_2. For example, when the outer side surfaces SP3_s of the lower support pattern SP3 extend in a conceptual curve and are connected to each other, the lower support pattern SP3 may be interpreted as having a circular shape.

[0063] Reference Figures 2A to 2C In the upper region UR, the middle region MR, and the lower region LR, the distances from the center of the first lower electrode structure 170_1 to the outer side surfaces SP1_s, SP2_s, and SP3_s of the support pattern may be different. In different viewpoints, the width (e.g., the maximum horizontal width) of the support pattern may be different in the upper region UR, the middle region MR, and the lower region LR.

[0064] In the upper region UR, a distance from the center of the first lower electrode structure 170_1 to an outer side surface SP1_s of the upper support pattern SP1 may be defined as a first radius R1. The first radius R1 may increase toward the upper surface of the substrate 101 in the upper region UR.

[0065] In the middle region MR, the distance from the center of the first lower electrode structure 170_1 to the outer side surface SP2_s of the middle support pattern SP2 may be defined as a second radius R2. The second radius R2 in the middle region MR may be greater than the first radius R1 in the upper region UR. Therefore, a ratio of the outer side surfaces 170_2s of the second lower electrode structure 170_2 in the middle region MR that contact the middle support pattern SP2 may be greater than a ratio of the outer side surfaces 170_2s of the second lower electrode structure 170_2 in the upper region UR that contact the upper support pattern SP1. For example, a ratio of an area of ​​the outer side surface 170_2s in contact with the middle support pattern SP2 in the middle region MR to a total surface area (e.g., a total side surface area) of the second lower electrode structure 170_2 in the middle region MR may be greater than a ratio of an area of ​​the outer side surface 170_2s in contact with the upper support pattern SP1 in the upper region UR to a total surface area (e.g., a total side surface area) of the second lower electrode structure 170_2 in the upper region UR. The second radius R2 may increase in the middle region MR toward the upper surface of the substrate 101.

[0066] In the lower region LR, a distance from the center of the first lower electrode structure 170_1 to the outer side surface SP3_s of the lower support pattern SP3 may be defined as a third radius R3. The third radius R3 in the lower region LR may be greater than the second radius R2 in the middle region MR. Therefore, a ratio of the outer side surfaces 170_2s of the second lower electrode structure 170_2 in the lower region LR that contact the lower support pattern SP3 may be greater than a ratio of the outer side surfaces 170_2s of the second lower electrode structure 170_2 in the middle region MR that contact the middle support pattern SP2. For example, a ratio of an area of ​​the outer side surface 170_2s in contact with the lower support pattern SP3 in the lower region LR to a total surface area (e.g., a total side surface area) of the second lower electrode structure 170_2 in the lower region LR may be greater than a ratio of an area of ​​the outer side surface 170_2s in contact with the middle support pattern SP2 in the middle region MR to a total surface area (e.g., a total side surface area) of the second lower electrode structure 170_2 in the middle region MR. The third radius R3 may increase toward the upper surface of the substrate 101 in the lower region LR.

[0067] In other words, in each of the upper region UR, the middle region MR, and the lower region LR, the horizontal width of the support pattern may increase toward the upper surface of the substrate 101. In addition, the width (e.g., maximum horizontal width) of the support pattern in the upper region UR may be smaller than the width (e.g., maximum horizontal width) of the support pattern in the middle region MR, and the width (e.g., maximum horizontal width) of the support pattern in the middle region MR may be smaller than the width (e.g., maximum horizontal width) of the support pattern in the lower region LR.

[0068] Reference Figures 2A to 2C , in the upper region UR, the middle region MR, and the lower region LR, angles formed by tangents of the outer side surfaces SP1_s, SP2_s, and SP3_s of the support pattern and tangents of corresponding outer side surfaces 170_2s of the second lower electrode structure 170_2 may be different.

[0069] In the upper region UR, at a point where the upper support pattern SP1 and the second lower electrode structure 170_2 contact each other, an angle formed by a tangent line of the outer side surface SP1_s of the upper support pattern SP1 and a tangent line of the outer side surface 170_2s of the second lower electrode structure 170_2 may be defined as a first angle θ1. The first angle θ1 may increase toward the upper surface of the substrate 101 in the upper region UR.

[0070] In the middle region MR, at a point where the middle support pattern SP2 and the second lower electrode structure 170_2 contact each other, an angle formed by a tangent line to the outer side surface SP2_s of the middle support pattern SP2 and a tangent line to the outer side surface 170_2s of the second lower electrode structure 170_2 may be defined as a second angle θ2. The second angle θ2 in the middle region MR may be greater than the first angle θ1 in the upper region UR. The second angle θ2 may increase in the middle region MR toward the upper surface of the substrate 101.

[0071] In the lower region LR, at a point where the lower support pattern SP3 and the second lower electrode structure 170_2 contact each other, an angle formed by a tangent line of the outer side surface SP3_s of the lower support pattern SP3 and a tangent line of the outer side surface 170_2s of the second lower electrode structure 170_2 may be defined as a third angle θ3. The third angle θ3 in the lower region LR may be greater than the second angle θ2 in the middle region MR. The third angle θ3 may increase in the lower region LR toward the upper surface of the substrate 101.

[0072] Reference Figures 2A to 2C , in the upper region UR, the middle region MR, and the lower region LR, open patterns OP1, OP2, and OP3 may be defined.

[0073] In the upper region UR, an upper open pattern OP1 may be defined by the upper support pattern SP1 and the plurality of second lower electrode structures 170_2. Specifically, the upper open pattern OP1 may be defined by the outer side surface SP1_s of the upper support pattern SP1 and the outer side surfaces 170_2s of the second lower electrode structures 170_2. The upper open pattern OP1 may extend in the horizontal direction.

[0074] In the middle region MR, the middle open pattern OP2 may be defined by the middle support pattern SP2 and the plurality of second lower electrode structures 170_2. Specifically, the middle open pattern OP2 may be defined by the outer side surface SP2_s of the middle support pattern SP2 and the outer side surfaces 170_2s of the second lower electrode structures 170_2. The middle open pattern OP2 may extend in the horizontal direction.

[0075] In the lower region LR, the lower open pattern OP3 may be defined by the lower support pattern SP3 and the plurality of second lower electrode structures 170_2. Specifically, the lower open pattern OP3 may be defined by the outer side surface SP3_s of the lower support pattern SP3 and the outer side surfaces 170_2s of the second lower electrode structures 170_2. The lower open pattern OP3 may extend in the horizontal direction.

[0076] Refer to it together Figure 1 and 2A In the upper region UR of the cell area CA, a ratio of a horizontal area of ​​the upper open pattern OP1 to the sum of the horizontal areas of the lower electrode structure 170, the upper support pattern SP1, and the upper open pattern OP1 may be defined as an open pattern ratio OR. According to some example embodiments, the open pattern ratio OR may be 30% or greater (e.g., 30% to 45%, 35% to 40%, or 38% to 40%). In some example embodiments, the open pattern ratio corresponding to the middle open pattern OP2 (e.g., a ratio of a horizontal area of ​​the middle open pattern OP2 in the middle region MR of the cell area CA to the sum of the horizontal areas of the lower electrode structure 170, the middle support pattern SP2, and the middle open pattern OP2) may be smaller than the open pattern ratio OR corresponding to the upper open pattern OP1, and the open pattern ratio corresponding to the lower open pattern OP3 (e.g., a ratio of a horizontal area of ​​the lower open pattern OP3 in the lower region LR of the cell area CA to the sum of the horizontal areas of the lower electrode structure 170, the lower support pattern SP3, and the lower open pattern OP3) may be smaller than the open pattern ratio corresponding to the middle open pattern OP2.

[0077] The open patterns OP1 , OP2 , and OP3 may be configured as regions where the upper electrode structure 174 is disposed.

[0078] Reference Figures 2A to 2C, in the upper region UR, the middle region MR, and the lower region LR, the distances (eg, the minimum horizontal distance) between the support patterns adjacent to each other in the horizontal direction may be different.

[0079] In the upper region UR, a first distance (eg, minimum horizontal distance) d1 between upper support patterns SP1 adjacent in the horizontal direction may be defined as a distance obtained by subtracting twice the size of the first radius R1 from the first distance L1. d1=L1-2 R1.

[0080] In the middle region MR, a second distance (eg, minimum horizontal distance) d2 between the middle support patterns SP2 adjacent in the horizontal direction may be defined as a distance obtained by subtracting twice the size of the second radius R2 from the first distance L1. d2=L1-2 R2.

[0081] In the lower region LR, a third distance (eg, minimum horizontal distance) d3 between the lower support patterns SP3 adjacent in the horizontal direction may be defined as a distance obtained by subtracting twice the size of the third radius R3 from the first distance L1. d3=L1-2 R3.

[0082] As described above, the third radius R3 may be greater than the second radius R2, so that the third minimum horizontal distance d3 may be smaller than the second minimum horizontal distance d2. Similarly, the second radius R2 may be greater than the first radius R1, so that the second minimum horizontal distance d2 may be smaller than the first minimum horizontal distance d1.

[0083] The dielectric layer 172 may cover the side surfaces and the upper surface of each of the lower electrode structures 170 on the surface of the lower electrode structures 170. The dielectric layer 172 may be disposed between the lower electrode structures 170 and the upper electrode structure 174. The dielectric layer 172 may cover the upper and lower surfaces of the support structures SS1, SS2, and SS3. The dielectric layer 172 may cover the upper surface of the etch stop layer 168. In a plan view, the first lower electrode structure 170_1 (e.g., a portion of the first lower electrode structure 170_1) may not be covered or surrounded by the dielectric layer 172 (see FIG. 1 ). Figure 2A and Figure 2C ).

[0084] The dielectric layer 172 may include a high dielectric material, silicon oxide, silicon nitride, or a combination thereof. According to some example embodiments, the dielectric layer 172 may include an oxide, nitride, silicide, oxynitride, or oxynitride-silicide of titanium (Ti), tantalum (Ta), hafnium (Hf), aluminum (Al), zirconium (Zr), and / or lanthanum (La) (e.g., doped with fluorine (F)), or a combination thereof.

[0085] The upper electrode structure 174 may be disposed on the dielectric layer 172. The upper electrode structure 174 may fill the spaces between the plurality of lower electrode structures 170, the spaces between the upper support patterns SP1 (or the "upper open pattern OP1" portion), the spaces between the middle support patterns SP2 (or the "middle open pattern OP2" portion), and the spaces between the lower support patterns SP3 (or the "lower open pattern OP3" portion). Figure 2A and Figure 2C , when viewed from a cross-sectional view taken in a horizontal direction, the upper electrode structure 174 may be provided in a honeycomb structure. However, the arrangement of the upper electrode structure 174 is not limited thereto.

[0086] In some example embodiments, the dielectric layer 172 and the upper electrode structure 174 may further extend into the interface area IA (not shown).The upper electrode structure 174 may include a conductive material.

[0087] The upper electrode structure 174 may include a single layer or multiple layers. In some example embodiments, the upper electrode structure 174 may be in contact with (e.g., directly in contact with) the dielectric layer 172 and may include a first material layer formed along the dielectric layer 172 and a second material layer overlying the first material layer. The first material layer may include a doped semiconductor, a metal, a conductive metal nitride, a metal-semiconductor compound, a conductive metal oxide, or a combination thereof. The second material layer may include a silicon material or a silicon-germanium material. For example, the second material layer may include a doped silicon material or a doped silicon-germanium material.

[0088] In some example embodiments, the upper electrode structure 174 may further include a protective material layer that may prevent or reduce the likelihood of natural oxidation of the upper electrode structure 174 and oxidation via the dielectric layer 172. For example, the protective material layer may be covered by the first material layer and may be in contact with (e.g., in direct contact with) the dielectric layer 172. The protective material layer may include at least one of a metal, a metal-silicon oxide, a metal-silicon nitride, and / or a metal-silicon oxynitride.

[0089] The semiconductor device 100 may further include an upper interlayer insulating layer 188 covering the data storage structure CAP. The upper interlayer insulating layer 188 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some example embodiments, the upper interlayer insulating layer 188 may include silicon oxide. The upper surface of the upper interlayer insulating layer 188 may be flat (e.g., parallel to the upper surface of the substrate 101).

[0090] The semiconductor device 100 may also include a cell contact plug CCP, an interlayer insulating layer ILD, and a plurality of upper contact plugs 92 disposed on the data storage structure CAP. The cell contact plug CCP may penetrate the upper interlayer insulating layer 188 and may be connected to the data storage structure CAP. For example, the cell contact plug CCP may penetrate the upper interlayer insulating layer 188 and may be connected to the upper electrode structure 174. The lower surface of the cell contact plug CCP may be disposed at a height lower than the upper surface of the upper electrode structure 174. The upper surfaces of the cell contact plug CCP may be coplanar with each other. The cell contact plug CCP may include a barrier layer CCPa and a conductive layer CCPb on the barrier layer CCPa. The side surface of the cell contact plug CCP may be in contact with the upper interlayer insulating layer 188.

[0091] An interlayer insulating layer ILD may be disposed on the upper interlayer insulating layer 188. The interlayer insulating layer ILD may cover the cell contact plugs CCP and the upper interlayer insulating layer 188. The interlayer insulating layer ILD may include silicon oxide.

[0092] The plurality of upper contact plugs 92 may penetrate the interlayer insulating layer ILD, and at least one of the plurality of upper contact plugs 92 may be connected to the cell contact plug CCP. The plurality of upper contact plugs 92 may include a barrier layer 90 and a conductive layer 91 on the barrier layer 90. The lower surfaces of the plurality of upper contact plugs 92 may be flat (e.g., parallel to the upper surface of the substrate 101). The lower surfaces of the plurality of upper contact plugs 92 may be disposed at the same height.

[0093] The barrier layer CCPa and the barrier layer 90 may include a metal nitride such as titanium nitride (TiN). The conductive layer CCPb and the conductive layer 91 may include a conductive material such as tungsten (W) and / or tungsten nitride (WN).

[0094] Reference Figure 1 and Figure 2B The semiconductor device 100 may further include a device isolation layer 10, a second active region ACT2, a first peripheral impurity region 5a, and a second peripheral impurity region 5b in the peripheral circuit area PA. The device isolation layer 10 may be configured as an insulating layer extending downward from the upper surface of the substrate 101 and may define the second active region ACT2. The first peripheral impurity region 5a and the second peripheral impurity region 5b may be spaced apart from each other, with the peripheral gate structure 40 between the first peripheral impurity region 5a and the second peripheral impurity region 5b.

[0095] The device isolation layer 10 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and may include a single layer or multiple layers. The first peripheral impurity region 5a and the second peripheral impurity region 5b may serve as source / drain regions of a transistor including the peripheral gate structure 40. The first peripheral impurity region 5a and the second peripheral impurity region 5b may include impurities having a conductivity type opposite to that of the substrate 101.

[0096] The semiconductor device 100 may further include a peripheral gate dielectric layer 30 and a peripheral gate structure 40 disposed on the substrate 101 in the peripheral circuit area PA. The peripheral gate structure 40 may have a structure and material similar to those of the bit line BL.

[0097] The peripheral gate structure 40 may include a first conductive pattern 41, a second conductive pattern 42, and a third conductive pattern 43 stacked in sequence on the peripheral gate dielectric layer 30 on the substrate 101. The peripheral gate dielectric layer 30 may include silicon oxide, silicon nitride, or a high-κ material. The high-κ material may refer to a dielectric material having a higher dielectric constant than that of silicon oxide. The first conductive pattern 41, the second conductive pattern 42, and the third conductive pattern 43 of the peripheral gate structure 40 may respectively include the same materials as the first conductive pattern 141, the second conductive pattern 142, and the third conductive pattern 143 of the bit line BL. A first peripheral capping pattern 46 may be provided on the peripheral gate structure 40. The first peripheral capping pattern 46 may include the same material as the first capping pattern 146 of the bit line capping pattern BC.

[0098] The semiconductor device 100 may further include a peripheral gate spacer SSP, a second peripheral capping pattern 47, an interlayer insulating layer 45, and a third peripheral capping pattern 48 in the peripheral circuit area PA. The peripheral gate spacer SSP may cover the side surfaces of the peripheral gate structure 40. For example, the peripheral gate spacers SSP may be spaced apart from each other, with the peripheral gate structure 40 between the peripheral gate spacers SSP, and the side surfaces of the first conductive pattern 41, the second conductive pattern 42, the third conductive pattern 43, and the first peripheral capping pattern 46 may be covered by the peripheral gate spacer SSP.

[0099] The second peripheral capping pattern 47 may cover the substrate 101, the peripheral gate spacers SSP, and the peripheral gate structure 40 and may be conformally formed. The interlayer insulating layer 45 may partially cover the second peripheral capping pattern 47. The upper surfaces of the interlayer insulating layer 45 may be coplanar with each other. The third peripheral capping pattern 48 may cover the interlayer insulating layer 45 and the second peripheral capping pattern 47.

[0100] The second and third peripheral capping patterns 47 and 48 may include the same materials as the second and third capping patterns 147 and 148 of the bit line capping pattern BC, respectively, and may include, for example, silicon nitride. The interlayer insulating layer 45 may include silicon oxide.

[0101] The semiconductor device 100 may further include a peripheral plug 63 and a peripheral interconnect 60 electrically connected to the first and second peripheral impurity regions 5a and 5b in the peripheral circuit area PA. The peripheral plug 63 may penetrate the interlayer insulating layer 45, may be disposed adjacent to the peripheral gate structure 40, and may contact the first and second peripheral impurity regions 5a and 5b. The peripheral interconnect 60 may be disposed on the third peripheral capping pattern 48 and the peripheral plug 63 and may extend in a horizontal direction. In some example embodiments, the peripheral interconnect 60 may be integrated with the peripheral plug 63. For example, the peripheral interconnect 60 may include a barrier layer 61 and a conductive layer 62, and the barrier layer 61 and the conductive layer 62 may extend vertically downward and may form the peripheral plug 63. In some example embodiments, the peripheral interconnect 60 may not be integrated with the peripheral plug 63.

[0102] The semiconductor device 100 may further include an insulating pattern 65 disposed between the peripheral interconnections 60. The insulating pattern 65 may spatially isolate the peripheral interconnections 60 and may electrically insulate the peripheral interconnections 60 from each other.

[0103] Semiconductor device 100 may further include an etch stop layer 68 disposed on peripheral interconnect 60. Etch stop layer 68 may be integrated with etch stop layer 168. For example, etch stop layer 68 may be formed by extending etch stop layer 168 to peripheral circuit region PA.

[0104] Semiconductor device 100 may further include a peripheral contact plug PCP and an upper contact plug 95 disposed on peripheral interconnect 60. Peripheral contact plug PCP may penetrate upper interlayer insulating layer 188, lower interlayer insulating layer 186, and etch stop layer 68 and may contact one of peripheral interconnects 60. Peripheral contact plug PCP may be electrically connected to first peripheral impurity region 5a or second peripheral impurity region 5b through peripheral interconnect 60 and peripheral plug 63. Upper surfaces of peripheral contact plug PCP may be coplanar with each other. Peripheral contact plug PCP may include a barrier layer PCPa and a conductive layer PCPb on barrier layer PCPa.

[0105] Upper contact plug 95 may penetrate interlayer insulating layer ILD and may be connected to peripheral contact plug PCP. Upper contact plug 95 may include barrier layer 93 and conductive layer 94 on barrier layer 93. The lower surface of upper contact plug 95 may be flat (e.g., parallel to the upper surface of substrate 101). The lower surface of upper contact plug 95 may be arranged at the same height as the lower surfaces of the plurality of upper contact plugs 92.

[0106] The barrier layer PCPa and the barrier layer 93 may include a metal nitride such as titanium nitride (TiN). The conductive layer PCPb and the conductive layer 94 may include a conductive material such as tungsten (W) and / or tungsten nitride (WN).

[0107] Figure 3 is a plan view illustrating a semiconductor device according to some example embodiments.

[0108] Reference Figure 3 , except for the configuration in which the circumferential surface of the second lower electrode structure 170_2 contacts the inner side surface of the lower support pattern SP3, the semiconductor device 100a according to some example embodiments may be similar to the reference Figures 1 to 2C The examples described are the same or similar.

[0109] Reference Figure 3 The lower support pattern SP3 may surround the first lower electrode structure 170_1 and may also surround the plurality of second lower electrode structures 170_2. Therefore, in a plan view, an outer side surface SP3_s of the lower support pattern SP3 may have a circular shape having a third radius R3'.

[0110] The third radius R3' may be larger than the reference Figure 2C The third radius R3 described above, therefore, the third distance (eg, the minimum horizontal distance) d3' may also be smaller than the reference Figure 2C Described is the third minimum horizontal distance d3.

[0111] Figure 4 is an enlarged view illustrating a portion of a semiconductor device according to some example embodiments.

[0112] Reference Figure 4 , except that the outer side surface SP1_fs of the upper support pattern SP1 has a configuration of a flat surface, the semiconductor device 100b according to some example embodiments may be similar to the reference Figures 1 to 3 The examples described are the same or similar.

[0113] Reference Figure 4 , when the outer side surfaces SP1_fs of the upper support pattern SP1 extend in a conceptual plurality of linear lines and are connected to each other, the upper support pattern SP1 may be interpreted as having a regular hexagonal shape. Figures 2A to 2C In the described example, the width (eg, maximum horizontal width) of the support pattern may be larger in the lower region LR.

[0114] In some example embodiments, unlike in the upper region UR, the outer side surface of the support pattern may not have a flat surface in the middle region MR and / or the lower region LR. For example, in the middle region MR, the outer side surface of the middle support pattern SP2 may be as shown in FIG. Figure 2CIn this case, in the lower region LR, the outer side surface of the lower support pattern SP3 may also be as shown in FIG. Figure 2C As in the example described, it has an outwardly curved shape.

[0115] Figure 5 is an enlarged view illustrating a portion of a semiconductor device according to example embodiments.

[0116] Reference Figure 5 , except that the outer side surface SP1_cs of the upper support pattern SP1 has a configuration of a concave surface, the semiconductor device 100c according to some example embodiments may be similar to the reference Figures 1 to 4 The examples described are the same or similar.

[0117] Reference Figure 5 , the outer side surface SP1_cs of the upper support pattern SP1 may have an inwardly concave shape. For example, the outer side surface SP1_cs of the upper support pattern SP1 may have a convex shape in a direction toward the center of the upper support pattern SP1.

[0118] In example embodiments, the curvature of the outer side surface of the support pattern may decrease toward the lower region LR. In other words, the curvature of the outer side surface of the support pattern may decrease toward the lower region LR. For example, the curvature in the middle region MR may be smaller than the curvature in the upper region UR, and the curvature in the lower region LR may be smaller than the curvature in the middle region MR.

[0119] Figure 6A It shows Figure 1 FIG. 1 is an enlarged view of a region “A” of a semiconductor device shown in FIG.

[0120] Figure 6B It is shown along Figure 6A Lines I-I' and Figure 1 A vertical cross-sectional view of the semiconductor device taken along line II-II' in FIG. Figure 6A It is shown along Figure 6B A plan view of the semiconductor device taken along line III-III' in FIG.

[0121] Figure 6C It is shown along Figure 6B A plan view of the semiconductor device taken along lines IV-IV' and V-V'.

[0122] Reference Figures 6A to 6C , except for the configuration including the lower electrode structures 170′ spaced apart from each other by a predetermined distance in the first horizontal direction X and arranged in the second horizontal direction Y perpendicular to the first horizontal direction X, the semiconductor device 200 according to some example embodiments may be similar to the reference Figures 1 to 5The examples described are the same or similar.

[0123] In a different viewpoint, the lower electrode structures 170 ′ may be arranged in a grid structure each having a right angle shape.

[0124] Reference Figure 6A and Figure 6B , the upper support structure SS1' may include upper support patterns SP1' connecting the upper regions UR of the lower electrode structures 170' to each other. The upper support patterns SP1' may be spaced apart from each other in a horizontal direction.

[0125] The upper support pattern SP1' may surround at least one first lower electrode structure 170_1' among the lower electrode structures 170' and may contact side surfaces of a plurality of second lower electrode structures 170_2' adjacent to the at least one first lower electrode structure 170_1'. Figure 6A Each of the upper support patterns SP1′ may surround four first lower electrode structures 170_1′ that are most adjacent to each other and may be disposed so as to contact at least a portion of a side surface of a second lower electrode structure 170_2′ that is closest to the first lower electrode structure 170_1′. In a plan view viewed from above, the second lower electrode structure 170_2′ may represent eight second lower electrode structures disposed on outer sides of the first lower electrode structure 170_1′.

[0126] The distance between the centers of adjacent upper support patterns SP1' in the horizontal direction (e.g., the X direction) may be defined as a second distance L2. From a different perspective, the second distance L2 may be defined as the horizontal distance in the X direction between a conceptual vertical axis X1' that passes through the centroids of the four first lower electrode structures 170_1' in the Z direction. The second distance L2 may be configured to be 95 nm or greater (e.g., 95 nm to 135 nm, or 95 nm to 120 nm, or 95 nm to 110 nm).

[0127] The distance between the centers of adjacent upper support patterns SP1' in a third horizontal direction intersecting the X and Y directions can be defined as a third distance L3. From a different perspective, the third distance L3 can be defined as the horizontal distance in the third horizontal direction between a conceptual vertical axis X1' that passes through the center of mass of the four first lower electrode structures 170_1' in the Z direction. The third distance L3 can be smaller than the second distance L2. For example, the third distance L3 can be 10 nm or less (e.g., 5 nm to 10 nm) smaller than the second distance L2.

[0128] Reference Figure 6A, the outer side surfaces SP1_s' of the upper support pattern SP1' may have an outwardly curved shape between the second lower electrode structures 170_2'. For example, when the outer side surfaces SP1_s' of the upper support pattern SP1' extend in a conceptual curve and are connected to each other, the upper support pattern SP1' may be interpreted as having a circular shape.

[0129] Reference Figure 6B and Figure 6C The intermediate support structure SS2' may include an intermediate support pattern SP2' that connects the intermediate regions MR of the lower electrode structures 170' to each other. Here, the intermediate region MR may be a term indicating a region disposed below the upper region UR and may not be limited to a specific region. The intermediate support patterns SP2' may be spaced apart from each other in the horizontal direction.

[0130] The middle support pattern SP2' may be aligned with the upper support pattern SP1' in a vertical direction (eg, in the Z direction). Specifically, the centers of the middle support pattern SP2' may be aligned with the centers of the upper support pattern SP1' on the same vertical axis X1'.

[0131] Thus, the middle support pattern SP2 ′ may surround the four first lower electrode structures 170_1 ′ and may make contact with at least a portion of side surfaces of the plurality of second lower electrode structures 170_2 ′ that are closest to the first lower electrode structures 170_1 ′.

[0132] Reference Figure 6C , the outer side surfaces SP2_s' of the intermediate support pattern SP2' may have an outwardly curved shape between the second lower electrode structures 170_2'. For example, when the outer side surfaces SP2_s' of the intermediate support pattern SP2' are connected to each other in a conceptual curve, the intermediate support pattern SP2' may be interpreted as having a circular shape.

[0133] Reference Figure 6B and Figure 6C The lower support structure SS3' may include lower support patterns SP3' that connect the lower regions LR of the lower electrode structures 170' to each other. Here, the lower region LR may be a term indicating a region disposed below the middle region MR and may not be limited to a specific region. The lower support patterns SP3' may be spaced apart from each other in the horizontal direction.

[0134] The lower support pattern SP3' can be aligned with the middle support pattern SP2' in the vertical direction (e.g., in the Z direction). Specifically, the center of the lower support pattern SP3' can be aligned with the center of the middle support pattern SP2' on the same vertical axis X1'. Therefore, the center of the lower support pattern SP3' can also be aligned with the center of the upper support pattern SP1' on the same vertical axis X1'.

[0135] Therefore, the lower support pattern SP3 ′ may also surround the four first lower electrode structures 170_1 ′ and may make contact with at least a portion of side surfaces of the plurality of second lower electrode structures 170_2 ′ that are closest to the first lower electrode structures 170_1 ′.

[0136] Reference Figure 6C , the outer side surfaces SP3_s' of the lower support pattern SP3' may have an outwardly curved shape between the second lower electrode structures 170_2'. For example, when the outer side surfaces SP3_s' of the lower support pattern SP3' are connected to each other in a conceptual curve, the lower support pattern SP3' may be interpreted as having a circular shape.

[0137] Reference Figures 6A to 6C , distances from the vertical axis X1 ′ to the outer side surfaces SP1_s′, SP2_s′, and SP3_s′ of the support pattern may be different in the upper region UR, the middle region MR, and the lower region LR.

[0138] In the upper region UR, a distance from the vertical axis X1' to an outer side surface SP1_s' of the upper support pattern SP1' may be defined as a first radius R1. The first radius R1 may increase toward the upper surface of the substrate 101 in the upper region UR.

[0139] In the middle region MR, the distance from the vertical axis X1' to the outer side surface SP2_s' of the middle support pattern SP2' may be defined as a second radius R2. The second radius R2 in the middle region MR may be greater than the first radius R1 in the upper region UR. Therefore, a ratio of the outer side surfaces 170_2s' of the second lower electrode structure 170_2' in the middle region MR that contacts the middle support pattern SP2' may be greater than a ratio of the outer side surfaces 170_2s' of the second lower electrode structure 170_2' in the upper region UR that contacts the upper support pattern SP1'. For example, a ratio of an area of ​​an outer side surface 170_2s' in contact with the middle support pattern SP2' in the middle region MR to a total surface area (e.g., total side surface area) of the second lower electrode structure 170_2' in the middle region MR may be greater than a ratio of an area of ​​an outer side surface 170_2s' in contact with the upper support pattern SP1' in the upper region UR to a total surface area (e.g., total side surface area) of the second lower electrode structure 170_2' in the upper region UR. The second radius R2 may increase in the middle region MR toward the upper surface of the substrate 101.

[0140] In the lower region LR, a distance from the vertical axis X1' to the outer side surface SP3_s' of the lower support member pattern SP3' may be defined as a third radius R3. The third radius R3 in the lower region LR may be greater than the second radius R2 in the middle region MR. Therefore, a ratio of the outer side surfaces 170_2s' of the second lower electrode structure 170_2' in the lower region LR that contacts the lower support member pattern SP3' may be greater than a ratio of the outer side surfaces 170_2s' of the second lower electrode structure 170_2' in the middle region MR that contacts the middle support member pattern SP2'. For example, a ratio of an area of ​​the outer side surface 170_2s' in contact with the lower support pattern SP3' in the lower region LR to a total surface area (e.g., a total side surface area) of the second lower electrode structure 170_2' in the lower region LR may be greater than a ratio of an area of ​​the outer side surface 170_2s' in contact with the middle support pattern SP2' in the middle region MR to a total surface area (e.g., a total side surface area) of the second lower electrode structure 170_2' in the middle region MR. The third radius R3 may increase toward the upper surface of the substrate 101 in the lower region LR.

[0141] Reference Figures 6A to 6C , in the upper region UR, the middle region MR, and the lower region LR, angles formed by tangents of the outer side surfaces SP1_s', SP2_s', and SP3_s' of the support pattern and tangents of the outer side surfaces 170_2s' of the corresponding second lower electrode structures 170_2' may be different.

[0142] In the upper region UR, at a point where the upper support pattern SP1' and the second lower electrode structure 170_2' contact each other, an angle formed by a tangent line of an outer side surface SP1_s' of the upper support pattern SP1' and a tangent line of an outer side surface 170_2s' of the second lower electrode structure 170_2' may be defined as a first angle θ1. The first angle θ1 may increase toward the upper surface of the substrate 101 in the upper region UR.

[0143] In the middle region MR, at a point where the middle support pattern SP2' and the second lower electrode structure 170_2' contact each other, an angle formed by a tangent line of an outer side surface SP2_s' of the middle support pattern SP2' and a tangent line of an outer side surface 170_2s' of the second lower electrode structure 170_2' may be defined as a second angle θ2. The second angle θ2 in the middle region MR may be greater than the first angle θ1 in the upper region UR. The second angle θ2 may increase in the middle region MR toward the upper surface of the substrate 101.

[0144] In the lower region LR, at a point where the lower support pattern SP3' and the second lower electrode structure 170_2' contact each other, an angle formed by a tangent line of an outer side surface SP3_s' of the lower support pattern SP3' and a tangent line of an outer side surface 170_2s' of the second lower electrode structure 170_2' may be defined as a third angle θ3. The third angle θ3 in the lower region LR may be greater than the second angle θ2 in the middle region MR. The third angle θ3 may increase toward the upper surface of the substrate 101 in the lower region LR.

[0145] Reference Figures 6A to 6C In the upper region UR, the middle region MR, and the lower region LR, open patterns OP1 ′, OP2 ′, and OP3 ′ may be defined.

[0146] In the upper region UR, an upper open pattern OP1' may be defined by the upper support pattern SP1' and the plurality of second lower electrode structures 170_2'. Specifically, the upper open pattern OP1' may be defined by the outer side surface SP1_s' of the upper support pattern SP1' and the outer side surfaces 170_2s' of the second lower electrode structures 170_2'. The upper open pattern OP1' may extend in the horizontal direction.

[0147] In the middle region MR, the middle open pattern OP2' may be defined by the middle support pattern SP2' and the plurality of second lower electrode structures 170_2'. Specifically, the middle open pattern OP2' may be defined by the outer side surface SP2_s' of the middle support pattern SP2' and the outer side surfaces 170_2s' of the second lower electrode structures 170_2'. The middle open pattern OP2' may extend in the horizontal direction.

[0148] In the lower region LR, the lower open pattern OP3' may be defined by the lower support pattern SP3' and the plurality of second lower electrode structures 170_2'. Specifically, the lower open pattern OP3' may be defined by the outer side surface SP3_s' of the lower support pattern SP3' and the outer side surfaces 170_2s' of the second lower electrode structures 170_2'. The lower open pattern OP3' may extend in the horizontal direction.

[0149] Refer to it together Figure 1 and Figure 6AIn the upper region UR of the cell area CA, a ratio of a horizontal area of ​​the upper open pattern OP1' to a sum of horizontal areas of the lower electrode structure 170', the upper support pattern SP1', and the upper open pattern OP1' may be defined as an open pattern ratio OR'. According to example embodiments, the open pattern ratio OR' may be 30% or less (e.g., 20% to 30%, or 24% to 30%). In some example embodiments, the open pattern ratio corresponding to the middle open pattern OP2' (e.g., the ratio of the horizontal area of ​​the middle open pattern OP2' in the middle region MR of the unit area CA to the sum of the horizontal areas of the lower electrode structure 170', the middle support pattern SP2', and the middle open pattern OP2') may be smaller than the open pattern ratio OR' corresponding to the upper open pattern OP1', and the open pattern ratio corresponding to the lower open pattern OP3' (e.g., the ratio of the horizontal area of ​​the lower open pattern OP3' in the lower region LR of the unit area CA to the sum of the horizontal areas of the lower electrode structure 170', the lower support pattern SP3', and the lower open pattern OP3') may be smaller than the open pattern ratio corresponding to the middle open pattern OP2'.

[0150] Similar to reference Figures 1 to 2C In the described example, the open patterns OP1 ′, OP2 ′, and OP3 ′ may be configured as regions where the upper electrode structure 174 is disposed.

[0151] Reference Figures 6A to 6C , in the upper region UR, the middle region MR, and the lower region LR, the distances (eg, the minimum horizontal distance) between the support patterns adjacent to each other in the horizontal direction may be different.

[0152] In the upper region UR, a first minimum horizontal distance d1 between upper support patterns SP1' adjacent to each other in a horizontal direction may be defined as a distance obtained by subtracting twice the size of the first radius R1 from the third distance L3. d1=L3-2 R1.

[0153] In the middle region MR, a second minimum horizontal distance d2 between the middle support patterns SP2' adjacent to each other in the horizontal direction may be defined as a distance obtained by subtracting twice the size of the second radius R2 from the third distance L3. d2=L3-2 R2.

[0154] In the lower region LR, a third minimum horizontal distance d3 between the lower support patterns SP3' horizontally adjacent to each other may be defined as a distance obtained by subtracting twice the size of the third radius R3 from the third distance L3. d3=L3-2 R3.

[0155] As described above, the third radius R3 may be greater than the second radius R2, so that the third minimum horizontal distance d3 may be smaller than the second minimum horizontal distance d2. Similarly, the second radius R2 may be greater than the first radius R1, so that the second minimum horizontal distance d2 may be smaller than the first minimum horizontal distance d1.

[0156] Figure 7 is an enlarged view illustrating a portion of a semiconductor device according to example embodiments.

[0157] Reference Figure 7 , except that the outer side surface SP1_fs′ of the upper support pattern SP1′ has a configuration of a flat surface, the semiconductor device 200a according to some example embodiments may be similar to the reference Figure 1 and Figures 6A to 6C The examples described are the same or similar.

[0158] Reference Figure 7 , when the outer side surfaces SP1_fs′ of the upper support pattern SP1 ′ extend in a conceptual plurality of linear lines and are connected to each other, the upper support pattern SP1 ′ may be interpreted as having a regular hexagonal shape.

[0159] Figure 8 is an enlarged view illustrating a portion of a semiconductor device according to example embodiments.

[0160] Reference Figure 8 , except that the outer side surface SP1_cs′ of the upper support pattern SP1′ has a configuration of a concave surface, the semiconductor device 200b according to some example embodiments may be similar to the reference Figure 1 and Figures 6A to 6C The examples described are the same or similar.

[0161] The curvature of the outer side surface SP1_cs' of the upper support member pattern SP1' may decrease from the upper region UR to the lower region LR. For example, the curvature in the lower region LR may be smaller than the curvature in the upper region UR. More specifically, in some example embodiments, the shape of the outer side surface SP1_cs' of the upper support member pattern SP1' may become similar to the reference region LR from the upper region UR toward the lower region LR. Figure 7 The shape of the outer side surface SP1_fs' of the upper support pattern SP1' is described.

[0162] Figures 9 to 20 are vertical cross-sectional views illustrating processes of a method of manufacturing a semiconductor device according to some example embodiments.

[0163] Reference Figure 9 , a mold structure ST may be formed on the lower structure including the substrate 101, the word lines, and the bit line structure BLS.

[0164] The molding structure ST may be formed by conformally forming an etch stop layer 168 on the lower structure and alternately stacking a molding layer 118 and preliminary support structures SS1p, SS2p, and SS3p on the etch stop layer 168. The molding structure ST may be disposed in the cell area CA, the interface area IA, and the peripheral circuit area PA.

[0165] Reference Figure 10 , in the cell area CA, a lower electrode structure 170 may be formed in the mold structure ST.

[0166] The lower electrode structure 170 may be formed by forming a hole by etching the mold structure ST and the etch stop layer 168 to expose the upper conductive pattern 160, and filling the hole with a conductive material. Figure 2A As shown in FIG, the lower electrode structure 170 may be provided in a honeycomb structure.

[0167] Reference Figure 11 , a hard mask HM may be formed on the mold structure ST across the cell area CA and the peripheral circuit area PA.

[0168] In the hard mask HM, a first layer M1 formed on the upper surface of the mold structure ST and a second layer M2 on the first layer M1 may be sequentially formed. The first layer M1 may be an amorphous carbon thin film layer deposited by a chemical vapor deposition (CVD) method, and the second layer M2 may be formed by a spin coating method and may include silicon oxynitride.

[0169] Reference Figure 12 , a photoresist layer PR having an open area P1 may be formed on the hard mask HM.

[0170] When viewed from above, the shape of the open area P1 of the photoresist layer PR may be similar to a circular shape formed by extending the outer side surface SP1_s of the upper support pattern SP1 in a conceptual curve and connecting the surfaces to each other (see FIG. Figure 2A In a different viewpoint, the photoresist layer PR may include a plurality of portions having a cylindrical shape.

[0171] Reference Figure 13 , you can use the Figure 12 The hard mask HM is patterned using the photoresist layer PR.

[0172] Reference Figure 13 The hard mask HM may be patterned using the photoresist layer PR so that at least a portion of the upper surface of the mold structure ST may be exposed. Thus, the patterned hard mask HM may have a first etch region OE1.

[0173] Through the patterning, the entire upper surface of the mold structure ST may be exposed in the peripheral circuit area PA.

[0174] The photoresist layer PR and the patterned second layer M2 may be removed so that only the patterned first layer M1 may remain. Here, the patterned second layer M2 may not be removed and may remain together with the patterned first layer M1.

[0175] Reference Figure 14 , an exposure device may be disposed on the first layer M1 (or the hard mask HM) having the first etch region OE1 , and a predetermined solvent W may be applied between the first layer M1 and a lens of the exposure device.

[0176] Refer to it together Figure 14 and Figure 15 , an etched region H penetrating the preliminary support structures SS1p, SS2p, and SS3p and the mold layer 118 may be formed by an immersion exposure method IL. Here, the immersion exposure method IL may be argon fluoride immersion exposure (ArF immersion lithography), and the predetermined solvent W may include water. According to some example embodiments, forming the etched region H by the argon fluoride immersion lithography (ArF immersion lithography) method may resolve the limitation of the minimum pitch between support patterns and may achieve a cost reduction effect.

[0177] Reference Figure 15 Through the immersion exposure method IL, an etch region H penetrating the preliminary support structures SS1p, SS2p, and SS3p and the mold layer 118 may be formed so that the surface of the etch stop layer 168 may be exposed.

[0178] In the peripheral circuit region PA, the mold structure ST may be completely removed. Thereafter, the remaining hard mask HM and the predetermined solvent W may be removed.

[0179] Reference Figure 16 , the remaining mold layer 118 in the cell area CA may be selectively removed.

[0180] Thus, the side surface of the lower electrode structure 170 may be exposed, and a plurality of supporter structures SS1 , SS2 , and SS3 supporting the lower electrode structure 170 at different heights may be formed.

[0181] Reference Figure 17 A dielectric layer 172 may be conformally formed along the surface of the lower electrode structure 170 and the support structures SS1 , SS2 , and SS3 . The dielectric layer 172 may also cover the etch stop layer 168 and the etch stop layer 68 .

[0182] Reference Figure 18, an upper electrode structure 174 covering the dielectric layer 172 may be formed in the cell area CA, the interface area IA, and the peripheral circuit area PA. The upper electrode structure 174 may fill the spaces between the lower electrode structures 170 and may cover the lower electrode structures 170 and the support structures SS1, SS2, and SS3. The lower electrode structures 170, the dielectric layer 172, and the upper electrode structure 174 may form a data storage structure CAP.

[0183] Reference Figure 19 The dielectric layer 172 and the upper electrode structure 174 in the peripheral circuit area PA may be removed by an etching process. Thus, the etch stop layer 68 may be exposed.

[0184] A lower interlayer insulating layer 186 may be formed on the exposed etch stop layer 68. The lower interlayer insulating layer 186 may also be formed on the etch stop layer 168 in the interface region 1A (not shown). A planarization process may be performed on the lower interlayer insulating layer 186 so that the lower interlayer insulating layer 186 may be present at the same height as the upper surface of the upper electrode structure 174.

[0185] Reference Figure 20 , an upper interlayer insulating layer 188 may be formed on the upper electrode structure 174 and the lower interlayer insulating layer 186 .

[0186] Thereafter, in the cell area CA, the cell contact plug CCP may penetrate the upper interlayer insulating layer 188 and may be connected to the data storage structure CAP. In the peripheral circuit area PA, the peripheral contact plug PCP may penetrate the upper interlayer insulating layer 188 and the lower interlayer insulating layer 186 and may be connected to the peripheral interconnection 60.

[0187] Afterwards, refer to Figure 2B , an interlayer insulating layer ILD may be formed on the upper interlayer insulating layer 188 , and upper contact plugs 92 and 95 penetrating the interlayer insulating layer ILD may be formed, so that the semiconductor device 100 may be manufactured.

[0188] According to the aforementioned example embodiments, a semiconductor device including a support structure having various designs according to the arrangement of a data storage structure may be provided.

[0189] Specifically, a semiconductor device including a support pattern having various designs according to the arrangement of a lower electrode structure of a data storage structure in a horizontal direction may be provided.

[0190] More specifically, by providing a semiconductor device including support patterns patterned to contact a plurality of second lower electrode structures surrounding and most adjacent to the first lower electrode structure, the limitation of the minimum pitch between support patterns can be resolved in a patterning process.

[0191] While certain example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the example embodiments as defined by the appended claims.

Claims

1. A semiconductor device comprising: an integrated circuit structure including a conductive region; a capacitor comprising a lower electrode structure electrically connected to a conductive region of an integrated circuit structure, a dielectric layer covering the lower electrode structure, and an upper electrode structure on the dielectric layer, the lower electrode structures being spaced apart from each other on the integrated circuit structure; as well as A support structure interconnecting the lower electrode structure, The support structure includes: an upper support structure interconnecting upper regions of the lower electrode structures with each other, the upper support structure including upper support patterns spaced apart from each other; and a lower support structure including lower support patterns interconnecting the lower electrode structures with each other, the lower support patterns being spaced apart from each other below the upper support pattern, wherein an outer side surface of the upper support pattern of the upper support structure and an outer side surface of an upper region of the lower electrode structure connected to each other through the upper support pattern define an upper open pattern extending in a horizontal direction, wherein an outer side surface of the lower support pattern of the lower support structure and an outer side surface of the lower electrode structure connected to each other through the lower support pattern define a lower open pattern extending in a horizontal direction, and Wherein, the first center of the upper support member pattern of the upper support member structure and the second center of the lower support member pattern of the lower support member structure corresponding to the first center are aligned respectively.

2. The semiconductor device according to claim 1, wherein Each of the upper support patterns of the upper support structure surrounds at least one first lower electrode structure of the lower electrode structures and contacts at least a portion of a side surface of each of a plurality of second lower electrode structures adjacent to the at least one first lower electrode structure.

3. The semiconductor device according to claim 2, wherein An outer side surface of the upper support pattern between second lower electrode structures adjacent to each other among the plurality of second lower electrode structures has a convex shape in a direction away from a center of the upper support pattern.

4. The semiconductor device according to claim 2, wherein An outer side surface of the upper support pattern between second lower electrode structures adjacent to each other among the plurality of second lower electrode structures has a flat surface.

5. The semiconductor device according to claim 2, wherein An outer side surface of the upper supporter pattern between second lower electrode structures adjacent to each other among the plurality of second lower electrode structures has a concave shape in a direction toward a center of the upper supporter pattern. The semiconductor device according to claim 1 , wherein: Each of the upper support patterns of the upper support structure surrounds an entire side surface of a first lower electrode structure among the lower electrode structures and contacts a portion of a side surface of each of a plurality of second lower electrode structures adjacent to the first lower electrode structure.

7. The semiconductor device according to claim 6, wherein A distance between centers of upper support patterns adjacent to each other in a horizontal direction is configured to be greater than or equal to 76 nm and less than or equal to 100 nm.

8. The semiconductor device according to claim 6, wherein At least one of the lower support patterns of the lower support structure surrounds the first lower electrode structure and contacts at least a portion of a side surface of each of the plurality of second lower electrode structures adjacent to the first lower electrode structure, and The at least one of the lower support patterns is between the upper support structure and the integrated circuit structure.

9. The semiconductor device according to claim 8, wherein A maximum horizontal width of the lower support pattern of the lower support structure is greater than a maximum horizontal width of the upper support pattern of the upper support structure.

10. The semiconductor device according to claim 8, wherein In a plan view, a circumferential surface of the second lower electrode structure contacts an inner side surface of the lower support pattern.

11. The semiconductor device according to claim 1, wherein At least one of the upper support member patterns of the upper support member structure surrounds the entire side surface of a plurality of first lower electrode structures in the lower electrode structure, the plurality of first lower electrode structures are adjacent to each other, and the at least one of the upper support member patterns is in contact with at least a portion of the side surface of each of a plurality of second lower electrode structures adjacent to each of the plurality of first lower electrode structures.

12. The semiconductor device according to claim 11, wherein A distance between centers of upper support patterns adjacent to each other in a horizontal direction is configured to be greater than or equal to 95 nm and less than or equal to 110 nm.

13. The semiconductor device according to claim 1, further comprising: The middle support structure is between the upper support structure and the lower support structure. wherein the intermediate support structure includes intermediate support patterns spaced apart from each other and interconnecting the lower electrode structures with each other, and Herein, outer side surfaces of the intermediate support pattern of the intermediate support structure and outer side surfaces of the lower electrode structures connected to each other through the intermediate support pattern define an intermediate open pattern extending in a horizontal direction.

14. The semiconductor device according to claim 13, wherein The third center of the intermediate support pattern of the intermediate support structure is aligned with the first center and the second center corresponding to the third center.

15. The semiconductor device according to claim 13, wherein The maximum horizontal width of the middle support pattern is greater than the maximum horizontal width of the upper support pattern, and Wherein, the maximum horizontal width of the lower support member pattern is greater than the maximum horizontal width of the middle support member pattern.

16. The semiconductor device according to claim 1, wherein The upper open pattern and the lower open pattern are filled with the upper electrode structure.

17. A semiconductor device comprising: an integrated circuit structure including a conductive region; A capacitor comprising a lower electrode structure electrically connected to a conductive region of an integrated circuit structure, a dielectric layer covering the lower electrode structure, and an upper electrode structure on the dielectric layer; an upper support structure including upper support patterns spaced apart from each other, each of the upper support patterns surrounding at least one first lower electrode structure of the lower electrode structures, and each of the upper support patterns contacting at least a portion of a side surface of each of a plurality of second lower electrode structures adjacent to the at least one first lower electrode structure; as well as a lower support structure below the upper support structure and including lower support patterns having centers aligned with centers of the upper support patterns, wherein at least a portion of the upper electrode structure of the capacitor surrounds a side surface of each of the upper support patterns and extends in a horizontal direction between the upper support patterns, and At least a portion of the upper electrode structure of the capacitor surrounds a side surface of each of the lower support patterns and extends in a horizontal direction between the lower support patterns.

18. The semiconductor device according to claim 17, wherein In a plan view, a portion of the at least one first lower electrode structure is not surrounded by the dielectric layer.

19. A semiconductor device comprising: integrated circuit structures, including conductive regions; A capacitor comprising a lower electrode structure electrically connected to a conductive region of an integrated circuit structure, a dielectric layer covering the lower electrode structure, and an upper electrode structure on the dielectric layer; as well as a support structure comprising a support pattern group sequentially located at different heights on the integrated circuit structure, the support pattern group surrounding at least one first lower electrode structure among the lower electrode structures at different heights and contacting at least a portion of a side surface of each of a plurality of second lower electrode structures adjacent to the at least one first lower electrode structure, The support member pattern group of the support member structure includes: upper support member patterns at the same height as that of the upper region of the lower electrode structure and spaced apart from each other in a horizontal direction; intermediate supporter patterns below the upper supporter patterns and having centers aligned with centers of the upper supporter patterns, respectively; and lower support patterns between the intermediate support pattern and the integrated circuit structure and having centers aligned with centers of the intermediate support patterns, respectively, wherein a minimum distance between outer side surfaces of mutually adjacent upper support patterns among the upper support patterns is greater than a minimum distance between outer side surfaces of mutually adjacent intermediate support patterns among the intermediate support patterns, and The minimum distance between outer side surfaces of adjacent intermediate support patterns among the intermediate support patterns is greater than the minimum distance between outer side surfaces of adjacent lower support patterns among the lower support patterns.

20. The semiconductor device according to claim 19, wherein A first angle between a side surface of the lower support pattern and at least one side surface of the plurality of second lower electrode structures is greater than a second angle between a side surface of the intermediate support pattern and at least one side surface of the plurality of second lower electrode structures, and The second angle is greater than a third angle between a side surface of the upper support pattern and at least one side surface of the plurality of second lower electrode structures.

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