Insulated gate bipolar transistor and manufacturing method

Abstract

The invention provides an insulated gate bipolar transistor and a manufacturing method thereof, belongs to the technical field of semiconductor devices, and is used for solving the problem that a gate of the insulated gate bipolar transistor is poor in stability and reliability. The insulated gate bipolar transistor comprises an N-type drift region, a front MOS (Metal Oxide Semiconductor) structure region, a planar PMOS (P-channel Metal Oxide Semiconductor) structure region and a P-type collector region. The N-type drift region includes an upper surface and a lower surface. And the front MOS structure region is positioned on the upper surface of the N-type drift region. And the planar PMOS structure region is positioned on the upper surface of the N-type drift region and is positioned on one side of the front MOS structure region. The P-type collector region is located on the lower surface of the N-type drift region. According to the insulated gate bipolar transistor, compromise between forward conduction voltage drop and turn-off loss of a device is better achieved, and meanwhile the reliability of the insulated gate bipolar transistor is enhanced.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to an insulated gate bipolar transistor and a manufacturing method thereof. Background Art

[0002] Insulated-gate bipolar transistors (IGBTs) are widely used in high-voltage, high-temperature, and high-power applications. However, further development of IGBTs is hampered by interface issues, dv / dt controllability, electromagnetic interference (EMI), dynamic avalanche, and short-circuit robustness. The high current density and high dv / dt during IGBT turn-off can trigger dynamic avalanche, generating more excess carriers. These excess carriers can have sufficient energy to inject into the trench oxide, compromising gate stability and causing reliability issues. While current IGBT research primarily focuses on the trade-off between output and turn-off characteristics, reliability issues are becoming a growing research focus driven by application needs.

[0003] Insulated gate bipolar transistors (IGBTs) typically have two basic structures: planar gate and trench gate. Planar gate IGBTs, due to the presence of a junction field-effect transistor (JFET) region, result in high resistance and poor on-state characteristics. Trench gate IGBTs, on the other hand, eliminate the JFET region, reducing resistance, increasing channel density, and significantly improving on-state characteristics. However, while the introduction of conductivity modulation significantly reduces on-state resistance and conduction losses in IGBTs, the presence of excess carriers within the device significantly increases turn-off losses when the device is turned off. Furthermore, since a majority of carriers still exist during the off-state phase, the stored excess holes dissipate through the P-type well region. When the electric field concentrates beneath the trench gate, the peak electric field exceeds the critical electric field. At this point, even if the collector voltage is well below the off-state breakdown voltage, dynamic avalanche is triggered, generating more excess carriers and leading to additional losses. Furthermore, the generated excess carriers may have sufficient energy to be injected into the trench oxide, compromising gate stability and causing related reliability issues. Summary of the Invention

[0004] Therefore, the technical problem to be solved by the present invention is to provide an insulated gate bipolar transistor and a manufacturing method thereof, which can reduce the on-state voltage drop and turn-off loss, and can also suppress dynamic avalanche.

[0005] To address the above-mentioned issues, the first aspect of the present invention provides an insulated gate bipolar transistor, comprising: an N-type drift region, a front-side MOS structure region, a planar PMOS structure region, and a P-type collector region. The N-type drift region includes an upper surface and a lower surface. The front-side MOS structure region is located on the upper surface of the N-type drift region. The planar PMOS structure region is located on the upper surface of the N-type drift region and is located on one side of the front-side MOS structure region. The P-type collector region is located on the lower surface of the N-type drift region.

[0006] Optionally, the front MOS structure region includes: a P-type Well region, an N-type source region, a P-type source region, and a trench gate structure region. The P-type Well region is arranged on the upper surface of the N-type drift region. The N-type source region is arranged on the upper surface of the P-type Well region. The P-type source region is arranged on the upper surface of the P-type Well region. The P-type source region is located on a side of the N-type source region away from the planar PMOS structure region. The trench gate structure region is located on the upper surface of the N-type drift region. The trench gate structure region is located on a side of the P-type Well region and the N-type source region that is close to the planar PMOS structure region.

[0007] Optionally, the trench gate structure region includes a trench, a trench gate oxide layer, and a gate material. The trench extends from the upper surface of the N-type drift region toward the interior of the N-type drift region and extends below the P-type well region. The trench gate oxide layer covers the surface of the trench. The gate material fills the trench.

[0008] Optionally, the planar PMOS structure region includes: a P-type shielding region, an N-type Well region, a P-type ohmic contact region, and a planar gate structure region. The P-type shielding region is arranged on the upper surface of the N-type drift region. The N-type Well region is arranged in the P-type shielding region. The N-type Well region is close to the side of the P-type shielding region away from the N-type drift region. The P-type ohmic contact region extends from the surface of the P-type shielding region away from the N-type drift region to the N-type Well region. The planar gate structure region is located above the P-type ohmic contact region.

[0009] Optionally, the planar gate structure region includes: a planar gate oxide layer and a gate material layer. The planar gate oxide layer covers the upper surface of the P-type shielding region and the P-type ohmic contact region. The gate material layer is disposed on the planar gate oxide layer.

[0010] Optionally, the insulated gate bipolar transistor further includes an isolation dielectric layer and an N-type buffer layer. The isolation dielectric layer covers the upper surfaces of the front MOS structure region and the planar PMOS structure region. The isolation dielectric layer includes two metal connection holes. The two metal connection holes respectively connect the front MOS structure region and the planar PMOS structure region. The two metal connection holes are filled with metal material. The N-type buffer layer is disposed on the lower surface of the N-type drift region. The P-type collector region is disposed on a side of the N-type buffer layer away from the N-type drift region.

[0011] In a second aspect, the present invention further provides a method for manufacturing an insulated gate bipolar transistor, the method comprising the following steps:

[0012] A front MOS structure region is prepared on the upper surface of the N-type drift region;

[0013] A planar PMOS structure region is prepared on the upper surface of the N-type drift region;

[0014] A P-type collector region is prepared on the lower surface of the N-type drift region.

[0015] Optionally, a front MOS structure region is prepared on the upper surface of the N-type drift region, including:

[0016] A P-type Well region is prepared on the N-type drift region by P-type ion implantation;

[0017] An N-type source region is prepared on the P-type Well region by N-type ion implantation;

[0018] A P-type source region is prepared on the P-type Well region by P-type ion implantation;

[0019] forming a trench in the N-type drift region by etching;

[0020] growing a trench gate oxide layer on the surface of the trench;

[0021] A gate material is deposited on the trench gate oxide layer in the trench and etched to form a trench gate structure region.

[0022] Optionally, a planar PMOS structure region is prepared on the upper surface of the N-type drift region, including:

[0023] forming a P-type shielding region on the N-type drift region by implanting P-type ions;

[0024] An N-type Well region is prepared in the P-type shielding region by N-type ion implantation;

[0025] A P-type ohmic contact region is prepared in the P-type shielding region and the N-type Well region by P-type ion implantation;

[0026] growing a planar gate oxide layer on the surfaces of the P-type shielding region and the P-type ohmic contact region;

[0027] A gate material is deposited on the planar gate oxide layer and then etched to form a planar gate structure region.

[0028] Optionally, forming a P-type collector region on the lower surface of the N-type drift region includes:

[0029] forming an N-type buffer layer on the lower surface of the N-type drift region;

[0030] A P-type collector region is formed on the lower surface of the N-type buffer layer by ion implantation;

[0031] Metal is deposited on the lower surface of the P-type collector region to form a collector ohmic contact layer.

[0032] Beneficial effects

[0033] 1. The insulated gate bipolar transistor provided by the present invention includes an N-type drift region, a front MOS structure region, a planar PMOS structure region and a P-type collector region. The present invention provides a hole extraction path through a planar PMOS structure. When the device is turned on, the hole extraction path is turned off by controlling the planar PMOS structure, thereby improving the conductivity modulation effect and reducing the on-state voltage drop. When the device is turned off transiently, the hole extraction path is adaptively opened by the planar PMOS structure to extract holes, reducing the accumulation of holes under the trench gate, reducing the turn-off loss and suppressing dynamic avalanche. The present invention better achieves a compromise between the forward conduction voltage drop and the turn-off loss of the device, while enhancing its reliability.

[0034] 2. The insulated gate bipolar transistor fabrication method provided by the present invention can produce the aforementioned insulated gate bipolar transistor, significantly reducing on-state voltage drop and off-state losses while suppressing dynamic avalanche. This method does not affect the device's breakdown voltage or gate oxide electric field strength, and utilizes a relatively mature fabrication process, achieving a better compromise between the device's forward voltage drop and off-state losses. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic structural diagram of an insulated gate bipolar transistor according to an embodiment of the present invention;

[0036] Figure 2 A flowchart of a manufacturing method according to an embodiment of the present invention;

[0037] Figure 3 A flowchart of a manufacturing method according to another embodiment of the present invention;

[0038] Figure 4 A flowchart of a manufacturing method according to another embodiment of the present invention;

[0039] Figure 5 A flowchart of a manufacturing method according to another embodiment of the present invention.

[0040] The reference numerals indicate:

[0041] 100. Insulated gate bipolar transistor;

[0042] 110, N-type drift region; 120, front MOS structure region; 130, planar PMOS structure region; 140, P-type collector region; 150, isolation dielectric layer;

[0043] 111, N-type buffer layer;

[0044] 121, P-type Well region; 122, N-type source region; 123, P-type source region; 124, trench gate structure region;

[0045] 1241. trench; 1242. trench gate oxide layer; 1243. gate material;

[0046] 131. P-type shielding region; 132. N-type well region; 133. P-type ohmic contact region; 134. planar gate structure region;

[0047] 1341. Planar gate oxide layer; 1342. Gate material layer;

[0048] 141. P-type collector region; 142. collector ohmic contact layer;

[0049] 151. Metal connection hole; 152. Metal material. DETAILED DESCRIPTION

[0050] In the description of the present invention, it should be understood that the terms "upper", "lower", "top", "bottom", "inside", "outside", "thickness", "depth", "width", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0051] In addition, the semiconductor field terms used in this article are technical terms commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ represents P-type with heavy doping concentration, P- represents P-type with light doping concentration, N+ represents N-type with heavy doping concentration, and N- represents N-type with light doping concentration.

[0052] The preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0053] In a first aspect, this embodiment provides an insulated gate bipolar transistor 100 . Figure 1 This is a schematic structural diagram of an insulated gate bipolar transistor 100 provided in this embodiment.

[0054] like Figure 1As shown, this embodiment provides an insulated gate bipolar transistor 100 including an N-type drift region 110, a front MOS structure region 120, a planar PMOS structure region 130, and a P-type collector region 140. The N-type drift region 110 includes an upper surface and a lower surface. The front MOS structure region 120 is located on the upper surface of the N-type drift region 110. The planar PMOS structure region 130 is located on the upper surface of the N-type drift region 110 and is located on one side of the front MOS structure region 120. The P-type collector region 140 is located on the lower surface of the N-type drift region 110.

[0055] In some examples, such as Figure 1 As shown, the insulated gate bipolar transistor 100 includes two planar PMOS structure regions 130. The two planar PMOS structure regions 130 are symmetrically arranged. Such an arrangement is conducive to extracting holes and reducing the accumulation of holes under the trench gate.

[0056] For some examples, see Figure 1 The N-type drift region 110 may be formed by epitaxial growth on an N-type substrate. For example, the N-type substrate may be made of silicon carbide (SiC).

[0057] In some examples, such as Figure 1 As shown, the N-type drift region 110 is an N-region.

[0058] The insulated gate bipolar transistor 100 of this embodiment includes an N-type drift region 110, a front MOS structure region 120, a planar PMOS structure region 130, and a P-type collector region 140. The present invention provides a hole extraction path through the planar PMOS structure region 130. When the device is turned on, the hole extraction path is turned off by controlling the planar PMOS structure region 130, thereby improving the conductivity modulation effect and reducing the on-state voltage drop. When the device is turned off transiently, the planar PMOS structure region 130 adaptively opens the hole extraction path to extract holes, reducing the accumulation of holes under the trench gate of the front MOS structure region 120, reducing the turn-off loss while suppressing dynamic avalanche, and better achieving a compromise between the forward conduction voltage drop and the turn-off loss of the device, while enhancing its reliability.

[0059] In some embodiments, as Figure 1As shown, the front MOS structure region 120 includes: a P-type Well region 121, an N-type source region 122, a P-type source region 123 and a trench gate structure region 124. The P-type Well region 121 is arranged on the upper surface of the N-type drift region 110. The N-type source region 122 is arranged on the upper surface of the P-type Well region 121. The P-type source region 123 is arranged on the upper surface of the P-type Well region 121. The P-type source region 123 is located on the side of the N-type source region 122 away from the planar PMOS structure region 130. The trench gate structure region 124 is located on the upper surface of the N-type drift region 110. The trench gate structure region 124 is located on the side of the P-type Well region 121 and the N-type source region 122 close to the planar PMOS structure region 130.

[0060] In some examples, such as Figure 1 As shown, the depth of the P-type well region 121 relative to the upper surface of the N-type drift region 110 is 1.0-3.0 μm. This configuration not only meets the requirements of use but also helps control the volume of the insulated gate bipolar transistor 100. Those skilled in the art can select the appropriate depth based on specific electrical performance requirements, and this embodiment does not impose any additional restrictions on this.

[0061] In some examples, such as Figure 1 As shown, the depth of the N-type source region 122 relative to the upper surface of the N-type drift region 110 is 0.5-2.0 μm. This configuration can meet the use requirements while also helping to control the volume of the insulated gate bipolar transistor 100. Those skilled in the art can make corresponding choices based on specific electrical performance requirements, and this embodiment does not impose too many restrictions on this.

[0062] In some examples, such as Figure 1 As shown, the depths of the P-type source region 123 and the N-type source region 122 are equal.

[0063] In some examples, such as Figure 1 As shown, the P-type Well region 121 is a P- region, the N-type source region 122 is an N+ region, and the P-type source region 123 is a P+ region.

[0064] In some examples, such as Figure 1 As shown, the trench gate structure region 124 may be made of polysilicon gate, aluminum gate, etc. This embodiment does not impose too many restrictions on this.

[0065] The surface MOS structure region 120 of this embodiment includes a P-type Well region 121, an N-type source region 122, a P-type source region 123 and a trench gate structure region 124. The trench gate structure region 124 is located on the side of the P-type Well region 121 and the N-type source region 122 close to the planar PMOS structure region 130, eliminating the junction field effect transistor structure, which is beneficial to reducing resistance and improving conduction characteristics.

[0066] In some embodiments, as Figure 1 As shown, the trench gate structure region 124 includes a trench 1241, a trench gate oxide layer 1242, and a gate material 1243. The trench 1241 extends from the upper surface of the N-type drift region 110 toward the interior of the N-type drift region 110 and extends below the P-type well region 121. The trench gate oxide layer 1242 covers the surface of the trench 1241. The gate material 1243 fills the trench 1241.

[0067] In some examples, such as Figure 1 As shown, the depth of the groove 1241 is 2-6 μm. This setting can meet the performance requirements. Those skilled in the art can select the corresponding depth of the groove 1241 according to the specific electrical performance requirements, and this embodiment does not impose too many restrictions on this.

[0068] In some examples, such as Figure 1 As shown, the thickness of the trench gate oxide layer 1242 is 50-120 nm. Those skilled in the art can select a corresponding thickness according to specific usage requirements, and this embodiment does not impose too many restrictions on this.

[0069] For some examples, see Figure 1 , the gate material 1243 is a polysilicon gate or an aluminum gate.

[0070] The trench gate structure region 124 of this embodiment includes a trench 1241 , a trench gate oxide layer 1242 and a gate material 1243 . Providing the trench gate oxide layer 1242 between the surface of the trench 1241 and the gate material 1243 can modulate the conductance of the channel and improve the stability of the device.

[0071] In some embodiments, as Figure 1 As shown, the planar PMOS structure region 130 includes: a P-type shielding region 131, an N-type Well region 132, a P-type ohmic contact region 133 and a planar gate structure region 134. The P-type shielding region 131 is arranged on the upper surface of the N-type drift region 110. The N-type Well region 132 is arranged in the P-type shielding region 131. The N-type Well region 132 is close to the side of the P-type shielding region 131 away from the N-type drift region 110. The P-type ohmic contact region 133 extends from the surface of the P-type shielding region 131 away from the N-type drift region 110 to the N-type Well region 132. The planar gate structure region 134 is located above the P-type ohmic contact region 133.

[0072] In some examples, such as Figure 1As shown, the depth of the P-type shielding region 131 relative to the upper surface of the N-type drift region 110 is 2.0-7.0 μm. This configuration can meet performance requirements. Those skilled in the art can select the appropriate depth based on specific electrical performance requirements, and this embodiment does not impose any additional restrictions on this.

[0073] In some examples, such as Figure 1 As shown, the width of the N-type well region 132 is 1.3-1.6 μm and the depth is 1.0-5.0 μm relative to the upper surface of the N-type drift region 110. This configuration can meet performance requirements. Those skilled in the art can select the appropriate depth based on specific electrical performance requirements, and this embodiment does not impose any additional restrictions on this.

[0074] In some examples, such as Figure 1 As shown, the width of the P-type ohmic contact region 133 relative to the upper surface of the N-type drift region 110 is 0.7-1.0 μm, and the depth is 0.5-3.0 μm. This configuration can meet performance requirements. Those skilled in the art can select the appropriate depth based on specific electrical performance requirements, and this embodiment does not impose too many restrictions on this.

[0075] In some examples, such as Figure 1 As shown, the planar gate structure region 134 may be made of polysilicon gate, aluminum gate, etc. This embodiment does not impose too many restrictions on this.

[0076] In some examples, such as Figure 1 As shown, the P-type shielding region 131 is a P-region, the N-type Well region 132 is an N-region, and the P-type ohmic contact region 133 is a P+region.

[0077] The planar PMOS structure region 130 of this embodiment includes a P-type shielding region 131, an N-type Well region 132, a P-type ohmic contact region 133 and a planar gate structure region 134, and a hole extraction path is provided through the planar PMOS structure. When the device is turned on, a hole barrier can be formed below the planar gate structure region 134 to prevent holes from flowing out of the emitter, shutting off the hole extraction path, thereby improving the conductivity modulation effect and reducing the on-state voltage drop. During the device off-state transient, the hole extraction path adaptively opens to extract holes and reduce the turn-off loss. At the same time, the accumulation of holes below the trench gate oxide layer 1242 is reduced to suppress dynamic avalanche, thereby better achieving a compromise between the forward conduction voltage drop and the turn-off loss of the device, and enhancing its reliability.

[0078] In some embodiments, as Figure 1As shown, the planar gate structure region 134 includes a planar gate oxide layer 1341 and a gate material layer 1342. The planar gate oxide layer 1341 covers the upper surface of the P-type shield region 131 and the P-type ohmic contact region 133. The gate material layer 1342 is disposed on the planar gate oxide layer 1341.

[0079] In some examples, such as Figure 1 As shown, the thickness of the planar gate oxide layer 1341 is 50-120 nm. Those skilled in the art can select a corresponding thickness according to specific usage requirements, and this embodiment does not impose too many restrictions on this.

[0080] For some examples, see Figure 1 The material of the planar gate oxide layer 1341 is silicon dioxide. Using silicon dioxide as a gate material can have good insulation properties and can effectively isolate the charge between the gate electrode and the underlying material. In addition, silicon dioxide has good interface properties and can have good matching with the silicon substrate material to form a uniform and smooth interface. In addition, silicon dioxide has good process controllability, with adjustable deposition methods and process parameters, making it easy to achieve the required film thickness and quality control during the manufacturing process.

[0081] In some examples, such as Figure 1 As shown, the planar gate oxide layer 1341 and the trench gate oxide layer 1242 are connected to each other, and the two are formed through a single process.

[0082] The planar gate structure region 134 of this embodiment includes a planar gate oxide layer 1341 and a gate material layer 1342 . The gate material layer 1342 is disposed on the planar gate oxide layer 1341 . This configuration forms a planar PMOS structure, providing a hole extraction path.

[0083] In some embodiments, as Figure 1 As shown, the insulated gate bipolar transistor 100 further includes an isolation dielectric layer 150 and an N-type buffer layer 111. The isolation dielectric layer 150 covers the upper surfaces of the front MOS structure region 120 and the planar PMOS structure region 130. The isolation dielectric layer 150 includes two metal connection holes 151. The two metal connection holes 151 respectively connect the front MOS structure region 120 and the planar PMOS structure region 130. The two metal connection holes 151 are filled with metal material 152. The N-type buffer layer 111 is disposed on the lower surface of the N-type drift region 110. The P-type collector region 141 is disposed on a side of the N-type buffer layer 111 away from the N-type drift region 110.

[0084] In some examples, such as Figure 1 As shown, the material of the isolation dielectric layer 150 includes at least one of silicon dioxide, silicon nitride, and borophosphosilicate glass.

[0085] In some examples, such as Figure 1 As shown, one metal connection hole 151 is connected to two planar PMOS structure regions 130 at the same time.

[0086] In some examples, such as Figure 1 As shown, the thickness of the N-type buffer layer 111 is 1-10 μm. This setting can meet the performance requirements. Those skilled in the art can select the corresponding thickness according to the specific electrical performance requirements, and this embodiment does not impose too many restrictions on this.

[0087] In some examples, such as Figure 1 As shown, the N-type buffer layer 111 is an N-region.

[0088] In this embodiment, an isolation dielectric layer 150 is deposited on the upper surfaces of the front MOS structure region 120 and the planar PMOS structure region 130. An emitter metal connection hole 151 is formed by etching the isolation dielectric layer 150, and a metal material 152 is deposited in the metal connection hole 151 to form an emitter ohmic contact. This does not affect the circuit connection of the insulated gate bipolar transistor 100, but can also protect the front MOS structure region 120 and the planar PMOS structure region 130.

[0089] In a second aspect, this embodiment provides a method for manufacturing an insulated gate bipolar transistor 100 . Figure 2 This is a flowchart of a manufacturing method provided in this embodiment.

[0090] like Figure 2 As shown, this embodiment provides a method for manufacturing an insulated gate bipolar transistor 100, comprising the following steps:

[0091] A front MOS structure region 120 is formed on the upper surface of the N-type drift region 110;

[0092] A planar PMOS structure region 130 is formed on the upper surface of the N-type drift region 110 ;

[0093] A P-type collector region 140 is formed on the lower surface of the N-type drift region 110 .

[0094] In some examples, such as Figure 1 As shown, the doping concentration and thickness of the N-type drift region 110 can be set according to the breakdown voltage, forward voltage drop, and dynamic characteristics of the insulated gate bipolar transistor 100. This embodiment does not impose too many restrictions on this.

[0095] It is understood that the manufacturing method of this embodiment can first form the upper surface structure of the N-type drift region 110, and then complete the related processes for the lower surface of the N-type drift region 110. Alternatively, the related processes for the lower surface of the N-type drift region 110 can be performed first, and then the upper surface structure of the N-type drift region 110 is completed. This embodiment does not impose too many restrictions on this.

[0096] The insulated gate bipolar transistor manufacturing method of this embodiment can produce the insulated gate bipolar transistor 100 of the above-mentioned embodiment, which can significantly reduce the on-state voltage drop and turn-off loss, and can suppress dynamic avalanche. It does not affect the breakdown voltage and gate oxide electric field strength of the device, adopts a more mature preparation process, and better achieves a compromise between the forward conduction voltage drop and turn-off loss of the device. In addition, the insulated gate bipolar transistor 100 structure obtained by the insulated gate bipolar transistor manufacturing method provided by this embodiment can be used as an IGBT cell structure. When completing the structure of the upper surface (front) and lower surface (back) of the N-type drift region, it is compatible with the traditional IGBT process and does not involve additional process operations, which is beneficial to reduce processing difficulty and cost and improve production efficiency.

[0097] Figure 3 Flowchart of another manufacturing method provided in this embodiment. In some embodiments, as Figure 3 As shown, a front MOS structure region 120 is prepared on the upper surface of the N-type drift region 110, including:

[0098] A P-type Well region 121 is formed on the N-type drift region 110 by P-type ion implantation;

[0099] Specifically, the doping level of the P-type Well region 121 is 2.0×10 16 -2.0×10 17 cm -3 , with a depth of 1-3μm.

[0100] An N-type source region 122 is formed on the P-type Well region 121 by N-type ion implantation;

[0101] Specifically, the doping level of the N-type source region 122 is 1.0×10 19 -1.0×10 20 cm -3 .

[0102] A P-type source region 123 is formed on the P-type Well region 121 by P-type ion implantation;

[0103] Specifically, the doping level of the P-type source region 123 is 1.0×10 19 -1.0×10 20 cm -3 , the depth is 0.5-2.0μm.

[0104] A trench 1241 is formed in the N-type drift region 110 by etching;

[0105] Specifically, the depth of the groove 1241 is 2-6 μm.

[0106] Growing a trench gate oxide layer 1242 on the surface of the trench 1241;

[0107] Specifically, the thickness of the trench gate oxide layer 1242 is 50-120 nm.

[0108] A gate material 1243 is deposited on the trench gate oxide layer 1242 in the trench 1241 and then etched to form a trench gate structure region 124 .

[0109] Specifically, the gate material 1243 may be a polysilicon gate or an aluminum gate.

[0110] The front MOS structure 120 is prepared using the method of this embodiment, which is compatible with the traditional IGBT process and does not involve additional process operations, thereby reducing processing difficulty and cost and improving production efficiency.

[0111] Figure 4 Flowchart of another manufacturing method provided in this embodiment. In some embodiments, as Figure 4 As shown, a planar PMOS structure region 130 is prepared on the upper surface of the N-type drift region 110, including:

[0112] A P-type shielding region 131 is formed on the N-type drift region 110 by P-type ion implantation;

[0113] Specifically, the doping level of the P-type shielding region 131 is 1.0×10 17 -1.0×10 18 cm -3 , with a depth of 1-5μm.

[0114] An N-type Well region 132 is formed in the P-type shield region 131 by N-type ion implantation;

[0115] Specifically, the doping level of the N-type Well region 132 is 5.0×10 17 -5.0×10 18 cm -3 When forming the N-type Well region 132 through ion implantation, the implantation profile should be adjusted so that the N-type impurity concentration on the upper surface of the N-type Well region 132 is lower than the P-type impurity concentration in the P-type shield region 131, thereby ensuring that the area above the upper surface of the N-type Well region 132 remains the P-type shield region 131.

[0116] A P-type ohmic contact region 133 is formed in the P-type shield region 131 and the N-type Well region 132 by P-type ion implantation;

[0117] Specifically, the doping level of the P-type ohmic contact region 133 is 1.0×10 19 -1.0×10 20 cm -3 , with a depth of 0.5-3.0μm.

[0118] A planar gate oxide layer 1341 is grown on the surfaces of the P-type shielding region 131 and the P-type ohmic contact region 133 ;

[0119] Specifically, the thickness of the planar gate oxide layer 1341 is 50-120 nm.

[0120] A gate material 1342 is deposited on the planar gate oxide layer 1341 and then etched to form a planar gate structure region 134 .

[0121] Specifically, the gate material 1342 may be a polysilicon gate or an aluminum gate.

[0122] The method of this embodiment is used to prepare the planar PMOS structure 130 , which is compatible with the traditional IGBT process and does not involve additional process operations, thereby reducing processing difficulty and cost and improving production efficiency.

[0123] Figure 5 Flowchart of another manufacturing method provided in this embodiment. In some embodiments, as Figure 5 As shown, a P-type collector region 140 is formed on the lower surface of the N-type drift region 110, including:

[0124] An N-type buffer layer 111 is formed on the lower surface of the N-type drift region 110 ;

[0125] Specifically, the doping level of the N-type buffer layer 111 is 1.0×10 16 -1.0×10 17 cm -3 The N-type buffer layer 111 has a thickness of 1-10 μm. The doping concentration of the N-type buffer layer 111 is higher than that of the N-type drift region 110 thereunder.

[0126] A P-type collector region 141 is formed on the lower surface of the N-type buffer layer 111 by ion implantation;

[0127] Specifically, the doping level of the P-type collector region 141 is 1.0×10 18 -1.0×10 19 cm -3 , with a thickness of 1-3μm.

[0128] Metal is deposited on the lower surface of the P-type collector region 141 to form a collector ohmic contact layer 142 .

[0129] Specifically, the deposited metal material can be selected according to actual usage requirements, and this embodiment does not impose too many restrictions on this.

[0130] The method is used to prepare the P-type collector region 140 on the lower surface of the N-type drift region 110 . The process is simple, and is conducive to improving production efficiency and reducing costs.

[0131] It should be noted that the processing steps in the above embodiments can be changed in order according to the actual processing technology settings. For example, in some embodiments, the production Figure 1 The IGBT shown includes the following steps:

[0132] Step 1: epitaxially forming a P-type collector region 141 on an N-type substrate; wherein the N-type substrate may be an N+-SiC substrate, and the P-type collector region 141 is a P+ region;

[0133] Step 2: epitaxially forming an N-type buffer layer 111 on the P-type collector region 141; wherein the material of the N-type buffer layer 111 is SiC;

[0134] Step 3: epitaxially forming an N-type drift region 110 on the N-type buffer layer 111; wherein the material of the N-type drift region 110 is SiC;

[0135] Step 4: forming a P-type Well region 121 in the N-type drift region 110 by ion implantation;

[0136] Step 5: Prepare an N-type source region 122 in the P-type Well region 121 by ion implantation;

[0137] Step 6: forming a P-type shielding region 131 in the N-type drift region 110 by ion implantation;

[0138] Step 7: Prepare an N-type Well region 132 in the P-type shield region 131 by ion implantation;

[0139] Step 8: Prepare a P-type source region 123 and a heavily doped P-type ohmic contact region 133 by ion implantation;

[0140] Step 9: Etching a trench 1241 in the N-type drift region 110 , oxidizing, depositing, and etching polysilicon to form a trench gate structure region 124 and a planar gate structure region 134 ;

[0141] Step 10: depositing an isolation dielectric layer 150 on the upper surface of the N-type drift region 110, etching metal connection holes 151, and depositing metal material 152 to form an emitter ohmic contact;

[0142] In step 11 , the N-type substrate is removed by grinding, and metal is deposited on the lower surface of the P-type collector region 141 to form a collector ohmic contact layer 142 .

[0143] In other embodiments, making Figure 1 The IGBT shown includes the following steps:

[0144] Step 1: forming a P-type Well region 121 in the N-type drift region 110 by ion implantation;

[0145] Step 2: Prepare an N-type source region 122 in the P-type Well region 121 by ion implantation;

[0146] Step 3: forming a P-type shielding region 131 in the N-type drift region 110 by ion implantation;

[0147] Step 4: Prepare an N-type Well region 132 in the P-type shielding region 131 by ion implantation;

[0148] Step 5: Prepare a P-type source region 123 and a heavily doped P-type ohmic contact region 133 by ion implantation;

[0149] Step 6: Etching a trench 1241 in the N-type drift region 110 , oxidizing, depositing, and etching polysilicon to form a trench gate structure 124 and a planar gate structure 134 ;

[0150] Step 7: Deposit an isolation dielectric layer 150 on the upper surface of the N-type drift region 110, etch metal connection holes 151, and deposit metal material 152 to form an emitter ohmic contact;

[0151] Step 8: Thinning the lower surface of the N-type drift region 110 to a required thickness according to different withstand voltage requirements;

[0152] Step 9: Forming an N-type buffer layer 111 on the lower surface of the N-type drift region 110 by ion implantation;

[0153] Step 10: Forming a P-type collector region 141 on the lower surface of the N-type buffer layer 111 by ion implantation;

[0154] Step 11: Deposit metal on the lower surface of the P-type collector region 141 to form a collector ohmic contact layer 142 .

[0155] In some other embodiments, making Figure 1 The IGBT shown includes the following steps:

[0156] Step 1: epitaxially forming an N-type buffer layer 111 on the upper surface of an N-type substrate;

[0157] Step 2: epitaxially forming an N-type drift region 110 on the N-type buffer layer 111;

[0158] Step 3: forming a P-type Well region 121 in the N-type drift region 110 by ion implantation;

[0159] Step 4: Prepare an N-type source region 122 in the P-type Well region 121 by ion implantation;

[0160] Step 5: forming a P-type shielding region 131 in the N-type drift region 110 by ion implantation;

[0161] Step 6: Prepare an N-type Well region 132 in the P-type shielding region 131 by ion implantation;

[0162] Step 7: Prepare a P-type source region 123 and a heavily doped P-type ohmic contact region 133 by ion implantation;

[0163] Step 8: Etching a trench 1241 in the N-type drift region 110 , oxidizing, depositing, and etching polysilicon to form a trench gate structure 124 and a planar gate structure 134 ;

[0164] Step 9: Deposit a layer of isolation dielectric 150 on the upper surface of the N-type drift region 110, etch metal connection holes 151, and deposit metal material 152 to form an emitter ohmic contact;

[0165] Step 10: On the lower surface of the N-type substrate, use a thinning process to thin the N-type substrate to a desired thickness of the N-type buffer layer 111;

[0166] Step 11: forming a P-type collector region 141 on the lower surface of the N-type buffer layer 111 by ion implantation;

[0167] Step 12: Deposit metal on the lower surface of the P-type collector region 141 to form a collector ohmic contact layer 142 .

[0168] It is easy for those skilled in the art to understand that, under the premise of no conflict, the above-mentioned advantageous methods can be freely combined and superimposed.

[0169] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention. The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art may make various improvements and variations without departing from the technical principles of the present invention, and such improvements and variations shall also be considered within the scope of protection of the present invention.

Claims

1. An insulated gate bipolar transistor, characterized in that include: N-type drift region, including upper and lower surfaces; A front MOS structure region, located on the upper surface of the N-type drift region; a planar PMOS structure region, located on the upper surface of the N-type drift region and on one side of the front MOS structure region; The P-type collector region is located on the lower surface of the N-type drift region.

2. The insulated gate bipolar transistor according to claim 1, wherein The front MOS structure area includes: A P-type Well region is provided on the upper surface of the N-type drift region; An N-type source region is provided on the upper surface of the P-type Well region; A P-type source region is provided on the upper surface of the P-type Well region; and the P-type source region is located on a side of the N-type source region away from the planar PMOS structure region; A trench gate structure region is located on the upper surface of the N-type drift region; and the trench gate structure region is located on a side of the P-type Well region and the N-type source region close to the planar PMOS structure region.

3. The insulated gate bipolar transistor according to claim 2, wherein: The trench gate structure region includes: a trench extending from an upper surface of the N-type drift region toward an interior of the N-type drift region and extending to below the P-type Well region; a trench gate oxide layer covering the surface of the trench; A gate material is filled in the trench.

4. The insulated gate bipolar transistor according to claim 1, wherein: The planar PMOS structure region includes: A P-type shielding region, provided on the upper surface of the N-type drift region; An N-type Well region is disposed in the P-type shield region; and the N-type Well region is close to a side of the P-type shield region away from the N-type drift region; A P-type ohmic contact region extends from a surface of the P-type shield region away from the N-type drift region to the N-type Well region; The planar gate structure region is located above the P-type ohmic contact region.

5. The insulated gate bipolar transistor according to claim 4, wherein: The planar gate structure region includes: a planar gate oxide layer covering the upper surfaces of the P-type shielding region and the P-type ohmic contact region; The gate material layer is disposed on the planar gate oxide layer.

6. The insulated gate bipolar transistor according to any one of claims 1 to 5, wherein: Also includes: an isolation dielectric layer covering the upper surfaces of the front MOS structure region and the planar PMOS structure region; The isolation dielectric layer includes two metal connection holes; the two metal connection holes are respectively connected to the front MOS structure area and the planar PMOS structure area; the two metal connection holes are filled with metal material; An N-type buffer layer is provided on the lower surface of the N-type drift region; and the P-type collector region is provided on a side of the N-type buffer layer away from the N-type drift region.

7. A method for manufacturing an insulated gate bipolar transistor, characterized in that: The method comprises the following steps: A front MOS structure region is prepared on the upper surface of the N-type drift region; A planar PMOS structure region is prepared on the upper surface of the N-type drift region; A P-type collector region is prepared on the lower surface of the N-type drift region.

8. The method for manufacturing an insulated gate bipolar transistor according to claim 7, wherein: The method of preparing a front MOS structure region on the upper surface of the N-type drift region includes: A P-type Well region is prepared on the N-type drift region by P-type ion implantation; An N-type source region is prepared on the P-type Well region by N-type ion implantation; A P-type source region is prepared on the P-type Well region by P-type ion implantation; forming a trench in the N-type drift region by etching; growing a trench gate oxide layer on the surface of the trench; A gate material is deposited on the trench gate oxide layer in the trench and etched to form a trench gate structure region.

9. The method for manufacturing an insulated gate bipolar transistor according to claim 7, wherein: The method of preparing a planar PMOS structure region on the upper surface of the N-type drift region includes: forming a P-type shielding region on the N-type drift region by implanting P-type ions; An N-type Well region is prepared in the P-type shielding region by N-type ion implantation; A P-type ohmic contact region is prepared in the P-type shielding region and the N-type Well region by P-type ion implantation; growing a planar gate oxide layer on the surfaces of the P-type shielding region and the P-type ohmic contact region; A gate material is deposited on the planar gate oxide layer and then etched to form a planar gate structure region.

10. The method for manufacturing an insulated gate bipolar transistor according to claim 7, wherein: The step of preparing a P-type collector region on the lower surface of the N-type drift region comprises: forming an N-type buffer layer on the lower surface of the N-type drift region; A P-type collector region is formed on the lower surface of the N-type buffer layer by ion implantation; Metal is deposited on the lower surface of the P-type collector region to form a collector ohmic contact layer.

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