Metal-insulator-metal capacitor and manufacturing method thereof
By designing a vertical structure that spans adjacent electrode layers and intermetallic dielectric layers, the problem of insufficient effective capacitance area in existing metal-insulator-metal capacitors is solved, and the capacitance area is increased.
Patent Information
- Application Number
- CN202410283267.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-13
- Publication Date
- 2025-09-16
AI Technical Summary
The effective capacitance area of existing metal-insulator-metal capacitors with an interdigitated stacked structure is limited and cannot be further improved.
By redesigning the layout and structure of the electrode layer and the intermetallic dielectric layer of the capacitor, a vertical structure is formed that spans adjacent electrode layers and intermetallic dielectric layers, thereby increasing the total surface area between the electrode layer and the intermetallic dielectric layer.
The effective capacitance area of the metal-insulator-metal capacitor is increased, the total surface area between the electrode layer and the intermetallic dielectric layer is enhanced, and higher capacitance performance is achieved.
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Figure CN120659529A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a metal-insulator-metal capacitor and a method for manufacturing the same. Background Art
[0002] Current Metal-Insulator-Metal (MIM) or Metal-Oxide-Metal (MOM) capacitors mostly have a finger-type stacked structure.
[0003] However, because the lower and upper electrode layers of an interdigitated metal-insulator-metal capacitor are located in the same interconnect metal layer, and the back-end-of-line (BEOL) intermetallic dielectric layer serves as the intermetallic dielectric layer between the electrode layers, the effective capacitance area of the metal-insulator-metal capacitor is limited. Summary of the Invention
[0004] An embodiment of the present disclosure provides a method for manufacturing a capacitor structure, which includes the following steps. A lower intermetallic dielectric layer is formed above a substrate, and the substrate is defined with a middle region and a peripheral region. A finger-shaped opening is formed in the lower intermetallic dielectric layer, penetrating the lower intermetallic dielectric layer. A lower electrode layer is formed in the finger-shaped opening. A barrier layer is formed on the lower electrode layer and the lower intermetallic dielectric layer. An upper intermetallic dielectric layer is formed on the barrier layer. A plurality of mutually staggered grooves and a plurality of columnar openings formed between the staggered grooves are formed in the upper intermetallic dielectric layer in the middle region, and an annular recess is formed in the upper intermetallic dielectric layer in the peripheral region, and the columnar opening exposes the top surface of the lower electrode layer. Conductive material is filled in the columnar openings, the annular recess, and the staggered grooves to form a lower electrode unit, a first upper electrode layer, and a plurality of second upper electrode layers, respectively, and the bottom surface of the lower electrode unit is in contact with the top surface of the lower electrode layer.
[0005] In some embodiments, since the first width of the cylindrical opening is greater than the second width of the annular recess, when the cylindrical opening and the annular recess are formed, the first depth of the cylindrical opening is greater than the second depth of the annular recess.
[0006] In some embodiments, the annular recess exposes the top surface of the barrier layer.
[0007] In some embodiments, since the second width of the annular recess is greater than the third width of the groove, when the annular recess and the groove are formed, the second depth of the annular recess is greater than the third depth of the groove.
[0008] In some embodiments, the groove extends to the peripheral region and communicates with the annular recess.
[0009] Embodiments disclosed herein provide a capacitor structure comprising a substrate, an interconnect structure, and a capacitor. The substrate defines a middle region and a peripheral region surrounding the middle region. The interconnect structure is disposed above the substrate. The capacitor is disposed on the interconnect structure and comprises a lower intermetallic dielectric layer, a lower electrode layer, a plurality of lower electrode units, a plurality of upper intermetallic dielectric units, a first upper electrode layer, and an upper intermetallic dielectric layer. The lower intermetallic dielectric layer is disposed on the interconnect structure. The lower electrode layer is disposed in the lower intermetallic dielectric layer and is electrically connected to the interconnect structure. The lower electrode units are located on the lower intermetallic dielectric layer and the lower electrode layer and are disposed in the middle region in a layout pattern, and the lower electrode units are electrically connected to the lower electrode layer. The upper intermetallic dielectric units are located on the lower intermetallic dielectric layer and the lower electrode layer and are disposed in the middle region in a layout pattern, and the upper intermetallic dielectric units surround the lower electrode units. The first upper electrode layer is located on the lower intermetallic dielectric layer and is disposed in the peripheral region to surround the upper intermetallic dielectric units. The upper intermetal dielectric layer is disposed on the lower intermetal dielectric layer and surrounds the first upper electrode layer.
[0010] In some embodiments, the metal-insulator-metal capacitor structure further includes a barrier layer, and the barrier layer is arranged between the lower intermetal dielectric layer and the upper intermetal dielectric layer and between the upper intermetal dielectric unit and the lower intermetal dielectric layer, and the top surface of the barrier layer contacts the first upper electrode layer.
[0011] In some embodiments, the metal-insulator-metal capacitor structure further includes a plurality of second upper electrode layers, and the second upper electrode layers are interlaced in the middle area on the lower intermetal dielectric layer and the lower electrode layer, and extend to the peripheral area to connect with the first upper electrode layer, and the interlaced plurality of second upper electrode layers surround the upper intermetal dielectric unit.
[0012] In some embodiments, a bottom surface of the lower electrode unit is lower than a bottom surface of the first upper electrode layer.
[0013] In some embodiments, a bottom surface of the first upper electrode layer is lower than a bottom surface of the second upper electrode layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The following examples are presented in conjunction with the accompanying drawings for a clearer understanding of the present disclosure. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity of discussion.
[0015] Figures 1 to 7 is a schematic diagram of various stages of a method for manufacturing a metal-insulator-metal capacitor according to some embodiments of the present disclosure, wherein Figure 5 is based on Figure 6A top view of one stage in a method of manufacturing a metal-insulator-metal capacitor. DETAILED DESCRIPTION
[0016] Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.
[0017] In addition, for ease of description, spatially relative terms such as "on", "above", "below", "between" and the like may be used in this disclosure to describe the relationship of one element or feature to another element as shown in the drawings) or function. In addition to the orientations depicted in the drawings, spatially relative terms are intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other directions), and the spatially relative descriptors used in this disclosure can also be interpreted accordingly. The terms "including", "having", "comprising" and the like used in this disclosure are open terms, meaning including but not limited to.
[0018] In order to increase the effective area of a metal-insulator-metal (MIM) capacitor, the present disclosure redesigns the layout and structure of the electrode layer and the intermetallic dielectric layer of the capacitor, thereby increasing the total surface area between the electrode layer and the intermetallic dielectric layer, thereby increasing the effective capacitance.
[0019] See also Figures 1 to 7 , Figures 1 to 7 is a schematic diagram of various stages of a method for manufacturing a metal-insulator-metal (MIM) capacitor according to some embodiments of the present disclosure, wherein Figure 5 is based on Figure 6 A top view of one stage in a method of manufacturing a metal-insulator-metal (MIM) capacitor.
[0020] like Figure 1 As shown, for clarity, although substrate 102 includes multiple functional components, they are omitted from the drawing. Substrate 102 defines a middle region MR and a peripheral region PR surrounding middle region MR. Specifically, substrate 102 includes an interconnect structure 104 above, and a lower intermetallic dielectric layer 110 is formed on interconnect structure 104. In some embodiments, the material forming lower intermetallic dielectric layer 110 includes an oxide, such as silicon dioxide. Subsequently, photolithography and etching processes are performed to penetrate lower intermetallic dielectric layer 110 to form interdigitated openings OP1 in lower intermetallic dielectric layer 110.
[0021] Then, if Figure 2 As shown, at the fork-shaped opening OP1 (as Figure 1) is filled with a conductive material to form a lower electrode layer 112, and the lower electrode layer 112 is electrically connected to the interconnect structure 104. In some embodiments, the conductive material of the lower electrode layer 112 includes copper (Cu), aluminum (Al), tungsten (W), or other conductive materials. In some embodiments, the lower electrode layer 112 is formed by, for example, a deposition process (such as physical vapor deposition (PVD), atomic layer deposition (ALD), or other deposition processes) and a subsequent planarization process (such as an etch-back process and / or a chemical mechanical polishing (CMP) process).
[0022] like Figure 3 As shown, a barrier layer 120 is formed on the lower intermetal dielectric layer 110 and the lower electrode layer 112. In some embodiments, the barrier layer 120 includes a dielectric material, such as an oxide.
[0023] like Figure 4 As shown, an upper intermetallic dielectric layer 130 is formed on the barrier layer 120. Furthermore, the lower intermetallic dielectric layer 110 has a first thickness TH1, and the upper intermetallic dielectric layer 130 has a second thickness TH2, and the second thickness TH2 is greater than the first thickness TH1. In some embodiments, the material of the upper intermetallic dielectric layer 130 includes oxide, low-k material, or other possible dielectric materials.
[0024] See also Figure 5 and Figure 6 Through photolithography and etching processes, a plurality of columnar openings OP2 and a plurality of staggered trenches TR are formed in the upper intermetallic dielectric layer 130 of the middle region MR, and a ring-shaped recess RS is formed in the upper intermetallic dielectric layer 130 of the peripheral region PR. Figure 5In the top view of the middle region MR, the columnar opening OP2 of the middle region MR is, for example, rectangular or circular. Some trenches TR are interlaced with other trenches TR to form a checkerboard pattern or a hexagonal pattern, and an upper intermetallic dielectric unit 132 is formed between the interlaced trenches TR, with the columnar opening OP2 located within the upper intermetallic dielectric unit 132. Furthermore, an annular recess RS is formed in the peripheral region PR surrounding the middle region MR, and the annular recess RS is connected to the trench TR extending into the peripheral region PR. Furthermore, taking the X direction as an example, the columnar opening OP2 has a first width W1, the annular recess RS has a second width W2, and the trench TR has a third width W3. The first width W1 is greater than the second width W2, and the second width W2 is greater than the third width W3. Similarly, the area of the columnar opening OP2 is greater than the unit area of the annular recess RS, and the unit area of the annular recess RS is greater than the unit area of the trench TR. It is worth mentioning that the width of the trench TR in the X direction may be different from the width of the trench TR in the Y direction to increase the metal-insulator-metal capacitor 100 (eg Figure 7 In some embodiments, after the etching process, a cleaning process is performed.
[0025] Furthermore, if Figure 6As shown above, based on the loading effect, the first width W1 of the columnar opening OP2 is greater than the second width W2 of the annular recess RS, and the second width W2 of the annular recess RS is greater than the third width W3 of the trench TR (or, the area of the columnar opening OP2 is greater than the unit area of the annular recess RS, and the unit area of the annular recess RS is greater than the unit area of the trench TR). The etching depths of the columnar opening OP2, the annular recess RS, and the trench TR are respectively controlled. Specifically, since the first width W1 and area of the columnar opening OP2 are larger than those of the annular recess RS and the trench TR, the etching rate of the columnar opening OP2 is greater than the etching rate of the annular recess RS and the trench TR. Therefore, the first depth D1 of the columnar opening OP2 reaches the top surface of the exposed lower electrode layer 112, while the second depth D2 of the annular recess RS only reaches the top surface of the exposed barrier layer 120. In addition, compared to the trench TR, the annular recess RS has a larger second width W2 and a larger unit area, so the etching rate of the annular recess RS is greater than that of the trench TR. Therefore, when the first depth D1 of the columnar opening OP2 reaches the point where the top surface of the lower electrode layer 112 is exposed, and the second depth D2 of the annular recess RS reaches the point where the top surface of the barrier layer 120 is exposed, the third depth D3 of the trench TR remains within the upper intermetallic dielectric layer 130 of the middle region MR, and the upper intermetallic dielectric layer 130 of the third thickness TH3 remains between the trench TR and the barrier layer 120, forming a bottom intermetallic dielectric layer 134 to interconnect the upper intermetallic dielectric units 132. As can be seen from the foregoing, the first depth D1 is greater than the second depth D2, and the second depth D2 is greater than the third depth D3. In some embodiments, the etching process is a dry etching process.
[0026] Then, if Figure 7 As shown, in the columnar opening OP2, the annular recess RS and the trench TR (as Figure 6 ) is filled with a conductive material to form a lower electrode unit 152, a first upper electrode layer 154, and a second upper electrode layer 156, respectively, to form a metal-insulator-metal (MIM) capacitor 100. In some embodiments, the conductive material filling the columnar opening OP2, the ring-shaped recess RS, and the trench TR includes Ta / TaN, Ti / TiN, Cu, Al, W, or other conductive materials. In some embodiments, the lower electrode unit 152, the first upper electrode layer 154, and the second upper electrode layer 156 are formed, for example, by a deposition process (e.g., a physical vapor deposition process (PVD), an atomic layer deposition process (ALD), or an electroplating process, or a combination thereof) followed by a planarization process (e.g., an etch-back process and / or a chemical mechanical polishing (CMP) process).
[0027] Specifically, if Figure 7The metal-insulator-metal capacitor 100 shown includes a substrate 102, an interconnect structure 104 disposed above the substrate 102, a barrier layer 120 disposed on the interconnect structure 104, and a capacitor CP disposed on the interconnect structure 104. Furthermore, the capacitor CP defines a middle region MR and a peripheral region PR surrounding the middle region MR, and the capacitor CP includes a lower intermetal dielectric layer 110, a lower electrode layer 112, a plurality of lower electrode units 152, a plurality of upper intermetal dielectric units 132, a first upper electrode layer 154, a second upper electrode layer 156, and an upper intermetal dielectric layer 130.
[0028] The lower intermetal dielectric layer 110 is disposed on the interconnect structure 104 . The lower electrode layer 112 is interdigitated and penetrates the lower intermetal dielectric layer 110 and is located in the middle region MR, and is electrically connected to the interconnect structure 104 .
[0029] Lower electrode units 152 are located on lower intermetallic dielectric layer 110 and lower electrode layer 112 and are arranged in a checkerboard pattern in middle region MR. The bottom surfaces of lower electrode units 152 contact the interdigitated lower electrode layer 112, meaning that lower electrode units 152 are electrically connected to lower electrode layer 112. Furthermore, lower electrode units 152 have a first height H1.
[0030] Upper IMD units 132 are located on lower IMD layer 110 and lower electrode layer 112 and are arranged in a layout pattern in middle region MR. The bottoms of upper IMD units 132 are connected to each other via bottom IMD layer 134 having a third thickness TH3. Furthermore, upper IMD units 132 surround sidewalls of lower electrode units 152. In some embodiments, the layout pattern is a checkerboard pattern or a hexagonal pattern.
[0031] The first upper electrode layer 154 is located on the lower inter-metal dielectric layer 110 and is disposed in the peripheral region PR to surround the upper inter-metal dielectric unit 132 arranged in a layout pattern. Furthermore, the bottom surface of the first upper electrode layer 154 contacts the top surface of the barrier layer 120, and the first upper electrode layer 154 has a second height H2. In some embodiments, the layout pattern is a checkerboard pattern or a hexagonal pattern. In some embodiments, the second height H2 is less than the first height H1.
[0032] The second upper electrode layer 156 is interlaced in the middle region MR on the lower intermetal dielectric layer 110 and the lower electrode layer 112, and extends to the peripheral region PR to connect with the first upper electrode layer 154. Furthermore, the interlaced second upper electrode layer 156 surrounds the sidewalls of the upper intermetal dielectric unit 132. Furthermore, the bottom of the second upper electrode layer 156 contacts the top surface of the bottom intermetal dielectric layer 134, and the second upper electrode layer 156 has a third height H3. In some embodiments, the third height H3 is less than the second height H2, and the third height H3 is less than the first height H1. In other words, the bottom surface of the lower electrode unit 152 is lower than the bottom surface of the first upper electrode layer 154, and the bottom surface of the first upper electrode layer 154 is lower than the bottom surface of the second upper electrode layer 156.
[0033] The upper IMD layer 130 is disposed on the lower IMD layer 110 and located in the peripheral region PR, and surrounds the outer sidewall of the first upper electrode layer 154 .
[0034] In summary, through the disclosed metal-insulator-metal capacitor and its manufacturing method, the metal-insulator-metal capacitor is designed as a vertical structure spanning adjacent electrode layers and intermetallic dielectric layers, thereby increasing the total surface area between the electrode layers and the intermetallic dielectric layers to increase the effective capacitance.
[0035] Although some embodiments of the present disclosure have been described in considerable detail, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the embodiments described herein.
[0036] The above briefly describes the features of various embodiments of the present disclosure, making it easier for those skilled in the art to understand the present disclosure. Anyone skilled in the art will understand that this disclosure can easily serve as a basis for modifying or designing other structures or processes to achieve the same objectives and / or obtain the same advantages as the embodiments of the present disclosure. Anyone skilled in the art will also understand that structures equivalent to the above do not depart from the spirit and scope of the present disclosure, and that changes, substitutions, and modifications may be made without departing from the spirit and scope of the present disclosure.
[0037]
Explanation of symbols
[0038] 100: Metal-Insulator-Metal Capacitor
[0039] 102:Substrate
[0040] 104: Interconnection structure
[0041] 110: Lower intermetallic dielectric layer
[0042] 112: lower electrode layer
[0043] 120: barrier layer
[0044] 130: Upper intermetallic dielectric layer
[0045] 132: Upper intermetallic dielectric unit
[0046] 134: bottom intermetallic dielectric layer
[0047] 152: Lower electrode unit
[0048] 154: first upper electrode layer
[0049] 156: Second upper electrode layer
[0050] CP:Capacitor
[0051] D1: First depth
[0052] D2: Second Depth
[0053] D3: Third Depth
[0054] H1: First Height
[0055] H2: Second height
[0056] H3: The third height
[0057] MR: Middle District
[0058] PR: Peripheral area
[0059] OP1: Fork-shaped opening
[0060] OP2: cylindrical opening
[0061] RS: Ring Depression
[0062] TH1: First thickness
[0063] TH2: Second thickness
[0064] TH3: third thickness
[0065] TR: Groove
[0066] W1: first width
[0067] W2: Second width
[0068] W3: Third width
[0069] X,Y: direction.
Claims
1. A method for manufacturing a metal-insulator-metal capacitor structure, characterized in that: include: forming a lower intermetallic dielectric layer over a substrate, wherein the substrate defines a middle region and a peripheral region surrounding the middle region; forming an interdigitated opening in the lower intermetal dielectric layer extending through the lower intermetal dielectric layer; forming a lower electrode layer in the interdigitated opening; forming a barrier layer on the lower electrode layer and the lower intermetallic dielectric layer; forming an upper intermetallic dielectric layer on the barrier layer; forming a plurality of mutually staggered trenches and a plurality of columnar openings formed between the plurality of staggered trenches in the upper intermetallic dielectric layer in the middle region, and forming an annular recess in the upper intermetallic dielectric layer in the peripheral region, wherein each of the columnar openings exposes a top surface of the lower electrode layer; as well as Conductive material is filled in the multiple columnar openings, the annular recesses and the multiple staggered grooves to respectively form a lower electrode unit, a first upper electrode layer and multiple second upper electrode layers, wherein the bottom surface of the lower electrode unit contacts the top surface of the lower electrode layer.
2. The method according to claim 1, characterized in that Since the first width of each columnar opening is greater than the second width of the annular recess, when forming the plurality of columnar openings and the annular recess, the first depth of each columnar opening is greater than the second depth of the annular recess.
3. The method according to claim 2, characterized in that The annular recess exposes the top surface of the barrier layer.
4. The method according to claim 1, wherein Since the second width of the annular recess is greater than the third width of each of the grooves, when the annular recess and the plurality of grooves are formed, the second depth of the annular recess is greater than the third depth of each of the grooves.
5. The method according to claim 1, characterized in that The plurality of grooves extend to the peripheral area and communicate with the annular recess.
6. A metal-insulator-metal capacitor structure, characterized in that: include: a substrate defining a middle region and a peripheral region surrounding the middle region; an interconnection structure, disposed above the substrate; as well as A capacitor is disposed on the interconnect structure and includes: a lower intermetallic dielectric layer disposed on the interconnect structure; a lower electrode layer disposed in the lower intermetallic dielectric layer and electrically connected to the interconnect structure; a plurality of lower electrode units located on the lower intermetallic dielectric layer and the lower electrode layer and arranged in the middle region in a layout pattern, wherein each of the lower electrode units is electrically connected to the lower electrode layer; a plurality of upper intermetallic dielectric units located on the lower intermetallic dielectric layer and the lower electrode layer and arranged in the middle region in the layout pattern, wherein each of the upper intermetallic dielectric units surrounds each of the lower electrode units; a first upper electrode layer located on the lower intermetal dielectric layer and disposed in the peripheral region to surround the plurality of upper intermetal dielectric units; and The upper intermetal dielectric layer is disposed on the lower intermetal dielectric layer and surrounds the first upper electrode layer.
7. The metal-insulator-metal capacitor structure according to claim 6, wherein: Further including: A barrier layer is disposed between the lower intermetallic dielectric layer and the upper intermetallic dielectric layer and between each of the upper intermetallic dielectric units and the lower intermetallic dielectric layer, wherein a top surface of the barrier layer contacts the first upper electrode layer.
8. The metal-insulator-metal capacitor structure according to claim 7, wherein: Further including: A plurality of second upper electrode layers are staggered in the middle area on the lower intermetal dielectric layer and the lower electrode layer, and extend to the peripheral area to connect with the first upper electrode layer, wherein the staggered second upper electrode layers surround each of the upper intermetal dielectric units.
9. The metal-insulator-metal capacitor structure according to claim 7, wherein: The bottom surface of each of the lower electrode units is lower than the bottom surface of the first upper electrode layer.
10. The metal-insulator-metal capacitor structure according to claim 8, wherein: The bottom surface of the first upper electrode layer is lower than the bottom surface of each of the second upper electrode layers.