System and method for performing energy efficient processing by reducing data movement

Abstract

A system for performing energy efficient computations reduces the amount of data transferred between a processor and an external memory device. The processor and the external memory device are respectively equipped with a first near data processing control unit (NCU) and a second near data processing control unit (NCU) that coordinate offloading of a preselected sub-process from the processor to a first processing circuit disposed on or near the external memory device. When the processor is executing one of the preselected processes, the first NCU sends a command and a memory address to the second NCU. The processing circuitry on or near the memory device executes one or more sub-processes and forwards a result by the second NCU to the first NCU, the first NCU forwarding the result to the processor to complete the process.

Description

[0001] Related technical description

[0002] A computing device may include multiple processor-based subsystems. Such a computing device may be, for example, a portable computing device ("PCD") such as a laptop or palmtop computer, a cellular phone or smartphone, a portable digital assistant, a portable game console, or the like. Still other types of PCDs may be included in automotive and Internet of Things ("IoT") applications.

[0003] Multiple subsystems may be included within the same integrated circuit chip or in different chips. A “system on a chip” or “SoC” is an example of a chip that integrates numerous components to provide system-level functionality. For example, an SoC may include one or more types of processors, such as a central processing unit (“CPU”), a graphics processing unit (“GPU”), a digital signal processor (“DSP”), and a neural processing unit (“NPU”). An SoC may include other subsystems, such as a transceiver or “modem” subsystem that provides wireless connectivity, a memory subsystem, and the like.

[0004] For example, processors in SoCs (such as CPUs, GPUs, and DSPs) perform extensive computations that require the processors to write and read large amounts of data to and from the SoC's main memory. This data transfer consumes significant energy within the SoC. For these large workloads, a method is needed to reduce data movement to achieve greater energy savings in energy-constrained systems. Summary of the Invention

[0005] Disclosed are systems, methods, and other examples for performing energy-efficient computing by reducing data movement between a processor and a memory device external to the processor. The method may include, using a processor, initiating a first process including at least a first sub-process. The method may also include, using a first near-data processing control unit (NCU) of the processor, outputting at least a first processing command associated with executing the first sub-process and a first address for storing data associated with the first sub-process in a memory device. The method may also include, using a second NCU disposed on or near the memory device, receiving the first processing command and the first address, and causing the data stored at the first address to be read from the memory device and forwarded to a processing circuit disposed on or near the memory device. The method may also include, in the processing circuit, executing at least the first sub-process by executing at least the first processing command on data read from the first memory address to produce a first result.

[0006] The system may include a processor including logic configured to initiate at least a first process including at least a first sub-process. The system may also include a memory device including a memory address configured to store data. The system may also include a first NCU embedded in or in communication with the processor, the first NCU including logic configured to receive at least a first processing command and a first address from the processor. The first processing command may include one or more commands for executing the first sub-process. The first address is an address of the memory device storing data to be processed by the first sub-process. The system may also include a second NCU disposed on or near the memory device and in communication with the first NCU. The second NCU may include logic configured to receive the first address and the first command from the first NCU. The system may also include processing circuitry disposed on or near the memory device, the processing circuitry including logic configured to receive the first command and the first address from the second NCU, read data from the first address, and execute the first command on the data read from the first address to produce a first result.

[0007] The computer program of the present disclosure includes computer instructions for performing energy-efficient computing by reducing data movement between a processor and a memory device external to the processor. These computer instructions are embodied in a non-transitory computer-readable medium and may include: a first set of computer instructions for execution by the processor to initiate a first process including at least a first sub-process; a second set of computer instructions for execution by a first NCU of the processor to cause the first NCU to output at least a first processing command for executing the first sub-process and a first address for storing data associated with the first sub-process in a memory device. The computer program may also include a third set of computer instructions for execution by a second NCU disposed on or near the memory device to cause the second NCU to receive the at least first processing command and the first address and cause the data stored at the first address to be read from the memory device and forwarded to a processing circuit disposed on or near the memory device. The computer program may also include a fourth set of computer instructions for execution by the processing circuit to cause the processing circuit to execute the at least first sub-process by executing the at least first processing command on the data read from the first address to produce a first result.

[0008] Another embodiment of a system for performing energy-efficient computing by reducing data movement between a processor and a memory device external to the processor may include a processor configured to initiate a first process including at least a first sub-process, the processor including logic configured to output at least a first processing command associated with executing the first sub-process and a first address in a memory device at which data associated with the first sub-process is stored. The system may also include processing circuitry embedded in the memory device and configured to receive the first processing command and the first address, and cause data stored at the first address to be read from the memory device and forwarded to the processing circuitry. The processing circuitry may include logic configured to execute at least the first sub-process to produce a first result by executing at least the first processing command on data read from the first memory address.

[0009] These and other features and advantages will become apparent from the following description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the drawings, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with alphabetic characters, such as "101a" or "101b," the alphabetic characters may distinguish between two similar parts or elements in the same figure. Alphabetic characters may be omitted from a reference numeral when it is intended that all parts having the same reference numeral in all figures be included.

[0011] Figure 1 is a block diagram of an Internet browser tab switching process, which shows the sub-processes that make up the tab switching process executed in a CPU executing the Google Chrome browser.

[0012] Figure 2 is a graph showing the percentage of energy consumed by moving data between the CPU and memory compared to the energy consumed by computing four different processes: (1) texture and color blits when scrolling using Google Chrome, (2) compression and decompression when switching tabs using Google Chrome, (3) packing, unpacking, and quantization when using TensorFlow artificial intelligence (AI) machine learning software, and (4) subpixel interpolation and deblocking filtering when using the VP9 encoder / decoder.

[0013] Figure 3 yes Figure 1 The block diagram of the label switching process shown in FIG is modified to eliminate the label switching process respectively Figure 1 The blocks 102 and 104 represent the reading process and the writing process, and will be Figure 1Block 103 represents the offloading of the compression sub-process to processing circuitry disposed on or near the memory device.

[0014] Figure 4 is a block diagram of a system for performing energy-efficient computing by reducing data movement between a processor and memory, according to a representative embodiment.

[0015] Figure 5 is a flow chart of a method for energy-efficient computing by reducing the amount of data transferred between a processor and an external memory device, according to a representative embodiment.

[0016] Figure 6 is a flow chart of a method for energy-efficient computing by reducing the amount of data transferred between a processor and an external memory device, according to a representative embodiment.

[0017] Figure 7A is a schematic diagram of a 3D stacked DRAM memory system that has been modified to include a bank logic component in a logic die of the memory system. Figure 4 The second NCU and the first processing circuit are shown in FIG.

[0018] Figure 7B yes Figure 7A A block diagram of a repository logic component shown in FIG. 1 having embedded therein Figure 4 The second NCU and the first processing circuit are shown in FIG.

[0019] Figure 8 This is a flowchart of the texture filling process currently executed by the CPU.

[0020] Figure 9 According to a representative embodiment of the present disclosure Figure 8 Flowchart of the texture filling process shown in .

[0021] Figure 10 This is a flowchart of the TensorFlow packaging and quantization process currently executed by the CPU.

[0022] Figure 11 Modified according to the representative embodiment of the present disclosure Figure 10 Flowchart of the TensorFlow process shown in .

[0023] Figure 12 An example of a PCD is illustrated in which exemplary embodiments of systems, methods, computer-readable media, and other examples providing energy-efficient processing with reduced data movement in accordance with the principles and concepts of the present invention may be implemented. DETAILED DESCRIPTION

[0024] The end of Dennard scaling has made computing systems energy-constrained and widened the gap between computational speed and data transfer rate, often referred to as the memory-wall. For data-intensive applications with limited temporal locality, the primary energy bottleneck in processing throughput is moving data between the processor and main memory.

[0025] Figure 1 1 is a block diagram of an internet browser tab switching process, illustrating the sub-processes that comprise the tab switching process executed in a CPU of a PCD. A first sub-process 101, executed by the CPU, retrieves N uncompressed pages 102 from main memory external to the CPU, where N is a positive integer corresponding to the number of pages to be swapped. A second sub-process 103, executed by the CPU, compresses the retrieved pages. A third sub-process 104, executed by the CPU, writes the compressed pages 105 to main memory.

[0026] A study of a very common internet browser workload executed on the SoCs used in current PCDs revealed that a large percentage of energy consumption was due to data movement between the CPU and memory. Figure 2 is a graph showing the percentage of energy consumed by moving data between the processor and memory compared to the energy consumed by computing four different processes, namely (1) texture and color bit block transfers when scrolling using an internet browser, (2) compression and decompression when switching tabs using an internet browser, (3) packing, unpacking, and quantization when using artificial intelligence (AI) machine learning software, and (4) sub-pixel interpolation and deblocking filtering when using the VP9 encoder / decoder.

[0027] Bars 201a to 201d represent the percentage of energy consumed due to data movement for the corresponding process, and bars 202a to 202d represent the energy consumed due to the calculations performed by the corresponding process. All of these processes use relatively simple operations (such as shifts, additions, and multiplications) to perform their corresponding calculations. As can be seen from the chart, the percentage of energy consumed due to data movement is very high compared to the percentage of energy consumed due to calculations and in some cases exceeds the percentage of energy consumed due to calculations. For data-intensive applications (such as deep neural networks and graphics processing applications) where there is no or very little temporal locality in the data, the energy consumed due to data movement is the main bottleneck in achieving performance per milliwatt (mW).

[0028] The present disclosure provides a solution for achieving energy-efficient computing by reducing the amount of data transferred between a processor and a memory device external to the processor. To achieve this, the processor is equipped with a first near-data processing control unit (NCU). The processing circuit and the second NCU are located on or near the external memory device. The first NCU and the second NCU coordinate the offloading of preselected subprocesses from the processor to the processing circuit located on or near the external memory device. When the processor is executing one of these preselected processes, which includes multiple subprocesses, the first NCU of the processor sends a command to the second NCU of the memory device, which notifies the processing circuit in or near the memory device in which to execute the subprocess. The first NCU also transmits to the second NCU a memory address in the memory device where data to be processed in the subprocess is stored. The processing circuit located on or near the memory device executes one or more subprocesses, and then the second NCU forwards the results of the one or more subprocesses to the first NCU, which then forwards the results to the processor. The processor then uses the results to complete the process.

[0029] Thus, significant data movement between the processor and the memory device for executing the process has been eliminated, while at the same time, the processor has been freed to perform other tasks while the processing circuitry executes one or more sub-processes.

[0030] In the following detailed description, exemplary or representative embodiments of the disclosure details are set forth for the purpose of explanation rather than limitation, so as to provide a thorough understanding of the embodiments according to the present teachings. The word "exemplary" is used herein to mean "serving as an example, instance or illustration". The words "exemplary" or "representative" may be used synonymously with "exemplary" herein. Any aspect described herein as "exemplary" is not necessarily to be construed as being preferred or having advantages over other aspects. However, it will be apparent to those skilled in the art who benefit from this disclosure that other embodiments according to the present teachings that depart from the specific details disclosed herein are still within the scope of the appended claims. In addition, descriptions of well-known devices and methods may be omitted so as not to obscure the description of the example embodiments. Such methods and devices are clearly within the scope of the present teachings.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. The defined terms are in addition to the technical and scientific meanings of the defined terms as commonly understood and accepted in the art to which the present teachings pertain.

[0032] As used in the specification and the appended claims, the terms "a," "an," and "the" include both singular and plural referents unless the context clearly dictates otherwise. Thus, for example, "a device" includes one device and a plurality of devices.

[0033] Relative terms may be used to describe the relationship of various elements to each other as illustrated in the figures. These relative terms are intended to encompass different orientations of the device and / or elements in addition to the orientation depicted in the figures.

[0034] It will be understood that when an element is described as being “connected to”, “coupled to” or “electrically coupled to” another element, the elements can be directly connected or coupled or intervening elements may be present.

[0035] The term "external memory device" (as that term is used herein) is intended to refer to a non-transitory computer-readable storage medium that is external to a processor, rather than a memory device or structure that is embedded in a processor and that is capable of storing computer instructions or computer code for execution by one or more processors. References herein to "memory device" or "external memory device" should be interpreted to include a memory controller, a memory bank, and associated elements interposed between the memory controller and the memory bank, such as an associated physical layer, associated memory channels, and associated memory ranks.

[0036] As used herein, the term "processor" encompasses an electronic component capable of executing a computer program or executable computer instructions. References herein to a computer comprising a "processor" should be interpreted as referring to one or more processors. A processor may, for example, be a multi-core processor comprising multiple processing cores, each of which may include multiple processing stages of a processing pipeline. A processor may also refer to a collection of processors within a single computer system or distributed across multiple computer systems.

[0037] A computing device may include multiple subsystems, cores, or other components. Such a computing device may be, for example, a PCD such as a laptop or palmtop computer, a cellular phone or smartphone, a portable digital assistant, a portable game console, an automotive safety system for an autonomous vehicle, or the like.

[0038] Reference herein to the processing circuitry and the second NCU being disposed "near" the external memory device means that the processing circuitry and the second NCU are physically located at a shorter distance from the memory device than they are from the processor (e.g., CPU, GPU, etc.), and that the processing circuitry and the second NCU are disposed somewhere between the interconnects that interconnect the processor with the system cache and the memory banks of the external memory device. For example, where the processor is a CPU and the external memory device is a dynamic random access memory (DRAM) memory device, the processing circuitry and the second NCU may be disposed in a system cache controller that is between the aforementioned interconnects and the DRAM banks in the memory hierarchy:

[0039] CPU-->Interconnect-->System cache and cache controller (2nd NCU + processing circuitry)-->DRAM / HBM controller-->PHY-->DRAM channels-->DRAM ranks-->DRAM banks.

[0040] Reference herein to the second NCU and processing circuitry being disposed "on" an external memory device means that the processing circuitry and the second NCU are disposed (1) in a memory controller of the external memory device, (2) in a memory bank of the external memory device, or (3) somewhere between the memory controller and the memory bank (e.g., in an associated physical layer, in an associated memory channel, in an associated memory rank, or anywhere in between). For example, where the processor is a CPU and the external memory device is a DRAM memory device, the processing circuitry and the second NCU may be disposed in the DRAM memory controller: CPU --> interconnect --> system cache and cache controller --> DRAM controller (second NCU + processing circuitry) --> PHY --> DRAM channel --> DRAM rank --> DRAM bank.

[0041] Figure 3 yes Figure 1 , which is modified to eliminate the reading process 101 and the writing process 104, respectively, and to offload the compression sub-process 103 to the processing circuit 310 disposed on or near the memory device. Figure 1 The compression subprocess 103 executed by the CPU in Figure 3 3 has been replaced by the compression sub-process 303 executed by the processing circuit 310. Because the processing circuit 310 is located in or near the memory, the data movement between the processing circuit 310 and the memory and the energy consumed by the data movement are negligible. In addition, it can be seen that the CPU processor is idle during the time it was previously occupied to execute the reading sub-process 101, the writing sub-process 104, and the compression sub-process 103, respectively, thereby freeing the CPU to perform other tasks.

[0042] It should be noted that although the CPU Figure 3 is shown as a processor from which subprocesses are offloaded, but the CPU may be any processor, including, for example, a GPU, a DSP, an NPU, or any other processor that can access external memory devices.

[0043] Figure 44 is a block diagram of a system 400 for performing energy-efficient computing by reducing data movement between a processor 410 and an external memory 430, according to an exemplary embodiment. System 400 can be used in a SoC package, such as that used in a PCD, but the principles and concepts of the present invention are not limited to the type of system in which they are employed. For exemplary purposes, the systems and methods of the present disclosure are described as being implemented in a SoC package 401.

[0044] The processor 410 and the external memory device 430 are each equipped with a first NCU 420 and a second NCU 440, which coordinate the offloading of preselected subprocesses from the processor 410 to a processing circuit 450 disposed on or near the external memory device 430. For exemplary purposes, the second NCU 440 and the processing circuit 450 are shown as being embedded in the memory device 430, but one or both of the NCU 440 and the processing circuit 450 may alternatively be external to the memory device 430 and in close proximity to the memory device and to each other. The processing circuit 450 communicates with the memory device 430 via a suitable interface for high-speed data transfer. Similarly, the processing circuit 450 communicates with the second NCU 440 via a suitable interface.

[0045] When the processor 410 is executing one of the preselected processes including a plurality of sub-processes, the first NCU 420 of the processor 410 sends a command to the second NCU 440 of the memory device 430, which the processing circuit 450 will use to execute one or more sub-processes offloaded from the processor 410 to the processing circuit 450. The first NCU 420 also transmits a memory address in the memory device 430 where data to be processed by the sub-process is stored to the second NCU 440. The processing circuit 450 retrieves the data from the memory address and executes the one or more sub-processes to produce a result. In some cases, the result may be stored by the processing circuit 450 in the memory device 430. For example, for Figure 3 , processing circuit 310 writes the compressed page to memory. Where further processing of the results is required by processor 410, second NCU 440 forwards the results of one or more sub-processes to first NCU 420, which then forwards the results to processor 410. Processor 410 then uses the results to complete the overall process.

[0046] As indicated above, processor 410 may be any processor, such as a CPU, GPU, DSP, NPU, etc. Memory device 430 may be any memory device, but is typically main memory and is typically a DRAM device, although it may be any type of memory device.

[0047] Figure 5 5 is a flow chart of a method for performing energy-efficient computing by reducing the amount of data transferred between a processor and an external memory device, according to an exemplary embodiment. According to this embodiment, results generated by processing circuitry are forwarded by a second NCU to a first NCU, which forwards the results to the processor for further processing. The processor initiates a process for which one or more preselected subprocesses are to be offloaded to processing circuitry located at or near an external memory device, as indicated by block 501. The first subprocess of the process can be a subprocess to be executed by the processor or a subprocess designated to be offloaded to processing circuitry located at or near the memory device. For ease of discussion, it will be assumed that the first subprocess will be offloaded and executed by processing circuitry located at or near the memory device.

[0048] A first NCU of the processor transmits a sub-process processing command and a first memory address storing data to be processed by the first sub-process to a second NCU disposed on or near an external memory device, as indicated by block 502. The second NCU reads the data stored at the first memory address of the memory device and forwards the read data and the command received from the first NCU to processing circuitry disposed on or near the memory device, as indicated by block 503. The processing circuitry executes the designated sub-process or sub-processes on the read data to produce a result, as indicated by block 504. The second NCU transmits the result to the first NCU, as indicated by block 505, which forwards the result to the processor, as indicated by block 506. The processor processes the result, as indicated by block 507.

[0049] As indicated above, the processor may execute additional sub-processes or tasks that utilize the results generated by the processing circuitry disposed on or near the memory device. The processor may execute one or more other related sub-processes to achieve other results. The results received from the second NCU in the first NCU may or may not be used by the processor in conjunction with the results of the other related sub-processes executed by the processor.

[0050] Figure 6 This is a flow chart of a method for performing energy-efficient computing by reducing the amount of data transferred between a processor and an external memory device, according to another exemplary embodiment. According to this embodiment, results generated by processing circuitry are not forwarded by a second NCU to a first NCU, but are instead stored in memory by the processing circuitry. According to this embodiment, further processing of the results by the processor is not required, and therefore the processing circuitry stores the results in memory.

[0051] The processor initiates a process for which one or more preselected sub-processes are to be offloaded to processing circuitry located at or near an external memory device, as indicated by block 601. The first sub-process of the process may be a sub-process that the processor is to execute or a sub-process that is designated to be offloaded to processing circuitry located at or near the memory device. For ease of discussion, it will be assumed that the first sub-process is to be offloaded and executed by processing circuitry located at or near the memory device.

[0052] The first NCU of the processor transmits a sub-process processing command and a first memory address storing data to be processed by the first sub-process to a second NCU disposed on or near an external memory device, as indicated by block 602. The second NCU reads the data stored at the first memory address of the memory device and forwards the read data and the command received from the first NCU to a processing circuit disposed on or near the memory device, as indicated by block 603. The processing circuit executes the specified one or more sub-processes on the read data to produce a result, as indicated by block 604. The processing circuit then stores the result in the external memory device, as indicated by block 605.

[0053] Reference again Figure 4 Each of the NCUs 420 and 440 may be, for example, a hardware unit configured to execute a near data processing (NDP) enabling instruction (NEI). Each of the NCUs 420 and 440 may include, for example, a computational logic unit and an operand buffer. The operand buffer may be, for example, a small static random access memory (SRAM) buffer that stores commands and addresses in a memory where data to be processed resides. The primary purpose of the operand buffer is to enable instruction-level parallelism. To use the NCU in this solution, an ISA extension in the host processor 410 may be used to identify a sub-process designated for offloading to the first processing circuit 450 disposed on or near the memory 430.

[0054] It is important to note the difference between the systems and methods of the present disclosure and known utilization of compute caches. Compute caches are channels that exploit the temporal locality of data patterns. Before a compute pipeline stage performs a load / store, the data needs to be brought back into the cache, which is an expensive off-chip data movement, especially in cases where multiple cache lines need to be fetched or where data prefetching occurs speculatively. If there are workloads that do not have temporal locality, such as utilizing, for example, matrix multiplication, then using the compute cache to handle these workloads will require a large number of cache accesses, which wastes energy in data movement: total energy cost = off-chip data movement energy cost + compute energy cost.

[0055] The solution of the present disclosure brings computation to memory or near memory, as opposed to the computation cache concept and is well suited for situations where the data to be processed has very little or no temporal locality.

[0056] The second NCU 440 and the first processing circuit 450 may be placed in, for example, a logic bank of a 3D stacked DRAM memory system, as will now be referenced. Figure 7A and Figure 7B described. Figure 7A is a schematic diagram of a 3D stacked DRAM memory device 700 having Figure 4 The second NCU 440 and processing circuit 450 shown in FIG. 4 are embedded in the bank logic component 720 of the logic die 710 of the DRAM memory device 700 . Figure 7B is embedded in it Figure 4 , a block diagram of the second NCU 440 and the bank logic unit 720 of the processing circuit 450 is shown in . Because the bank logic unit 720 is close to the memory bank of the DRAM die 711 in which the data to be processed by the sub-process is stored, the data movement between the DRAM die 711 and the processing circuit 450 provided in the bank logic unit 720 and the energy cost associated with writing to and reading from the memory are negligible.

[0057] exist Figure 7A In the exemplary embodiment shown in FIG, the first interface device 730 of the SoC mounted on the second interface device 740 of the SoC is used to interface the DRAM memory device 700 with the processor die 410 and to interface both components with other components of the SoC (not shown). However, the principles and concepts of the present invention are not limited to this configuration. Figure 7A All of the components shown in may, for example, be integrated into the same SoC package and formed in layers of the SoC package, the layers being interconnected by vias, traces, and other electrical wiring of the SoC.

[0058] It should be noted that the second NCU 440 and processing circuit 450 may be located at any suitable location on or near the external memory device. Figure 7A and Figure 7BIn a 3D memory device of the type shown in , preferably, the second NCU 440 and processing circuitry 450 will be located in the logic die of the external memory device, or at some other location along the route between the logic die and the memory banks. As indicated above, the processing circuitry 450 can be implemented with relatively simple logic components (such as adders and multipliers) that do not consume a large amount of space and are therefore well suited for implementation in the logic die of the memory device. For planar memory devices, the processing circuitry 450 can be implemented in the processor-in-memory (PIM) compute logic components of the external memory device and can be integrated per memory bank group to exploit memory bank-level parallelism.

[0059] Figure 8 This is a flow chart of the texture filling process currently performed by the CPU. The texture tiling process is the primary source of data movement between the CPU and main memory and utilizes large rasterized bitmaps (e.g., 4 megabytes (Mb)). Additionally, the data processed during this process has poor temporal locality, which means that the process would not greatly benefit from using cache memory to reduce transfers between the CPU and main memory.

[0060] The process begins with a rasterization sub-process 801 that generates a linear bitmap and writes the linear bitmap to memory. The CPU executes a sub-process that reads the linear bitmap from memory 803, converts the linear bitmap into texture tiles 804, and writes the texture tiles to memory 805.

[0061] Figure 9 is a flow chart of a texture filling process according to a representative embodiment of the present disclosure, wherein the sub-processes of generating a linear bitmap 902 and converting the linear bitmap into a texture tile 903 are performed by the combined actions of the second NCU 440 and the processing circuit 450 disposed on or near the memory. For ease of illustration, Figure 9 The second NCU 440 is not shown. Figure 4 The processor 410 shown in FIG. Figure 9900. The CPU 900 performs a rasterization sub-process 901 that generates a linear bitmap, and the second NCU 440 writes the linear bitmap to the memory. The sub-processes of generating a linear bitmap 902 and converting the linear bitmap into texture tiles 903 are performed by the processing circuit 450. Because the second NCU 440 and the processing circuit 450 are located on or near the memory, data movement is negligible when writing the linear bitmap to the memory, reading the linear bitmap from the memory, and writing the texture file to the memory. In addition, a large number of logic components are not required to implement the second NCU 440 and the processing circuit 450 because the texture blocking operation is a relatively simple operation that requires simple primitive processing, such as memory copy operations, bit-by-bit operations, and simple arithmetic operations.

[0062] Figure 10 Flowchart of the packing / unpacking and quantization process currently performed by the CPU. This process is the primary source of data movement between the CPU and main memory and utilizes large amounts of data with poor temporal locality. The process performed by the CPU includes the following subprocesses: reading a 32-bit matrix from memory and finding the minimum and maximum values ​​of the matrix 1001, quantizing each matrix value using the minimum and maximum values ​​to produce an 8-bit matrix 1002, performing a convolution on the 8-bit matrix to produce a 32-bit result matrix and writing the result matrix to memory 1003, and then requantizing the result matrix by reading the 32-bit result matrix from memory, finding the minimum and maximum matrix element values ​​1004, and producing an 8-bit matrix using the minimum and maximum values ​​1005.

[0063] Figure 11 yes Figure 9 , which is modified according to a representative embodiment of the present disclosure to be performed by the combined actions of a second NCU 440 (not shown for ease of illustration) and a first processing circuit 450 disposed on or near the memory. Figure 10 The sub-processes of blocks 1001 and 1002 are respectively Figure 11 1 and 1102 in the same manner. Figure 10 The sub-processes of blocks 1004 and 1005 are performed by the combined actions of the second NCU 440 and the processing circuit 450 disposed on or near the memory, respectively as Figure 11 To avoid having to employ complex logic components in the processing circuit 450, the convolution sub-process 1103 may continue to be performed by the CPU 1100 because it is a more processing intensive sub-process than the other sub-processes.

[0064] Therefore, by Figure 11The sub-processes represented by blocks 1101 to 1104 have all been offloaded from the CPU 1100 to the processing circuitry 450. This greatly reduces the amount of data movement between the CPU 1100 and external memory and the amount of energy consumed by the data movement, while also freeing up the CPU 1100 to perform other tasks.

[0065] It should be noted that Figure 3 、 Figure 9 and Figure 11 The sub-processes shown in FIG2 as being offloaded to be executed on or near memory are merely examples of sub-processes that are suitable for offloading because the temporal locality of the data used in these processes is poor and because the operations of these processes are relatively simple operations that can be performed in relatively simple logic components that do not consume a large amount of die area.

[0066] Figure 12 An example of a PCD 1200 is illustrated, such as a mobile phone, a smartphone, a portable gaming console (such as an extended reality (XR) device, a virtual reality (VR) device, an augmented reality (AR) device, or a mixed reality (MR) device), in which exemplary embodiments of systems, methods, computer-readable media, and other examples of providing energy-efficient processing with reduced data movement according to the principles and concepts of the present invention may be implemented. For purposes of clarity, Figure 12 Some interconnects, signals, etc. are not shown.

[0067] PCD 1200 may include SoC 1202. SoC 1202 may include CPU 1204, NPU 1205, GPU 1206, DSP 1207, analog signal processor 1208, modem / modem subsystem 1254, or other processors. CPU 1204 may include one or more CPU cores, such as a first CPU core 12041, a second CPU core 12042, and so on up to an Mth CPU core 1204. M .

[0068] A display controller 1209 and a touch screen controller 1212 may be coupled to the CPU 1204. A touch screen display 1214 external to the SoC 1202 may be coupled to the display controller 1210 and the touch screen controller 1212. The PCD 1200 may also include a video decoder 1216 coupled to the CPU 1204. A video amplifier 1218 may be coupled to the video decoder 1216 and the touch screen display 1214. A video port 1220 may be coupled to the video amplifier 1218. A universal serial bus ("USB") controller 1222 may also be coupled to the CPU 1204, and a USB port 1224 may be coupled to the USB controller 1222. A subscriber identity module ("SIM") card 1226 may also be coupled to the CPU 1204.

[0069] One or more memories 1228 may be coupled to CPU 1204. One or more memories 1228 may include both volatile memory and non-volatile memory. Examples of volatile memory include static random access memory ("SRAM") and dynamic random access memory ("DRAM"). Such memory may be external to SoC 1202 or internal to SoC 1202. One or more memories 1228 may include local cache memory or system-level cache memory. Second NCU 440 and processing circuitry 450 may be located on or near one or more memories 1228.

[0070] A stereo audio CODEC 1234 may be coupled to the analog signal processor 1208. Furthermore, an audio amplifier 1236 may be coupled to the stereo audio CODEC 1234. A first stereo speaker 1238 and a second stereo speaker 1240 may each be coupled to the audio amplifier 1236. Furthermore, a microphone amplifier 1242 may be coupled to the stereo audio CODEC 1234, and a microphone 1244 may be coupled to the microphone amplifier 1242. A frequency modulation ("FM") radio tuner 1246 may be coupled to the stereo audio CODEC 1234. An FM antenna 1248 may be coupled to the FM radio tuner 1246. Furthermore, stereo headphones 1250 may be coupled to the stereo audio CODEC 1234. Other devices that may be coupled to the CPU 1204 include one or more digital (e.g., CCD or CMOS) cameras 1252.

[0071] A modem or RF transceiver 1254 may be coupled to the analog signal processor 1208 and the CPU 1204. An RF switch 1256 may be coupled to the RF transceiver 1254 and the RF antenna 1258. Additionally, a keypad 1260 and a mono headset with a microphone 1262 may be coupled to the analog signal processor 1208. The SoC 1202 may have one or more internal or on-chip thermal sensors 1270. A power supply 1274 and a PMIC 1276 may provide power to the SoC 1202.

[0072] The firmware or software may be stored in any of the aforementioned memories, or in local memory directly accessible to the processor hardware on which the software or firmware is executed. Execution of such firmware or software may control aspects of any of the aforementioned methods or configure aspects of any of the aforementioned systems. Any such memory or other non-transitory storage medium having firmware or software stored therein in a computer-readable form for execution by processor hardware may be an example of a "computer-readable medium," as that term is understood in patent dictionaries.

[0073] Specific implementation examples are described in the following numbered clauses:

[0074] 1. A method for performing energy-efficient computing by reducing data movement between a processor and a memory device external to the processor, the method comprising:

[0075] Initiating, with a processor, a first process comprising at least a first sub-process;

[0076] outputting, using a first near processing control unit (NCU) of the processor, at least a first processing command associated with executing the first sub-process and a first address for storing data associated with the first sub-process in the memory device;

[0077] receiving, using a second NCU disposed on or near the memory device, the first processing command and the first address, and causing the data stored at the first address to be read from the memory device and forwarded to a processing circuit disposed on or near the memory device; and

[0078] The at least first sub-process is performed in the processing circuit by executing the at least first processing command on the data read from the first memory address to produce a first result.

[0079] 2. The method according to clause 1, further comprising:

[0080] The first result is stored in the memory device using the processing circuit.

[0081] 3. The method according to clause 1, further comprising:

[0082] using the second NCU to transmit the first result to the first NCU;

[0083] forwarding the first result to the processor using the first NCU; and processing the first result in the processor.

[0084] 4. A method according to any one of clauses 1 to 3, wherein the first process comprises a tag switching process, and the at least first sub-process comprises a compression sub-process, which compresses the data read from the first address to produce the first result.

[0085] 5. A method according to any one of clauses 1 to 3, wherein the first process includes a texture blocking process, and the at least first sub-process includes a linear bitmap generation sub-process and a conversion sub-process, wherein the linear bitmap generation process processes the data read from the first address to produce a linear bitmap, and the conversion sub-process processes the linear bitmap to convert the linear bitmap into a texture block.

[0086] 6. A method according to clause 3, wherein the first process includes a quantization and packing process, and the at least first sub-process includes at least a first quantization sub-process, and the at least first quantization process processes the data read from the first address to determine a first minimum matrix element value and a first maximum matrix element value.

[0087] 7. A method according to clause 6, wherein the at least first quantization sub-process also includes a sub-process for quantizing the data read from the first address using the first minimum matrix element value and the first maximum matrix element value to produce a multi-bit matrix, wherein the multi-bit matrix includes the first result forwarded by the second NCU to the host processor.

[0088] 8. The method according to clause 7, further comprising:

[0089] A sub-process is executed in the processor, the sub-process comprising performing a convolution on the multi-bit matrix to produce a

[0090] Second result;

[0091] forwarding the second result to the second NCU using the first NCU;

[0092] receiving the second result in the second NCU and forwarding the second result to the processing circuit;

[0093] as well as

[0094] A second quantization sub-process is performed in the processing circuitry, the second quantization sub-process processing the second result to determine a second minimum matrix element value and a second maximum matrix element value for the second result.

[0095] 9. The method of clause 8, wherein the second quantization sub-process further comprises generating a second multi-bit matrix using the second minimum matrix element value and the second maximum matrix element value.

[0096] 10. The method of any of clauses 1 to 9, wherein the host processor and the memory device are components of a system-on-chip (SoC) integrated circuit (IC) package of a portable computing device.

[0097] 11. A method for performing energy-efficient processing by reducing data movement between a processor and a memory device external to the host processor.

[0098] A computing system, the system comprising:

[0099] A processor comprising logic configured to initiate at least a first process comprising at least a first sub-process

[0100] Edit components;

[0101] a memory device comprising a memory address configured to store data;

[0102] a first near data processing control unit (NCU), the first near data processing control unit (NCU) being embedded in the processor or in communication with the processor, the first NCU comprising logic components configured to receive at least a first processing command and a first address from the processor, the at least first processing command comprising one or more commands for executing the first sub-process, the first address being a memory location of the memory device to be used by the first sub-process;

[0103] The address of the data processed by the process;

[0104] A second NCU is disposed on or near the memory device and in communication with the first NCU, the second NCU including a module configured to receive the first address and the first command from the first NCU.

[0105] logical components; and

[0106] a processing circuit disposed on or near the memory device, the processing circuit including a logic component configured to: receive the first command and the first address from the second NCU, read data from the first address, and execute the first command on the data read from the first address to generate a first result.

[0107] 12. The system of clause 11, wherein the processing circuit is further configured to store the first result at an address in the memory device.

[0108] 13. The system of clause 11, wherein the second NCU is further configured to transmit the first result to the first NCU, and wherein the first NCU is further configured to forward the first result to the processor, the processor being further configured to process the first result.

[0109] 14. A system according to any one of clauses 11 to 13, wherein the first process includes a tag switching process and the at least first sub-process includes a compression sub-process, and the processing circuit is further configured to perform the compression sub-process to compress the data read from the first address to produce the first result.

[0110] 15. A system according to any one of clauses 11 to 13, wherein the first process includes a texture blocking process, and the at least first sub-process includes a linear bitmap generation sub-process and a conversion sub-process, and the processing circuit is further configured to execute the linear bitmap generation sub-process to process the data read from the first address to generate a linear bitmap, and execute the conversion sub-process to process the linear bitmap to convert the linear bitmap into a texture tile.

[0111] 16. A system according to any one of clauses 11 to 13, wherein the first process comprises a quantization and a packaging process, and

[0112] The at least first sub-process includes at least a first quantization sub-process, and the processing circuit is configured to perform the at least first quantization process to process the data read from the first address to determine a first minimum matrix element value and a first maximum matrix element value.

[0113] 17. The system method of clause 16, wherein the at least first quantization sub-process further comprises a sub-process of quantizing the data read from the first address using the first minimum matrix element value and the first maximum matrix element value to generate a multi-bit matrix, the processing circuit being further configured to perform the quantization of the data read from the first address using the first minimum matrix element value and the first maximum matrix element value to generate a multi-bit matrix.

[0114] sub-process, and wherein the multi-bit matrix includes the first result forwarded to the processor by the second NCU.

[0115] 18. A system according to clause 17, wherein the processor is further configured to execute a sub-process comprising performing a convolution on the multi-bit matrix to produce a second result, and wherein the first NCU is further configured to forward the second result to the second NCU, the second NCU is further configured to receive the second result and forward the second result to the processing circuit, the processing circuit is further configured to execute a second quantization sub-process, the second quantization sub-process processes the second result to determine a second minimum matrix element value and a second maximum matrix element value of the second result.

[0116] 19. A system according to clause 18, wherein the second quantization sub-process also includes a sub-process for generating a second multi-bit matrix using the second minimum matrix element value and the second maximum matrix element value, and the processing circuit is further configured to generate a sub-process for generating a second multi-bit matrix using the second minimum matrix element value and the second maximum matrix element value.

[0117] 20. A system according to claim 11, wherein the system is part of a system-on-chip (SoC) integrated circuit (IC) package of a portable computing device, and wherein the processing circuit, the second NCU and the memory device are part of a stacked dynamic random access (DRAM) memory system of the SoC IC package, the memory device comprising a plurality of stacked DRAM dies, the second NCU and the processing circuit being embedded in a bank logic component of a logic die of the stacked DRAM memory system.

[0118] 21. A computer program comprising computer instructions for performing energy-efficient computing by reducing data movement between a processor and a memory device external to the processor, the computer instructions embodied in a non-transitory computer-readable medium,

[0119] The computer instructions include:

[0120] A first set of computer instructions for execution by a processor to initiate a program comprising:

[0121] The first process of the first subprocess is less;

[0122] a second set of computer instructions for execution by a first near processing control unit (NCU) of the processor to cause the first NCU to output at least a first processing command for executing the first sub-process and a first address for storing data associated with the first sub-process in the memory device;

[0123] a third set of computer instructions for execution by a second NCU disposed on or near the memory device to cause the second NCU to receive the at least first processing command and the first address, and to cause the data stored at the first address to be read from the memory device and forwarded to a second NCU disposed on or near the memory device.

[0124] processing circuitry on or near the memory device; and

[0125] A fourth set of computer instructions for execution by the processing circuit to cause the processing circuit to perform the at least first sub-process to produce a first result by executing the at least first processing command on the data read from the first address.

[0126] 22. The computer program according to clause 21, further comprising:

[0127] A fifth set of computer instructions for execution by the processing circuit causes the processing circuit to store the first result in the memory device.

[0128] 23. The computer program according to clause 21, further comprising:

[0129] A fifth set of computer instructions for execution by the second NCU to:

[0130] The second NCU transmits the first result to the first NCU;

[0131] A sixth set of computer instructions for execution by the first NCU to:

[0132] The first NCU forwards the first result to the processor; and

[0133] A seventh set of computer instructions for execution by the processor causes the processor to process the first result.

[0134] 24. A computer program according to clause 21, wherein the first process comprises a tag switching process and the at least first sub-process comprises a compression sub-process, the fourth set of computer instructions comprising instructions for compressing the data read from the first address to produce the first result.

[0135] 25. A computer program according to clause 21, wherein the first process includes a texture blocking process, and the at least first sub-process includes a linear bitmap generation sub-process and a conversion sub-process, and the fourth set of computer instructions includes computer instructions for processing the data read from the first address to generate a linear bitmap and computer instructions for processing the linear bitmap to convert the linear bitmap into a texture tile.

[0136] 26. A computer program according to clause 23, wherein the first process comprises a quantization and packing process and the at least first sub-process comprises at least a first quantization sub-process, the fourth set of computer instructions comprising instructions for processing the data from the first sub-process.

[0137] Computer instructions for reading the data at an address to determine a first minimum matrix element value and a first maximum matrix element value.

[0138] 27. A computer program according to clause 26, wherein the at least first quantization sub-process also includes a sub-process for quantizing the data read from the first address using the first minimum matrix element value and the first maximum matrix element value to produce a multi-bit matrix, and the fourth computer instruction set also includes computer instructions for quantizing the data read from the first address using the first minimum matrix element value and the first maximum matrix element value to produce the multi-bit matrix, wherein the multi-bit matrix includes the first result forwarded by the second NCU to the host processor.

[0139] 28. A computer program according to clause 27, wherein the seventh set of computer instructions includes computer instructions for performing a convolution on the multi-bit matrix to produce a second result, and wherein the second set of computer instructions also includes computer instructions for causing the first NCU to forward the second result to the second NCU, and wherein the third set of computer instructions also includes computer instructions for causing the second NCU to receive the second result and forward the second result to the processing circuit, and wherein the fourth set of computer instructions includes computer instructions for causing the processing circuit to perform a second quantization sub-process, which processes the second result to determine a second minimum matrix element value and a second maximum matrix element value of the second result.

[0140] 29. A computer program according to clause 27, wherein the second quantization sub-process also includes using the second minimum matrix element value and the second maximum matrix element value to produce a second multi-bit matrix, and wherein the fourth set of computer instructions also includes computer instructions for using the second minimum matrix element value and the second maximum matrix element value to produce the second multi-bit matrix.

[0141] 30. A method for performing energy-efficient processing by reducing data movement between a processor and a memory device external to the processor

[0142] A computing system, the system comprising:

[0143] a processor configured to initiate a first process including at least a first sub-process, the processor including a logic component configured to output at least a first processing command associated with executing the first sub-process and a first address for storing data associated with the first sub-process in the memory device; and

[0144] a processing circuit embedded in the memory device, the processing circuit comprising logic components configured to receive the first processing command and the first address, and cause the data stored at the first address to be read from the memory device and forwarded to the processing circuit, the processing circuit comprising logic components configured to perform the at least first sub-process to produce a first result by executing the at least first processing command on the data read from the first memory address.

[0145] Alternative embodiments will become apparent to those skilled in the art.Thus, while selected aspects have been illustrated and described in detail, it should be understood that various substitutions and changes can be made therein.

Claims

1. A method for performing energy-efficient computing by reducing data movement between a processor and a memory device external to the processor, the method comprising: Initiating, with a processor, a first process comprising at least a first sub-process; outputting, using a first near processing control unit (NCU) of the processor, at least a first processing command associated with executing the first sub-process and a first address for storing data associated with the first sub-process in the memory device; receiving, using a second NCU disposed on or near the memory device, the first processing command and the first address, and causing the data stored at the first address to be read from the memory device and forwarded to a processing circuit disposed on or near the memory device; as well as The at least first sub-process is performed in the processing circuit by executing the at least first processing command on the data read from the first memory address to produce a first result.

2. The method according to claim 1, further comprising: The first result is stored in the memory device using the processing circuit.

3. The method according to claim 1, further comprising: using the second NCU to transmit the first result to the first NCU; forwarding the first result to the processor using the first NCU; as well as The first result is processed in the processor. 4 . The method of claim 1 , wherein the first process comprises a tag switching process, and the at least first sub-process comprises a compression sub-process that compresses the data read from the first address to produce the first result.

5. The method of claim 1 , wherein the first process comprises a texture blocking process, and the at least first sub-process comprises a linear bitmap generation sub-process and a conversion sub-process, the linear bitmap generation sub-process processing the data read from the first address to produce a linear bitmap, and the conversion sub-process processing the linear bitmap to convert the linear bitmap into a texture tile.

6. The method of claim 3 , wherein the first process comprises a quantization and packing process, and the at least first sub-process comprises at least a first quantization sub-process that processes the data read from the first address to determine a first minimum matrix element value and a first maximum matrix element value.

7. The method of claim 6 , wherein the at least first quantization sub-process further comprises a sub-process of quantizing the data read from the first address using the first minimum matrix element value and the first maximum matrix element value to produce a multi-bit matrix, wherein the multi-bit matrix comprises the first result forwarded by the second NCU to the host processor.

8. The method according to claim 7, further comprising: executing a subprocess in the processor, the subprocess comprising performing a convolution on the multi-bit matrix to produce a second result; forwarding the second result to the second NCU using the first NCU; receiving the second result in the second NCU and forwarding the second result to the processing circuit; as well as A second quantization sub-process is performed in the processing circuitry, the second quantization sub-process processing the second result to determine a second minimum matrix element value and a second maximum matrix element value for the second result.

9. The method of claim 8, wherein the second quantization sub-process further comprises generating a second multi-bit matrix using the second minimum matrix element value and the second maximum matrix element value.

10. The method of claim 1, wherein the host processor and the memory device are components of a system-on-chip (SoC) integrated circuit (IC) package of a portable computing device.

11. A system for performing energy-efficient computing by reducing data movement between a processor and a memory device external to the host processor, the system comprising: a processor comprising logic configured to initiate at least a first process comprising at least a first sub-process; a memory device comprising a memory address configured to store data; a first near data processing control unit (NCU), the first near data processing control unit (NCU) being embedded in the processor or in communication with the processor, the first NCU comprising logic components configured to receive at least a first processing command and a first address from the processor, the at least first processing command comprising one or more commands for executing the first sub-process, the first address being an address of the memory device storing data to be processed by the first sub-process; a second NCU disposed on or near the memory device and in communication with the first NCU, the second NCU comprising logic configured to receive the first address and the first command from the first NCU; as well as a processing circuit disposed on or near the memory device, the processing circuit including a logic component configured to: receive the first command and the first address from the second NCU, read data from the first address, and execute the first command on the data read from the first address to generate a first result. 12 . The system of claim 11 , wherein the processing circuit is further configured to store the first result at an address in the memory device.

13. The system of claim 11, wherein the second NCU is further configured to transmit the first result to the first NCU, and wherein the first NCU is further configured to forward the first result to the processor, the processor being further configured to process the first result.

14. The system of claim 11, wherein the first process comprises a tag switching process, and the at least first sub-process comprises a compression sub-process, the processing circuit being further configured to perform the compression sub-process to compress the data read from the first address to produce the first result.

15. The system of claim 11 , wherein the first process comprises a texture blocking process, and the at least first sub-process comprises a linear bitmap generation sub-process and a conversion sub-process, the processing circuit being further configured to execute the linear bitmap generation sub-process to process the data read from the first address to generate a linear bitmap, and execute the conversion sub-process to process the linear bitmap to convert the linear bitmap into a texture tile.

16. The system of claim 13 , wherein the first process comprises a quantization and packing process, and the at least first sub-process comprises at least a first quantization sub-process, the processing circuit being configured to perform the at least first quantization process to process the data read from the first address to determine a first minimum matrix element value and a first maximum matrix element value.

17. The system method of claim 16, wherein the at least first quantization sub-process further comprises a sub-process of quantizing the data read from the first address using the first minimum matrix element value and the first maximum matrix element value to generate a multi-bit matrix, the processing circuit being further configured to perform the sub-process of quantizing the data read from the first address using the first minimum matrix element value and the first maximum matrix element value to generate a multi-bit matrix, and wherein the multi-bit matrix comprises the first result forwarded to the processor by the second NCU.

18. The system of claim 17 , wherein the processor is further configured to execute a sub-process comprising performing a convolution on the multi-bit matrix to produce a second result, and wherein the first NCU is further configured to forward the second result to the second NCU, the second NCU is further configured to receive the second result and forward the second result to the processing circuit, the processing circuit is further configured to execute a second quantization sub-process, the second quantization sub-process processes the second result to determine a second minimum matrix element value and a second maximum matrix element value of the second result.

19. The system of claim 18 , wherein the second quantization sub-process further comprises a sub-process for generating a second multi-bit matrix using the second minimum matrix element value and the second maximum matrix element value, and the processing circuit is further configured to generate the second multi-bit matrix sub-process using the second minimum matrix element value and the second maximum matrix element value.

20. The system of claim 11, wherein the system is part of a system-on-chip (SoC) integrated circuit (IC) package of a portable computing device, and wherein the processing circuit, the second NCU, and the memory device are part of a stacked dynamic random access (DRAM) memory system of the SoC IC package, the memory device comprising a plurality of stacked DRAM dies, the second NCU and the processing circuit being embedded in a bank logic component of a logic die of the stacked DRAM memory system.

21. A computer program comprising computer instructions for performing energy-efficient computing by reducing data movement between a processor and a memory device external to the processor, the computer instructions embodied in a non-transitory computer-readable medium, the computer instructions comprising: a first set of computer instructions for execution by a processor to initiate a first process comprising at least a first sub-process; a second set of computer instructions for execution by a first near processing control unit (NCU) of the processor to cause the first NCU to output at least a first processing command for executing the first sub-process and a first address for storing data associated with the first sub-process in the memory device; a third set of computer instructions for execution by a second NCU disposed on or near the memory device to cause the second NCU to receive the at least first processing command and the first address, and to cause the data stored at the first address to be read from the memory device and forwarded to processing circuitry disposed on or near the memory device; as well as A fourth set of computer instructions for execution by the processing circuit to cause the processing circuit to perform the at least first sub-process to produce a first result by executing the at least first processing command on the data read from the first address.

22. The computer program according to claim 21, further comprising: A fifth set of computer instructions for execution by the processing circuit causes the processing circuit to store the first result in the memory device.

23. The computer program of claim 21 , further comprising: a fifth set of computer instructions for execution by the second NCU to cause the second NCU to transmit the first result to the first NCU; a sixth set of computer instructions for execution by the first NCU to cause the first NCU to forward the first result to the processor; as well as A seventh set of computer instructions for execution by the processor causes the processor to process the first result.

24. The computer program of claim 21 , wherein the first process comprises a tag switching process and the at least first sub-process comprises a compression sub-process, the fourth set of computer instructions comprising instructions for compressing the data read from the first address to produce the first result.

25. A computer program according to claim 21, wherein the first process includes a texture blocking process, and the at least first sub-process includes a linear bitmap generation sub-process and a conversion sub-process, and the fourth set of computer instructions includes computer instructions for processing the data read from the first address to generate a linear bitmap and computer instructions for processing the linear bitmap to convert the linear bitmap into a texture tile.

26. The computer program of claim 23, wherein the first process comprises a quantization and packing process and the at least first sub-process comprises at least a first quantization sub-process, the fourth set of computer instructions comprising computer instructions for processing the data read from the first address to determine a first minimum matrix element value and a first maximum matrix element value.

27. The computer program of claim 26 , wherein the at least first quantization sub-process further comprises a sub-process for quantizing the data read from the first address using the first minimum matrix element value and the first maximum matrix element value to produce a multi-bit matrix, and the fourth set of computer instructions further comprises computer instructions for quantizing the data read from the first address using the first minimum matrix element value and the first maximum matrix element value to produce the multi-bit matrix, wherein the multi-bit matrix comprises the first result forwarded by the second NCU to the host processor.

28. A computer program according to claim 27, wherein the seventh set of computer instructions includes computer instructions for performing a convolution on the multi-bit matrix to produce a second result, and wherein the second set of computer instructions also includes computer instructions for causing the first NCU to forward the second result to the second NCU, and wherein the third set of computer instructions also includes computer instructions for causing the second NCU to receive the second result and forward the second result to the processing circuit, and wherein the fourth set of computer instructions includes computer instructions for causing the processing circuit to perform a second quantization sub-process, which processes the second result to determine a second minimum matrix element value and a second maximum matrix element value of the second result.

29. The computer program of claim 27 , wherein the second quantization subprocess further comprises generating a second multi-bit matrix using the second minimum matrix element value and the second maximum matrix element value, and wherein the fourth set of computer instructions further comprises computer instructions for generating the second multi-bit matrix using the second minimum matrix element value and the second maximum matrix element value.

30. A system for performing energy-efficient computing by reducing data movement between a processor and a memory device external to the processor, the system comprising: a processor configured to initiate a first process including at least a first sub-process, the processor including a logic component configured to output at least a first processing command associated with executing the first sub-process and a first address for storing data associated with the first sub-process in the memory device; as well as a processing circuit embedded in the memory device, the processing circuit comprising logic components configured to receive the first processing command and the first address, and cause the data stored at the first address to be read from the memory device and forwarded to the processing circuit, the processing circuit comprising logic components configured to perform the at least first sub-process to produce a first result by executing the at least first processing command on the data read from the first memory address.

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