Address allocation of devices coupled to shared bus

Abstract

A slave device participates in address allocation by iteratively communicating with a host device. The slave device receives a first broadcast command through a multipoint serial bus; decoupling the daisy chain input end of the slave device from the daisy chain output end of the slave device; receiving a second broadcast command through the multipoint serial bus; responding to the second broadcast command when the signal received through the daisy chain input is in an active state; ignoring the second broadcast command when the signal received through the daisy chain input is in an inactive state; and ignoring the subsequent broadcast command after responding to the second broadcast command. Responding to the second broadcast command includes configuring a unique device identifier of the slave device using an address provided in the second broadcast command, and coupling a daisy chain input of the slave device to a daisy chain output of the slave device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to pending U.S. non-provisional application No. 18 / 171,264, filed on February 17, 2023, which is assigned to the assignee of the present application and is hereby expressly incorporated herein by reference as if fully set forth below and for all applicable purposes. Technical Field

[0003] The present disclosure relates generally to serial communications and, more particularly, to addressing a device coupled to a serial bus having a predefined initial device address. Background Art

[0004] Mobile communication devices may include various components, including circuit boards, integrated circuit (IC) devices, and / or system-on-chip (SoC) devices. These components may include processing devices, user interface components, storage devices, and other peripheral components that communicate via a shared data communication bus, which may include a multi-point serial bus or a parallel bus. Common serial interfaces known in the industry include Inter-Integrated Circuit (I2C or I2C) and Inter-Integrated Circuit (I2C). 2 C) Serial interfaces and their derivatives and alternatives.

[0005] The Mobile Industry Processor Interface (MIPI) Alliance defines standards and protocols for the improved Inter-IC (I3C) serial interface, the Radio Frequency Front-End (RFFE) interface, the System Power Management Interface (SPMI), and other interfaces. These interfaces can be used to connect, for example, processors, sensors, and other peripheral devices. In some interfaces, multiple host devices are coupled to a serial bus, allowing two or more devices to act as hosts for different types of messages sent on the serial bus. The RFFE interface defines a communication interface that can be used to control various radio frequency (RF) front-end devices, including power amplifiers (PAs), low-noise amplifiers (LNAs), antenna tuners, filters, sensors, power management devices, switches, and more. These devices can be co-located in a single IC device or provided in multiple IC devices. In mobile communication devices, multiple antennas and radio transceivers can support multiple concurrent RF links. In another example, the SPMI specification defined by the MIPI Alliance provides a hardware interface that can be implemented between a baseband or application processor and peripheral components. In some implementations, SPMI is deployed to support power management operations within the device.

[0006] As device complexity increases, the demand for increased device density also increases, and there is a need for improved address management of standardized bus architectures and protocols. Summary of the Invention

[0007] Certain aspects of the present disclosure relate to systems, apparatus, methods, and techniques that can dynamically configure device addresses after initial system initialization or power-up without regard to the possibility of duplicate device addresses on a multi-drop serial bus.

[0008] In various aspects of the present disclosure, a method for communicating data at a slave device includes: receiving a first broadcast command via a multi-point serial bus; decoupling a daisy-chain input of the slave device from a daisy-chain output of the slave device; receiving a second broadcast command via the multi-point serial bus; responding to the second broadcast command when a signal received via the daisy-chain input is active; ignoring the second broadcast command when the signal received via the daisy-chain input is inactive; and ignoring subsequent broadcast commands after responding to the second broadcast command. Responding to the second broadcast command may include configuring a unique device identifier of the slave device using an address provided in the second broadcast command, and coupling the daisy-chain input of the slave device to the daisy-chain output of the slave device.

[0009] In various aspects of the present disclosure, a slave device is implemented using an interface circuit and a controller, the interface circuit being adapted to couple the slave device to a multi-drop serial bus. The controller may be configured to: receive a first broadcast command via the multi-drop serial bus; decouple a daisy-chain input of the slave device from a daisy-chain output of the slave device; receive a second broadcast command via the multi-drop serial bus; when a signal received via the daisy-chain input is active, respond to the second broadcast command by configuring a unique device identifier of the slave device using an address provided in the second broadcast command and coupling the daisy-chain input of the slave device to the daisy-chain output of the slave device; and ignore subsequent broadcast commands after responding to the second broadcast command.

[0010] In various aspects of the present disclosure, a method for communicating data at a host device includes: sending a first broadcast command over a first multi-point serial bus, the first broadcast command configured to: decouple a daisy-chain input of a first slave device from a daisy-chain output of the first slave device, and, for each of a plurality of slave devices coupled to the first multi-point serial bus, decouple the daisy-chain input of each slave device from the daisy-chain output of each slave device, the daisy-chain input of each slave device being coupled to the daisy-chain output of another slave device. The method also includes: activating a programming enable signal coupled to the daisy-chain input of the first slave device, and broadcasting a first sequence of address configuration commands over the first multi-point serial bus. Each slave device is configured to respond to a first address configuration command received after detecting the activated programming enable signal at its daisy-chain input. Each slave device is further configured to ignore subsequent address configuration commands. Each address configuration command is configured to configure a unique device identifier in a slave device responsive to the each address configuration command and to couple the daisy chain input of the slave device responsive to the each address configuration command to the daisy chain output of the slave device responsive to the each address configuration command.

[0011] In various aspects of the present disclosure, a data communication device includes an interface circuit and a controller, the interface circuit being adapted to couple the data communication device to one or more multi-point serial buses. The controller is configured to transmit a first broadcast command via a first multi-point serial bus, the first broadcast command being configured to decouple a daisy-chain input of a first slave device from a daisy-chain output of the first slave device, and, for each of a plurality of slave devices coupled to the first multi-point serial bus, decouple the daisy-chain input of each slave device from the daisy-chain output of each slave device, the daisy-chain input of each slave device being coupled to the daisy-chain output of another slave device. The controller is configured to activate a programming enable signal coupled to the daisy-chain input of the first slave device and broadcast a first sequence of address configuration commands via the first multi-point serial bus. Each slave device may be configured to respond to a first address configuration command received after detecting the activated programming enable signal at its daisy-chain input. Each slave device may be further configured to ignore subsequent address configuration commands. Each address configuration command is configured to configure a unique device identifier in a slave device responsive to the each address configuration command and to couple the daisy chain input of the slave device responsive to the each address configuration command to the daisy chain output of the slave device responsive to the each address configuration command. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1An apparatus is illustrated that employs a data link between IC devices that selectively operates according to one of a plurality of available standards.

[0013] Figure 2 The system architecture of an apparatus employing a data link between IC devices is illustrated.

[0014] Figure 3 Certain aspects of a two-data-line serial peripheral interface that may be adapted according to certain aspects disclosed herein are illustrated.

[0015] Figure 4 Illustrated is a device configuration for coupling various RF front-end devices using multiple RFFE buses.

[0016] Figure 5 Illustrated is a system in which single-wire slave devices and two-wire slave devices coexist according to certain aspects disclosed herein.

[0017] Figure 6 An example of a hardware configurable device address in a peripheral device coupled to a multi-drop serial bus is illustrated.

[0018] Figure 7 A slave device that has been configured to support dynamic address configuration according to certain aspects of the present disclosure is illustrated.

[0019] Figure 8 A first example of a system configured to support dynamic address configuration in accordance with certain aspects of the present disclosure is illustrated.

[0020] Figure 9 A second example of a system configured to support dynamic address configuration in accordance with certain aspects of the present disclosure is illustrated.

[0021] Figure 10 A third example of a system configured to support dynamic address configuration in accordance with certain aspects of the present disclosure is illustrated.

[0022] Figure 11 A fourth example of a system configured to support dynamic address configuration in accordance with certain aspects of the present disclosure is illustrated.

[0023] Figure 12 A fifth example of a system configured to support dynamic address configuration in accordance with certain aspects of the present disclosure is illustrated.

[0024] Figure 13 One example of an apparatus employing processing circuitry that may be adapted according to certain aspects disclosed herein is illustrated.

[0025] Figure 14 is a flow chart illustrating a method performed at a slave device coupled to a multi-drop serial bus according to certain aspects disclosed herein.

[0026] Figure 15 A hardware implementation of a slave device coupled to a multi-drop serial bus according to certain aspects disclosed herein is illustrated.

[0027] Figure 16 is a flow chart illustrating a method performed at a host device coupled to a multi-drop serial bus according to certain aspects disclosed herein.

[0028] Figure 17 Illustrated is a hardware implementation of a host device coupled to a multi-drop serial bus according to certain aspects disclosed herein. DETAILED DESCRIPTION

[0029] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0030] Several aspects of the present invention will now be described with reference to various devices and methods. These devices and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0031] Certain aspects of the present disclosure relate to serial bus configurations in which multiple devices can communicate at various times. The described serial buses typically operate in a hierarchical manner, with one device controlling communications during a transaction. The controlling device may be referred to as a host device, bus master, management device, or another terminology supported by the standard defining the protocol implemented by the controlling device. In some serial bus configurations, a single controlling device manages or controls communications during all transactions conducted over the serial bus. In other serial bus configurations, multiple devices may operate as controlling devices, with one device acting as the controlling device for each transaction conducted over the serial bus. The controlling device may provide a common clock signal transmitted over a conventional two-wire serial bus. The controlling device may provide control signaling that identifies the type of transaction to be conducted over the conventional two-wire serial bus. During certain transactions, the controlling device may send commands directed to one or more receiving devices using address information provided in or with the command. Receiving devices may be referred to as slave devices, client devices, slave devices, peripheral devices, or another terminology supported by the standard defining the protocol implemented by the controlling device. For the purposes of this disclosure, the controlling device will be referred to as the host device, and the associated receiving devices will be referred to as slave devices.

[0032] Overview

[0033] Devices that include multiple SoCs and other IC devices often employ a shared communication interface that may include a serial bus or other data communication link for connecting the processor to a modem and other peripheral devices. The serial bus or other data communication link may operate according to one or more defined standards or protocols. For example, the serial bus may operate according to the I2C, I3C, SPMI, and / or RFFE protocols, or another protocol that may be configured for half-duplex operation. Increased functionality and operational complexity may result in an increase in the number of devices coupled to the serial bus, including multiple instances of the same type of device. Certain types of devices are preprogrammed with the same device identifier that is intended to identify the device when communicating over the serial bus. Some devices are programmed with a small number of device identifiers that are selectable using hardware jumpers provided externally to the device. The limited availability of the device identifiers may limit the functionality of the system and / or may necessitate the use of multiple serial buses.

[0034] Certain aspects of the present disclosure relate to systems, circuits, and processes for implementing configuration of device identifiers, including situations where a device does not have a pre-assigned device identifier or where multiple devices are pre-configured with the same device identifier. In one example, a method for communicating data at a slave device includes: receiving a first broadcast command via a multi-point serial bus; decoupling a daisy-chain input of the slave device from a daisy-chain output of the slave device; receiving a second broadcast command via the multi-point serial bus; responding to the second broadcast command when a signal received via the daisy-chain input is active; ignoring the second broadcast command when the signal received via the daisy-chain input is inactive; and ignoring subsequent broadcast commands after responding to the second broadcast command. Responding to the second broadcast command may include: configuring a unique device identifier of the slave device using an address provided in the second broadcast command, and coupling the daisy-chain input of the slave device to the daisy-chain output of the slave device.

[0035] Certain aspects disclosed herein may be applicable to serial buses operating according to standardized protocols such as I2C, I3C, SPMI, RFFE, and / or Serial Peripheral Interface (SPI) protocols. Certain aspects may be applicable to serial buses operating in half-duplex mode or full-duplex mode. Certain aspects may be applicable to multi-point interfaces and / or interfaces operating in point-to-point mode.

[0036] Example of a device using a serial data link

[0037] According to certain aspects of the present disclosure, serial data links may be used to interconnect electronic devices that are subcomponents of devices such as: cellular phones, smartphones, Session Initiation Protocol (SIP) phones, laptops, notebooks, netbooks, smartbooks, personal digital assistants (PDAs), satellite radios, Global Positioning System (GPS) devices, smart home devices, smart lighting, multimedia devices, video devices, digital audio players (e.g., MP3 players), cameras, game consoles, entertainment devices, vehicle components, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), appliances, sensors, security devices, vending machines, smart meters, drones, multi-rotor helicopters, or any other similarly functional devices.

[0038] Figure 1An example of an apparatus 100 that may employ a data communication bus is illustrated. Apparatus 100 may include an SoC, processing circuitry 102 having a plurality of circuits or devices 104, 106, and / or 108, which may be implemented in one or more ASICs or SoCs. In one example, apparatus 100 may be a communications device, and processing circuitry 102 may include a processing device provided in ASIC 104, one or more peripheral devices 106, and a transceiver 108 that enables the apparatus to communicate with a radio access network, a core access network, the Internet, and / or another network via an antenna 124.

[0039] ASIC 104 may have one or more processors 112, one or more modems 110, onboard memory 114, bus interface circuitry 116, and / or other logic circuitry or functionality. Processing circuit 102 may be controlled by an operating system, which may provide an application programming interface (API) layer that enables one or more processors 112 to execute software modules residing in onboard memory 114 or other processor-readable storage devices 122 provided on processing circuit 102. Software modules may include instructions and data stored in onboard memory 114 or processor-readable storage devices 122. ASIC 104 may access its onboard memory 114, processor-readable storage devices 122, and / or storage devices external to processing circuit 102. Onboard memory 114 and processor-readable storage devices 122 may include read-only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM), flash memory cards, or any other memory device useful in processing systems and computing platforms. The processing circuit 102 may include, implement, or access a local database or other parameter storage device that can maintain operating parameters and other information used to configure and operate the device 100 and / or the processing circuit 102. The local database can be implemented using registers, database modules, flash memory, magnetic media, EEPROM, a floppy disk, or a hard disk, etc. The processing circuit 102 can also be operably coupled to external devices such as an antenna 124, a display 126, operator controls such as switches or buttons 128, 130, and / or an integrated or external keyboard 132, and other components. The user interface module can be configured to operate with the display 126, the external keyboard 132, etc. via a dedicated communication link or via one or more serial data interconnects.

[0040] Processing circuitry 102 may provide one or more buses 118a, 118b, 120 that enable certain devices 104, 106, and / or 108 to communicate. In one example, ASIC 104 may include bus interface circuitry 116 that includes a combination of circuits, counters, timers, control logic, and other configurable circuits or modules. In one example, bus interface circuitry 116 may be configured to operate according to a communication specification or protocol. Processing circuitry 102 may include or control power management functionality that configures and manages the operation of apparatus 100.

[0041] Figure 2 The example includes a plurality of devices 202 and 2220-222 coupled to a serial bus 220. N Certain aspects of the apparatus 200. Devices 202 and 2220-222 N The devices 202 and 2220-222 may be implemented in one or more semiconductor IC devices such as application processors, SoCs, or ASICs. N The slave devices 2220-222 may include, support, or operate as modems, signal processing devices, display drivers, cameras, user interfaces, sensors, sensor controllers, media players, transceivers, RFFE devices, and / or other such components or devices. N One or more of the devices 202 and 2220-222 may be used to control, manage, or monitor sensor devices. N Communication between the devices over the serial bus 220 is controlled by the master device 202. Some types of buses can support multiple master devices 202.

[0042] In one example, the master device 202 may include an interface controller 204 that manages access to the serial bus, configures the slave devices 2220-222 N The master device 202 may include a configuration register 206 or other storage device 224 and other control logic components 212 configured to handle protocols and / or higher-level functions. The control logic component 212 may include processing circuits such as a state machine, a sequencer, a signal processor, or a general-purpose processor. The master device 202 includes a transceiver 210 and line drivers / receivers 214a and 214b. The transceiver 210 may include a receiver, a transmitter, and common circuitry, wherein the common circuitry may include timing, logic, and storage circuitry and / or devices. In one example, the transmitter encodes and transmits data based on the timing in the clock signal 228 provided by the clock generation circuit 208. Other timing clocks 226 may be used by the control logic component 212 and other functions, circuits, or modules.

[0043] At least one device 2220-222 N It can be configured to operate as a slave device on the serial bus 220 and may include circuits and modules that support a display, an image sensor, and / or control and communicate with one or more sensors that measure environmental conditions. In one example, the device 2220 configured to operate as a slave device may provide control functions, modules, or circuits 232, including circuits and modules for supporting a display, an image sensor, and / or control and communicate with one or more sensors that measure environmental conditions. The slave device 2220 may include configuration registers 234 or other storage 236, control logic 242, a transceiver 240, and line drivers / receivers 244a and 244b. The control logic 242 may include processing circuitry such as a state machine, a sequencer, a signal processor, or a general-purpose processor. The transceiver 210 may include a receiver, a transmitter, and common circuitry, wherein the common circuitry may include timing, logic, and storage circuitry and / or devices. In one example, the transmitter encodes and transmits data based on the timing in the clock signal 248 provided by the clock generation and / or recovery circuit 246. Clock signal 248 may be derived from a signal received from clock line 218. Other timing clocks 238 may be used by control logic 242 and other functions, circuits, or modules.

[0044] The serial bus 220 may operate according to RFFE, I2C, I3C, SPMI, or another protocol. N Can be configured to selectively operate as a master device or a slave device on the serial bus 220. Two or more devices 202, 2220-222 N Can be configured to operate as a master device on the serial bus 220 .

[0045] In some specific implementations, the serial bus 220 can operate according to the I3C protocol. Devices that communicate using the I3C protocol can coexist on the same serial bus 220 with devices that communicate using the I2C protocol. The I3C protocol can support different communication modes, including a single data rate (SDR) mode that is compatible with the I2C protocol. The high data rate (HDR) mode can provide data transfer rates between 6 megabits per second (Mbps) and 16 Mbps, and some HDR modes can provide higher data transfer rates. The I2C protocol can comply with the de facto I2C standard, providing data rates that can range between 100 kilobits per second (kbps) and 3.2 Mbps. In addition to data format and bus control aspects, the I2C and I3C protocols can also define electrical and timing aspects of signals sent on the two-wire serial bus 220. In some aspects, the I2C and I3C protocols can define direct current (DC) characteristics that affect certain signal levels associated with the serial bus 220 and / or alternating current (AC) characteristics that affect certain timing aspects of signals sent on the serial bus 220. In some examples, two-wire serial bus 220 sends data on data line 216 and a clock signal on clock line 218. In some instances, data can be encoded in signaling states or signaling state transitions of data line 216 and clock line 218.

[0046] According to certain aspects of the present disclosure, a serial bus operating according to the Serial Peripheral Interface (SPI) protocol can be used to provide a simple, low-power communication interface. In one example, the SPI interface can be primarily used to exchange data between processing circuitry and a touch panel of a display. The SPI interface can be coupled to a serial bus having a clock line, two data lines (a Master In Slave Out (MISO) line and a Master Out Slave In (MOSI) line), and a chip select (CS) for each slave device. The presence of the MISO and MOSI lines enables full-duplex operation. Figure 3 300. Certain aspects related to the operation of a dual data line SPI 300 are illustrated. In some instances, a master device 302 may be incorporated into a SoC that acts as an application processor, a host processor, or other functional component of an apparatus or system. The master device 302 uses a multi-line bus 310 to couple to a plurality of slave devices 304, 306, 308. The master device 302 drives data to the slave devices 304, 306, 308 via a master-out slave-in line (MOSI line 316) of the multi-line bus 310. The slave devices 304, 306, 308 can each drive data to the master device 302 via a shared master-in slave-out line (MISO line 314) of the multi-line bus 310.

[0047] The multi-line bus 310 includes at least one slave select line 318, 320, 322 for each slave device 304, 306, 308. As illustrated, a first slave select line 318 (SS1) controls bus access for the first slave device 304, a second slave select line 320 (SS2) controls bus access for the second slave device 306, and a third slave select line 322 (SS3) controls bus access for the third slave device 304. The master device 302 can assert the slave select lines 318, 320, 322 to cause the corresponding slave device 304, 306, 308 to receive data via the MOSI line 316 and / or grant permission to the corresponding slave device 304, 306, 308 to transmit via the MISO line 314.

[0048] In one example, when a low voltage level is applied to the slave select lines 318, 320, 322, the slave select lines 318, 320, 322 are not asserted, and the slave select lines 318, 320, 322 are asserted by driving the slave select lines 318, 320, 322 to a high voltage level (e.g., toward a power supply level). In another example, when a high voltage level (e.g., a power supply level) is applied to the slave select lines 318, 320, 322, the slave select lines 318, 320, 322 are not asserted, and the slave select lines 318, 320, 322 are asserted by driving the slave select lines 318, 320, 322 to a low voltage level. For each slave select line 318 , 320 , 322 , a driver in the master device 302 may be operated to charge and discharge the slave select line 318 , 320 , 322 based on the desired asserted state of the slave select line 318 , 320 , 322 .

[0049] Data is transmitted between the master device 302 and the slave devices 304, 306, 308 according to a clock signal provided on a clock line 312 of the multi-wire bus 310. Data signaling is unidirectional on the MISO line 314 and on the MOSI line 316. The direction of data transmission over the MISO line 314 is opposite to the direction of data transmission over the MOSI line 316. The data transmission over the MISO line 314 and the MOSI line 316 is synchronized with the clock signal provided on the clock line 312.

[0050] Figure 4FIG4 is a diagram 400 illustrating an example of a configuration of communication links in a chipset or device 402 that employs multiple RFFE buses 430, 432, 434 to couple various RF front-end devices 418, 420, 422, 424, 426, 428. In this example, a modem 404 includes an RFFE interface 408 that couples the modem 404 to a first RFFE bus 430. The modem 404 can communicate with a baseband processor 406 and a radio frequency integrated circuit (RFIC 412) via respective communication links 410, 436, or, in some implementations, via a common communication link 410 or 436. The illustrated device 402 can be embodied in one or more of a mobile communication device, a mobile phone, a mobile computing system, a mobile phone, a laptop computer, a tablet computing device, a media player, a gaming device, a wearable computing device, a wearable communication device, an appliance, and the like.

[0051] In various examples, the chipset or device 402 may be implemented using one or more baseband processors 406, a modem 404, an RFIC 412, multiple communication links 410, 436, multiple RFFE buses 430, 432, 434, and / or other types of buses. Each of the RFFE buses 430, 432, 434 is managed by a bus owner master (BoM) device. Figure 4 In the illustrated example, the modem 404 and the RFIC 412 may be designated as the BoM for one or more of the RFFE buses 430, 432, 434. The chipset or device 402 may include other processors, circuits, modules, and may be configured for various operations and / or different functionality.

[0052] exist Figure 4 In the illustrated example, the modem 404 is coupled to the RF tuner 418 via its RFFE interface 408 and a first RFFE bus 430. The RFIC 412 may include one or more RFFE interfaces 414, 416, a controller, a state machine, and / or a processor that configure and control certain aspects of the RF front end. In the illustrated example, the RFIC 412 communicates with the PA 420 and the power tracking module 422 via a first RFFE interface and a second RFFE bus 432 in its RFFE interface 414. In the illustrated example, the RFIC 412 communicates with the switch 424 and one or more LNAs 426, 428 via a second RFFE interface and a third RFFE bus 434 in its RFFE interface 416.

[0053] Bus latency can affect the ability of a serial bus to handle high-priority, real-time, and / or other time-constrained messages. Low-latency messages, or messages requiring low bus latency, may involve sensor states, real-time events generated by devices, and virtualized GPIOs. In one example, bus latency can be measured as the time elapsed between a message becoming available for transmission and the delivery of the message. In another example, bus latency can be measured as the time elapsed between a message becoming available for transmission and the start of transmission of the message. Other measures of bus latency may be used. Bus latency typically includes delays incurred when sending higher priority messages, interrupt processing, the time required to terminate a datagram in progress on the serial bus, the time to send commands to cycle the bus between transmit and receive modes, bus arbitration, and / or the sending of commands specified by the protocol.

[0054] In one example, a latency-sensitive message carries or includes a coexistence message. Coexistence messages can be sent across a multi-system platform to prevent or mitigate situations where certain types of RFFE devices collide with each other. RFFE devices that can be the source or subject of coexistence messages include, for example, the switch 424, LNAs 426, 428, PA 420, and other types of devices operating concurrently in a manner that generates inter-device RF interference and / or could potentially cause damage to one or more devices. Coexistence management messages can be exchanged between certain devices shared across different radio access technologies, wireless subscriptions, and / or applications. For example, the switch 424, LNAs 426, 428, PA 420, and / or antennas may be shared by two different radio access technologies with different transmit and receive schedules, and if a device begins transmitting using one radio access technology and receiving using another, damage to the LNAs 426, 428 or other devices may occur. Devices that may interfere with each other can exchange coexistence management (CxM) messages to allow each device to signal impending actions that could cause interference or collisions. For example, the two modems 404 may exchange CxM messages to manage the operation of the shared components.

[0055] According to certain aspects disclosed herein, a two-wire serial bus can be adapted to operate alternately in a conventional two-wire mode and a single-wire mode. In one example, the serial bus can operate according to an RFFE protocol, such that a clock line and a data line are used for communication with a two-wire slave device coupled to the serial bus, and the data line is used for communication with a single-wire slave device coupled to the serial bus without a clock signal. A host device can use pulse width modulation to encode data sent to a single-wire slave device.

[0056] Figure 5A system 500 is illustrated in accordance with certain aspects disclosed herein, in which a single-wire slave device 504 and a two-wire slave device 506 can coexist, and in which a host device 502 can communicate with both the single-wire slave device 504 and the two-wire slave device 506. The host device 502 can be provided in an RFIC, a modem, an application processor, or another type of device. The host device 502 is coupled to one or more slave devices 504, 506 via at least an SDATA line 510 of a two-wire serial bus 508 that also includes an SCLK line 512. Data can be encoded in a data signal transmitted via the SDATA line 510, and in a two-wire communication mode, a receiver can extract the data using a clock signal transmitted via the SCLK line 512. In the illustrated example, the serial bus 508 operates according to the RFFE protocol. In other examples, the serial bus 508 can operate according to another protocol, such as the I3C protocol, the SPMI protocol, or the like. In the illustrated example, each single-wire slave device 504 and each two-wire slave device 506 is coupled to SDATA line 510. Single-wire slave device 504 is adapted for single-wire communication mode, while two-wire slave device 506 is also coupled to SCLK line 512 to receive a clock signal used in two-wire communication mode.

[0057] The host device 502 may include a protocol controller 514, which may be implemented as processing circuitry including a processor, controller, state machine, or other logical components. The protocol controller 514 may be configured to support one or more protocols that may be used to manage the operation of the serial bus 508. In some implementations, the protocol controller 514 may be operable to configure one or more slave devices 504, 506. The protocol controller 514 may determine the configuration of the slave devices 504, 506 that are designated recipients of data to be transmitted via the serial bus 508 and may accordingly encode the data in the signal to be transmitted via the SDATA line 510. In some examples, a broadcast message for a combination of single-wire slave devices 504 and dual-wire slave devices 506 may be transmitted twice: once in single-wire communication mode and once in dual-wire communication mode. The protocol controller 514 may also determine whether and / or when a clock signal is to be transmitted via the SCLK line 512. In some implementations, the clock signal is suppressed when data is being transmitted to one or more single-wire slave devices 504 in single-wire communication mode.

[0058] According to certain aspects disclosed herein, a host device 502 can select between a single-wire slave device 504 and a two-wire slave device 506 when initiating a transaction. In one example, the host device 502 can use different sequence start conditions (SSCs) to precede single-wire and two-wire transactions. In some implementations, certain interface characteristics of the single-wire slave device 504 and / or the two-wire slave device 506 can be configurable. For example, the single-wire slave device 504 and / or the two-wire slave device 506 coupled to the serial bus 508 can match a specified bus capacitance when driving the SDATA line 510 based on a configurable register setting that defines a specified capacitance for the SDATA line 510. In other examples, the specified bus capacitance can be hardwired into the single-wire slave device 504 and / or the two-wire slave device 506.

[0059] The number of active devices that can be coupled to a multi-point serial bus is generally limited by the protocol. Certain protocols and standards defined by the MIPI Alliance provide an addressing structure in which each slave device is assigned a unique device identifier, which is represented as a multi-bit quantity. In one example, the RFFE protocol defines a device identifier with four bits. The unique device identifier may be referred to as a "USID" assigned to the associated device. The BoM of the multi-point serial bus may uniquely identify each device coupled to the multi-point serial bus based on the unique address assigned to the slave / peripheral device. In a conventional implementation, each device is assigned a fixed four-bit USID by design. Certain peripheral devices may be capable of being configured with multiple different USIDs, which may be selected based on the hardware configuration. In one example, a designer who desires to couple multiple instances of a peripheral device to a single multi-point serial bus may use two hardware configurable pins to select between the USID options provided for the peripheral device.

[0060] Figure 6An example of a hardware-configurable USID in a peripheral device 600 that is intended to be coupled to a multi-drop serial bus operating according to the RFFE protocol is illustrated. USID 608 is selected to configure the PHY 606 of the peripheral device 600 using external jumpers that define the signaling state of two input / output pins (I / O pins 612 and 614). In the illustrated example, the signaling state of each of the I / O pins 612, 614 is configured using switching circuitry 610 to select between pull-up mode or pull-down mode. I / O pins 612, 614 are coupled to a multiplexer 604 and provide a two-bit select control input for the multiplexer 604. The switch settings in the switching circuitry 610 enable the multiplexer 604 to select between four pre-programmed addresses 602a-602d available for use by the peripheral device 600. In other implementations, the signaling states of the I / O pins 612, 614 are configured by hardwiring the pins to one of two voltage rails (typically through resistors). Providing two I / O pins 612, 614 and associated selection circuitry increases the cost of manufacturing the peripheral device 600 and increases the complexity of the hardware design.

[0061] exist Figure 6 In the illustrated example, up to four peripherals in peripheral device 600 can be active on the same multi-drop serial bus because only four pre-programmed addresses 602a-602d are available for use. In some instances, system design requirements may dictate that more than four peripherals in peripheral device 600 be included in the system, and a second multi-drop serial bus may be provided to couple some of peripherals in peripheral device 600 to an SoC, modem, or other host device. These and other issues with hardware-configurable USIDs limit the usefulness of associated devices and increase the complexity of integrating such devices into many systems.

[0062] For example, conventional methods of "pin binding" for configuring the USID 608 of the peripheral device 600 are cumbersome for a two-wire RFFE slave device 600 and cumbersome for a single-wire RFFE slave device 600. One goal of implementing a simpler, cost-constrained single-wire RFFE slave device 600 is to reduce the I / O pin count required for the slave device 600, and the use of pin binding requires allocating two additional I / O pins 612, 614 to implement static functions. Both the two-wire RFFE slave device and the single-wire RFFE slave device must also include additional resistors to pull up or down these RF devices, and the I / O pins 612, 614 are used to select the USID 608.

[0063] According to certain aspects of the present disclosure, a USID to be used by a peripheral device to communicate over a multi-point serial bus can be dynamically configured by the BoM, regardless of whether multiple devices share the same pre-programmed address or whether the device to be configured does not have an initially assigned address. A multi-point serial bus can be coupled to any number of peripheral devices of the same type, as long as the BoM assigns a unique address to each peripheral device coupled to the multi-point serial bus. In the example of a multi-point serial bus operating according to the RFFE protocol, when the BoM assigns a unique address to each peripheral device, the addressing and address management scheme disclosed herein can allow a maximum number of 15 peripheral devices to be coupled to the multi-point serial bus. In some implementations, two I / O pins for selecting a USID from four or more pre-programmed addresses can be used to support address configuration by the BoM. In other implementations, two I / O pins used for testing, troubleshooting, or other purposes can be used to support address configuration by the BoM.

[0064] Figure 7 1 illustrates a slave device 700 that has been configured to support dynamic address configuration by a BoM in accordance with certain aspects of the present disclosure. A controller 702 can monitor communications received via a physical layer circuit (PHY 706) coupled to a multi-point serial bus 712. In this example, the multi-point serial bus 712 operates according to the RFFE protocol. The controller 702 can write to a register 704 that stores the USID assigned to the slave device 700. The slave device 700 is configured to respond to broadcast commands received via the multi-point serial bus, as well as to respond to other types of commands addressed to the slave device 700 using the USID configured for the slave device 700.

[0065] The controller 702 receives an input signal 720 via an input I / O pin 714. According to one aspect of the present disclosure, the input signal 720 can be used to control or indicate dynamic address configuration. The controller 702 provides a control signal 718 that configures the switch 708 during dynamic address configuration. The controller can open or close the switch 708. When closed, the switch 708 couples the input I / O pin 714 to the output I / O pin 716. The I / O pins 714, 716 enable the slave device 700 to be included in a daisy chain of peripheral / slave devices that are also coupled to the multi-drop serial bus 712. In some examples, the I / O pins 714, 716 can be reconfigurable I / O pins, such as Figure 66, which provide two-bit selection control inputs to the multiplexer 604. When the switch 708 is closed, the input signal 720 can be relayed along the daisy chain. In some implementations, the input I / O pin 714 is connected to a pull-up or pull-down resistor or circuit within the slave device 700 to maintain the input signal 720 in an unasserted state when the input I / O pin 714 is not actively driven by the upstream device.

[0066] Figure 8 8. A system 800 is illustrated that includes a multi-drop serial bus 810 that connects a host device 802 to multiple slave devices 8040-8044 according to certain aspects of the present disclosure. N The master device 802 is coupled to the multi-drop serial bus 810 via physical interface circuits 808, which are configured to operate as a BoM with respect to the multi-drop serial bus 810. The slave devices 8040-804 N Each of is adapted to support, for example, Figure 7 The illustrated slave device 700 provides daisy-chain capability. In some implementations, the multi-drop serial bus 810 can operate according to the RFFE protocol.

[0067] The controller 806 in the host device 802 is configured to drive a programming enable signal (PID signal 812) via an I / O pin. During dynamic address configuration, the PID signal 812 is asserted by the controller 806. The controller 806 initiates dynamic address configuration by sending an initial broadcast command via the multi-drop serial bus 810. Through the protocol, all slave devices 8040-804 coupled to the multi-drop serial bus 810 N Respond to the initial broadcast command without referring to their internal USID. The initial broadcast command is not required from any slave device 8040-804 N Generally, slave devices 8040-804 are programmed with the same USID. N Two or more of the may respond to the initial broadcast command by, for example, writing to internal registers without interfering with each other.

[0068] According to one aspect of the present disclosure, the initial broadcast command causes the slave devices 8040-804 N Each of the switches 8140-814 opens its corresponding switch 8140-814 N and enters the device address configuration mode of operation. In some examples, each slave device 8040-804 N A flag may be set to indicate that device address configuration is in progress. The controller 806 may configure the slave devices 8040-804 by sending a series of address configuration commands. NEach address configuration command is expected in the slave device 8040-804 N In some implementations, the controller 806 sends different USIDs in the address configuration commands, and these address configuration commands are sent to the slave devices 8040-804 in the daisy chain. N For example, the first address configuration command is configured with the USID of the first slave device 8040 in the daisy chain. The first slave device 8040 directly receives the PID signal 812 from the host device 802. The first address configuration command causes the USID to be written into a register in the first slave device 8040 in the daisy chain.

[0069] Each slave device 8040-804 N is configured to respond to the next address configuration command sent via the multi-drop serial bus 810 after it detects that the PID signal 812 is asserted. N It can sense the input I / O pins 8160-816 N The assertion of the PID signal 812 is detected by the state of the PID signal 812. As shown in the first interval 822 in the time series 820, all switches 8140-814 N After both have been disconnected, the PID signal 812 initially drives only the input I / O pin 8160 of the slave device 8040. The USID of the slave device 8040 is configured in response to the first address configuration command sent during the first interval 822. When the USID of the slave device 8040 is written, the slave device closes its switch 8140 and may set a configuration flag indicating that its USID has been configured. Subsequent address configuration commands are ignored by the slave device 8040 based on the setting of the configuration flag. In some implementations, the switch 8140 may be configured to switch the input I / O pin 8160 between the internal sensing circuit or the output pin 818 of the slave device 8040. In these latter implementations, the slave device 8040 is no longer coupled to the PID signal 812 after receiving its USID, and the input to the sensing device may be pulled by a pull-up or pull-down circuit, allowing the slave device 8040 to effectively sense the unasserted PID signal 812.

[0070] Closing the switch 8140 in the slave device 8040 extends the daisy chain to the next device, which is the slave device 8041. The slave device 8041 then senses that the PID signal 812 is asserted, and the USID of the slave device 8041 is configured in response to the next transmitted address configuration command sent during the second interval 824. Upon writing the USID of the slave device 8041, the slave device closes its switch 8141 and may set a configuration flag indicating that its USID has been configured. Subsequent address configuration commands are ignored by the slave device 8041 based on the setting of the configuration flag or the operation of the switch 8141. Address configuration continues until the last slave device 8041 in the daisy chain is reached. N The USID of has been configured during the illustrated third interval 826.

[0071] In some implementations, the controller 806 in the host device 802 can cause a broadcast command to be sent via the multi-drop serial bus 810 to cause the slave devices 8040-804 N Terminate or exit the device address configuration mode of operation. In some implementations, the master device 802 may query the slave devices 8040-804 after configuring their USIDs. N The master device 802 may send a read command to cause the slave devices 8040-804 N Read back its newly configured USID. In some instances, only the most recently configured slave device 8040-804 N Read commands are processed during the address configuration mode of operation, and the master device 802 may subsequently send write commands to the recently configured slave devices 8040-804. N Close its switch 8140-814 N And / or set a configuration flag indicating that its USID has been configured.

[0072] The presently disclosed dynamic address configuration process can be used to assign device addresses for a variety of bus architectures and protocols. Figure 8 The illustrated example is described with respect to a multi-point serial bus 810 operating in accordance with the RFFE protocol. The concepts and processes disclosed herein may be implemented using any serial bus architecture that supports broadcasting. The concepts and processes disclosed herein may be implemented in single-wire, dual-wire, or other multi-wire serial bus architectures. The concepts and processes disclosed herein may be used to independently assign addresses to single-wire peripheral devices and dual-wire peripheral devices coupled to data lines of the same serial bus.

[0073] Figure 9A system 900 is illustrated in which an RFFE host device 902 is a designated or configured BoM for two multi-drop serial buses that operate independently and according to the RFFE protocol. In one example, the RFFE host device 902 may correspond to Figure 4 The illustrated RFIC 412. The RFFE host device 902 can configure the slave devices 9040-904 coupled to the first multi-point serial bus 906 N and slave devices 9140-914 coupled to the second multi-drop serial bus 916 N Slave devices 9040-904 coupled to the first multi-drop serial bus 906 N and slave devices 9140-914 coupled to the second multi-drop serial bus 906 N Can be configured concurrently or at different times.

[0074] The RFFE host device 902 is configured to drive a programming enable signal (PID signal 910) via an I / O pin. During dynamic address configuration for either or both of the multi-drop serial buses 906, 916, the RFFE host device 902 asserts the PID signal 910. The RFFE host device 902 initiates dynamic address configuration by sending an initial broadcast command via one or both of the multi-drop serial buses 906, 916. Through the protocol, all slave devices 9040-904 M 、9140-914 N are configured to respond to initial broadcast commands without reference to their internal USIDs. The initial broadcast command may be sent via either or both of the multi-point serial buses 906, 916. According to one aspect of the present disclosure, when the initial broadcast command is not sent by the slave devices 9040-904 M 、9140-914 N When the PID signal 910 is sent to the multi-drop serial bus 906 or 916 coupled to the slave device, the PID signal 910 can be ignored by these slave devices. For the purpose of this description, an example will be described in which the initial broadcast command is sent through both multi-drop serial buses 906, 916 concurrently or within a short period of time so that the initial broadcast command is sent to the slave devices 9040-904 M and 9140-914 N The address configuration process of the two devices overlaps to some extent.

[0075] According to one aspect of the present disclosure, the initial broadcast command causes the slave devices 9040-904 M and 9140-914 N Each of the switches 9080-908 opens its corresponding M 、9180-918N and enters the device address configuration mode of operation. In some examples, each slave device 9040-904 M and 9140-914 N A flag may be set to indicate that device address configuration is in progress. The RFFE host device 902 may configure the slave devices 9040-904 by sending a first series of address configuration commands via the first multi-drop serial bus 906. M The RFFE host device 902 may send a second series of address configuration commands via the second multi-point serial bus 916 to configure the slave devices 9140-914 N The first series of address configuration commands and the second series of address configuration commands may be sent concurrently or asynchronously with respect to each other.

[0076] Each address configuration command sent via the first multi-drop serial bus 906 is sent to the slave devices 9040-904 M Each address configuration command sent via the second multi-drop serial bus 916 is sent to the slave devices 9140-914. N In some implementations, the RFFE host device 902 communicates with the slave devices 9040-904 M or slave devices 9140-914 N The USIDs are sent in the address configuration command in an order corresponding to their positions in their respective daisy chains. In one example, a first address configuration command sent over the first multi-point serial bus 906 is configured with the USID of the first slave device 9040 in the first daisy chain, where the slave device 9040 receives the PID signal 910 directly from the RFFE host device 902. The first address configuration command sent over the first multi-point serial bus 906 causes the USID to be written to a register in the first slave device 9040 in the daisy chain. In another example, a first address configuration command sent over the second multi-point serial bus 916 is configured with the USID of the first slave device 9140 in the second daisy chain, where the slave device 9140 receives the PID signal 910 directly from the RFFE host device 902. The first address configuration command sent over the first multi-point serial bus 906 causes the USID to be written to a register in the slave device 9040, and the first address configuration command sent over the second multi-point serial bus 916 causes the USID to be written to a register in the slave device 9140.

[0077] Each slave device 9040-904 M and 9140-914 Nis configured to respond to the next address configuration command sent via its corresponding multi-drop serial bus 906, 916 after detecting that the PID signal 910 has been asserted. M 、9140-914 N The assertion of the PID signal 910 may be detected by sensing the state of the input I / O pins and may then respond to the next received address configuration command. M 、9140-914 N By storing the provided USID and by closing its daisy chain switches 9080-908 M 、9180-918 N To respond to the address configuration command. Subsequent address configuration commands are in the slave devices 9040-904 M 、9140-914 N After the address has been configured and based on the setting of the configuration flag or the corresponding switches 9080-908 M 、9180-918 N The operations are ignored by these slave devices.

[0078] Closing the switch 9080 in the slave device 9040 extends the first daisy chain to the slave device 9041. The slave device 9041 then senses that the PID signal 910 is asserted, and the USID of the slave device 9041 is configured in response to the next address configuration command sent over the first multi-drop serial bus 906. When the USID of the slave device 9041 is written, the slave device closes its switch 9081 and may set a configuration flag indicating that its USID has been configured. Subsequent address configuration commands are ignored by the slave device 9041 based on the setting of the configuration flag or the operation of the switch 9081. Address configuration continues until the last slave device 9041 in the first daisy chain is reached. M The USID has been configured.

[0079] Closing the switch 9180 in the slave device 9140 extends the second daisy chain to the slave device 9141. The slave device 9141 then senses that the PID signal 910 is asserted, and the USID of the slave device 9141 is configured in response to the next address configuration command sent over the second multi-drop serial bus 916. When the USID of the slave device 9141 is written, the slave device closes its switch 9181 and may set a configuration flag indicating that its USID has been configured. Subsequent address configuration commands are ignored by the slave device 9141 based on the setting of the configuration flag or the operation of the switch 9181. Address configuration continues until the last slave device 9141 in the first daisy chain is reached. M The USID has been configured.

[0080] Address configuration for the two multi-drop serial buses 906, 916 may begin at different times, may proceed at different rates, and / or may involve different numbers of slave devices 9040-904 M or 9140-914 N When performing address configuration for any of the multi-drop serial buses 906, 916, the shared PID signal 910 may be asserted. M or 9140-914 N The address configuration mode is entered in response to a broadcast command, thereby allowing the RFFE host device 902 to independently operate the multi-drop serial buses 906, 916. In one example, the PID signal 910 is asserted when it is in a high signaling state and de-asserted when it is in a low signaling state, wherein the high signaling state can be identified by a higher voltage level than the low signaling state. In another example, the PID signal 910 is asserted when it is in a low signaling state and de-asserted when it is in a high signaling state, wherein the low signaling state can be identified by a lower voltage level than the high signaling state.

[0081] Figure 10 Illustrated is a system 1000 in which an RFFE host device 1002 is the designated or configured BoM for a multi-drop serial bus that supports two-wire slave devices 10040-1004 operating independently and according to the RFFE protocol. N and single-wire slave devices 10140-1014 N In one example, the RFFE host device 1002 may correspond to Figure 5 The illustrated RFFE host device 502. Two-wire slave devices 10040-1004 N and single-wire slave devices 10140-1014 N Can be configured concurrently or at different times.

[0082] The RFFE host device 1002 is configured to drive the programming enable signal (PID signal 1010) through an I / O pin. N or single-line slave devices 10140-1014 N During dynamic address configuration of the RFFE master device 1002, the PID signal 1010 is asserted by the RFFE master device 1002. N and single-wire slave devices 10140-1014 NDuring concurrent dynamic address configuration of the RFFE host device 1002, the PID signal 1010 may be asserted by the RFFE host device 1002. The RFFE host device 1002 initiates a two-wire initial broadcast command to the two-wire slave devices 10040-1004 via the multi-drop serial bus 1006 using SDATA 1012a and SCLK 1012b. N The RFFE host device 1002 initiates a single-wire initial broadcast command to the single-wire slave devices 10040-1004 by sending the single-wire initial broadcast command over the multi-drop serial bus 1006 using SDATA 1012a while suppressing SCLK 1012b. N In some implementations, the single-wire broadcast command and the dual-wire broadcast command can be distinguished by the duration of the SSC timing. When SCLK 1012b is inhibited, the dual-wire slave devices 10040-1004 N Ignore single-line sends.

[0083] By protocol, all slave devices 10040-1004 M 、10140-1014 N According to one aspect of the present disclosure, when a two-wire initial broadcast command has not yet been sent over the multi-drop serial bus 1006, the PID signal 1010 is sent by the two-wire slave devices 10040-1004 M Ignored, and when a single-wire initial broadcast command has not been sent over the multi-drop serial bus 1006, the PID signal 1010 is used by the single-wire slave devices 10140-1014 N For the purpose of this description, an example will be described in which a single-wire initial broadcast command and a two-wire initial broadcast command have been sent over the multi-drop serial bus 1006 to initiate address configuration.

[0084] According to one aspect of the present disclosure, the initial broadcast command causes the corresponding slave devices 10040-1004 M and 10140-1014 N Each of the switches 10080-1008 is opened. M 、10180-1018 N and enters the device address configuration mode of operation. In some examples, each slave device 10040-1004 M and 10140-1014 N A flag may be set to indicate that device address configuration is in progress. The RFFE host device 1002 may configure the two-wire slave devices 10040-1004 by sending a series of two-wire address configuration commands over the multi-drop serial bus 1006. MThe RFFE host device 1002 can configure the single-wire slave devices 10140-1014 by sending a series of single-wire address configuration commands via the multi-drop serial bus 1006. N USID.

[0085] Each two-wire address configuration command sent via the multi-drop serial bus 1006 is sent to the two-wire slave devices 10040-1004 M Each single-wire address configuration command sent via the multi-drop serial bus 1006 is a broadcast command that generates a response in one of the single-wire slave devices 10140-1014. N In some implementations, the RFFE host device 1002 communicates with the slave devices 10040-1004 M or 10140-1014 N The USIDs are sent in address configuration commands in an order corresponding to their positions in their respective daisy chains. In one example, a first two-wire address configuration command sent over multi-drop serial bus 1006 is configured with the USID of the first slave device 10040 in the first daisy chain. Slave device 10040 receives PID signal 1010 directly from RFFE host device 1002. The first two-wire address configuration command causes the USID to be written to a register in the first slave device 10040. In another example, a first single-wire address configuration command sent over multi-drop serial bus 1006 is configured with the USID of the first slave device 10140 in the second daisy chain. Slave device 10140 receives PID signal 1010 directly from RFFE host device 1002. The first two-wire address configuration command causes the USID to be written to a register in slave device 10040, and the first single-wire address configuration command sent over multi-drop serial bus 1006 causes the USID to be written to a register in slave device 10140.

[0086] Each slave device 10040-1004 M and 10140-1014 N is configured to respond to the next recognizable address configuration command sent via the multi-drop serial bus 1006 after detecting that the PID signal 1010 has been asserted. M 、10140-1014 N The assertion of the PID signal 1010 may be detected by sensing the state of the input I / O pins and may then respond to the next received address configuration command. M 、10140-1014 N By storing the provided USID and closing its daisy chain switches 10080-1008M 、10180-1018 N To respond to the recognized address configuration command. Subsequent address configuration commands are based on the setting of the configuration flag or the corresponding switches 10080-1008 M 、10180-1018 N The operation is ignored by the slave device 8040.

[0087] Closing switch 10080 in slave device 10040 extends the first daisy chain to slave device 10041. Slave device 10041 then senses that PID signal 1010 is asserted, and the USID of slave device 10041 is configured in response to the next two-wire address configuration command sent over multi-drop serial bus 1006. When the USID of slave device 10041 is written, the slave device closes its switch 10081 and may set a configuration flag indicating that its USID has been configured. Subsequent address configuration commands are ignored by slave device 10041 based on the setting of the configuration flag or the operation of switch 10081. Address configuration continues until the last slave device 10041 in the first daisy chain is reached. M The USID has been configured.

[0088] Closing switch 10180 in slave device 10140 extends the second daisy chain to slave device 10141. Slave device 10141 then senses that PID signal 1010 is asserted, and the USID of slave device 10141 is configured in response to the next single-wire address configuration command sent over the multi-drop serial bus 1006. When the USID of slave device 10141 is written, the slave device closes its switch 10181 and may set a configuration flag indicating that its USID has been configured. Subsequent address configuration commands are ignored by slave device 10141 based on the setting of the configuration flag or the operation of switch 10181. Address configuration continues until the last slave device 10141 in the first daisy chain is reached. M The USID has been configured.

[0089] For two-wire slave devices 10040-1004 N and single-wire slave devices 10140-1014 N The address configuration can be performed sequentially or can be interleaved. In one example, in a single-line slave device 10140-1014 N Before or after being configured, two-wire slave devices 10040-1004 N are configured so that there is no overlap of the address configuration process. In another example, the two-wire slave devices 10040-1004 N and single-wire slave devices 10140-1014 Nare configured concurrently, whereby some two-wire address configuration commands may be interleaved with some single-wire address configuration commands.

[0090] When targeting two-wire slave devices 10040-1004 N Or for single-line slave devices 10140-1014 N When performing address configuration, the shared PID signal 1010 may be asserted. In one example, the PID signal 1010 is asserted when it is in a high signaling state and de-asserted when it is in a low signaling state, wherein the high signaling state may be identified by a higher voltage level than the low signaling state. In another example, the PID signal 1010 is asserted when it is in a low signaling state and de-asserted when it is in a high signaling state, wherein the low signaling state may be identified by a lower voltage level than the high signaling state.

[0091] Figure 11 A system 1100 is illustrated in which a host device 1102 is a designated or configured BoM for different types of multi-drop serial buses 1104, 1106, 1108. The host device 1102 is a designated or configured BoM for two multi-drop serial buses 1106, 1108 that operate independently and according to the RFFE protocol and include support for two-wire slave devices 11160-1116 M and single-wire slave devices 11180-1118 N The host device 1102 is also the designated bus master of the multi-drop serial bus 1104 which operates according to the SPI protocol.

[0092] Supports two-wire slave devices 11160-1116 M and single-wire slave devices 11180-1118 N The multi-drop serial bus 1108 corresponds to Figure 10 The illustrated multi-drop serial bus 1006 is configured to connect to two-wire slave devices 11160-1116. M and single-wire slave devices 11180-1118 N The address configuration can follow the Figure 10 The process described. Figure 9 Consistent with the described address configuration process, a master device can communicate with two-wire slave devices 11140-1114 coupled to the multi-drop serial bus 1108. L and single-wire slave devices 11160-1116 M Configure two-wire slave devices 11180-1118 concurrently or independently N .

[0093] Figures 8 to 10The process described in Configuring a USID Address on a Multi-drop Serial Bus can be applied to SPI peripheral devices 11120-1112 coupled to the multi-drop serial bus 1104. K That is, the daisy-chained PID signal 1110 can be used with the SPI broadcast command sent over the multi-drop serial bus 1104 to facilitate the configuration of the SPI peripheral devices 11120-1112. K The SPIPHY circuitry in the host device 1102 does not provide a slave select signal to control communications, but instead relies on using a USID configured according to certain aspects of the present disclosure. The host device 1102 uses a single I / O pin to provide the PID signal 1110, and the SPI peripheral devices 11120-1112 K This can be achieved using an input I / O pin that receives the PID signal 1110 and an output I / O pin that forwards the PID signal 1110. The input I / O pin and the output I / O pin are connected by switches that operate according to certain aspects of the present disclosure (e.g., see Figure 8 ) to couple. In the case of two-wire slave devices 11140-1114 coupled to the RFFE multi-drop serial bus 1106 or 1108 L 、11160-1116 M and single-wire slave devices 11180-1118 N and SPI peripheral devices 11120-1112 coupled to the multi-drop serial bus 1104 K During configuration, the same PID signal 1110 is used.

[0094] In some subsystems, existing architectural features may be adapted to support dynamic address configuration according to certain aspects of the present disclosure. In one example, a power management integrated circuit (PMIC) may be used to manage power within a system having multiple functional elements provided by various IC devices powered using multiple power domains. The PMIC may be coupled to the SoC using a high-speed serial bus operating according to the SPMI protocol. In more complex systems, multiple PMICs may be used to manage a power grid that supports some combination of the SoC, modem, application processor, display subsystem, camera subsystem, etc. Multiple instances of the same type of PMIC may be deployed within a system, with each PMIC or a small number of PMICs coupled via one of several SPMI interfaces. Fault indications may be communicated in certain conventional PMICs using a fault indication signal daisy-chained between the PMICs. According to certain aspects of the present disclosure, the PMIC may be adapted to support dynamic address configuration using a common SPMI bus and a modified fault indication daisy chain.

[0095] Figure 12An example of a system 1200 is illustrated, including a SoC 1202 and multiple PMICs 12040, 12041, 12042, 12043, 12044. For clarity, other SoCs, modems, application processors, subsystems, and peripherals coupled to or managed by the PMICs 12040, 12041, 12042, 12043, 12044 are omitted from the diagram. The PMICs 12040, 12041, 12042, 12043, 12044 can manage power distribution, manage budgets, and monitor power usage using multiple instances of the same type of PMIC. The PMICs 12040, 12041, 12042, 12043, 12044 can be communicatively coupled via a high-speed serial bus 1210. In the illustrated example, the high-speed serial bus 1210 is implemented according to the SPMI protocol defined by the MIPI Alliance. The SPMI protocol may be optimized for real-time control of one or more devices including PMICs 12040 , 12041 , 12042 , 12043 , and 12044 .

[0096] The high-speed serial bus 1210 can additionally couple the SoC 1202 and other devices and / or subsystems to the PMICs 12040, 12041, 12042, 12043, and 12044. The SoC 1202 is coupled to the high-speed serial bus 1210 via an SPMI physical layer circuit (SPMIPHY 1218), and the PMICs 12040, 12041, 12042, 12043, and 12044 are coupled to the high-speed serial bus 1210 via corresponding SPMI physical layer circuits (SPMIPHYs 12080-12184). In some examples, the SPMIPHY 1208 in the SoC 1202 can be configured to operate as a BoM for the high-speed serial bus 1210. The SoC 1202 operating as a BoM can be configured to manage and control operations on the high-speed serial bus 1210. The combination of the high-speed serial bus 1210 and the SPMI protocol enables the high-speed serial bus 1210 to operate as a shared bus that provides high-speed, low-latency connections for various devices or device types, and enables data transmission to be managed according to priorities assigned to different traffic classes.

[0097] The fault signaling circuitry in each of the PMICs 12040, 12041, 12042, 12043, 12044 may be modified by adding switches 12140, 12141, 12142, 12143, 12144 that may be used to interrupt the fault indication signal 1212 that is daisy-chained between the PMICs 12040, 12041, 12042, 12043, 12044. In normal operation, the switches 12140, 12141, 12142, 12143, 12144 are closed, and the fault indication signal 1212 may flow unimpeded between the PMICs 12040, 12041, 12042, 12043, 12044. The fault indication signal 1212 is used by all PMICs 12040, 12041, 12042, 12043, 12044 and is used to indicate the occurrence of a fault condition in one PMIC 12040, 12041, 12042, 12043, or 12044 to all other PMICs 12040, 12041, 12042, 12043, and / or 12044. The fault indication signal 1212 is not used during system configuration.

[0098] During system configuration, switches 12140, 12141, 12142, 12143, and 12144 are opened to facilitate the address configuration process according to certain aspects of the present disclosure. The controller 1206 in the SoC 1202 is configured to assert a fault indication signal 1212 at the input to the first PMIC 12040 during address configuration. Fault indication signal 1212 can be asserted when the controller activates the output of the line driver, which is in high impedance during normal operation. Fault indication signal 1212 serves as a programming enable signal during dynamic address configuration. The controller 1206 initiates dynamic address configuration by sending an initial broadcast command via the high-speed serial bus 1210. All PMICs 12040-12044 coupled to the high-speed serial bus 1210 respond to the initial broadcast command through the protocol without referencing their internal USIDs. The initial SPMI broadcast command is a write command that does not require a communication response from any PMIC 12040-12044. Two or more of the PMICs 12040 - 12044 programmed with the same USID may respond to the initial broadcast command without interfering with each other.

[0099] According to one aspect of the present disclosure, an initial broadcast command causes each of the PMICs 12040-12044 to open its corresponding switch 12140-12144 and enter a device address configuration mode of operation. In some examples, each PMIC 12040-12044 may set a flag to indicate that device address configuration is in progress. The controller 1206 may configure the USIDs of the PMICs 12040-12044 by sending a series of address configuration commands. Each address configuration command is a broadcast command that generates a response in one of the PMICs 12040-12044. In some implementations, the controller 1206 sends the USIDs in the address configuration commands in an order corresponding to the position of the PMICs 12040-12044 in the daisy chain. For example, the first address configuration command is configured with the USID of the first PMIC 12040 in the daisy chain, which received the fault indication signal 1212 directly from the SoC 1202. The first address configuration command causes the USID to be written to a register in the first PMIC 12040 in the daisy chain.

[0100] Each PMIC 12040-12044 is configured to respond to the next address configuration command sent via high-speed serial bus 1210 after detecting assertion of fault indication signal 1212. PMICs 12040-12044 can detect assertion of fault indication signal 1212 by sensing the state of their fault inputs. After all switches 12140-12144 have been opened, fault indication signal 1212 initially drives only the fault input of PMIC 12040. The USID of PMIC 12040 is configured in response to the first address configuration command sent. When writing to the USID of PMIC 12040, the PMIC closes its switch 12140 and may set a configuration flag indicating that its USID has been configured. Subsequent address configuration commands are ignored by PMIC 12040 based on the setting of the configuration flag. Closing switch 12140 in PMIC 12040 extends the daisy chain to the next device, which is PMIC 12041. PMIC 12041 then senses that fault indication signal 1212 is asserted, and the USID of PMIC 12041 is configured in response to the next sent address configuration command. When writing to the USID of PMIC 12041, the PMIC closes its switch 12141 and may set a configuration flag indicating that its USID has been configured. Subsequent address configuration commands may be ignored by PMIC 12041 based on the setting of the configuration flag or the operation of switch 12141. In some implementations, subsequent commands related to address configuration may also be ignored because the address field in the ignored command does not match the USID of one or more of PMICs 12040-12044. Address configuration continues until the USID of the last PMIC 12044 in the daisy chain has been configured.

[0101] In some implementations, the controller 1206 in the SoC 1202 can cause a broadcast command to be sent over the high-speed serial bus 1210 to cause the PMICs 12040-12044 to terminate or exit the device address configuration mode of operation. In some implementations, the SoC 1202 can interrogate the PMICs 12040-12044 after configuring their USIDs. The SoC 1202 can send a read command to cause the PMICs 12040-12044 to read back their newly configured USIDs. In some instances, only the most recently configured PMIC 12040-12044 processes the read command during the address configuration mode of operation, and the SoC 1202 can subsequently send a write command to cause the most recently configured PMIC 12040-12044 to close its switch 12140-12144 and / or set a configuration flag indicating that its USID has been configured.

[0102] When the USID has been configured in all PMICs 12040-12044, all 12140-12144 are expected to be closed, and the fault indication signal 1212 can be used for fault indication purposes. According to one aspect of the present disclosure, the controller 1206 can transmit a terminate broadcast command that causes each of the PMICs 12040-12044 to close its corresponding switch 12140-12144 and exit the device address configuration operating mode.

[0103] According to certain aspects of the present disclosure, provision may be made for modifying the disclosed address configuration process when a fault occurs in one or more slave devices (or PMICs) that would otherwise prevent USID configuration for all devices. Figure 8 In the illustrated example, for example, the failure of slave device 8041 to participate in the address configuration process may prevent the configuration of the USID of slave device 8041-8041. In some specific implementations, when this type of failure occurs, address configuration can be performed by using a second daisy chain or by performing the address configuration in the reverse order. In the example where slave device 8041 does not participate, address configuration can be completed by resuming the process using the configuration of slave device 8041. The reverse process may require that the slave device be configured with a bidirectional driver and switch.

[0104] Examples of Processing Circuits and Methods

[0105] Figure 13 1300 is a diagram illustrating an example of a hardware implementation of apparatus 1300. In some examples, apparatus 1300 may perform one or more functions disclosed herein. According to various aspects of the present disclosure, processing circuitry 1302 may be used to implement an element, any portion of an element, or any combination of elements as disclosed herein. Processing circuitry 1302 may include one or more processors 1304 controlled by some combination of hardware and software modules. Examples of processors 1304 include microprocessors, microcontrollers, digital signal processors (DSPs), SoCs, ASICs, field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic components, discrete hardware circuits, and other suitable hardware configured to perform the various functionalities described throughout this disclosure. One or more processors 1304 may include a dedicated processor that performs a specific function and may be configured, enhanced, or controlled by one of software modules 1316. One or more processors 1304 may be configured by a combination of software modules 1316 loaded during initialization, and may further be configured by loading or unloading one or more software modules 1316 during operation.

[0106] In the illustrated example, processing circuit 1302 may be implemented using a bus architecture, generally represented by bus 1310. Bus 1310 may include any number of interconnecting buses and bridges, depending on the specific application of processing circuit 1302 and the overall design constraints. Bus 1310 links together various circuits, including one or more processors 1304 and storage 1306. Storage 1306 may include memory devices and mass storage devices and may be referred to herein as computer-readable media and / or processor-readable media. Bus 1310 may also link various other circuits, such as timing sources, timers, peripherals, voltage regulators, and power management circuits. Bus interface 1308 may provide an interface between bus 1310 and one or more transceivers 1312a, 1312b. A transceiver 1312a, 1312b may be provided for each networking technology supported by the processing circuit. In some instances, multiple networking technologies may share some or all of the circuitry or processing modules found in transceivers 1312a, 1312b. Each transceiver 1312a, 1312b provides a means for communicating with various other devices via a transmission medium. In one example, transceiver 1312a can be used to couple device 1300 to a multi-line bus. In another example, transceiver 1312b can be used to connect device 1300 to a radio access network. Depending on the nature of device 1300, a user interface 1318 (e.g., a keypad, display, speaker, microphone, joystick) may also be provided and communicatively coupled to bus 1310 directly or via bus interface 1308.

[0107] The processor 1304 may be responsible for managing the bus 1310 and for general processing, which may include executing software stored in a computer-readable medium (which may include a storage device 1306). In this regard, the processing circuit 1302 (including the processor 1304) may be used to implement any of the methods, functions, and techniques disclosed herein. The storage device 1306 may be used to store data that is manipulated by the processor 1304 when executing the software, and the software may be configured to implement any of the methods disclosed herein.

[0108] One or more processors 1304 in the processing circuit 1302 can execute software. Software should be interpreted broadly to mean instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, algorithms, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside in computer-readable form in the storage device 1306 or in an external computer-readable medium. The external computer-readable medium and / or the storage device 1306 may include non-transitory computer-readable media. For example, non-transitory computer-readable media include magnetic storage devices (e.g., hard disks, floppy disks, magnetic strips), optical disks (e.g., compact disks (CDs) or digital versatile disks (DVDs)), smart cards, flash memory devices (e.g., "flash drives," cards, sticks, or key drives), RAM, ROM, programmable read-only memory (PROM), erasable PROM (EPROM, including EEPROM), registers, removable disks, and any other suitable medium for storing software and / or instructions that can be accessed and read by a computer. Computer-readable media and / or storage 1306 may also include, for example, carrier waves, transmission lines, and any other suitable medium for transmitting software and / or instructions that can be accessed and read by a computer. Computer-readable media and / or storage 1306 may reside in processing circuit 1302, in processor 1304, external to processing circuit 1302, or distributed across multiple entities including processing circuit 1302. Computer-readable media and / or storage 1306 may be embodied in a computer program product. For example, a computer program product may include a computer-readable medium in packaging material. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure depending on the particular application and the overall design constraints imposed on the overall system.

[0109] Storage 1306 may maintain software maintained and / or organized in loadable code segments, modules, applications, programs, and the like, which may be referred to herein as software modules 1316. Each of software modules 1316 may include instructions and data that, when installed or loaded into processing circuitry 1302 and executed by one or more processors 1304, facilitates a runtime image 1314 that controls the operation of one or more processors 1304. Certain instructions, when executed, may cause processing circuitry 1302 to perform functions according to certain methods, algorithms, and processes described herein.

[0110] Some of the software modules 1316 may be loaded during initialization of the processing circuit 1302, and these software modules 1316 may configure the processing circuit 1302 to perform the various functions disclosed herein. For example, some of the software modules 1316 may configure the internal devices and / or logic circuits 1322 of the processor 1304 and may manage access to external devices such as the transceivers 1312a, 1312b, the bus interface 1308, the user interface 1318, timers, a math coprocessor, and the like. The software modules 1316 may include a control program and / or an operating system that interacts with an interrupt handler and device drivers and controls access to various resources provided by the processing circuit 1302. Resources may include memory, processing time, access to the transceivers 1312a, 1312b, the user interface 1318, and the like.

[0111] The one or more processors 1304 of the processing circuit 1302 can be multifunctional, whereby some of the software modules 1316 are loaded and configured to perform different functions or different instances of the same function. The one or more processors 1304 can also be adapted to manage background tasks initiated in response to inputs from, for example, the user interface 1318, the transceivers 1312a, 1312b, and device drivers. To support the execution of multiple functions, the one or more processors 1304 can be configured to provide a multitasking environment, whereby each of the multiple functions is implemented as a set of tasks serviced by the one or more processors 1304 as needed or desired. In one example, the multitasking environment can be implemented using a time-sharing program 1320 that transfers control of the processors 1304 between different tasks, whereby each task returns control of the one or more processors 1304 to the time-sharing program 1320 upon completion of any outstanding operations and / or in response to inputs such as interrupts. When a task has control of the one or more processors 1304, the processing circuit is effectively dedicated to the purpose addressed by the function associated with the control task. The time sharing program 1320 may include an operating system, a main loop that transfers control on a cycle basis, functionality that allocates control of one or more processors 1304 based on functional prioritization, and / or an interrupt-driven main loop that responds to external events by providing control of one or more processors 1304 to processing functionality.

[0112] Figure 14Flowchart 1400 is a method that can be performed at a slave device coupled to a multi-drop serial bus when the slave device participates in address allocation by iteratively communicating with a master device. The slave device may include a controller and a switch. At block 1402, the controller may receive a first broadcast command via the multi-drop serial bus. At block 1404, the controller may decouple a daisy-chain input of the slave device from a daisy-chain output of the slave device. At block 1406, the controller may receive a second broadcast command via the multi-drop serial bus. At block 1408, the controller may determine whether a signal received via the daisy-chain input is active. If the signal received via the daisy-chain input is inactive, then at block 1410, the controller may ignore the second broadcast command and may wait for additional broadcast commands until the daisy-chain input is active. If the signal received via the daisy-chain input is active, then at block 1412, the controller may respond to the second broadcast command. Responding to the second broadcast command may include configuring a unique device identifier of the slave device using the address provided in the second broadcast command and coupling the daisy-chain input of the slave device to the daisy-chain output of the slave device. At block 1414, the controller may ignore subsequent broadcast commands after responding to the second broadcast command.

[0113] In some examples, decoupling the daisy-chain input of the slave device from the daisy-chain output of the slave device includes opening a switch coupling the daisy-chain input of the slave device to the daisy-chain output of the slave device. Coupling the daisy-chain input of the slave device to the daisy-chain output of the slave device may include closing a switch in the slave device.

[0114] In some examples, the multi-point serial bus operates according to the RFFE protocol defined by the MIPI Alliance.The first broadcast command and the second broadcast command can be received using a single wire of the multi-point serial bus.

[0115] In some examples, the multi-drop serial bus operates according to the SPI protocol defined by the MIPI Alliance.

[0116] In some implementations, the multi-point serial bus operates according to the SPMI protocol defined by the MIPI Alliance. In some implementations, the slave device is a PMIC. The daisy-chain input of the slave device and the daisy-chain output of the slave device can be configured to communicate or respond to a fault indication signal generated by one of the plurality of PMICs coupled to the multi-point serial bus.

[0117] In some implementations, the controller may set a flag indicating that the unique device identifier is configured after responding to the second broadcast command. Each slave device may be further configured to ignore subsequent address configuration commands when the flag is set.

[0118] Figure 15 1500 is a diagram illustrating a simplified example of a hardware implementation of an apparatus 1500 employing a processing circuit 1502. The processing circuit typically has a controller or processor 1516, which may include one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines. Processing circuit 1502 may be implemented using a bus architecture, generally represented by bus 1510. Bus 1510 may include any number of interconnecting buses and bridges, depending on the specific application of processing circuit 1502 and the overall design constraints. Bus 1510 links together various circuits, including one or more processors and / or hardware modules, represented by controller or processor 1516, modules or circuits 1504, 1506, and 1508, and processor-readable storage media 1518. One or more physical layer circuits and / or modules 1514 may be provided to support communications via communication links implemented using multi-wire bus 1512, communications via antenna or antenna array 1522 (e.g., to a radio access network), and the like. The bus 1510 may also link various other circuits such as timing sources, peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further.

[0119] Processor 1516 is responsible for general processing, including executing software, code, and / or instructions stored on processor-readable storage medium 1518. The processor-readable storage medium may include non-transitory storage media. When executed by processor 1516, the software causes processing circuit 1502 to perform the various functions described above for any particular device. The processor-readable storage medium may be used to store data manipulated by processor 1516 when executing the software. Processing circuit 1502 also includes at least one of modules 1504, 1506, and 1508. Modules 1504, 1506, and 1508 may be software modules running on processor 1516, resident / stored on processor-readable storage medium 1518, one or more hardware modules coupled to processor 1516, or some combination thereof. Modules 1504, 1506, and 1508 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0120] In one configuration, the device 1500 includes: a module and / or circuit 1504 adapted to manage a daisy-chain signal path through the device 1500; a module and / or circuit 1506 adapted to receive, decode and selectively respond to commands received over a multi-point serial bus; and a module and / or circuit 1508 adapted to manage and configure a USID to be used by the device 1500 when communicating over the multi-point serial bus.

[0121] In one example, apparatus 1500 may be configured to operate as a slave device, the slave device including physical layer circuitry and / or modules 1514 implementing interface circuitry adapted to couple the slave device to a multi-point serial bus. The slave device may have a controller adapted or programmed to: receive a first broadcast command via the multi-point serial bus; decouple a daisy-chain input of the slave device from a daisy-chain output of the slave device; receive a second broadcast command via the multi-point serial bus; and respond to the second broadcast command when a signal received via the daisy-chain input is active. The controller may be further adapted or programmed to respond to the second broadcast command by configuring a unique device identifier of the slave device using an address provided in the second broadcast command and coupling the daisy-chain input of the slave device to the daisy-chain output of the slave device. The controller may be further adapted or programmed to ignore subsequent broadcast commands after responding to the second broadcast command.

[0122] In some examples, the controller is further configured to, when the daisy-chain input of the slave device is decoupled from the daisy-chain output of the slave device, open a switch coupling the daisy-chain input of the slave device to the daisy-chain output of the slave device. The controller may be further adapted or programmed to, when the daisy-chain input of the slave device is coupled to the daisy-chain output of the slave device, close a switch coupling the daisy-chain input of the slave device to the daisy-chain output of the slave device.

[0123] In some examples, the multi-drop serial bus may operate according to an RFFE protocol, an SPMI protocol, or an SPI protocol. The first slave device may be implemented in a PMIC. The controller may be further configured to: configure the daisy-chain input of the apparatus and the daisy-chain output of the first slave device to communicate or respond to a fault indication signal generated by one of a plurality of PMICs coupled to the first multi-drop serial bus.

[0124] The processor-readable storage medium 1518 may include a transient or non-transitory storage device configured to store code, instructions, and / or parameters for implementing one or more methods or processes disclosed herein. The processor-readable storage medium 1518 may include code for performing the following operations: receiving a first broadcast command via a multi-point serial bus; decoupling a daisy-chain input of the slave device from a daisy-chain output of the slave device; receiving a second broadcast command via the multi-point serial bus; responding to the second broadcast command when a signal received via the daisy-chain input is active; ignoring the second broadcast command when the signal received via the daisy-chain input is inactive; and ignoring subsequent broadcast commands after responding to the second broadcast command. Responding to the second broadcast command may include configuring a unique device identifier of the slave device using an address provided in the second broadcast command, and coupling the daisy-chain input of the slave device to the daisy-chain output of the slave device.

[0125] In some examples, decoupling the daisy-chain input of the slave device from the daisy-chain output of the slave device includes opening a switch coupling the daisy-chain input of the slave device to the daisy-chain output of the slave device. Coupling the daisy-chain input of the slave device to the daisy-chain output of the slave device may include closing a switch in the slave device.

[0126] In some implementations, the first broadcast command and the second broadcast command can be received using a single conductor of the multi-drop serial bus.

[0127] In some examples, the multi-drop serial bus may operate according to an RFFE protocol, an SPMI protocol, or an SPI protocol. The slave device may be a PMIC, and the processor-readable storage medium 1518 may include code for configuring the daisy-chain input of the slave device and the daisy-chain output of the slave device to communicate or respond to a fault indication signal generated by one of a plurality of PMICs coupled to the multi-drop serial bus.

[0128] In some implementations, the processor-readable storage medium 1518 includes code for, after responding to the second broadcast command, setting a flag indicating that the unique device identifier is configured. The processor-readable storage medium 1518 may include code for, when the flag is set, ignoring the subsequent address configuration command.

[0129] Figure 161600 is a flow chart of a method that can be performed by a master device coupled to a multi-drop serial bus. The method can be used to assign device addresses by iteratively communicating with a plurality of slave devices coupled to the master device via the multi-drop serial bus. In some implementations, one or more single-wire slave devices and one or more two-wire slave devices can be coupled to the multi-drop serial bus.

[0130] At block 1602, the host device may send a first broadcast command via a first multi-point serial bus. The first broadcast command may be configured to decouple a daisy-chain input of a first slave device from a daisy-chain output of the first slave device. For each of a plurality of slave devices coupled to the first multi-point serial bus, the host device may decouple the daisy-chain input of each slave device from the daisy-chain output of each slave device. The daisy-chain input of each slave device may be coupled to a daisy-chain output of another slave device.

[0131] At block 1604, the master device may activate a programming enable signal coupled to the daisy-chain input of the first slave device.

[0132] At block 1606, the host device may broadcast a first sequence of address configuration commands via the first multi-drop serial bus. Each slave device may be configured to respond to a first address configuration command received after detecting an activated programming enable signal at its daisy chain input. Each slave device may be further configured to ignore subsequent address configuration commands. Each address configuration command is configured to cause the responding slave device to write or otherwise store a unique device identifier of the responding slave device. The responding slave device may also couple its daisy chain input to its daisy chain output.

[0133] In some examples, the first broadcast command is configured to cause the first slave device to open a switch coupling the daisy-chain input of the first slave device to the daisy-chain output of the first slave device. The responding slave device may couple its daisy-chain input to its daisy-chain output by closing the switch in response to the address configuration command.

[0134] In some examples, the host device may send a second broadcast command via a second multi-point serial bus. The second broadcast command may be configured to decouple a daisy chain input of a second slave device from a daisy chain output of the second slave device, and for each of a plurality of slave devices coupled to the second multi-point serial bus, decouple the daisy chain input of each slave device from the daisy chain output. The daisy chain input of each slave device is coupled to a daisy chain output of another slave device. The host device may broadcast a second sequence of address configuration commands via the second multi-point serial bus. Each slave device may be configured to respond to a first address configuration command received after detecting an activated programming enable signal at its daisy chain input. Each slave device may be further configured to ignore subsequent address configuration commands.

[0135] In some examples, the host device may use one conductor of the first multi-point serial bus to send a single-wire broadcast command. In contrast, the first broadcast command is sent using two conductors of the first multi-point serial bus. The single-wire broadcast command may be configured to decouple a daisy-chain input of a first single-wire slave device from a daisy-chain output of the first single-wire slave device, and for each of a plurality of single-wire slave devices coupled to the first multi-point serial bus, decouple the daisy-chain input of the single-wire slave device from the daisy-chain output of the single-wire slave device. The daisy-chain input of each single-wire slave device may be coupled to a daisy-chain output of another single-wire slave device. The host device may broadcast a sequence of single-wire address configuration commands over the first multi-point serial bus. Each single-wire slave device may be configured to respond to a first address single-wire configuration command received after detecting an activated programming enable signal at its daisy-chain input. Each single-wire slave device may be further configured to ignore subsequent single-wire address configuration commands.

[0136] The multi-point serial bus may operate according to the RFFE protocol, the SPMI protocol, the SPI protocol, or other proprietary or standards-based protocols.

[0137] In one example, the first slave device is a PMIC, and the host device may cause the PMIC to configure a daisy-chain input of the first PMIC and a daisy-chain output of the first PMIC to communicate or respond to a fault indication signal generated by one of the plurality of PMICs coupled to the first multi-drop serial bus.

[0138] In some implementations, each slave device is configured to set a flag indicating that its unique device identifier has been configured after receiving the first address configuration command after detecting an activated programming enable signal at its daisy-chain input. Each slave device can be further configured to ignore subsequent address configuration commands when the flag is set.

[0139] Figure 17 1702 is a diagram illustrating a simplified example of a hardware implementation of an apparatus 1700 employing a processing circuit 1702. The processing circuit typically has a controller or processor 1716, which may include one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines. Processing circuit 1702 may be implemented using a bus architecture, generally represented by bus 1710. Bus 1710 may include any number of interconnecting buses and bridges, depending on the specific application of processing circuit 1702 and the overall design constraints. Bus 1710 links together various circuits, including one or more processors and / or hardware modules, represented by controller or processor 1716, modules or circuits 1704, 1706, and 1708, and processor-readable storage media 1718. One or more physical layer circuits and / or modules 1714 may be provided to support communications via communication links implemented using multi-wire bus 1712, communications via antenna or antenna array 1722 (e.g., to a radio access network), and the like. The bus 1710 may also link various other circuits such as timing sources, peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further.

[0140] Processor 1716 is responsible for general processing, including executing software, code, and / or instructions stored on processor-readable storage medium 1718. The processor-readable storage medium may include non-transitory storage media. When executed by processor 1716, the software causes processing circuit 1702 to perform the various functions described above for any particular device. The processor-readable storage medium may be used to store data manipulated by processor 1716 when executing the software. Processing circuit 1702 further includes at least one of modules 1704, 1706, and 1708. Modules 1704, 1706, and 1708 may be software modules running on processor 1716, resident / stored on processor-readable storage medium 1718, one or more hardware modules coupled to processor 1716, or some combination thereof. Modules 1704, 1706, and 1708 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0141] In one configuration, the apparatus 1700 includes modules and / or circuitry 1704 adapted to manage an operating mode of a daisy-chain signal path through slave devices. The apparatus 1700 may include modules and / or circuitry 1708 adapted to manage addresses associated with slave devices, and modules and / or circuitry 1708 adapted to generate broadcast commands for implementing and controlling an address management process according to certain aspects of the present disclosure.

[0142] In one example, the apparatus 1700 includes a physical layer circuit and / or module 1714 implementing an interface circuit adapted to couple the apparatus 1700 to a serial bus. The apparatus 1700 may include a controller. A processor 1716 may be configured to send a first broadcast command via a first multi-point serial bus, the first broadcast command being configured to decouple a daisy-chain input of a first slave device from a daisy-chain output of the first slave device. The processor 1716 may be configured to cause each of a plurality of slave devices coupled to the first multi-point serial bus to decouple the daisy-chain input of each slave device from the daisy-chain output of each slave device. The daisy-chain input of each slave device may be coupled to a daisy-chain output of another slave device. The processor 1716 may be configured to activate a programming enable signal coupled to the daisy-chain input of the first slave device and broadcast a first sequence of address configuration commands via the first multi-point serial bus. Each slave device is configured to respond to a first address configuration command received after detecting an activated programming enable signal at its daisy-chain input. Each slave device may be further configured to ignore subsequent address configuration commands. Each address configuration command may be configured to: configure a unique device identifier in the slave device responding to each address configuration command, and couple the daisy-chain input of the slave device responding to each address configuration command to the daisy-chain output of the slave device responding to each address configuration command.

[0143] In some specific implementations, the processor 1716 may be further configured to send a second broadcast command via the second multi-point serial bus, the second broadcast command being configured to: decouple the daisy-chain input of the second slave device from the daisy-chain output of the second slave device, and, for each of the plurality of slave devices coupled to the second multi-point serial bus, decouple the daisy-chain input of each slave device from the daisy-chain output of each slave device. The daisy-chain input of each slave device may be coupled to the daisy-chain output of another slave device. The processor 1716 may be configured to broadcast a second sequence of address configuration commands via the second multi-point serial bus. Each slave device may be configured to respond to the first address configuration command received after detecting an activated programming enable signal at its daisy-chain input. Each slave device may be further configured to ignore subsequent address configuration commands.

[0144] In some embodiments, processor 1716 may be configured to transmit a single-wire broadcast command using one conductor of the first multi-point serial bus, while the first broadcast command is transmitted using two conductors of the first multi-point serial bus. The single-wire broadcast command may be configured to decouple a daisy-chain input of a first single-wire slave device from a daisy-chain output of the first single-wire slave device, and, for each of a plurality of single-wire slave devices coupled to the first multi-point serial bus, decouple the daisy-chain input of each single-wire slave device from the daisy-chain output of each single-wire slave device. The daisy-chain input of each single-wire slave device may be coupled to the daisy-chain output of another single-wire slave device. Processor 1716 may be configured to broadcast a sequence of single-wire address configuration commands via the first multi-point serial bus. Each single-wire slave device may be configured to respond to a first address single-wire configuration command received after detecting an activated programming enable signal at its daisy-chain input. Each single-wire slave device may be further configured to ignore subsequent single-wire address configuration commands.

[0145] The multi-point serial bus may operate according to the RFFE protocol, the SPMI protocol, the SPI protocol, or other proprietary or standards-based protocols.

[0146] In some implementations, the first slave device is embodied in a PMIC. The processor 1716 can be configured to configure the daisy-chain input of the first slave device and the daisy-chain output of the first slave device to communicate or respond to a fault indication signal generated by one of the plurality of PMICs coupled to the first multi-drop serial bus.

[0147] The processor-readable storage medium 1718 may include a transient or non-transitory storage device configured to store code, instructions, and / or parameters for implementing one or more methods or processes disclosed herein. The processor-readable storage medium 1718 may include code for performing the following operations: sending a first broadcast command over a first multi-point serial bus, the first broadcast command configured to: decouple a daisy-chain input of a first slave device from a daisy-chain output of the first slave device, and, for each of a plurality of slave devices coupled to the first multi-point serial bus, decouple the daisy-chain input of each slave device from the daisy-chain output of each slave device, the daisy-chain input of each slave device being coupled to the daisy-chain output of another slave device. The processor-readable storage medium 1718 may include code for performing the following operations: activating a programming enable signal coupled to the daisy-chain input of the first slave device, and broadcasting a first sequence of address configuration commands over the first multi-point serial bus. Each slave device may be configured to respond to a first address configuration command received after detecting an activated programming enable signal at its daisy-chain input. Each slave device may be further configured to ignore subsequent address configuration commands. Each address configuration command may be configured to: configure a unique device identifier in the slave device responding to each address configuration command, and couple the daisy-chain input of the slave device responding to each address configuration command to the daisy-chain output of the slave device responding to each address configuration command.

[0148] In some examples, the first broadcast command is configured to cause the first slave device to open a switch coupling the daisy-chain input of the first slave device to the daisy-chain output of the first slave device. By closing the switch in the slave device that responds to the each address configuration command, the daisy-chain input of the slave device that responds to the each address configuration command is coupled to the daisy-chain output of the slave device that responds to the each address configuration command.

[0149] Processor-readable storage medium 1718 may include code for performing the following operations: sending a second broadcast command via a second multi-point serial bus. The second broadcast command may be configured to decouple a daisy-chain input of a second slave device from a daisy-chain output of the second slave device, and for each slave device in a plurality of slave devices coupled to the second multi-point serial bus, decouple the daisy-chain input of each slave device from the daisy-chain output of each slave device. The daisy-chain input of each slave device may be coupled to a daisy-chain output of another slave device. Processor-readable storage medium 1718 may include code for performing the following operations: broadcasting a second sequence of address configuration commands via the second multi-point serial bus. Each slave device may be configured to respond to a first address configuration command received after detecting an activated programming enable signal at its daisy-chain input. Each slave device may be further configured to ignore subsequent address configuration commands.

[0150] In some implementations, the processor-readable storage medium 1718 includes code for transmitting a single-wire broadcast command using one conductor of the first multi-point serial bus, wherein the first broadcast command is transmitted using two conductors of the first multi-point serial bus. The single-wire broadcast command can be configured to decouple a daisy-chain input of a first single-wire slave device from a daisy-chain output of the first single-wire slave device, and, for each of a plurality of single-wire slave devices coupled to the first multi-point serial bus, decouple the daisy-chain input of each single-wire slave device from the daisy-chain output of each single-wire slave device. The daisy-chain input of each single-wire slave device can be coupled to the daisy-chain output of another single-wire slave device. The processor-readable storage medium 1718 can include code for broadcasting a sequence of single-wire address configuration commands over the first multi-point serial bus. Each single-wire slave device can be configured to respond to the first address single-wire configuration command received after detecting an activated programming enable signal at its daisy-chain input. Each 1-wire slave device may be further configured to ignore subsequent 1-wire address configuration commands.

[0151] The first multi-point serial bus may operate according to the RFFE protocol, the SPMI protocol, the SPI protocol, or other proprietary or standards-based protocols.

[0152] In some implementations, the first slave device is embodied in a PMIC. The processor 1716 can be configured to configure the daisy-chain input of the first slave device and the daisy-chain output of the first slave device to communicate or respond to a fault indication signal generated by one of the plurality of PMICs coupled to the first multi-drop serial bus.

[0153] In some implementations, each slave device sets a flag indicating that its unique device identifier has been configured after receiving the first address configuration command after detecting an activated programming enable signal at its daisy-chain input. Each slave device can be further configured to ignore subsequent address configuration commands when the flag is set.

[0154] Some specific implementation examples are described in the following numbered clauses:

[0155] 1. A method for communicating data at a slave device, the method comprising: receiving a first broadcast command via a multi-point serial bus; decoupling a daisy-chain input of the slave device from a daisy-chain output of the slave device; receiving a second broadcast command via the multi-point serial bus; responding to the second broadcast command when a signal received via the daisy-chain input is active; ignoring the second broadcast command when the signal received via the daisy-chain input is in an inactive state; and ignoring subsequent broadcast commands after responding to the second broadcast command, wherein responding to the second broadcast command comprises configuring a unique device identifier of the slave device using an address provided in the second broadcast command, and coupling the daisy-chain input of the slave device to the daisy-chain output of the slave device.

[0156] 2. The method of clause 1, wherein decoupling the daisy-chain input of the slave device from the daisy-chain output of the slave device comprises opening a switch coupling the daisy-chain input of the slave device to the daisy-chain output of the slave device.

[0157] 3. The method of clause 1 or clause 2, wherein coupling the daisy-chain input of the slave device to the daisy-chain output of the slave device comprises closing a switch in the slave device.

[0158] 4. A method as described in any one of clauses 1 to 3, wherein the first broadcast command and the second broadcast command are received using a single conductor of the multi-point serial bus.

[0159] 5. A method according to any one of clauses 1 to 4, wherein the multi-drop serial bus is based on a mobile industry processor interface.

[0160] It operates based on the Radio Frequency Front-End (RFFE) protocol defined by the MIPI Alliance.

[0161] 6. A method according to any one of clauses 1 to 4, wherein the multi-drop serial bus is based on a mobile industry processor interface.

[0162] It operates based on the System Power Management Interface (SPMI) protocol defined by the MIPI Alliance.

[0163] 7. A method according to any one of clauses 1 to 4, wherein the multi-drop serial bus is based on a serial peripheral interface (SPI)

[0164] Protocol to operate.

[0165] 8. A method according to any one of clauses 1 to 7, wherein the slave device includes a power management integrated circuit (PMIC), and the method further comprises: configuring the daisy-chain input end of the slave device and the daisy-chain output end of the slave device to convey or respond to a fault indication signal generated by one of a plurality of PMICs coupled to the multi-point serial bus.

[0166] 9. A method as described in any one of clauses 1 to 8, further comprising: after responding to the second broadcast command, setting a flag indicating that the unique device identifier is configured.

[0167] 10. The method of clause 9, further comprising: ignoring the subsequent broadcast command when the flag is set.

[0168] 11. A slave device, comprising: an interface circuit adapted to couple the slave device to a multi-point serial bus; and a controller configured to: receive a first broadcast command via the multi-point serial bus; decouple a daisy-chain input of the slave device from a daisy-chain output of the slave device; receive a second broadcast command via the multi-point serial bus; when a signal received via the daisy-chain input is active, respond to the second broadcast command by configuring a unique device identifier of the slave device using an address provided in the second broadcast command, and coupling the daisy-chain input of the slave device to the daisy-chain output of the slave device; and ignoring subsequent broadcast commands after responding to the second broadcast command.

[0169] 12. A slave device as described in claim 11, wherein the controller is further configured to: when the daisy-chain input end of the slave device is decoupled from the daisy-chain output end of the slave device, disconnect the switch coupling the daisy-chain input end of the slave device with the daisy-chain output end of the slave device.

[0170] 13. A slave device according to claim 11 or 12, wherein the controller is further configured to: when the daisy chain input end of the slave device is coupled to the daisy chain output end of the slave device, close the switch coupling the daisy chain input end of the slave device with the daisy chain output end of the slave device.

[0171] 14. A slave device as described in any one of clauses 11 to 13, wherein the multi-point serial bus operates according to a Radio Frequency Front End (RFFE) protocol, a System Power Management Interface (SPMI) protocol or a Serial Peripheral Interface (SPI) protocol.

[0172] 15. A slave device as described in any one of clauses 11 to 14, wherein the slave device includes a power management integrated circuit (PMIC), and wherein the controller is further configured to: configure the daisy-chain input end of the slave device and the daisy-chain output end of the slave device to convey or respond to a fault indication signal generated by one of a plurality of PMICs coupled to the multi-point serial bus.

[0173] 16. A data communication device, comprising: an interface circuit adapted to couple the data communication device to one or more multi-point serial buses; and a controller configured to: send a first broadcast command via a first multi-point serial bus, the first broadcast command being configured to: decouple a daisy-chain input terminal of a first slave device from a daisy-chain output terminal of the first slave device, and, for each slave device in a plurality of slave devices coupled to the first multi-point serial bus, decouple the daisy-chain input terminal of each slave device from the daisy-chain output terminal of each slave device, the daisy-chain input terminal of each slave device being coupled to the daisy-chain output terminal of another slave device; activating a programming enable signal coupled to the daisy-chain input of the first slave device; and broadcasting a first sequence of address configuration commands over the first multi-point serial bus, wherein each of the slave devices is configured to respond to a first address configuration command received after detecting the activated programming enable signal at its daisy-chain input, wherein each of the slave devices is further configured to ignore subsequent address configuration commands, and wherein each address configuration command is configured to: configure a unique device identifier in the slave device that responds to each address configuration command, and couple the daisy-chain input of the slave device that responds to each address configuration command to the daisy-chain output of the slave device that responds to each address configuration command.

[0174] 17. A data communication device according to claim 16, wherein the controller is further configured to: send a second broadcast command via a second multi-point serial bus, the second broadcast command being configured to: decouple the daisy-chain input of the second slave device from the daisy-chain output of the second slave device, and for each slave device among the multiple slave devices coupled to the second multi-point serial bus, decouple the daisy-chain input of each slave device from the daisy-chain output of each slave device, the daisy-chain input of each slave device being coupled to the daisy-chain output of another slave device; and broadcast a second sequence of address configuration commands via the second multi-point serial bus, wherein each slave device is configured to respond to a first address configuration command received after detecting an activated programming enable signal at its daisy-chain input, and wherein each slave device is further configured to ignore subsequent address configuration commands.

[0175] 18. A data communication device according to claim 16 or 17, wherein the controller is further configured to: send a single-wire broadcast command using one conductor of the first multi-point serial bus, wherein the first broadcast command is sent using two conductors of the first multi-point serial bus, and the single-wire broadcast command is configured to: decouple a daisy-chain input of a first single-wire slave device from a daisy-chain output of the first single-wire slave device, and for each single-wire slave device in a plurality of single-wire slave devices coupled to the first multi-point serial bus, decouple the daisy-chain input of each single-wire slave device from the daisy-chain output of each single-wire slave device, the daisy-chain input of each single-wire slave device being coupled to the daisy-chain output of another single-wire slave device; and broadcast a sequence of single-wire address configuration commands over the first multi-point serial bus, wherein each single-wire slave device is configured to respond to the first single-wire address configuration command received after detecting an activated programming enable signal at its daisy-chain input, and wherein each single-wire slave device is further configured to ignore subsequent single-wire address configuration commands.

[0176] 19. A data communication device as described in any one of clauses 16 to 18, wherein the first multi-point serial bus operates according to a Radio Frequency Front End (RFFE) protocol, a System Power Management Interface (SPMI) protocol or a Serial Peripheral Interface (SPI) protocol.

[0177] 20. A data communication apparatus according to any one of clauses 16 to 19, wherein the first slave device comprises a power management integrated circuit (PMIC), and wherein the controller is further configured to: configure the daisy-chain input of the first slave device and the daisy-chain output of the first slave device to communicate or respond to a fault indication signal generated by one of a plurality of PMICs coupled to the first multi-point serial bus.

[0178] 21. A method for performing data communication at a host device, the method comprising: sending a first broadcast command over a first multi-point serial bus, the first broadcast command being configured to: decouple a daisy-chain input of a first slave device from a daisy-chain output of the first slave device, and for each of a plurality of slave devices coupled to the first multi-point serial bus, decouple the daisy-chain input of each slave device from the daisy-chain output of each slave device, the daisy-chain input of each slave device being coupled to the daisy-chain output of another slave device; activating an encoder coupled to the daisy-chain input of the first slave device; a programming enable signal; and broadcasting a first sequence of address configuration commands over the first multi-point serial bus, wherein each of the slave devices is configured to respond to a first address configuration command received after detecting the activated programming enable signal at its daisy-chain input, wherein each of the slave devices is further configured to ignore subsequent address configuration commands, and wherein each address configuration command is configured to: configure a unique device identifier in the slave device that responds to each address configuration command, and couple the daisy-chain input of the slave device that responds to each address configuration command to the daisy-chain output of the slave device that responds to each address configuration command.

[0179] 22. The method of clause 21, wherein the first broadcast command is configured to cause the first slave device to open a switch coupling the daisy-chain input of the first slave device with the daisy-chain output of the first slave device.

[0180] 23. A method according to clause 21 or clause 22, wherein the daisy chain input end of the slave device that responds to each address configuration command is coupled to the daisy chain output end of the slave device that responds to each address configuration command by closing a switch in the slave device that responds to each address configuration command.

[0181] 24. The method according to any one of clauses 21 to 23, further comprising: sending a second broadcast command via a second multi-point serial bus, the second broadcast command being configured to: decouple the daisy-chain input of the second slave device from the daisy-chain output of the second slave device, and for each slave device among the plurality of slave devices coupled to the second multi-point serial bus, decouple the daisy-chain input of each slave device from the daisy-chain output of each slave device, the daisy-chain input of each slave device being coupled to the daisy-chain output of another slave device; and broadcasting a second sequence of address configuration commands via the second multi-point serial bus, wherein each slave device is configured to respond to a first address configuration command received after detecting an activated programming enable signal at its daisy-chain input, and wherein each slave device is further configured to ignore subsequent address configuration commands.

[0182] 25. A method according to any one of clauses 21 to 24, the method further comprising: sending a single-wire broadcast command using one conductor of the first multi-point serial bus, wherein the first broadcast command is sent using two conductors of the first multi-point serial bus, the single-wire broadcast command being configured to: decouple a daisy-chain input of a first single-wire slave device from a daisy-chain output of the first single-wire slave device, and for each single-wire slave device in a plurality of single-wire slave devices coupled to the first multi-point serial bus, decouple the daisy-chain input of each single-wire slave device from the daisy-chain output of each single-wire slave device, the daisy-chain input of each single-wire slave device being coupled to the daisy-chain output of another single-wire slave device; and broadcasting a sequence of single-wire address configuration commands over the first multi-point serial bus, wherein each single-wire slave device is configured to respond to a first single-wire address configuration command received after detecting an activated programming enable signal at its daisy-chain input, and wherein each single-wire slave device is further configured to ignore subsequent single-wire address configuration commands.

[0183] 26. A method as described in any of clauses 21 to 25, wherein the first multi-point serial bus operates in accordance with the Radio Frequency Front End (RFFE) protocol defined by the Mobile Industry Processor Interface (MIPI) Alliance.

[0184] 27. A method as described in any of clauses 21 to 25, wherein the first multi-point serial bus operates in accordance with the System Power Management Interface (SPMI) protocol defined by the Mobile Industry Processor Interface (MIPI) Alliance.

[0185] 28. A method as described in any one of clauses 21 to 25, wherein the first multi-drop serial bus operates according to a Serial Peripheral Interface (SPI) protocol.

[0186] 29. A method according to any one of clauses 21 to 28, wherein the first slave device includes a power management integrated circuit (PMIC), and the method further includes: causing the PMIC to configure the daisy-chain input end of the first slave device and the daisy-chain output end of the first slave device to convey or respond to a fault indication signal generated by one of a plurality of PMICs coupled to the first multi-point serial bus.

[0187] 30. A method according to any one of clauses 21 to 29, wherein each slave device sets a flag indicating that its unique device identifier is configured after receiving the first address configuration command in response to detecting an activated programming enable signal at its daisy chain input, and wherein each slave device is further configured to: ignore subsequent address configuration commands when the flag is set.

[0188] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but rather to the full scope consistent with the language claims, wherein elements mentioned in the singular are not intended to mean "one and only one" unless specifically stated otherwise, but rather "one or more". Unless otherwise specified, the term "some" refers to one or more. All structural and functional equivalents of the elements of the various aspects described throughout this disclosure that are known or will later be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be dedicated to the public, regardless of whether such disclosure is explicitly stated in the claims. No claim element can be interpreted as a component plus function unless the element is explicitly stated using the phrase "component for..."

Claims

1. A method for performing data communication at a slave device, the method comprising: receiving a first broadcast command via the multipoint serial bus; decoupling the daisy-chain input of the slave device from the daisy-chain output of the slave device; receiving a second broadcast command via the multi-point serial bus; responding to the second broadcast command when the signal received through the daisy chain input terminal is in an active state; when the signal received through the daisy chain input terminal is in an inactive state, ignoring the second broadcast command; as well as ignoring subsequent broadcast commands after responding to the second broadcast command, Wherein responding to the second broadcast command includes: configuring a unique device identifier of the slave device using the address provided in the second broadcast command, and The daisy-chain input of the slave device is coupled to the daisy-chain output of the slave device.

2. The method of claim 1 , wherein decoupling the daisy-chain input of the slave device from the daisy-chain output of the slave device comprises: A switch coupling the daisy-chain input of the slave device with the daisy-chain output of the slave device is opened.

3. The method of claim 1 , wherein coupling the daisy-chain input of the slave device to the daisy-chain output of the slave device comprises: Close the switch in the slave device. 4 . The method of claim 1 , wherein the first broadcast command and the second broadcast command are received using a single conductor of the multi-point serial bus.

5. The method of claim 1, wherein the multi-point serial bus operates according to a Radio Frequency Front End (RFFE) protocol defined by the Mobile Industry Processor Interface (MIPI) Alliance.

6. The method of claim 1, wherein the multi-drop serial bus operates according to a System Power Management Interface (SPMI) protocol defined by the Mobile Industry Processor Interface (MIPI) Alliance.

7. The method of claim 1, wherein the multi-drop serial bus operates according to a serial peripheral interface (SPI) protocol.

8. The method of claim 1 , wherein the slave device comprises a power management integrated circuit (PMIC), and the method further comprises: The daisy-chain input of the slave device and the daisy-chain output of the slave device are configured to communicate or respond to a fault indication signal generated by one of a plurality of PMICs coupled to the multi-drop serial bus.

9. The method according to claim 1, further comprising: After responding to the second broadcast command, a flag is set indicating that the unique device identifier is configured.

10. The method according to claim 9, further comprising: When the flag is set, subsequent broadcast commands are ignored.

11. A slave device, comprising: an interface circuit adapted to couple the slave device to a multi-drop serial bus; and A controller configured to: receiving a first broadcast command via the multi-point serial bus; decoupling the daisy-chain input of the slave device from the daisy-chain output of the slave device; receiving a second broadcast command via the multi-point serial bus; When the signal received through the daisy chain input terminal is in an active state, responding to the second broadcast command in the following manner: configuring a unique device identifier of the slave device using the address provided in the second broadcast command, and coupling the daisy-chain input of the slave device to the daisy-chain output of the slave device; as well as Subsequent broadcast commands are ignored after responding to the second broadcast command.

12. The slave device according to claim 11, wherein the controller is further configured to: When the daisy-chain input of the slave device is decoupled from the daisy-chain output of the slave device, a switch coupling the daisy-chain input of the slave device with the daisy-chain output of the slave device is opened.

13. The slave device according to claim 11, wherein the controller is further configured to: When the daisy-chain input of the slave device is coupled to the daisy-chain output of the slave device, a switch coupling the daisy-chain input of the slave device with the daisy-chain output of the slave device is closed.

14. The slave device of claim 11, wherein the multi-drop serial bus operates according to a Radio Frequency Front End (RFFE) protocol, a System Power Management Interface (SPMI) protocol, or a Serial Peripheral Interface (SPI) protocol.

15. The slave device of claim 11 , wherein the slave device comprises a power management integrated circuit (PMIC), and wherein the controller is further configured to: The daisy-chain input of the slave device and the daisy-chain output of the slave device are configured to communicate or respond to a fault indication signal generated by one of a plurality of PMICs coupled to the multi-drop serial bus.

16. A data communication device, comprising: interface circuitry adapted to couple the data communications device to one or more multi-drop serial buses; and A controller configured to: sending a first broadcast command via a first multi-point serial bus, the first broadcast command being configured to: decouple a daisy-chain input terminal of a first slave device from a daisy-chain output terminal of the first slave device, and, for each slave device of a plurality of slave devices coupled to the first multi-point serial bus, decouple the daisy-chain input terminal of each slave device from the daisy-chain output terminal of each slave device, the daisy-chain input terminal of each slave device being coupled to the daisy-chain output terminal of another slave device; activating a programming enable signal coupled to the daisy-chain input of the first slave device; as well as A first sequence of address configuration commands is broadcast over the first multi-point serial bus, wherein each of the slave devices is configured to respond to a first address configuration command received after detecting an activated programming enable signal at its daisy-chain input, wherein each of the slave devices is further configured to ignore subsequent address configuration commands, and wherein each address configuration command is configured to: configure a unique device identifier in the slave device that responds to each address configuration command, and couple the daisy-chain input of the slave device that responds to each address configuration command to the daisy-chain output of the slave device that responds to each address configuration command.

17. The data communication device according to claim 16, wherein the controller is further configured to: Sending a second broadcast command via the second multi-point serial bus, wherein the second broadcast command is configured to: decoupling the daisy-chain input of the second slave device from the daisy-chain output of the second slave device, and For each slave device of the plurality of slave devices coupled to the second multi-drop serial bus, decoupling a daisy-chain input terminal of each slave device from a daisy-chain output terminal of each slave device, the daisy-chain input terminal of each slave device being coupled to the daisy-chain output terminal of another slave device; and A second sequence of address configuration commands is broadcast over the second multi-drop serial bus, wherein each of the slave devices is configured to respond to a first address configuration command received after detecting an activated programming enable signal at its daisy-chain input, and wherein each of the slave devices is further configured to ignore subsequent address configuration commands.

18. The data communication device according to claim 16, wherein the controller is further configured to: Using one conductor of the first multi-point serial bus to send a single-line broadcast command, wherein the first broadcast command is sent using two conductors of the first multi-point serial bus, and the single-line broadcast command is configured as follows: decoupling a daisy-chain input of a first single-wire slave device from a daisy-chain output of said first single-wire slave device, and For each single-wire slave device of a plurality of single-wire slave devices coupled to the first multi-drop serial bus, decoupling a daisy-chain input of each of the single-wire slave devices from a daisy-chain output of each of the single-wire slave devices, the daisy-chain input of each of the single-wire slave devices being coupled to the daisy-chain output of another single-wire slave device; and A sequence of single-wire address configuration commands is broadcast over the first multi-drop serial bus, wherein each of the single-wire slave devices is configured to respond to a first single-wire address configuration command received after detecting an activated programming enable signal at its daisy-chain input, and wherein each of the single-wire slave devices is further configured to ignore subsequent single-wire address configuration commands.

19. The data communication device of claim 16, wherein the first multi-point serial bus operates according to a radio frequency front end (RFFE) protocol, a system power management interface (SPMI) protocol, or a serial peripheral interface (SPI) protocol.

20. The data communication apparatus of claim 16, wherein the first slave device comprises a power management integrated circuit (PMIC), and wherein the controller is further configured to: The daisy-chain input of the first slave device and the daisy-chain output of the first slave device are configured to communicate or respond to a fault indication signal generated by one of a plurality of PMICs coupled to the first multi-drop serial bus.

21. A method for performing data communication at a host device, the method comprising: Sending a first broadcast command via the first multi-point serial bus, wherein the first broadcast command is configured to: decoupling a daisy-chain input of a first slave device from a daisy-chain output of said first slave device, and For each slave device of a plurality of slave devices coupled to the first multi-drop serial bus, decoupling a daisy-chain input terminal of each slave device from a daisy-chain output terminal of each slave device, the daisy-chain input terminal of each slave device being coupled to the daisy-chain output terminal of another slave device; activating a programming enable signal coupled to the daisy-chain input of the first slave device; as well as broadcasting a first sequence of address configuration commands over the first multi-drop serial bus, wherein each of the slave devices is configured to respond to a first address configuration command received after detecting an activated programming enable signal at its daisy-chain input, wherein each of the slave devices is further configured to ignore subsequent address configuration commands, and wherein each address configuration command is configured to: configuring a unique device identifier in the slave device in response to each of said address configuration commands, and The daisy-chain input of the slave device that responds to each address configuration command is coupled to the daisy-chain output of the slave device that responds to each address configuration command.

22. The method of claim 21, wherein the first broadcast command is configured to cause the first slave device to open a switch coupling the daisy-chain input of the first slave device with the daisy-chain output of the first slave device.

23. The method of claim 21 , wherein the daisy-chain input of the slave device that responds to each address configuration command is coupled to the daisy-chain output of the slave device that responds to each address configuration command by closing a switch in the slave device that responds to each address configuration command.

24. The method according to claim 21, further comprising: Sending a second broadcast command via the second multi-point serial bus, wherein the second broadcast command is configured to: decoupling the daisy-chain input of the second slave device from the daisy-chain output of the second slave device, and For each slave device of the plurality of slave devices coupled to the second multi-drop serial bus, decoupling a daisy-chain input terminal of each slave device from a daisy-chain output terminal of each slave device, the daisy-chain input terminal of each slave device being coupled to the daisy-chain output terminal of another slave device; as well as A second sequence of address configuration commands is broadcast over the second multi-drop serial bus, wherein each of the slave devices is configured to respond to a first address configuration command received after detecting an activated programming enable signal at its daisy-chain input, and wherein each of the slave devices is further configured to ignore subsequent address configuration commands.

25. The method according to claim 21, further comprising: Using one conductor of the first multi-point serial bus to send a single-line broadcast command, wherein the first broadcast command is sent using two conductors of the first multi-point serial bus, and the single-line broadcast command is configured as follows: decoupling a daisy-chain input of a first single-wire slave device from a daisy-chain output of said first single-wire slave device, and For each single-wire slave device of a plurality of single-wire slave devices coupled to the first multi-drop serial bus, decoupling a daisy-chain input terminal of each single-wire slave device from a daisy-chain output terminal of each single-wire slave device, the daisy-chain input terminal of each single-wire slave device being coupled to the daisy-chain output terminal of another single-wire slave device; as well as A sequence of single-wire address configuration commands is broadcast over the first multi-drop serial bus, wherein each of the single-wire slave devices is configured to respond to a first single-wire address configuration command received after detecting an activated programming enable signal at its daisy-chain input, and wherein each of the single-wire slave devices is further configured to ignore subsequent single-wire address configuration commands.

26. The method of claim 21, wherein the first multi-point serial bus operates according to a Radio Frequency Front End (RFFE) protocol defined by the Mobile Industry Processor Interface (MIPI) Alliance.

27. The method of claim 21, wherein the first multi-drop serial bus operates according to a System Power Management Interface (SPMI) protocol defined by the Mobile Industry Processor Interface (MIPI) Alliance.

28. The method of claim 21, wherein the first multi-drop serial bus operates according to a serial peripheral interface (SPI) protocol.

29. The method of claim 21 , wherein the first slave device comprises a power management integrated circuit (PMIC), and the method further comprises: The PMIC is caused to configure the daisy-chain input of the first slave device and the daisy-chain output of the first slave device to communicate or respond to a fault indication signal generated by one of a plurality of PMICs coupled to the first multi-drop serial bus.

30. A method according to claim 21, wherein each slave device sets a flag indicating that its unique device identifier is configured after receiving the first address configuration command in response to detecting the activated programming enable signal at its daisy chain input terminal, and wherein each slave device is further configured to: ignore the subsequent address configuration command when the flag is set.

Images