Display device

Abstract

[Problem] The present disclosure provides a display device with which a line capacitance difference between wires can be suppressed. [Solution] The display device comprises: a supply unit for supplying a pixel voltage indicating the luminance level of each pixel through a plurality of wirings; a plurality of switching devices, one end of which is connected to the plurality of wirings; a plurality of data lines connected to the other ends of the plurality of switching devices; a plurality of pixels connected to each of the plurality of data lines, two-dimensionally arranged, and emitting light based on a pixel voltage; and an adjustment capacitance unit that adjusts line capacitances of adjacent wirings among the plurality of wirings.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] Organic electroluminescent (EL) devices are self-luminous devices and do not require a backlight, thus enabling thinner display panels and lower power consumption. Consequently, their use in portable devices such as smartphones and large TVs is expected to increase.

[0003] A display panel using a self-luminous device such as an organic EL device can adjust brightness by controlling a signal voltage to be applied to the self-luminous device. The signal voltage is supplied from a data line driving unit.

[0004] Reference List

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2015-169690 Summary of the Invention

[0007] Technical Problems to be Solved by the Invention

[0008] However, line capacitances differ between adjacent ones of wirings for supplying a signal voltage from a data line driving unit, which may affect the signal voltage.

[0009] Therefore, the present disclosure provides a display device capable of reducing a line capacitance difference between wirings.

[0010] Technical solutions to technical problems

[0011] In order to solve the above problems, according to the present disclosure, a display device is provided, which includes:

[0012] a supply unit configured to supply a pixel voltage indicating a brightness level of each pixel via a plurality of wirings;

[0013] a plurality of switching devices, one end of each of the plurality of switching devices being connected to the plurality of wirings;

[0014] a plurality of data lines connected to the other ends of the plurality of switching devices;

[0015] a plurality of pixels connected to each of the plurality of data lines and configured to emit light based on a pixel voltage; and

[0016] The capacitance adjustment unit is configured to adjust line capacitances of adjacent wirings among the plurality of wirings.

[0017] The adjustment capacitance unit can make the potential difference between adjacent wirings among the plurality of wirings within a predetermined value when pixel voltages having the same potential are applied to adjacent wirings.

[0018] The adjusting capacitance unit may be a conductive line electrically connected to an adjacent wiring.

[0019] The longer the length of the adjacent wiring is, the shorter the length of the wire can be.

[0020] The capacitance adjustment unit may be at least a partial range of adjacent wirings, and the cross-sectional areas of the wirings in the partial ranges may be made different.

[0021] The longer the length of adjacent wiring, the smaller the cross-sectional area can be.

[0022] It may be configured such that the capacitance adjustment unit is at least a partial range of adjacent wirings, and the resistance in the partial range is made the same.

[0023] The display device according to (7), wherein, in the adjustment capacitance unit, a shape of at least a partial range of adjacent wirings is different for each adjacent wiring.

[0024] The adjustment capacitance unit may be a capacitor connected to an adjacent wiring.

[0025] The longer the length of adjacent wiring, the smaller the capacitance can be.

[0026] The capacitor may include a MOM (Metal-Oxide-Metal) capacitor or a MIM (Metal-Insulator-Metal) capacitor.

[0027] The supply unit may include a plurality of pads arranged in a two-dimensional manner, and

[0028] One end of the plurality of wirings may be connected to each of the plurality of pads.

[0029] The adjusting capacitance unit may be a conductive line electrically connected to each of the pads, and the length of the conductive line may be shorter as the length of the adjacent wiring is longer.

[0030] The conductive line may not be arranged within the range vertically above or below the pad.

[0031] The conductive line may be arranged within a range vertically above or below a pad to which the conductive line is connected, and not arranged within a range vertically above or below a pad to which the conductive line is not connected.

[0032] A conductive line may be electrically connected to each of the contacts of the pad.

[0033] The conductors may be internal wiring of the supply unit.

[0034] The switching device may be a MOS transistor.

[0035] Pixels may include self-luminous devices whose light emission can be individually controlled.

[0036] The apparatus may further include a signal processing unit configured to generate a second video signal corresponding to pixel data displayed on the plurality of pixels based on the first video signal,

[0037] The supply unit may include a plurality of amplifiers connected to each of the pads and configured to supply a pixel voltage based on the second video signal, and

[0038] The supply unit and the signal processing unit can be stacked.

[0039] The adjustment capacitance unit can reduce the potential difference between adjacent wirings to such an extent that the luminance difference when pixels connected to the adjacent wirings emit light is not visually recognized as a linear step. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a block diagram showing a schematic configuration of a display device according to the present embodiment.

[0041] Figure 2 is a circuit diagram showing an example of a circuit configuration of a sub-pixel.

[0042] Figure 3 is a diagram schematically showing a stack configuration example of a data line drive unit.

[0043] Figure 4A 1 is a planar layout diagram of the data line driving unit, the first wiring portion, the second wiring portion, and the switching unit.

[0044] Figure 4B 1 and 2 are a plan view of the adjustment capacitor unit and a diagram showing the AA cross-sectional line.

[0045] Figure 4C This is an AA cross-sectional view when using flip chip bumps.

[0046] Figure 4D This is an AA cross-sectional view when wire bonding is used.

[0047] Figure 5 is a diagram showing a connection relationship from a data line driving unit to data lines.

[0048] Figure 6 is a diagram indicating an example of operating characteristics of a connection transistor.

[0049] Figure 7 is a plan layout diagram showing an arrangement example of conductive lines according to a first modification example of the first embodiment.

[0050] Figure 8 is a plan layout diagram showing an arrangement example of wiring according to a second modification example of the first embodiment.

[0051] Figure 9 is a plan layout diagram showing an arrangement example of conductive lines according to a third modification example of the first embodiment.

[0052] Figure 10 is a plan layout diagram showing an arrangement example of wirings according to a fourth modification example of the first embodiment.

[0053] Figure 11 is a plan layout diagram showing an arrangement example of wirings according to a fifth modification example of the first embodiment.

[0054] Figure 12 is a plan layout diagram showing an arrangement example of IC internal wiring according to a sixth modification of the first embodiment.

[0055] Figure 13 is a diagram showing a first configuration example of a pixel.

[0056] Figure 14 is a diagram showing another configuration example of pixels.

[0057] Figure 15 is a diagram showing another configuration example of pixels.

[0058] Figure 16 is a diagram showing another configuration example of pixels.

[0059] Figure 17 is a diagram showing another configuration example of pixels.

[0060] Figure 18 is a diagram showing another configuration example of pixels.

[0061] Figure 19 is a diagram showing another configuration example of pixels.

[0062] Figure 20 is a diagram showing another configuration example of pixels.

[0063] Figure 21 is a diagram showing an example of the appearance of a head-mounted display.

[0064] Figure 22 is a diagram showing an appearance example of another head-mounted display.

[0065] Figure 23 is a front view showing an example of the appearance of a digital camera.

[0066] Figure 24 is a side view showing an example of the appearance of a digital camera.

[0067] Figure 25 is a diagram showing an example of the appearance of a television device.

[0068] Figure 26 is a diagram showing an example of the appearance of a smartphone.

[0069] Figure 27 is a diagram showing an example of the interior of a vehicle viewed from the rear of the vehicle;

[0070] Figure 28 is a diagram showing an example of the interior of a vehicle viewed from the left rear of the vehicle. DETAILED DESCRIPTION

[0071] Hereinafter, embodiments of a display device will be described with reference to the accompanying drawings. Although the following will mainly describe the main components of the display device, the display device may have components or functions not shown or described. The following description is not intended to exclude components and functions not shown or described.

[0072] Figure 1 : is a block diagram showing a schematic configuration of the display device 1 according to the present embodiment. Figure 1 The screen size of the display device 1 is not limited. Figure 1 The display device 1 may be a display device for a stationary TV or a personal computer (PC), or may be a display device for a portable device such as a smartphone. Figure 1 The display device 1 includes a display panel unit 2 and a host processing unit 3. The display panel unit 2 displays a static image or a dynamic image on a plurality of pixels 4 arranged on a two-dimensional plane. The host processing unit 3 generates a video signal including pixel data to be displayed on the plurality of pixels 4 of the display panel unit 2 and provides the video signal to the display panel unit 2. The host processing unit 3 can be configured by a PC, a server, a workstation, etc. The display panel unit 2 and the host processing unit 3 send and receive video signals in a wired or wireless manner. The host processing unit 3 can be arranged separately from the display panel unit 2, or can be attached to the back of the display panel unit 2, etc.

[0073] The display panel unit 2 includes a pixel array unit 5, a display control unit 6 and an interface unit 7. The pixel array unit 5, the display control unit 6 and the interface unit 7 are, for example, arranged on the same substrate. The display control unit 6 and the interface unit 7 can be formed on the substrate using semiconductor process technology, or the display control unit 6 or the interface unit 7 formed as a chip can be mounted on the substrate. The display panel unit 2 can be not only a unit including a display screen that allows direct visual recognition (such as a monitor of a TV or PC or a smart phone), but also a microdisplay that allows visual recognition of a projection screen on which an image of the display panel unit 2 is projected. An example of a microdisplay is an organic light emitting diode (OLED) formed on a single crystal silicon substrate.

[0074] The pixel array unit 5 includes a plurality of pixels 4 arranged on a two-dimensional plane. The number of pixels 4 in the pixel array unit 5 is not particularly limited, but may be, for example, 2k (1920×1080 pixels), 4k (3840×2160 pixels), or other numbers.

[0075] Each pixel 4 may have a plurality of sub-pixels 4a that emit light in different colors. For example, the plurality of sub-pixels 4a may include red (R), green (G), and blue (B) pixels. Alternatively, the sub-pixels 4a may include white (W) pixels or pixels of other colors.

[0076] The plurality of sub-pixels 4a in each pixel 4 include self-luminous devices capable of individually controlling light emission. A self-luminous device is a device based on a sub-pixel 4a that emits light without providing a backlight. A typical example of a self-luminous device is an organic EL device. Note that the self-luminous device may be a plasma display device or a field emission display (FED) device. Hereinafter, an example in which an organic EL device is used as a self-luminous device will be mainly described.

[0077] The display control unit 6 drives the plurality of pixels 4 in the pixel array unit 5 at a predetermined frame frequency. The frame frequency can be changed. Note that the term "frame" refers to all pixels in the pixel array unit 5. The frame frequency is a frequency for driving all the plurality of pixels 4 in the pixel array unit 5.

[0078] The display control unit 6 includes a signal processing unit 11, a timing control unit 12, a scan line drive unit 13, a power line drive unit 14, a data line drive unit 15, a first wiring section 16, a second wiring section 17, a switch unit 18, and an adjustment capacitor unit 19. Note that the adjustment capacitor unit 19 according to this embodiment is configured in at least one of the data line drive unit 15 and the first wiring section 16. In addition, the configuration of the data line drive unit 15 and the first wiring section 16 itself can also function as the adjustment capacitor unit 19.

[0079] Based on the first video signal transmitted from the host processing unit 3, the signal processing unit 11 generates a second video signal corresponding to the pixel data displayed on the pixel 4 of the pixel array unit 5, and supplies the second video signal to the data line driving unit 15. As described later, the processing content of the signal processing unit 11 can vary according to the signal format of the first video signal transmitted from the host processing unit 3. The data format of the pixel data transmitted from the signal processing unit 11 to the data line driving unit 15 is different between the case where normal display is performed and the case where sparse display is performed. Sparse display indicates that some pixels are not displayed, and for example, display is performed with some pixels replaced with black pixels. The signal processing unit 11 can perform existing signal processing such as gamma correction on the first video signal transmitted from the host processing unit 3.

[0080] The timing control unit 12 generates a control signal for synchronizing the scan line drive unit 13 , the power line drive unit 14 , and the data line drive unit 15 based on a synchronization signal supplied from the host processing unit 3 or the like, and supplies the control signal to the scan line drive unit 13 , the power line drive unit 14 , and the data line drive unit 15 .

[0081] The scanning line driving unit 13 sequentially supplies scanning signals to the plurality of scanning lines according to the control signal from the timing control unit 12 to sequentially select the sub-pixels 4 a .

[0082] The data line drive unit 15 generates a signal Sig including a pixel voltage Vsig that instructs the light emission luminance of each sub-pixel 4a based on the second video signal Sdisp2 supplied from the signal processing unit 11 and the control signal supplied from the timing control unit 12, and applies the signal Sig to each data line DL. Note that the data line drive unit 15 according to this embodiment corresponds to a supply unit.

[0083] First wiring section 16 is a connection wiring that connects data line driver unit 15 and second wiring section 17. Second wiring section 17 is, for example, a fan-out wiring, and regulates the number of output terminals of data line driver unit 15 and the number of switching devices included in switch unit 18, that is, the number of data lines DL. For example, the number of output terminals of data line driver unit 15 and the number of data lines DL are, for example, 1 to n. n is a natural number including 1, and is, for example, 4.

[0084] The switch unit 18 sequentially supplies a signal Sig including a pixel voltage Vsig to the plurality of data lines DL in response to a control signal from the timing control unit 12. The switch unit 18 places the second wiring portion 17 and the data lines DL in a conductive or non-conductive state in response to the control signal from the timing control unit 12. For example, the switch unit 18 includes the same number of switching devices as the number of data lines DL. These switching devices are, for example, P-channel metal oxide semiconductor (MOS) thin film transistors (TFTs).

[0085] The capacitance adjustment unit 19 adjusts the line capacitance of the wiring in the first wiring section 16. For example, when the pixel voltage Vsig having the same potential is applied to adjacent wirings among the plurality of wirings, the capacitance adjustment unit 19 adjusts the potential difference between the adjacent wirings to within a predetermined value. Note that the details of the capacitance adjustment unit 19 will be described later.

[0086] The line capacitance in this embodiment refers to the line capacitance when the wiring in first wiring section 16 is connected to the wiring in second wiring section 17, but is not limited to this. For example, the length difference between adjacent wirings in second wiring section 17 may be small, and the line capacitance of second wiring section 17 may not significantly affect the line capacitance difference between adjacent wirings. In this case, the line capacitance in this embodiment means that it is approximately equal to the line capacitance of the wiring in first wiring section 16.

[0087] The interface unit 7 performs processing for receiving a video signal from the host processing unit 3 and transmitting the video signal to the display control unit 6. In some cases, the interface unit 7 converts parallel / serial data and then provides pixel data included in the video signal to the display control unit 6. Note that in this embodiment, the two-dimensional plane of the pixel array unit 5 can be referred to as an XY plane, and the Z direction orthogonal to the XY plane can be referred to as a vertically upward direction.

[0088] Figure 2is a circuit diagram illustrating an example of the circuit configuration of a subpixel 4a. The pixel array unit 5 includes a plurality of scan lines WL and a plurality of power lines PL extending in the row direction, as well as a plurality of data lines DL extending in the column direction. Although not shown, one end of the data line DL is connected to the data line driver 15 via the switch unit 18, the second wiring portion 17, and the first wiring portion 16. One end of the scan line WL is connected to the scan line driver 13, and one end of the power line PL is connected to the power line driver 14. Each subpixel 4a is arranged at the intersection of a scan line WL and a data line DL. The power line driver 14 controls the light emission of the subpixel 4a by sequentially providing a power signal DS to the plurality of power lines PL based on a control signal provided by the timing control unit 12. The power signal DS transitions between a drive voltage and an initialization voltage. The initialization voltage is a voltage used to initialize the subpixel 4a, and the drive voltage is a voltage used to cause a current Ids to flow through the drive transistor DRTr, causing the self-luminous device to emit light.

[0089] The sub-pixel 4a includes a writing transistor Q1, a driving transistor Q2, a self-luminous device 160 such as an organic EL device, and a capacitor Cs. In other words, in this example, the sub-pixel 4a has a so-called "2Tr1C" configuration including two transistors (writing transistor Q1, driving transistor Q2) and one capacitor Cs, but is not limited thereto. For example, as will be described later, Figures 13 to 20 Other configurations may be employed as described above.

[0090] The write transistor Q1 and the drive transistor Q2 are, for example, N-channel metal oxide semiconductor (MOS) thin film transistors (TFTs). The gate of the write transistor Q1 is connected to the scan line WL, the source is connected to the data line DL, and the drain is connected to the gate of the drive transistor Q2 and one end of the capacitor Cs. The gate of the drive transistor Q2 is connected to the drain of the write transistor Q1 and one end of the capacitor Cs, the drain is connected to the power line PL, and the source is connected to the other end of the capacitor Cs and the anode of the self-luminous device 160.

[0091] One end of the capacitor device Cs is connected to the gate of the driving transistor Q2, etc., and the other end is connected to the source of the driving transistor Q2, etc. The self-luminous device 160 is a light-emitting device configured using an organic EL device, and has an anode connected to the source of the driving transistor Q2 and the other end of the capacitor device Cs, and a voltage Vcath as a DC voltage is provided to the cathode. The self-luminous device 160 emits white light. In other words, in this example, as will be described later, the sub-pixel 4a is provided with a self-luminous device 160 that emits white light and color filters that generate red (R), green (G) and blue (B) light, respectively. Color filters of colors other than RGB can be provided, and sub-pixels of four or more colors can constitute one pixel. Note that, as the self-luminous device 160, three or more types of self-luminous devices 160 that emit light in different emission colors such as red, green and blue can be provided in the sub-pixel 4a in the pixel 4. In this case, a color filter is not required.

[0092] The display control unit 6 according to the present embodiment writes the pixel voltage Vsig to each sub-pixel 4a in one horizontal period. As a result, the self-luminous device 160 emits light with a luminance corresponding to the written pixel voltage Vsig.

[0093] The display control unit 6 can cause all of the plurality of pixels 4 to emit light in each of a plurality of consecutive frames. As described above, when a static image is displayed on the plurality of pixels 4, the display control unit 6 can display the static image at full display resolution in a plurality of consecutive frames. Note that the display control unit 6 can also thin out and drive a plurality of pixels 4 in each of the consecutive frames. In this case, the pixels 4 to be thinned out can be different for each frame.

[0094] Figure 3 1 is a diagram schematically illustrating an example of a stacked configuration of the data line driver unit 15. For example, the data line driver unit 15 is configured on a substrate on which the signal processing unit 11 and the timing control unit 12 are configured. For example, the data line driver unit 15 according to this embodiment is an example of a chip-on-chip (COC) configuration. Note that the stacked configuration example is merely an example and is not intended to be limiting.

[0095] Here, we will refer to Figures 4A to 4D as well as Figure 5 Adjusting the wiring capacitance of the capacitance unit 19 is described. Figure 4A 1 is a planar layout diagram of the data line driving unit 15 , the first wiring portion 16 , the second wiring portion 17 , the switch unit 18 , and the adjustment capacitor unit 19 .

[0096] like Figure 4AAs shown, the data line driving unit 15 includes pads P1 to Pm in the column direction. The adjacent first wiring L1a to L1m of the first wiring section 16 are connected to m pads P1 to Pm via contacts Con1 to Conm, respectively. The total number of pads is the same as the number of wirings in the first wiring section 16. For example, the pads arranged along the column direction of P1 to Pm are repeatedly configured along the row direction. Note that in FIG4 , for simplicity of description, m=5, but m is not limited to this. In addition, the arrangement relationship of the pads P1 to Pm arranged along the column direction is not limited to this.

[0097] The adjustment capacitance unit 19 is composed of wires L1b to Lmb connected to the first wirings L1a to Lma, and adjusts the line capacitance Clin. These wires L1b to Lmb are connected to the contacts Con1 to Conm in the direction opposite to the second wiring portion 17. For example, the wires L1b to Lmb are formed of the same material as the first wirings L1a to Lma. In other words, the adjustment capacitance unit 19 can also be configured by extending the wires L1a to Lma from the contacts Con1 to Conm, respectively. Note that according to this embodiment, the wires L1b to Lmb are connected to the contacts Con1 to Conm, but the connection destination is not limited to this. For example, one end of the wires L1b to Lmb can be electrically connected to the wirings L1a to Lma.

[0098] Each of the wirings L1a to Lma is connected to a wiring of the second wiring section 17. The connection transistors Q3 of the n switch units 18 are connected to the corresponding wiring of the second wiring section 17. The wiring section 17 indicates a fan-out section that widens the output pitch of the IC to the pitch of the pixel selector unit.

[0099] Figure 4B 1 is a plan view of the adjustment capacitor unit 19 and is a diagram showing the AA cross-sectional line. Figure 4C This is the AA cross-sectional view when using flip chip bumps. Figure 4C As shown, for example, the first wiring L3a and the conductive line L3b are connected to the lower portion of the pad P3 via the contact Con3. A flip-chip bump corresponding to the data line driving unit 15 is electrically connected to the pad P3.

[0100] Figure 4D This is the AA cross-sectional view when wire bonding is used. Figure 4D As shown, for example, first wiring L3a and conductive line L3b are connected to the lower portion of pad P3 via contact Con3. Pad P3a corresponding to data line drive unit 15 is electrically connected to pad P3 via wire bonding. Pad P3a is electrically connected to a display driver integrated circuit (DDIC) included in data line drive unit 15.

[0101] Figure 5is a diagram illustrating the connection relationship between the data line driver unit 15 and the data line DL. The portion from the contact Conm of the data line driver unit 15 to the connection point n2m of the first wiring portion 16 corresponds to the first wiring Lma. The portion from the connection point n2m to the connection point n3m is the second wiring of the second wiring portion 17. For example, n connection points n3m are connected to the connection point n2m. As described above, n is a natural number including 1, and is, for example, 4.

[0102] One end of the connection transistor Q3 of the switch unit 18 is connected to the connection point n3m. The connection point n4m is connected to one end of the connection transistor Q3, and the data line DL is connected to the connection point n4m.

[0103] The magnitude of the line capacitance Clinm of the wiring Lma is adjusted by the wiring Lmb (see FIG4 ) serving as the adjustment capacitance unit 19. For example, a length difference corresponding to five pads is formed between the wiring L5a of the contact Con5 and the wiring L1a of the adjacent contact Con1. The difference between the line capacitances Clin1 and Clin5 due to the difference in wiring length creates a potential difference when a signal Sig including the same pixel voltage Vsig level is applied to each data line DL. This potential difference can be visually recognized as streaks in the column direction of an image, for example.

[0104] More specifically, the reason why stripes in the row direction of an image are visually recognized will be described. Figure 6 This is a diagram showing an example of the operating characteristics of the connection transistor Q3. The horizontal axis represents time, and the vertical axis represents potential. The connection transistor Q3 is turned on when a potential equal to or lower than the threshold value Vth is applied to the gate, and is turned off when a potential higher than the threshold value Vth is applied to the gate.

[0105] With the connection transistor Q3 in the on state, the amplifier Amp of the data line driving unit 15 applies the pixel voltage Vsig to the data line DL and writes a signal to the pixel 4. Next, the state of the connection transistor Q3 changes from the on state to the off state.

[0106] In this case, during the transition from the potential L to the potential Vth, the connection transistor Q3 is in the on state. Therefore, a transition voltage ΔVc1 is generated in the total capacitance Clinm + Csig of the line capacitance Clin and the capacitance Csig of the pixel 4 via the channel capacitance of the connection transistor Q3. As a result, the potential Vline at the contact point Conm becomes Vline = Vsig = Vsig1 + ΔVc1.

[0107] Next, during the transition from potential Vth to potential H, connection transistor Q3 is in an off state. Therefore, via the channel capacitance of connection transistor Q3, line capacitance Clinm and pixel 4 capacitance Csig are in a non-conductive state. As a result, potential fluctuation ΔVc2 appears in each of line capacitance Clinm and pixel 4 capacitance Csig via the channel capacitance of connection transistor Q3. In this case, Vsig = Vsig1 + ΔVc1 + ΔVc2. As can be seen from this, pixel voltage Vsig is affected by transition voltages ΔVc1 and ΔVc2. Trip voltage ΔVc2 has approximately the same value regardless of data line DL.

[0108] On the other hand, the transition voltage ΔVc1 is affected by the line capacitance Clinm. In other words, if the line capacitance Clinm differs for each of the adjacent wiring lines L1a to L1m of the first wiring section 16, the pixel voltage Vsig differs for each of the data lines DL. The difference in voltage ΔVc1 between each of the wiring lines L1a to L1m can be visually recognized as streaks in the row direction of the image when the pixel 4 emits light. Note that if the connection transistor Q3 is in the off state and a predetermined period of time has passed, the potential Vline of the contact point Conm approaches Vsig1 due to the action of the amplifier Amp.

[0109] Therefore, in this embodiment, by making the lengths of the wires L1b to Lmb, which serve as the adjustment capacitor unit 19, different, the line capacitance generated by the wiring length differences between the wirings L1a to Lma is adjusted to the same value, Clin. More specifically, the longer the wirings L1a to Lma, the shorter the lengths of the wires L1b to Lmb. In other words, by making the lengths of the wires L1b to Lmb different, adjustment is performed so that the jump voltage ΔVc1 becomes the same value. In other words, when the signal Sig including the pixel voltage Vsig of the same level is applied to adjacent data lines DL, the adjustment capacitor unit 19 suppresses fluctuations in the line capacitance Clin to such an extent that the difference in brightness when the pixels 4 connected to the adjacent data lines DL emit light is not visually perceived as a linear step. Note that the length of the wire Lmb can be set to zero. In other words, as the wirings L1a to Lma become longer, the line capacitance generated by the wirings L1b to Lmb is further reduced by making the lengths of the wires L1b to Lmb shorter. Note that in the present embodiment, the wiring length of the second wiring portion 17 is not considered because the fluctuation between adjacent wirings is gentle and the capacitance difference between adjacent wirings is not large enough to be visually recognized.

[0110] As described above, according to this embodiment, the lengths of the wires L1b to Lmb of the contacts C1 to Cm to which the wirings L1a to Lma electrically connected to the data line drive unit 15 are connected are made different. This makes it possible to equalize the line capacitances Clin of adjacent wirings L1a to Lma. Consequently, fluctuations in the pixel voltage Vsig caused by differences in the line capacitances Clin are suppressed, and the occurrence of visible streaks in the column direction when the pixels 4 emit light is also suppressed.

[0111] (First Modification of the First Embodiment)

[0112] In the display device according to the first embodiment, the wires L1b to Lmb are arranged vertically above the pads P1 to Pm. However, the display device according to the first modified example of the first embodiment differs in that the wires L1c to Lmc are not arranged vertically above the pads P1 to Pm. The differences from the display device according to the first embodiment will be described below.

[0113] Figure 7 1 is a plan layout diagram showing an example of arrangement of the wires L1c to Lmc according to the first modification example of the first embodiment. Figure 7 As shown, wires L1c to Lmc for adjusting line capacitance Clin are connected to contacts Con1 to Conm. In other words, capacitance adjustment unit 19 according to the first modified example of the first embodiment comprises wires L1c to Lmc connected to first wiring lines L1a to L1m, and adjusts line capacitance Clin. Wires L1c to Lmc are, for example, made of the same material as wiring lines L1a to L1m. Alternatively, wiring lines L1a to L1m may be configured by extending from contacts Con1 to Conm, respectively. Wires L1c to Lmc are arranged vertically above pads P1 to Pm.

[0114] This makes it possible to suppress the electromagnetic influence of the pads P1 to Pm. In addition, the vertical thickness of the insulator that insulates the wires L1c to Lmc can be further reduced.

[0115] (Second Modification of the First Embodiment)

[0116] In the display device according to the first embodiment, wires L1b to Lmb are provided in addition to the wires L1a to Lma. However, the display device according to the second modified example of the first embodiment differs in that the lengths of the wires L1d to Lmd are configured so that the line capacitance Clin and the resistance are the same. The differences from the display device according to the first embodiment will be described below.

[0117] Figure 8 1 is a plan layout diagram showing an example of arrangement of wirings L1d to Lmd according to a second modification example of the first embodiment. Figure 8As shown, wirings L1d to Lmd are configured to connect contacts Con1 to Conm and second wiring portion 17. In other words, adjustment capacitance unit 19 according to the second modification example of the first embodiment is wirings L1d to Lmd.

[0118] The lengths and folded shapes of these wirings L1d to Lmd are configured so that the line capacitance Clin and resistance are the same. For example, the lengths of wirings L1d to Lmd are configured to be the same. As described above, these wirings L1d to Lmd are at least partially adjacent wirings, and the shape of this portion varies for each adjacent wiring.

[0119] As described above, in addition to the same effects as those of the display device 1 according to the first embodiment, the display device according to the second modification of the first embodiment can be configured to make the line capacitance Clin and the resistance the same by adjusting the lengths and shapes of the wirings L1d to Lmd.

[0120] (Third Modification of First Embodiment)

[0121] The display device according to the third modification of the first embodiment differs from the display device according to the first embodiment in that the wires L1e to Lme are arranged vertically above the pads P1 to Pm to which only the wires L1e to Lme are connected. Hereinafter, the differences from the display device according to the first embodiment will be described.

[0122] Figure 9 1 is a plan layout diagram showing an example of arrangement of the wires L1e to Lme according to the third modification example of the first embodiment. Figure 9 As shown, the wires L1e to Lme for adjusting the line capacitance Clin are connected to the contacts Con1 to Conm. In other words, the adjustment capacitance unit 19 according to the third modified example of the first embodiment is the wires L1e to Lme. The wires L1e to Lme are arranged vertically above the pads P1 to Pm to which only the wires L1e to Lme are connected.

[0123] As a result, in the display device 1 according to the third modification of the first embodiment, in addition to the same effects as the display device 1 according to the first embodiment, the influence of the wires L1e to Lm is limited to the electromagnetic influence of only the pads P1 to Pm to which the wires L1e to Lm are connected.

[0124] (Fourth Modification of First Embodiment)

[0125] The display device according to the fourth modification of the first embodiment is different from the display device according to the first embodiment in that the cross-sectional area sizes of the wirings L1f to Lmf are made different. Hereinafter, the differences from the display device according to the first embodiment will be described.

[0126] Figure 10 1 is a plan layout diagram showing an example of arrangement of wirings L1f to Lmf according to a fourth modification example of the first embodiment. Figure 10 As shown, wirings L1f to Lmf capable of adjusting line capacitance Clin are connected to contacts Con1 to Conm. In other words, capacitance adjustment unit 19 according to the fourth modified example of the first embodiment comprises wirings L1f to Lmf. The thickness of wirings L1f to Lmf varies depending on the length of wirings L1f to Lmf. More specifically, the cross-sectional area of ​​wirings L1f to Lmf decreases as the length of wirings L1f to Lmf increases. For example, if the cross-section of wirings L1f to Lmf is circular, the radius of wirings L1f to Lmf decreases as the length of wirings L1f to Lmf increases.

[0127] As a result, the display device according to the fourth modification of the first embodiment is configured such that the line capacitances Clin become the same by making the cross-sectional areas of the wirings L1f to Lmf different, so that the same effects as those of the display device 1 according to the first embodiment can be obtained.

[0128] (Fifth Modification of the First Embodiment)

[0129] The display device of the fifth modification example of the first embodiment differs from the display device of the first embodiment in that the capacitors electrically connected to the wirings L1a to Lma are configured in a form different from the wiring shape. The differences from the display device of the first embodiment will be described below.

[0130] Figure 11 1 is a plan layout diagram showing an example of arrangement of wirings L1a to Lma according to a fifth modification example of the first embodiment. Figure 11 As shown, capacitors C1 to Cm capable of adjusting the line capacitance Clin are connected to wirings L1a to Lma. In other words, the adjustment capacitor unit 19 according to the fifth modification of the first embodiment is composed of capacitors C1 to Cm. As the length of wirings L1f to Lmf increases, the capacitance of capacitors C1 to Cm decreases. For example, capacitors C1 to Cm can be configured as metal-oxide-metal (MOM) capacitors or metal-insulator-metal (MIM) capacitors.

[0131] As a result, the display device 1 according to the fifth modification of the first embodiment can obtain the same effect as the display device 1 according to the first embodiment by further reducing the capacitances of the capacitors C1 to Cm as the lengths of the wirings L1 a to Lma become longer.

[0132] (Sixth Modification of the First Embodiment)

[0133] The display device according to the sixth modification of the first embodiment differs from the display device according to the first embodiment in that the line capacitance Clin is adjusted by IC internal wirings L1f to Lmf electrically connected to wirings L1a to Lma. Hereinafter, the differences from the display device according to the first embodiment will be described.

[0134] Figure 12 1 is a plan layout diagram showing an example of arrangement of IC internal wirings L1f to Lmf according to a sixth modification of the first embodiment. Figure 12 As shown, IC internal wiring lines L1f to Lmf, which are capable of adjusting line capacitance Clin, are connected to pads P1 to Pm, to which wiring lines L1a to Lma are connected. A source amplifier (Samp) is connected to the ends of IC internal wiring lines L1f to Lmf. In other words, the adjustment capacitance unit 19 according to the sixth modification of the first embodiment is IC internal wiring lines L1f to Lmf.

[0135] As a result, the display device 1 according to the sixth modification of the first embodiment can obtain the same effect as that of the display device 1 according to the first embodiment by further reducing the capacitance generated by the IC internal wirings L1f to Lmf as the lengths of the wirings L1f to Lmf become longer.

[0136] [Configuration Example of Pixel Circuit]

[0137] The pixel 4 of the display device 1 according to the first embodiment to the sixth modification of the first embodiment may be composed of Figures 13 to 20 The pixel PIX shown in the following description is composed of the pixel PIX and the pixel 4 (4a) (see Figure 2 )correspond.

[0138] Figure 13is a diagram showing an example configuration of a pixel PIX. Pixel PIX includes a capacitor C01, transistors MN02 and MN03, and a light-emitting device EL. Transistors MN02 and MN03 are N-type metal oxide semiconductor field effect transistors (MOSFETs). The gate of transistor MN02 is connected to the control line WSL, the drain is connected to the signal line SGL, and the source is connected to the gate of transistor MN03 and capacitor C01. One end of capacitor C01 is connected to the source of transistor MN02 and the gate of transistor MN03, and the other end is connected to the source of transistor MN03 and the anode of light-emitting device EL. The gate of transistor MN03 is connected to the source of transistor MN02 and one end of capacitor C01, the drain is connected to the power supply line VCCP, and the source is connected to the other end of capacitor C01 and the anode of light-emitting device EL. Light-emitting device EL is, for example, an organic EL light-emitting device and has an anode connected to the source of transistor MN03 and the other end of capacitor C01, and a cathode connected to the power supply line Vcath.

[0139] With this configuration, in pixel PIX, transistor MN02 is turned on, setting the voltage across capacitor C01 based on the pixel signal supplied from signal line SGL. Transistor MN03 causes a current corresponding to the voltage across capacitor C01 to flow through light-emitting device EL. Light-emitting device EL emits light based on the current supplied by transistor MN03. In this manner, pixel PIX emits light having a brightness corresponding to the pixel signal.

[0140] Figure 14is a diagram showing another configuration example of a pixel PIX. Pixel PIX includes capacitors C11 and C12, transistors MP12 to MP15, and a light-emitting device EL. Transistors MP12 to MP15 are P-type MOSFETs. Transistor MP12 has a gate connected to control line WSL, a source connected to signal line SGL, and a drain connected to the gate of transistor MP14 and capacitor C12. One end of capacitor C11 is connected to power line VCCP, and the other end is connected to capacitor C12, the drain of transistor MP13, and the source of transistor MP14. One end of capacitor C12 is connected to the other end of capacitor C11, the drain of transistor MP13, and the source of transistor MP14, and the other end is connected to the drain of transistor MP12 and the gate of transistor MP14. Transistor MP13 has a gate connected to control line DSL, a source connected to power line VCCP, and a drain connected to the source of transistor MP14, the other end of capacitor C11, and one end of capacitor C12. The gate of the transistor MP14 is connected to the drain of the transistor MP12 and the other end of the capacitor C12, the source is connected to the drain of the transistor MP13, the other end of the capacitor C11, and one end of the capacitor C12, and the drain is connected to the anode of the light-emitting device EL and the source of the transistor MP15. The gate of the transistor MP15 is connected to the control line AZSL, the source is connected to the drain of the transistor MP14 and the anode of the light-emitting device EL, and the drain is connected to the power supply line VSS.

[0141] With this configuration, in pixel PIX, since transistor MP12 is turned on, the voltage across capacitor C12 is set based on the pixel signal supplied from signal line SGL. Transistor MP13 is turned on and off based on the signal from control line DSL. While transistor MP13 is on, transistor MP14 allows a current corresponding to the voltage across capacitor C12 to flow through light-emitting device EL. Light-emitting device EL emits light based on the current supplied by transistor MP14. In this way, pixel PIX emits light with a brightness corresponding to the pixel signal. Transistor MP15 is turned on and off based on the signal from control line AZSL. During the period when transistor MP15 is on, the voltage at the anode of light-emitting device EL is initialized by being set to the voltage of power supply line VSS.

[0142] Figure 15is a diagram illustrating another configuration example of a pixel PIX. Pixel PIX includes a capacitor C21, transistors MN22 to MN25, and a light-emitting device EL. Transistors MN22 to MN25 are N-type MOSFETs. Transistor MN22 has its gate connected to control line WSL, its drain connected to signal line SGL, and its source connected to the gate of transistor MN24 and capacitor C21. One end of capacitor C21 is connected to the source of transistor MN22 and the gate of transistor MN24, and its other end is connected to the source of transistor MN24, the drain of transistor MN25, and the anode of light-emitting device EL. Transistor MN23 has its gate connected to control line DSL, its drain connected to power supply line VCCP, and its source connected to the drain of transistor MN24. Transistor MN24 has its gate connected to the source of transistor MN22 and one end of capacitor C21, its drain connected to the source of transistor MN23, and its source connected to the other end of capacitor C21, the drain of transistor MN25, and the anode of light-emitting device EL. The transistor MN25 has a gate connected to the control line AZSL, a drain connected to the source of the transistor MN24 , the other end of the capacitor C21 , and the anode of the light emitting device EL, and a source connected to the power supply line VSS.

[0143] With this configuration, in pixel PIX, since transistor MN22 is turned on, the voltage across capacitor C21 is set based on the pixel signal supplied from signal line SGL. Transistor MN23 is turned on and off based on the signal from control line DSL. During the period when transistor MN23 is on, transistor MN24 allows a current corresponding to the voltage across capacitor C21 to flow through light-emitting device EL. Light-emitting device EL emits light based on the current supplied from transistor MN24. In this way, pixel PIX emits light having a brightness corresponding to the pixel signal. Transistor MN25 is turned on and off based on the signal from control line AZSL. During the period when transistor MN25 is on, the voltage at the anode of light-emitting device EL is initialized by being set to the voltage of power supply line VSS.

[0144] Figure 16is a diagram illustrating another configuration example of a pixel PIX. Pixel PIX includes a capacitor C31, transistors MP32 to MP36, and a light-emitting device EL. Transistors MP32 to MP36 are P-type MOSFETs. Transistor MP32 has a gate connected to a control line WSL, a source connected to a signal line SGL, and a drain connected to the gate of transistor MP33, the drain of transistor MP34, and capacitor C31. One end of capacitor C31 is connected to a power supply line VCCP, and the other end is connected to the drain of transistor MP32, the gate of transistor MP33, and the drain of transistor MP34. Transistor MP34 has a gate connected to a control line AZSL1, a source connected to the drain of transistor MP33 and the source of transistor MP35, and a drain connected to the drain of transistor MP32, the gate of transistor MP33, and the other end of capacitor C31. Transistor MP35 has a gate connected to a control line DSL, a source connected to the drain of transistor MP33 and the source of transistor MP34, and a drain connected to the source of transistor MP36 and the anode of light-emitting device EL. The gate of the transistor MP36 is connected to the control line AZSL2 , the source is connected to the drain of the transistor MP35 and the anode of the light emitting device EL, and the drain is connected to the power supply line VSS.

[0145] With this configuration, in pixel PIX, since transistor MP32 is turned on, the voltage across capacitor C31 is set based on the pixel signal supplied from signal line SGL. Transistor MP35 is turned on and off based on the signal from control line DSL. During the period when transistor MP35 is on, transistor MP33 allows a current corresponding to the voltage across capacitor C31 to flow through light-emitting device EL. Light-emitting device EL emits light based on the current supplied by transistor MP33. In this way, pixel PIX emits light with a brightness corresponding to the pixel signal. Transistor MP34 is turned on and off based on the signal from control line AZSL1. The drain and gate of transistor MP33 are connected to each other during the period when transistor MP34 is on. Transistor MP36 is turned on and off based on the signal from control line AZSL2. During the period when transistor MP36 is on, the voltage at the anode of light-emitting device EL is initialized by being set to the voltage of power supply line VSS.

[0146] Figure 17 is a diagram showing another configuration example of a pixel PIX. One end of a capacitor C48 is connected to the signal line SGL1, and the other end is connected to the power supply line VSS. One end of a capacitor C49 is connected to the signal line SGL1, and the other end is connected to the signal line SGL2. A transistor MP49 is a P-type MOSFET having a gate connected to the control line WSL2, a source connected to the signal line SGL1, and a drain connected to the signal line SGL2.

[0147] Pixel PIX includes a capacitor C41, transistors MP42 to MP46, and a light-emitting device EL. Transistors MP42 to MP46 are P-type MOSFETs. Transistor MP42 has a gate connected to control line WSL1, a source connected to signal line SGL2, and a drain connected to the gate of transistor MP43 and capacitor C41. One end of capacitor 41 is connected to power line VCCP, and the other end is connected to the drain of transistor MP42 and the gate of transistor MP43. Transistor MP43 has a gate connected to the drain of transistor MP42 and the other end of capacitor C41, a source connected to power line VCCP, and a drain connected to the sources of transistors MP44 and MP45. Transistor MP44 has a gate connected to control line AZSL1, a source connected to the drain of transistor MP43 and the source of transistor MP45, and a drain connected to signal line SGL2. Transistor MP45 has a gate connected to control line DSL, a source connected to the drain of transistor MP43 and the source of transistor MP44, and a drain connected to the source of transistor MP46 and the anode of light-emitting device EL. The transistor MP46 has a gate connected to the control line AZSL2 , a source connected to the drain of the transistor MP45 and the anode of the light emitting device EL, and a drain connected to the power supply line VSS.

[0148] With this configuration, in pixel PIX, since transistor MP42 is turned on, the voltage across capacitor C41 is set based on the pixel signal supplied from signal line SGL1 via capacitor C49. Transistor MP45 is turned on and off based on the signal on control line DSL. During the period when transistor MP45 is on, transistor MP43 allows a current corresponding to the voltage across capacitor C41 to flow through light-emitting device EL. Light-emitting device EL emits light based on the current supplied by transistor MP43. In this way, pixel PIX emits light with a brightness corresponding to the pixel signal. Transistor MP44 is turned on and off based on the signal on control line AZSL1. During the period when transistor MP44 is on, the drain of transistor MP43 and signal line SGL2 are connected. Transistor MP46 is turned on and off based on the signal on control line AZSL2. During the period when transistor MP46 is on, the voltage at the anode of light-emitting device EL is initialized by being set to the voltage of power supply line VSS.

[0149] Figure 18 1 is a diagram showing another configuration example of the pixel PIX. A plurality of pixels PIX are arranged in a matrix in the display region 100, and the display region 100 is provided between the first control unit 40 and the second control unit 70.

[0150] The first control unit 40 includes transmission gates TG45 and TG46, transistors MP56 and MP57, and a capacitor C61. Transistors MP56 and MP57 are P-type MOSFETs. A pixel signal is supplied to the input of transmission gate TG45, and the output of transmission gate TG45 is connected to one end of signal line 14a. The input of transmission gate TG46 is connected to signal line 14b, and the output of transmission gate TG46 is connected to power line Vorst. One end of capacitor C61 is connected to signal line 14a, and the other end is connected to power line VSS1. Transistor MP56 has a gate connected to control line INIL, a source connected to power line Vini, and a drain connected to signal line 14b. Transistor MP57 has a gate connected to control line ELL, a source connected to power line Vel, and a drain connected to signal line 14b.

[0151] The second control unit 70 includes a transmission gate TG72, a transistor MP73, and a capacitor C82. The transistor MP73 is a P-type MOSFET. The input terminal of the transmission gate TG72 is connected to the other end of the signal line 14a, and the output terminal is connected to the drain of the transistor MP73 and one end of the capacitor C82. The gate of the transistor MP73 is connected to the control line REFL, the source is connected to the power supply line Vref, and the drain is connected to the output terminal of the transmission gate TG72 and one end of the capacitor C82. One end of the capacitor C82 is connected to the output terminal of the transmission gate TG72 and the drain of the transistor MP73, and the other end is connected to one end of the signal line 14b.

[0152] Pixel PIX includes a capacitor C132, transistors MP121 to MP125, and a light-emitting device EL. Transistors MP121 to MP125 are P-type MOSFETs. The gate of transistor MP122 is connected to control line WSL, the source is connected to signal line 14b, and the drain is connected to the gate of transistor MP121 and capacitor C132. One end of capacitor C132 is connected to power line Vel, and the other end is connected to the drain of transistor MP122 and the gate of transistor MP121. The gate of transistor MP121 is connected to the drain of transistor MP122 and the other end of capacitor C132, the source is connected to power line Vel, and the drain is connected to the sources of transistors MP123 and MP124. The gate of transistor MP123 is connected to control line AZSL, the source is connected to the drain of transistor MP121 and the source of transistor MP124, and the drain is connected to signal line 14b. The transistor MP124 has a gate connected to the control line DSL, a source connected to the drain of the transistor MP121 and the source of the transistor MP123, and a drain connected to the drain of the transistor MP125 and the anode of the light-emitting device 130. The transistor MP125 has a gate connected to the control line AZSL, a source connected to the power supply line Vorst, and a drain connected to the drain of the transistor MP124 and the anode of the light-emitting device 130.

[0153] With this configuration, in pixel PIX, since transistor MP122 is turned on, the voltage across capacitor C132 is set based on the pixel signal supplied via transfer gate TG45, signal line 14a, transfer gate TG72, capacitor C82, and signal line 14b. Transistor MP124 is turned on and off based on the signal on control line DSL. During the period when transistor MP124 is on, transistor MP121 allows a current corresponding to the voltage across capacitor C132 to flow through light-emitting device EL. Light-emitting device EL emits light based on the current supplied by transistor MP121. In this way, pixel PIX emits light with a brightness corresponding to the pixel signal. Transistors MP123 and MP125 are turned on and off based on the signal on control line AZSL. During the period when transistor MP123 is on, the drain of transistor MP121 and the source of transistor MP124 are connected to signal line 14b. During the period when transistor MP125 is in the on state, the voltage at the anode of light-emitting device EL is initialized by being set to the voltage of power supply line Vorst. Furthermore, transistor MP56 is turned on and off based on a signal from control line INIL, transistor MP57 is turned on and off based on a signal from control line ELL, and transistor MP73 is turned on and off based on a signal from control line REFL. If transistor MP56 is in the on state, signal line 14b is set to the voltage of power supply line Vini, and if transistor MP57 is in the on state, signal line 14b is set to the voltage of power supply line Vel. If transistor MP73 is in the on state, one end of capacitor C82 is initialized by being set to the voltage of power supply line Vref.

[0154] Figure 19is a diagram illustrating another configuration example of a pixel PIX. Pixel PIX includes a capacitor C51, transistors MP52 to MP60, and a light-emitting device EL. Transistors MP52 to MP60 are P-type MOSFETs. Transistor MP52 has a gate connected to a control line WSL, a source connected to a signal line SGL, and a drain connected to the drain of transistor MP53 and the source of transistor MP54. Transistor MP53 has a gate connected to a control line DSL, a source connected to a power supply line VCCP, and a drain connected to the drain of transistor MP52 and the source of transistor MP54. Transistor MP54 has a gate connected to the source of transistor MP55, a drain of transistor MP57, and capacitor C51, a source connected to the drains of transistors MP52 and MP53, and a drain connected to the sources of transistors MP58 and MP59. Capacitor C51 has one end connected to the power supply line VCCP, and the other end connected to the gate of transistor MP54, the source of transistor MP55, and the drain of transistor MP57. Capacitor C51 may include two capacitors connected in parallel. Transistor MP55 has a gate connected to control line AZSL1, a source connected to the gate of transistor MP54, the drain of transistor MP57, and the other end of capacitor C51, and a drain connected to the source of transistor MP56. Transistor MP56 has a gate connected to control line AZSL1, a source connected to the drain of transistor MP55, and a drain connected to power supply line VSS. Transistor MP57 has a gate connected to control line WSL, a drain connected to the gate of transistor MP54, the source of transistor MP55, and the other end of capacitor C51, and a source connected to the drain of transistor MP58. Transistor MP58 has a gate connected to control line WSL, a drain connected to the source of transistor MP57, and a source connected to the drain of transistor MP54 and the source of transistor MP59. Transistor 59 has a gate connected to control line DSL, a source connected to the drain of transistor MP54 and the source of transistor MP58, and a drain connected to the source of transistor MP60 and the anode of light-emitting device EL. The gate of the transistor MP60 is connected to the control line AZSL2 , the source is connected to the drain of the transistor MP59 and the anode of the light emitting device EL, and the drain is connected to the power supply line VSS.

[0155] With this configuration, in pixel PIX, since transistors MP52, MP54, MP58, and MP57 are turned on, the voltage across capacitor C51 is set based on the pixel signal supplied from signal line SGL. Transistors MP53 and MP59 are turned on and off based on the signal from control line DSL. During the period when transistors MP53 and MP59 are on, transistor MP54 allows a current corresponding to the voltage across capacitor C51 to flow through light-emitting device EL. Light-emitting device EL emits light based on the current supplied by transistor MP54. In this way, pixel PIX emits light with a brightness corresponding to the pixel signal. Transistors MP55 and MP56 are turned on and off based on the signal from control line AZSL1. During the period when transistors MP55 and MP56 are on, the voltage at the gate of transistor MP54 is initialized by being set to the voltage of power supply line VSS. Transistor MP60 is turned on and off based on the signal from control line AZSL2. During a period in which the transistor MP60 is in the on state, the voltage of the anode of the light emitting device EL is initialized by being set to the voltage of the power line VSS.

[0156] Figure 20 1 is a diagram showing another configuration example of the pixel PIX. The signal of the control line WSNL and the signal of the control line WSPL are inverted signals.

[0157] Pixel PIX includes capacitors C61 and C62, transistors MN63, MP64, and MN65 to MN67, and a light-emitting device EL. Transistors MN63, MN65, and MN67 are N-type MOSFETs, and transistor MP64 is a P-type MOSFET. The gate of transistor MN63 is connected to the control line WSNL, the drain is connected to the signal line SGL and the source of transistor MP64, and the source is connected to the drain of transistor MP64, capacitors C61 and C62, and the gate of transistor MN65. The gate of transistor MP64 is connected to the control line WSPL, the source is connected to the signal line SGL and the drain of transistor MN63, and the drain is connected to the source of transistor MN63, capacitors C61 and C62, and the gate of transistor MN65. Capacitor C61, for example, comprises a metal-oxide-metal (MOM) capacitor and has one end connected to the source of transistor MN63, the drain of transistor MP64, capacitor C62, and the gate of transistor MN65, and the other end connected to power supply line VSS2. Note that capacitor C61 can be configured using, for example, a MOS capacitor or a metal-insulator-metal (MIM) capacitor. Capacitor C62 comprises, for example, a MOS capacitor and has one end connected to the source of transistor MN63, the drain of transistor MP64, one end of capacitor C61, and one end of the gate of transistor MN65, and the other end connected to power supply line VSS2. Note that capacitor C62 can be configured using, for example, a MOM capacitor or a MIM capacitor. Transistor MN65 has a gate connected to the source of transistor MN63, the drain of transistor MP64, and one end of capacitors C61 and C62, a drain connected to power supply line VCCP, and a source connected to the drains of transistors MN66 and MN67. Transistor MN66 has a gate connected to control line AZL, a drain connected to the source of transistor MN65 and the drain of transistor MN67, and a source connected to power supply line VSS1. Transistor MN67 has a gate connected to control line DSL, a drain connected to the source of transistor MN65 and the drain of transistor MN66, and a source connected to the anode of light-emitting device EL.

[0158] With this configuration, in pixel PIX, since at least one of transistors MN63 or MP64 is turned on, the voltage across capacitors C61 and C62 is set based on the pixel signal supplied from signal line SGL. Transistor MN67 is turned on and off based on the signal from control line DSL. During the period when transistor MN67 is on, transistor MN65 allows a current corresponding to the voltage across capacitors C61 and C62 to flow through light-emitting device EL. Light-emitting device EL emits light based on the current supplied from transistor MP65. In this manner, pixel PIX emits light having a brightness corresponding to the pixel signal. Transistor MN66 can be turned on and off based on the signal from control line AZL. Furthermore, transistor MN66 can function as a resistor having a resistance value corresponding to the signal from control line AZL. In this case, transistors MN65 and MN66 form a so-called source follower circuit.

[0159] <2. Application Examples>

[0160] Next, application examples of the display systems described in the above-mentioned embodiments and modifications will be described.

[0161] (First Application Example)

[0162] Figure 21 1 is a diagram showing an example of the appearance of a head-mounted display 110. For example, the head-mounted display 110 includes ear hooks 112 worn on the user's head on both sides of a glass-shaped display unit 111. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 110.

[0163] (Second application example)

[0164] Figure 22 This figure shows an example of the appearance of another head-mounted display 120. The head-mounted display 120 is a transmissive head-mounted display that includes a main body 121, an arm 122, and a lens barrel 123. The head-mounted display 120 is mounted on glasses 128. The main body 121 includes a control panel for controlling the operation of the head-mounted display 120, as well as a display unit. The display unit emits image light that displays an image. The arm 122 connects the main body 121 and the lens barrel 123 and supports the lens barrel 123. The lens barrel 123 projects the image light, which is provided from the main body 121 via the arm 122, toward the user's eyes via lenses 129 of the glasses 128. The techniques described in the above embodiments and the like can be applied to this head-mounted display 120.

[0165] Note that the head-mounted display 120 is a so-called light guide plate head-mounted display, but is not limited thereto and may be, for example, a so-called birdbath head-mounted display. For example, a birdbath head-mounted display includes a beam splitter and a partially transparent reflector. The beam splitter outputs light encoded with image information to the reflector, and the reflector reflects the light toward the user's eyes. Both the beam splitter and the partially transparent reflector are partially transparent. As a result, light from the surrounding environment reaches the user's eyes.

[0166] (Third Application Example)

[0167] Figure 23 and Figure 24 is a diagram showing an example of the appearance of a digital camera 130, Figure 23 shows a front view, and Figure 24 A rear view is shown. The digital camera 130 is a single-lens reflex camera with interchangeable lenses and includes a camera body (camera body) 131, an imaging lens unit 132, a grip 133, a monitor 134, and an electronic viewfinder 135. The imaging lens unit 312 is an interchangeable lens unit and is disposed approximately near the center of the front surface of the camera body 311. The grip 133 is disposed on the left side of the front surface of the camera body 311, and the camera operator grips the grip 133. The monitor 134 is disposed on the left side of the approximately center of the back surface of the camera body 131. The electronic viewfinder 135 is disposed above the monitor on the back surface of the camera body 131. By observing the electronic viewfinder 135, the camera operator can visually recognize the optical image of the subject guided from the imaging lens unit 132 and determine the composition. The technology according to the above-described embodiment and the like can be applied to the electronic viewfinder 135.

[0168] (Fourth Application Example)

[0169] Figure 25 140 is a diagram showing an example of the appearance of a television device 140. The television device 140 includes a video display screen section 141 including a front panel 142 and a filter glass 143. The technology according to the above-described embodiment and the like can be applied to the video display screen section 141.

[0170] (Fifth Application Example)

[0171] Figure 26 1 is a diagram showing an example of the appearance of a smartphone 150. The smartphone 150 includes a display section 151 that displays various types of information and an operation section 152 including buttons and the like that receives user input operations. The techniques according to the above-described embodiments and the like can be applied to the display section 151.

[0172] (Sixth Application Example)

[0173] Figure 27 and Figure 28 is a diagram showing a configuration example of a vehicle to which the technology of the present disclosure is applied, Figure 27 An example of the interior of the vehicle viewed from the rear of the vehicle 200 is shown, and Figure 28 An example of the interior of the vehicle viewed from the left rear of the vehicle 200 is shown.

[0174] Figure 27 and Figure 28 The vehicle includes a central display 201 , a console display 202 , a head-up display 203 , a digital rearview mirror 204 , a steering wheel display 205 and a rear entertainment display 106 .

[0175] The central display 201 is arranged on the instrument panel 261 in a position facing the driver's seat 262 and the passenger seat 263 . Figure 27 While the central display 201 is shown as having a horizontally long shape extending from the driver's seat 262 to the passenger seat 263, the screen size and placement of the central display 201 are not limited thereto. The central display 201 can display information detected by various sensors. Specifically, the central display 201 can display images captured by an image sensor, distance images to obstacles in front of or to the side of the vehicle measured by a Time of Flight sensor, and the occupant's body temperature detected by an infrared sensor. The central display 201 can be used to display, for example, at least one of safety-related information, operational-related information, a life log, health-related information, authentication / identification-related information, or entertainment-related information.

[0176] Safety-related information includes information such as dozing off detection, gaze aversion detection, mischief detection by children traveling with the passenger, seatbelt wearing, and detection of occupant departure based on sensor detection results. Operation-related information includes information about occupant gestures detected using sensors. These gestures may include the operation of various vehicle features, such as the air conditioning system, navigation system, audio-visual (AV) equipment, and lighting. A life log includes the life logs of all occupants. For example, a life log includes a record of each occupant's movements. By acquiring and storing life logs, the occupant's condition at the time of an accident can be confirmed. Health-related information includes information about the occupant's body temperature detected using a temperature sensor and the occupant's health status estimated based on the detected body temperature. Alternatively, information about the occupant's health status can be estimated based on the occupant's face captured by an image sensor. Furthermore, information about the occupant's health status can be estimated based on the occupant's responses obtained by communicating with the occupant using automated voice recognition. Authentication / identification-related information includes information such as that used for keyless entry functions using sensors for facial authentication and automatic seat height and position adjustment functions using facial recognition. The entertainment-related information includes operation information of an AV device of an occupant detected by a sensor, information of content suitable for the occupant detected and identified by the sensor, and the like.

[0177] For example, console display 202 can be used to display life log information. Console display 202 is located near shift lever 265 in center console 264 between driver's seat 262 and passenger seat 263. Console display 202 can also display information detected by various sensors. Furthermore, console display 202 can display images of the vehicle's surroundings captured by an image sensor, or can display distance images to obstacles around the vehicle.

[0178] A head-up display 203 is virtually displayed behind a windshield 266 in front of a driver's seat 262. The head-up display 203 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, or entertainment-related information. Since the head-up display 203 is typically virtually positioned in front of the driver's seat 262, it is suitable for displaying information directly related to vehicle operation, such as the vehicle's speed, remaining fuel level, and remaining battery level.

[0179] The digital rearview mirror 204 can not only display the rear of the vehicle, but also display the status of rear seat passengers, and thus can be used to display life log information of rear seat passengers, for example.

[0180] Steering wheel display 205 is positioned near the center of the vehicle's steering wheel 267. Steering wheel display 205 can be used to display at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, or entertainment-related information. Specifically, steering wheel display 205 is positioned close to the driver's hands and is therefore suitable for displaying life log information such as the driver's body temperature, or information regarding the operation of AV devices, air conditioning equipment, and the like.

[0181] Rear entertainment display 206 is attached to the rear sides of driver's seat 262 and passenger seat 263 and is intended for viewing by rear-seat occupants. Rear entertainment display 206 can be used to display, for example, at least one of safety-related information, operational-related information, a life log, health-related information, authentication / identification-related information, or entertainment-related information. Specifically, because rear entertainment display 206 is located in front of the rear-seat occupants, it displays information relevant to the rear-seat occupants. Rear entertainment display 206 can display, for example, information regarding the operation of an AV device or air conditioning system, or the results of a temperature sensor measuring the rear-seat occupant's body temperature.

[0182] The technology according to the above-described embodiment and the like can be applied to the center display 201 , the console display 202 , the head-up display 203 , the digital rearview mirror 204 , the steering wheel display 205 , and the rear entertainment display 206 .

[0183] Note that the present technology can have the following configurations. (1)

[0185] A display device, comprising:

[0186] a supply unit configured to supply a pixel voltage indicating a brightness level of each pixel via a plurality of wirings;

[0187] a plurality of switching devices, one end of each of the plurality of switching devices being connected to the plurality of wirings;

[0188] a plurality of data lines connected to the other ends of the plurality of switching devices;

[0189] a plurality of pixels connected to each of the plurality of data lines and configured to emit light based on a pixel voltage; and

[0190] The capacitance adjustment unit is configured to adjust line capacitances of adjacent wirings among the plurality of wirings. (2)

[0192] The display device according to (1), wherein the capacitance adjustment unit makes the potential difference between adjacent wirings within a predetermined value when pixel voltages having the same potential are applied to adjacent wirings among the plurality of wirings. (3)

[0194] The display device according to (1), wherein the adjustment capacitance unit is a conductive line electrically connected to an adjacent wiring. (4)

[0196] The display device according to (3), wherein the longer the length of the adjacent wiring is, the shorter the length of the conductive line is. (5)

[0198] The display device according to (1), wherein at least a partial range of the wiring adjacent to the capacitor unit is adjusted, and the cross-sectional area of ​​the wiring in the partial range is made different. (6)

[0200] The display device according to (5), wherein the longer the length of the adjacent wiring is, the smaller the cross-sectional area is. (7)

[0202] The display device according to (1), wherein the capacitance unit is adjusted in at least a partial range of adjacent wirings, and the resistance in the partial range is made uniform. (8)

[0204] The display device according to (7), wherein, in the adjustment capacitance unit, a shape of at least a partial range of the adjacent wirings is different for each of the adjacent wirings. (9)

[0206] The display device according to (1), wherein the adjustment capacitance unit is a capacitance connected to an adjacent wiring. (10)

[0208] The display device according to (9), wherein the longer the length of the adjacent wiring is, the smaller the capacitance is. (11)

[0210] The display device according to (10), wherein the capacitor includes a MOM (metal-oxide-metal) capacitor or a MIM (metal-insulator-metal) capacitor. (12)

[0212] The display device according to (1), wherein

[0213] The supply unit includes a plurality of pads arranged in a two-dimensional manner, and

[0214] One end of the plurality of wirings is connected to each of the plurality of pads. (13)

[0216] The display device according to (12), wherein the adjustment capacitance unit is a conductive line electrically connected to each of the pads, and the longer the length of the adjacent wiring is, the shorter the length of the conductive line is. (14)

[0218] The display device according to (13), wherein the conductive line is not arranged within a range vertically above or vertically below the pad. (15)

[0220] The display device according to (13), wherein the conductive line is arranged in a range vertically above or below a pad to which the conductive line is connected, and is not arranged in a range vertically above or below a pad to which the conductive line is not connected. (16)

[0222] The display device according to (15), wherein the conductive line is electrically connected to each of the contacts of the pad. (17)

[0224] The display device according to (16), wherein the conductive line is an internal wiring of the supply unit. (18)

[0226] The display device according to (1), wherein the switching device is a MOS transistor. (19)

[0228] The display device according to (1), wherein

[0229] Pixels consist of self-luminous devices whose light emission can be individually controlled.

[0230] The display device further includes a signal processing unit configured to generate a second video signal corresponding to pixel data displayed on the plurality of pixels based on the first video signal,

[0231] The supply unit includes a plurality of amplifiers connected to each of the pads and configured to supply a pixel voltage based on the second video signal, and

[0232] The supply unit and the signal processing unit are stacked. (20)

[0234] The display device according to (2), wherein the adjustment capacitance unit reduces the potential difference between the wirings to such an extent that the luminance difference when pixels connected to adjacent wirings emit light is not visually recognized as a linear step.

[0235] The various aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that can be thought of by those skilled in the art, and the effects of the present disclosure are not limited to the above. In other words, various additions, changes, and partial deletions can be made without departing from the conceptual concept and spirit of the present disclosure obtained from the contents defined in the claims and their equivalents.

[0236] Reference Symbols List

[0237] 1 display device, 4, 4a, PIX pixel, 15 data line driving unit, 19 adjustment capacitor unit, 160, EL self-luminous device, Amp amplifier, C1 to Cm capacitors, Clin, Clinm line capacitors, Con1 to Conm contacts, DL data line, L1a to L1m wiring, L1b to Lmb wire, L1c to Lmc wire, L1d to Lmd wiring, L1e to Lme wire, L1f to Lmf, IC internal wiring, P1 to Pm pads, Q3 connection transistor.

Claims

1. A display device, comprising: a supply unit configured to supply a pixel voltage indicating a brightness level of each pixel via a plurality of wirings; a plurality of switching devices, one end of each of the plurality of switching devices being connected to the plurality of wirings; a plurality of data lines connected to the other ends of the plurality of switching devices; a plurality of pixels connected to each of the plurality of data lines and configured to emit light based on the pixel voltage; as well as The capacitance adjustment unit is configured to adjust line capacitances of adjacent wirings among the plurality of wirings.

2. The display device according to claim 1, wherein The capacitance adjustment unit makes a potential difference between adjacent wirings among the plurality of wirings fall within a predetermined value when pixel voltages having the same potential are applied to the adjacent wirings.

3. The display device according to claim 1, wherein The adjusting capacitance unit is a conductive line electrically connected to the adjacent wiring.

4. The display device according to claim 3, wherein The longer the length of the adjacent wiring is, the shorter the length of the conductive wire is.

5. The display device according to claim 1, wherein The capacitance adjustment unit is at least a portion of the adjacent wirings, and the cross-sectional areas of the wirings in the portion are made different. The display device according to claim 5 , wherein: The longer the length of the adjacent wirings is, the smaller the cross-sectional area is.

7. The display device according to claim 1, wherein The capacitance adjustment unit is at least a partial range of the adjacent wirings, and makes the resistance in the partial range the same.

8. The display device according to claim 7, wherein: In the capacitance adjustment unit, a shape of at least a partial range of the adjacent wirings is different for each of the adjacent wirings.

9. The display device according to claim 1, wherein The adjustment capacitance unit is a capacitor connected to the adjacent wiring.

10. The display device according to claim 9, wherein The longer the length of the adjacent wiring is, the smaller the capacitance is.

11. The display device according to claim 10, wherein: The capacitor includes a MOM (metal-oxide-metal) capacitor or a MIM (metal-insulator-metal) capacitor.

12. The display device according to claim 1, wherein The supply unit includes a plurality of pads arranged in a two-dimensional manner, and One end of the plurality of wirings is connected to each of the plurality of pads.

13. The display device according to claim 12, wherein: The adjusting capacitance unit is a conductive line electrically connected to each of the pads, and the longer the length of the adjacent wiring is, the shorter the length of the conductive line is.

14. The display device according to claim 13, wherein: The conductive line is not arranged in a range vertically above or vertically below the pad.

15. The display device according to claim 13, wherein The conductive line is arranged in a range vertically above or below the pad to which the conductive line is connected, and is not arranged in a range vertically above or below the pad to which the conductive line is not connected.

16. The display device according to claim 15, wherein The conductive line is electrically connected to each of the contacts of the pad.

17. The display device according to claim 16, wherein: The conductive wires are internal wiring of the supply unit.

18. The display device according to claim 1, wherein The switching device is a MOS transistor.

19. The display device according to claim 1, wherein The pixels include self-luminous devices capable of individually controlling light emission, The display device further includes a signal processing unit configured to generate a second video signal corresponding to pixel data displayed on the plurality of pixels based on the first video signal, The supply unit includes a plurality of amplifiers connected to each of the pads and configured to supply the pixel voltage based on the second video signal, and The supply unit and the signal processing unit are stacked.

20. The display device according to claim 2, wherein The adjustment capacitance unit reduces the potential difference between the adjacent wirings to such an extent that a luminance difference when pixels connected to the adjacent wirings emit light is not visually recognized as a linear step.

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