Methods and semiconductor devices

Abstract

In at least one embodiment, a method for producing a semiconductor device (1) includes: A) providing a semiconductor body (2) based on a group IV semiconductor material, B) doping a first region (21) in the semiconductor body (2) of a first conductivity type and starting from a surface (20) of the semiconductor body (2), and C) forming a recess (3) in the semiconductor body (2) by selectively and wet chemically etching the first region (21).

Description

Technical Field

[0001] A method for manufacturing a semiconductor device is provided. A corresponding semiconductor device is also provided. Background Technology

[0002] Document US2009 / 0174002 A1 discloses a method for selectively removing source and drain extension regions by dopant concentration-dependent etching or dopant type-dependent etching, and growing embedded stress-generating materials, such as SiGe alloys or Si:C alloys, on a semiconductor substrate within the source and drain extension regions. The embedded stress-generating materials can be grown only in the source and drain extension regions, or in both the source and drain extension regions and in deep source and drain regions. An etching process can be employed that selectively removes doped semiconductor regions of one conductivity type while retaining doped semiconductor regions of another conductivity type. Alternatively, a dopant concentration-dependent etching process can be employed that selectively removes doped semiconductor regions without affecting undoped semiconductor regions, regardless of their conductivity type.

[0003] Document US2013 / 0330896 A1 discloses a method for manufacturing a silicon carbide semiconductor device, the method comprising: forming a drift layer on a silicon carbide substrate; forming a base region on or therein a surface portion of the drift layer; forming a source region in the surface portion of the base region; forming a trench penetrating the base layer and reaching the drift layer; forming a gate electrode on a gate insulating film in the trench; forming a source electrode electrically connected to the source region and the base region; and forming a drain electrode on the back side of the substrate. The formation of the trench includes: planarizing the substrate surface; and forming the trench by etching after planarization.

[0004] Document US2020 / 0119141 A1 discloses a gate interconnect layer including a portion disposed on an external trench, with a gate insulating film disposed therebetween. A first main electrode includes a main contact portion electrically connected to a well region and a first impurity region in an active region; it also includes an external contact portion spaced apart from the active region and contacting the bottom surface of the external trench. A trench bottom electric field mitigation region is disposed in the drift layer. An impurity concentration in a high-concentration region at the bottom of the trench is higher than that in the trench bottom electric field mitigation region; this high-concentration region is disposed on the trench bottom electric field mitigation region and extends from a position opposite to the gate interconnect layer (separated by the gate insulating film) to a position contacting the external contact portion of the first main electrode.

[0005] Document US2015 / 0333175 A1 discloses a method for manufacturing a semiconductor device, comprising the steps of: forming a semiconductor layer comprising a first semiconductor region of a first conductivity type on a main surface of a substrate; and forming a trench in the semiconductor layer with its bottom located in the first semiconductor region. The method further includes the step of forming a trench bottom doped region of a second conductivity type covering the bottom of the trench, wherein the step involves annealing to move a portion of the semiconductor layer corresponding to the upper corner portion of the trench to be positioned at the bottom of the trench.

[0006] Document EP 1 011 130 A1 relates to a method for fabricating a silicon-based accelerometer using electrochemical etching.

[0007] Document US2022 / 0399442 A1 discloses a power semiconductor device having a recess in the semiconductor body.

[0008] The paper "Analysis of Photoelectrochemical Processes in α-SiC substrates with Atomically Flat Surfaces" published by H. Mikami et al. in the Japanese Journal of Applied Physics, Vol. 44, 8329 (2005), DOF 10.1143 / JJAP.44.8329 involves the etching of SiC.

[0009] The paper "Deep levels induced by reactiveion etching in n-and p-type 4H–SiC" published by K. Kawahara et al. in the Journal of Applied Physics, Vol. 108, 023706 (2010), DOI: 10.1063 / 1.3460636 discusses energy levels in SiC.

[0010] The paper "Highperformance SiC trench devices with ultra-low ron" published by T. Nakamura et al. at the "2011 International Electron Devices Meeting" in December 2011, DOI:10.1109 / IEDM.2011.6131619, involves SiC-based MOSFETs.

[0011] The papers "Optical properties of mesoporous 4H-SiC prepared by anodic electrochemical etching" by M. Rashid et al. in "Journal of Applied Physics", Vol. 120, 194303 (2016), DOI:10.1063 / 1.4968172, and "Systematic Characterization of Plasma-Etched Trenches on 4H-SiC Wafers" by MDPirnaci et al. in "ACS Omega", Vol. 6, 20667 (2021), DOI:10.1021 / acsomega.1c02905, both relate to SiC properties related to SiC processing.

[0012] The papers “Vertical and bevel-structured SiC etching techniques incorporating different gas mixture plasmas for various microelectronic applications” published by HKSung et al. in Scientific Reports, Vol. 7, 3915 (2017), DOI:10.1038 / s41598-017-04389-y, and “Surface polishing by electrochemical etching of p-type 4H SiC” published by Y. Ke et al. in Journal of Applied Physics, Vol. 106, 064901 (2009), DOI:10.1063 / 1.3212541, both involve the roughness produced by etching SiC. Summary of the Invention

[0013] The goal is to provide a method for the efficient production of semiconductor devices.

[0014] This objective is achieved, in particular, by a method and a semiconductor device as defined in the independent patent claim. Exemplary further developments constitute the subject matter of the dependent claims.

[0015] For example, using this method, trenches are generated in SiC trench MOSFETs by ion implantation and selective wet etching of the ion-implanted regions.

[0016] In at least one embodiment, the method is used to produce a semiconductor device and includes, for example, the following steps in the stated order:

[0017] A) Provide a semiconductor body based on group IV semiconductor materials.

[0018] B) Doping one or more first regions in the semiconductor body, at least one first region being of a first conductivity type, and starting from, for example, the surface of the semiconductor body, and

[0019] C) A recess is formed in the semiconductor body by selectively and wet chemically etching the at least one first region. Optionally, the finished semiconductor device is one of a metal-insulator-semiconductor field-effect transistor (MISFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), or a reverse-biased insulated-gate bipolar transistor (RC-IGBT). Further optionally, the method may further include:

[0020] D) In ​​the semiconductor body, on the side of the first region away from the surface, a second region of the second conductivity type is doped, and the etching in step C) automatically stops at the second region, such that after step C), the second region is located directly at the bottom surface of the recess away from the semiconductor body surface (20), the root mean square RMS roughness of the bottom surface is at most 15 nm, and the second region is configured as a shielding region in the finished semiconductor device.

[0021] Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE) is a selective dry etching fabrication process used to form trenches, mesas, etc. This process relies on mask deposition, offers good accuracy and reproducibility, and can be used for SiC device fabrication. Due to the chemical inertness of SiC, for example, different types of plasma can be used, typically chloride or fluoride, and mixtures of oxygen and inert gases can also be used. The etching rate depends on the plasma and also on the power consumed, ranging from 500 nm / min to at most 800 nm / min. Among the adverse effects of using ICP-RIE, for example, inhomogeneities may appear on the bottom surface of SiC trenches due to reflection of plasma ions on the sidewalls. This inhomogeneity may occur on the sidewalls themselves, resulting in micro-trenches. This adverse effect can be avoided by additional processing steps (such as sidewall passivation layers) or by adding oxides to the Cl-based plasma. Another adverse effect may be the formation of carbon vacancies in the etched epitaxial layer, i.e., in the epitaxially grown semiconductor layer. Furthermore, the RIE may generate two electroactive levels, labeled IN6 and EN, at 1.0 eV and 1.6 eV below the conduction band edge, respectively, according to the literature of K. Kawahara et al. as described above.

[0022] Therefore, in order to improve semiconductor devices, the method described in this paper can produce SiC trench devices without the use of RIE.

[0023] Instead of RIE, the method described herein performs ion implantation and electrochemical etching (ECE) to form trenches. ECE is a selective wet chemical etching method. ECE involves immersing the area to be etched in a solution, such as HF-based solutions. SiC wafers can be used as the anode in the solution. The etching rate can be controlled by varying the current density. Etching occurs only in areas of the correct conductivity type (i.e., depending on the applied potential), which are conductive, for example, with a resistivity of about 0.03 Ωcm, while areas with higher resistivity remain intact. It is also possible to etch materials with opposite conductivity types by reversing the polarity of the applied potential. Etching rates can be as high as 200 μm / h.

[0024] Unlike RIE, the method described in this paper does not require an etching endpoint detection system because ECE stops when a region with a different doping concentration is reached. Furthermore, unlike RIE, trench ECE avoids point defects (such as carbon vacancies V0). C The formation of ) In addition, ECE leads to a reduction in the roughness of the etched surface; for example, Cl-based RIE will produce a surface roughness of about 60 nm to 70 nm, while ECE can produce a surface roughness of about 2 nm to 7 nm (RMS).

[0025] By injecting, trenches of any depth and shape can be defined, and then ECE forms these trenches much faster than RIE.

[0026] For example, plasma immersion ion implantation (PIII) following trench ECE can form an electric field confinement layer and remove any potential V-type defects formed by ion implantation. C .

[0027] Using the method described herein, V-grooves and the like can be fabricated by tilted ion implantation (e.g., at an angle of 54.7° for the 0-33-8 plane).

[0028] X-ray photoelectron spectroscopy (XPS) can be used to reverse engineer the final product. Compared with RIE-etched 4H-SiC, ECE-etched 4H-SiC exhibits unique characteristics in the energy range of 280 eV to 290 eV, as described above in the literature of M. Rashid et al. and MDPirnaci et al.

[0029] Reverse engineering of the final product can also be performed using deep-level transient spectroscopy (DLTS). The presence of ON1, ON2, and IN2 energy levels after implantation of n-type SiC indicates the use of an ECE-based method, see the literature of T. Nakamura et al. as mentioned above. Similarly, the presence of HK0, IP5, IP7, and IP8 energy levels after implantation of p-type SiC indicates the use of an ECE-based method, also see the literature of T. Nakamura et al. as mentioned above.

[0030] According to at least one embodiment, the group IV semiconductor material (also known as the group 14 semiconductor material) is C (such as diamond), Si, Ge, or any mixture thereof, such as SiC. In particular, the semiconductor material is SiC, such as stoichiometric SiC.

[0031] According to at least one embodiment, the first region is defined by doping. That is, all regions that begin at the surface and are doped in step B) can be referred to as the first region. In other words, the first region is defined by doping in step B). However, multiple first regions can be defined by doping in step B), but one or some of these first regions will not be etched; such a first region may be covered by another material before step C). In the following, such a region covered by another material and not configured for etching is not referred to as a first region because such a region does not begin at the surface as described in this context.

[0032] According to at least one embodiment, the recesses in the semiconductor body are formed solely by wet chemical etching of the first region. Therefore, all material removal that produces the recesses originates from the wet chemical etching process.

[0033] According to at least one embodiment, wet chemical etching is selective etching. This means, for example, that the etching rate during wet chemical etching of the first region is at least 10 times, or at least 100 times, or at least 10 times the etching rate of other regions of the semiconductor body exposed to the etching liquid used for wet chemical etching. 3 times, or at least 10 4 times, or at least 10 5 Therefore, "selectively" can mean that only at least one first region is actually etched, and no significant material removal occurs in other regions of the semiconductor body.

[0034] According to at least one embodiment, at least one first region exposed to the etching liquid is completely etched away. Therefore, the corresponding at least one first region will not remain in the finished semiconductor device.

[0035] According to at least one embodiment, the etching liquid is an acid or a solution containing at least one acid. For example, the etching liquid is an HF-based solution. For example, the HF-based solution is a mixture of 5% to 10% aqueous HF and ethanol at a ratio of 1:1 or 2:1. Alternatively, for example, a ratio of HF (50%):acetic acid:H2O of 4:6:2 or 1:1:5 can be used.

[0036] According to at least one embodiment, in the ECE, the applied voltage is selected such that the current density is maintained at at least 10 mA / cm². 2 and / or up to 80 mA / cm 2 .

[0037] According to at least one embodiment, method step B) includes:

[0038] B1) Applying a potential to the semiconductor body such that at least a portion of the semiconductor body is used as an etching electrode, and

[0039] B2) The first region is removed by means of electrochemical etching (ECE, which is wet chemical etching).

[0040] Therefore, ECE is used to selectively remove at least one first region.

[0041] According to at least one embodiment, when the first conductivity type is p-type conductivity, the etching electrode is a cathode, or when the first conductivity type is n-type conductivity, the etching electrode is an anode. That is, if the first region is p-type conductivity, a negative voltage is applied to the semiconductor body, and correspondingly, if the first region is n-type conductivity, a positive voltage is applied to the semiconductor body.

[0042] According to at least one embodiment, the etched electrode is formed from at least a portion of the semiconductor substrate of the semiconductor body. For example, the portion is located on the side of the semiconductor body away from the surface. For example, this surface is the top surface of the semiconductor body opposite to the substrate. This top surface may be oriented perpendicular to the growth direction of the epitaxial layer of the semiconductor body.

[0043] According to at least one embodiment, the first region has a first doping concentration that is at least 10 times, or at least 10 times, the doping concentration of a second doping concentration of the semiconductor body material adjacent to the first region and also of the first conductivity type. 2 The doping concentration is at least 100 times, or even 100 times, higher. Correspondingly, the first region is also embedded in a semiconductor material of the first conductivity type, but with a lower doping concentration. Alternatively or additionally, the semiconductor body adjacent to the first region has a second conductivity type different from the first conductivity type. For example, in the latter case, the first region is n-type doped and embedded in a p-type doped region, or vice versa. The two cases described above can be mixed.

[0044] According to at least one embodiment, the resistivity of the first region is at most 10 Ωcm, or at most 1 Ωcm, or at most 0.1 Ωcm; this also applies to the etching electrode. Accordingly, the first region can be considered conductive, as is the case for the etching electrode. If the semiconductor material adjacent to the first region in the semiconductor body has the same first conductivity type, then the resistivity of the adjacent semiconductor material is, for example, greater than 10 Ωcm, or at least 0.1 kΩcm or at least 1 kΩcm. The aforementioned values ​​can be applied to room temperature, i.e., 293 K.

[0045] According to at least one embodiment, the etching electrode and at least one first region are spaced apart from each other. That is, the etching electrode and at least one first region do not contact each other. For example, a non-conductive semiconductor material, i.e., a semiconductor material with a resistivity greater than 10 Ωcm, or at least 0.1 kΩcm, or at least 1 kΩcm, may be present between the etching electrode and at least one first region. The distance between the etching electrode and at least one first region may be at least 1 μm, or at least 5 μm, or at least 40 μm.

[0046] According to at least one embodiment, in a cross-section perpendicular to the top side of the semiconductor body, the recess narrows monotonically or strictly monotonically in a direction away from the top side. "Monotonically" means that the thickness t at position x is equal to or greater than the thickness t' at a position x+d further from the top side: t(x) ≥ t'(x+d), where d is a distance greater than zero, d>0. Therefore, in the strictly monotonically case, t(x) > t'(x+d) applies. This can apply to the actual sidewalls of the recess, or to virtual sidewalls of the recess, visible in a cross-section perpendicular to the top side of the recess and / or a cross-section perpendicular to the main extension direction of the recess (the main extension direction is determined in the top view of the top side), which is the best-fitting straight line through the roughened portion of the actual sidewall.

[0047] According to at least one embodiment, the recess is formed without using reactive ion etching (RIE).

[0048] According to at least one embodiment, in step B), the first region is doped by means of ion implantation. Alternatively or additionally, in step B), doping is performed by means of epitaxial growth.

[0049] According to at least one embodiment, the recess is a groove. For example, the aspect ratio of the maximum depth to the maximum width of the groove is at least 0.8, or at least 1, or at least 1.0, or at least 2. Alternatively or additionally, the aspect ratio is at most 20, or at most 10, or at most 5.

[0050] According to at least one embodiment, the method further includes:

[0051] D) Doping at least one second region of a second conductivity type in the semiconductor body, either directly and exclusively or at least on one side of the recess or on the side of the first region away from the surface. The at least one second region may be located away from or directly in the first region or the recess. Therefore, the second region can be formed by doping before or after etching the recess.

[0052] According to at least one embodiment, the second region is configured as a shielding region. That is, the second region is highly doped and may be conductive. For the definition of "conductive", see the definition provided above in the context of the first region.

[0053] According to at least one embodiment, the maximum depth of the recess is at least 1 μm, or at least 5 μm, or at least 15 μm. Alternatively or additionally, the maximum depth is at most 0.1 mm, or at most 50 μm, or at most 30 μm.

[0054] According to at least one embodiment, the maximum doping concentration of the first region is at least 10. 18 cm -3 or at least 5x10 18 cm -3 or at least 1x 10 19 cm -3 Alternatively or additionally, the doping concentration is at most 10. 21 cm -3 or at most 5x10 20 cm -3 .

[0055] According to at least one embodiment, the recess is formed in an epitaxial growth layer of the semiconductor body. During growth, all said layers can be of a first conductivity type. For example, the doping concentration of said layers during growth is at most 10. 16 cm -3 or at most 5x10 15 cm -3 Alternatively or additionally, the doping concentration is at least 5 x 10⁻⁶. 14 cm -3 or at least 1x 10 15 cm -3 .

[0056] According to at least one embodiment, after the recess is formed, the method further includes:

[0057] E1) Apply an electrically insulating film to the wall of the recess, and

[0058] E2) provides a gate electrode in the recess.

[0059] Therefore, the finished semiconductor device may include a gate electrode housed in a trench (i.e., housed in a recess).

[0060] A semiconductor device is also provided. Using this method, the semiconductor device can be manufactured as indicated in at least one embodiment described above. Therefore, features of the semiconductor device are also disclosed with respect to this method, and vice versa.

[0061] In at least one embodiment, the semiconductor device includes a semiconductor body based on a group IV semiconductor material (such as Si or SiC), and the semiconductor device is one of a metal-insulator-semiconductor field-effect transistor (MISFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), or a reverse-biased insulated-gate bipolar transistor (RC-IGBT). At least one recess is formed in the semiconductor body, and the root mean square (RMS) roughness of the bottom surface of the recess is at most 15 nm, or at most 10 nm, or at most 7 nm, and / or at least 1 nm, or at least 2 nm. A gate electrode is located in at least one recess.

[0062] According to at least one embodiment, the semiconductor device is one of a metal-insulator-semiconductor field-effect transistor (MISFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), or a reverse-biased insulated-gate bipolar transistor (RC-IGBT). Attached Figure Description

[0063] The methods and semiconductor devices described herein are explained in more detail below with reference to the accompanying drawings and exemplary embodiments. The same elements in the various figures are indicated by the same reference numerals. However, the relationships between the elements are not shown to scale, but rather the individual elements may be shown exaggeratedly to aid understanding.

[0064] In the attached diagram:

[0065] Figure 1 This is a schematic block diagram of an exemplary embodiment of a method for producing the semiconductor device described herein.

[0066] Figures 2 to 6 This is a schematic cross-sectional view of method steps in an exemplary embodiment of a method for producing a semiconductor device described herein.

[0067] Figure 7 This is a schematic cross-sectional view of the bottom surface of the trench of an exemplary embodiment of the semiconductor device described herein.

[0068] Figures 8 to 12 This is a schematic cross-sectional view of method steps in an exemplary embodiment of another method for producing the semiconductor device described herein.

[0069] Figure 13 and Figure 14This is a schematic cross-sectional view of method steps in an exemplary embodiment of another method for producing the semiconductor device described herein.

[0070] Figures 15 to 20 This is a schematic cross-sectional view of method steps in an exemplary embodiment of another method for producing the semiconductor device described herein.

[0071] Figure 21 This is a schematic cross-sectional view of an exemplary embodiment of the semiconductor device described herein.

[0072] Figure 22 These are schematic top views of various recesses used in exemplary embodiments of the semiconductor devices described herein, and

[0073] Figure 23 These are schematic cross-sectional views of various recesses used in exemplary embodiments of the semiconductor devices described herein. Detailed Implementation

[0074] exist Figure 1 The diagram shows a block diagram of a method for manufacturing a semiconductor device 1. In the first method step S1, a semiconductor body 2 is provided, and see also the following... Figure 2 Semiconductor body 2 is based on group IV semiconductor materials, such as SiC or Si.

[0075] In the subsequent method step S2, the first region 21 is defined by doping a portion of the semiconductor body 2, see also below. Figure 3 The first region 21 is of the first conductivity type and begins from the surface 20 of the semiconductor body 2.

[0076] Then, in method step S3, a recess 3 is formed in the semiconductor body 2 by selectively and wet chemically etching the first region 21, see also below. Figure 4 Optionally, method step S3 may include two steps S31 and S32, or consist of both steps. In step S31, a potential is applied to the semiconductor body 2, such that the semiconductor body 2 or a portion thereof serves as an etching electrode 41, as follows: Figure 4 As indicated in [the document]. In step S32, the first region 21 is removed by means of electrochemical etching (ECE). Steps S31 and S32 can be performed simultaneously. ECE can be continuous etching or pulsed etching.

[0077] Alternatively, there is a subsequent method step S5 in which the gate electrode 44 is generated, as described below. Figure 11Step S5 may include steps S51 and S52. In step S51, an electrically insulating film 5 is applied to the wall and bottom surfaces of the recess 3. Then, in step S52, a gate electrode material (such as polysilicon) is applied to the recess 3 to form a gate electrode.

[0078] As a further option, in step S4, a second region 22 of a second conductivity type is formed in the semiconductor body 2 by means of doping, for example, directly on one side of the recess 3 or on the side of the first region 21 away from the surface 20, for example, referring to the following Figure 6 and Figure 9 Step S4 can be performed, for example, between steps S2 and S3, or it can be performed after step S3, such as between steps S3 and S5.

[0079] exist Figures 2 to 6 The method is described in more detail with examples. Figure 2 In this embodiment, a semiconductor body 2 is provided. For example, the semiconductor body 2 includes a semiconductor substrate 23, for example, made of highly n-type doped SiC. On the semiconductor substrate 23, a layer 29 is epitaxially grown. For example, layer 29 is made of moderately n-type doped SiC. The main side of layer 29 away from the substrate 23 is the top side 20 and corresponds to, for example,... Figure 1 Surface 20 mentioned in the text.

[0080] Then, in Figure 3 In this step, a first region 21 is applied to the epitaxially grown layer 29. In cross-section, the first region 21 may have a rectangular shape. Perpendicular to... Figure 3 The drawing plane in the diagram, the first region 21 can extend in a straight line. The first region 21 terminates at a point spaced apart from the substrate 23.

[0081] For example, the first region 21 is formed with a box-shaped profile by ion implantation. The term "box-shaped profile" can also be referred to as a multi-energy implantation profile. Therefore, the doping concentration in the first region 21 can be approximately constant, for example, between 0.5 and 2 times the average doping concentration, or between 0.75 and 1.3 times. Thus, the first region 21 is conductive, but the remaining portion of the epitaxial layer 29, which has the same conductivity type as the first region 21 and has exposed surfaces, is only semi-conductive, so that only conductive material with the correct conductivity type is selectively etched by ECE.

[0082] exist Figure 4Selective etching is illustrated. Therefore, the first region 21 is immersed in and exposed to the etching liquid 62 within the etching tube 61. An external electrode 63 for etching is applied at the substrate 23, which serves as the etching electrode 41 of the semiconductor body 2, and a voltage is applied between the etching liquid 62 and the etching electrode 41. In the case of the n-type conductive first region, the etching electrode 41 is the anode, as shown... Figure 4 The diagram is shown schematically.

[0083] exist Figure 4 In the diagram, area 21 is shown as only partially removed because etching is still in progress, but after etching is complete, see [link to diagram]. Figure 5 The first region 21 was completely removed. Therefore, the shape of the resulting recess 3 was determined by... Figure 3 The shape of the doped region is defined in the steps.

[0084] according to Figure 6 After forming the recess 3, a second region 22 of a second conductivity type may optionally be generated. This is accomplished, for example, by ion implantation through the recess 3. The recess 3 may be referred to as a trench, which is perpendicular to... Figure 6 The drawing plane is extended in the drawing plane.

[0085] Therefore, for example, from a thickness of 10 μm to 100 μm and a doping concentration of 1 x 10⁻⁶... 15 cm -3 Up to 1x 10 16 cm -3 N, P, B, and / or Al implantation begins on the n-type 4H-SiC epitaxial layer 29 to obtain an implantation doping concentration of approximately 1 x 10⁻⁶. 18 cm -3 Up to 1x10 20 cm -3 The first region 21. One or more implantation energies used to generate the first region 21 are selected between 100 keV and 100 MeV to form trenches, for example, with depths from 0.2 μm to 90 μm. For example, after implantation, activation can be performed at approximately 1600 °C or approximately 1700 °C for 30 minutes. n is formed in the epitaxial layer 29. + or p + After the first zone 21, ECE is performed, and trench 3 is formed through ECE.

[0086] Then, for example, an electric field confinement layer, namely the second region 22, can be formed using ion beam technology: therefore, starting from the n-type epitaxial layer 29, p... + or n + Injection and activation to generate the first region 21. According to... Figures 2 to 6 For example, n + Injection was applied to region 21. If region 21 is n...+ Type, then can be injected by p + To form an electric field confinement layer 22, and vice versa. After dopant activation, n is etched using ECE. + Zone 21, which will form trench 3 and expose p at the bottom 71. + Zone 22. Accordingly, the second zone 22 can be formed after ECE (e.g., Figure 6 (as shown), or it can be formed before ECE.

[0087] Optionally, after trench ECE in the n-type epitaxial layer 29, an energy of, for example, 5 keV to 10 keV and 10 15 cm -2 With 10 16 cm -2 Plasma immersion ion implantation of C is performed at room temperature with a dose between these values. This will inject carbon atoms into the epitaxial layer 29 to remove carbon vacancies throughout the layer 29.

[0088] exist Figures 2 to 6 For simplicity, only one trench 3 is shown in this example. In contrast, multiple trenches 3 can certainly exist, and multiple semiconductor devices 1 can be manufactured simultaneously. Trenches 3 of different shapes (e.g., different depths) can be produced simultaneously because the etching automatically terminates at the corresponding trench 3 when the designated first region 21 is completely removed. This also applies to all other examples.

[0089] In addition, with Figure 1 The same situation can also be applied to Figures 2 to 6 ,vice versa.

[0090] It should be noted that Cl-based RIEs used for SiC etching result in surface roughness ranging from 60 nm to 70 nm, while ECEs can achieve surface roughness of only 2 nm to 7 nm, as seen in the literature of HKSung et al. and Y. Ke et al., as mentioned above. Therefore, ECEs offer significantly better surface roughness, and consequently, improved electrical performance. This is in Figure 7 As shown in the figure, the RMS value of the roughened portion 7 at the bottom surface 71 of the recess 3 is less than 10 nm.

[0091] In addition, with Figures 1 to 6 The same situation can also be applied to Figure 7 ,vice versa.

[0092] exist Figures 8 to 12 Another example of this method is described in [the document / section]. Figure 8 In, similar to Figure 2A semiconductor body 2 is provided. Then, a first region 21 and a second region 22 are formed by ion implantation, wherein the first region 21 is n + Type, and the second zone 22 is p + Type, see Figure 9 .

[0093] according to Figure 10 n + Type 1 region 21 is completely removed. ECE is affected by the applied voltage at p + The second section of type 2 automatically stopped at point 22, and n - The epitaxial layer 29 was not etched due to insufficient conductivity.

[0094] Then, see Figure 11 An electrically insulating film 5 is applied to the walls of trench 3 and also to the bottom surface 71. Subsequently, a gate electrode 44 is applied to the remaining portion of trench 3.

[0095] Finally, see Figure 12 For example, p-type well regions 25 and p can be generated by ion implantation. + Type plug area 27 and n + Type source region 26, thereby completing semiconductor body 2.

[0096] Not shown in the figure, additional electrodes, passivation layers, protective layers, and bonding pads can then be created.

[0097] Therefore, the above method can be used to fabricate SiC trench MOSFETs. For example, firstly, provide n + A SiC epitaxial layer 29 is grown on a substrate 29. For example, high-dose P and Al implantation is performed in any order at temperatures between 200°C and 600°C, followed by activation at temperatures above 1600°C to form the first region 21 and the second region 22. In the formation of n... + Type 1, Zone 21 and p + After the second region 22 of type, perform ECE, using only n removal + The polarity of the injection region. The remaining p + The type region will be used as field confinement layer 22. Alternatively, it can be used in n + After ECE of type 1 zone 21, p + Type injection. In either case, during the formation of p + Following the second type region, C-plasma ion implantation can be performed, for example, PIII, at 5 keV to 30 keV, with a dose of 10. 12 cm -2 Up to 10 16 cm -2In this way, previously formed carbon vacancies can be removed. Afterward, the trenches are filled with SiO2, and then the gate electrode 44 is filled with polysilicon. Finally, regions 25, 26, and 27 are formed.

[0098] In addition, with Figures 1 to 7 The same situation can also be applied to Figures 8 to 12 ,vice versa.

[0099] The method described in this article, which involves implantation after ECE, can also be used to fabricate V-groove MOSFETs. Figure 13 and Figure 14 Starting from the 4H-SiC epitaxial layer 29, p-type epitaxial layers are formed through implantation. + Type plug area 27, p + Type II region 22, p-type well region 25 and n + Type 1, Zone 21. + Type 1 region 21 is formed, for example, by obliquely implanting N or P at an angle of 54.7° along the 0-33-8 plane of SiC, see [link to relevant documentation]. Figure 13 .

[0100] Then, n is etched away using ECE. + Type 1, Zone 21 (e.g.) Figure 14 (as shown), then C PIII can be performed. Finally, n is formed through injection and activation. + Type source pole region 26. Similar to Figure 11 Then, trench 3 can be coated with SiO2, and a gate electrode can be applied.

[0101] In addition, with Figures 1 to 12 The same situation can also be applied to Figure 13 and Figure 14 ,vice versa.

[0102] Figures 15 to 20 The diagram illustrates another example of this method. Therefore, another possibility is to use Al or BPIII to form the channel without ion implantation. The first regions 21a and 21b are n-diode implanted in epitaxial layer 29. + type and p + Type injection, see Figure 15 The region 21a near the top side 20 is p. + The type is, while the deeper lower region 21b is n. + Type.

[0103] Then, ECE removes p near the top 20. + Type 21a, see Figure 16 After completion, for example, use 5keV to 30keV and 10 12 cm -2 Up to 1014 cm -2 The dosage of A1 PIII is administered, such as Figure 17 As shown, refer to the arrow pointing to the wall of trench 3. Afterwards, perform ECE to remove n. + Type 21b, see Figure 18 .

[0104] Then, a second field-confined region 22 is formed at the bottom surface 71 of trench 3, see [reference]. Figure 19 The trench 3 is also filled with oxide and polysilicon, which are used for the electrical insulating film 5 and the gate electrode 44, respectively.

[0105] Finally, p is formed + Type 27 plug region, p-type well region 25 and n + Type source pole region 26, such as Figure 20 As shown.

[0106] In addition, with Figures 1 to 14 The same situation can also be applied to Figures 15 to 20 ,vice versa.

[0107] exist Figure 21 The diagram schematically illustrates the finished semiconductor device 1, where only one trench 3 is shown. As is possible in all other examples, regions 25, 26, 27, and 28 can be arranged on both sides of the trench 3.

[0108] according to Figure 20 Semiconductor device 1 is an insulated gate bipolar transistor (IGBT), or a metal-insulator-semiconductor field-effect transistor (MISFET) or a metal-oxide-semiconductor field-effect transistor (MOSFET). In the case of an IGBT, region 25 is a well region. Within well region 25, p... + Insertion area 27, this p + The plug region is located, for example, at the first electrode 42, which is, for example, the emitter electrode. Further, in the well region 25, there exists n configured as the emitter region. + Zone 26. Therefore, Zone 24 is n. - Type-type drift region. The doping concentration of drift layer 24 is, for example, about 2 x 10⁻⁶. 14 cm -3 .

[0109] Alternatively, another layer 284 of the semiconductor body 2 may exist below the drift region 24; this additional layer could be a buffer. For example, the buffer 284 may be n-type doped with a maximum doping concentration of approximately 1 x 10⁻⁶. 18 cm -3 For example, the thickness of buffer 284 can be between 2 μm and 10 μm (inclusive).

[0110] Another region 28 of the semiconductor body 2 is located on the side of the drift region 24 away from the top side 20 or on the side of the buffer 284 away from the top side 20. This other region 28 is a collector region with the same conductivity type as the plug region 27. The doping concentration of the collector region 28 is, for example, about 1 x 10⁻⁶. 19 cm -3 The second electrode 43 at the collector region 28 is the collector electrode.

[0111] Similarly, semiconductor device 1 can be a MISFET or a MOSFET. In this case, region 284 can be omitted, and region 28 is an n-type doped drain region with a maximum doping concentration of, for example, at least 1 x 10⁻⁶. 18 cm -3 or at least 5 x 10 18 cm -3 or at least 1x 10 19 cm -3 , and / or up to 5 x 10 20 cm -3 or at most 2 x 10 20 cm -3 or at most 1x 10 20 cm -3 In this case, region 26 is the source region, and the first electrode 42 and the second electrode 43 are the source and drain, respectively.

[0112] In addition, with Figures 1 to 20 The same situation can also be applied to Figure 21 ,vice versa.

[0113] exist Figure 22 The diagram illustrates various geometries of the recess 3 that can be achieved by doping the first region 21, as seen in the top view. For example, as seen in the top view, the recess 3 can have shapes such as square, rectangle, triangle, trapezoid, pentagon, hexagon, octagon, or polygon, or even be shaped like a cross. Although in... Figure 22 The diagram shows regular triangles, pentagons, hexagons, octagons, and polygons, but irregular shapes with different angles at the corners can also be used. For example, it can be implemented... Figure 22 Any combination of shapes shown in the figure.

[0114] Accordingly, comparison Figure 23 By doping the first region 21 and subsequent ECE, the resulting recess can have different cross-sectional shapes. Similarly, similar to... Figure 22 In the same semiconductor device 1, any combination of shapes is possible.

[0115] For example, as seen in the cross-section, the concave portion can be a symmetrical or asymmetrical trapezoidal shape that widens or narrows towards the top side 20, a triangular shape, a square shape, a rectangular shape, or a pentagonal shape with the apex pointing away from the top side. Furthermore, sharpened and rounded corners are also possible. In addition, a U-shaped groove 3 with a curved bottom surface 71 is also possible.

[0116] In addition, with Figures 1 to 21 The same situation can also be applied to Figure 22 and Figure 23 ,vice versa.

[0117] Unless otherwise indicated, the components shown in the figures are exemplarily arranged one on top of the other in a specific order. Components that do not touch are exemplarily spaced apart from each other. If the lines are drawn parallel to each other, the corresponding surfaces may be oriented parallel to each other. Similarly, unless otherwise indicated, the positions of the drawn components relative to each other are correctly reproduced in the figures.

[0118] The invention described herein is not limited to a description based on exemplary embodiments. Rather, the invention covers any new features and any combination of features, particularly any combination of features included in the patent claims, even if such feature or combination is not expressly specified in the patent claims or exemplary embodiments.

[0119] This patent application claims priority to European Patent Application 23164334.7, the disclosure of which is incorporated herein by reference.

[0120] List of reference numerals

[0121] 1. Semiconductor devices

[0122] 2 Semiconductor body

[0123] 20 Surface (Top Side)

[0124] 21. Zone 1 (Etching Limited Area)

[0125] 22. Second Zone (Shielded Zone)

[0126] 23 Semiconductor substrates

[0127] 24 Drift Zone

[0128] 25 Tunnel Area

[0129] 26 Source / Emitting Region

[0130] 27 Insertion area

[0131] 28 Drain / Collector Region

[0132] 284 Buffer

[0133] 29 Epitaxial Growth Layer

[0134] 3 recess (groove)

[0135] 41 Etching Electrode

[0136] 42 First electrode (source electrode, emitter electrode)

[0137] 43 Second electrode (drain electrode, collector electrode)

[0138] 44 Gate electrode

[0139] 5 Electrically insulating film

[0140] 61 Etched Tube

[0141] 62 Etching Liquid

[0142] 62 External electrodes for etching

[0143] 7. Roughening section

[0144] 71 Bottom of recess

[0145] S.. Method and Steps

Claims

1. A method for producing a semiconductor device (1), said semiconductor device being one of a metal-insulator-semiconductor field-effect transistor (MISFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), or a reverse-biased insulated-gate bipolar transistor (RC-IGBT), said method comprising: A) Provide a semiconductor body based on group IV semiconductor materials (2). B) Doping a first region (21) in the semiconductor body (2), the first region (21) being of a first conductivity type and starting from the surface (20) of the semiconductor body (2), and C) By means of electrochemical etching (ECE), the first region (21) is selectively and wet chemically etched to form a recess (3) in the semiconductor body (2). D) In ​​the semiconductor body (2), on the side of the first region (21) away from the surface (20), a second region (22) of the second conductivity type is doped. In step C), the etching automatically stops at the second region (22), such that after step C), the second region (22) is located directly on the bottom surface (71) of the recess (3) away from the surface (20) of the semiconductor body (2), and the root mean square RMS roughness of the bottom surface (31) is at most 15 nm. The second region (22) is configured as a shielding region in the finished semiconductor device (1). After forming the recess (3), the method further includes: E1) Apply the electrically insulating film (5) to the wall of the recess (3), and E2) provides a gate electrode (44) in the recess (3).

2. The method according to claim 1, wherein, Step B) includes: B1) Apply a potential to the semiconductor body (2) such that the semiconductor body (2) is used as an etching electrode (41), and B2) Remove the first region (21) by means of the ECE. Wherein, when the first conductivity type is p-type conductivity, the etching electrode (41) is a cathode, or when the first conductivity type is n-type conductivity, the etching electrode (41) is an anode.

3. The method according to claim 2, in, The etched electrode (41) is formed from a portion of the semiconductor substrate (23) of the semiconductor body (2), the portion being located on the side of the semiconductor body (2) away from the surface (20).

4. The method according to any one of claims 1 to 3, wherein, One or both of the following apply: - said first region (21) has a first doping concentration which is at least 10 times greater than a second doping concentration of a material of said semiconductor body (2) adjacent to said first region (21) and of the same first conductivity type, or 2 - said first region (21) has a first doping concentration which is at least 10 times greater than a second doping concentration of a material of said semiconductor body (2) adjacent to said first region (21) and of the same first conductivity type, or - The semiconductor body (2) adjacent to the first region (21) has a second conductivity type different from the first conductivity type.

5. The method according to any one of claims 1 to 3, in, In a cross section perpendicular to the top side (20) of the semiconductor body (2), the recess (3) narrows monotonically or strictly monotonically in a direction away from the top side (20).

6. The method according to any one of claims 1 to 3, in, The recess (3) is formed without using reactive ion etching (RIE).

7. The method according to any one of claims 1 to 3, in, In step B), the first region (21) is doped by at least one of ion implantation or epitaxial growth.

8. The method according to any one of claims 1 to 3, in, The recess (3) is a groove. The aspect ratio of the maximum depth to the maximum width of the trench is at least 1 and at most 10.

9. The method according to any one of claims 1 to 3, in, - The maximum depth of the recess (3) is at least 5 µm and at most 50 µm. - the maximum doping concentration of the first region (21) is at least 10 18 cm -3 and at most 10 21 cm -3 .

10. The method according to any one of claims 1 to 3, in, The recess (3) is formed in the epitaxial growth layer (29) of the semiconductor body (2), the epitaxial growth layer is of the first conductivity type and the doping concentration of the epitaxial growth layer during growth is at most 10. 16 cm -3 .

11. The method according to any one of claims 1 to 3, in, The group IV semiconductor material is SiC.

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