Low dropout regulator

Abstract

The invention discloses a low dropout regulator. The low dropout linear regulator comprises a main body circuit which is provided with a control end and an output end, the control end is used for providing control voltage, and the output end is used for providing output voltage under the control of the control voltage; and the undershoot suppression circuit is connected with the control end and the output end of the main body circuit, and is used for monitoring the change of the output voltage, amplifying the variable quantity of the output voltage, and reducing the control voltage and increasing the output voltage when the amplified voltage value is greater than a preset voltage value so as to recover the output voltage. By adopting the scheme, the recovery time of the LDO undershoot can be shortened.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a low voltage difference linear regulator. Background Art

[0002] A low dropout regulator (LDO) is a universal voltage regulator circuit that can provide a stable output voltage within a certain input voltage and load range.

[0003] In practical applications, LDOs often experience load switching. When the LDO's load switches from a light load to a heavy load, the load current suddenly increases, causing the LDO's output to drop significantly. This phenomenon is called undershoot, and the voltage value after the output voltage Vout undershoots is called the undershoot voltage.

[0004] Undershoot is particularly pronounced when loop gain is low, reducing the LDO's load regulation. The greater the rate of change in load current, the lower the undershoot voltage, the longer it lasts, and the slower the recovery. Excessively low output voltage can cause transient malfunctions in downstream circuits, while excessively long recovery times can reduce their reliability. Furthermore, excessive recovery times can affect the LDO's response speed.

[0005] Therefore, how to shorten the recovery time of LDO undershoot and reduce the undershoot amplitude has become an urgent problem to be solved. Summary of the Invention

[0006] The problem to be solved by the present invention is: how to shorten the recovery time of LDO undershoot and reduce the undershoot amplitude.

[0007] To solve the above problems, an embodiment of the present invention provides a low voltage dropout linear regulator, the low voltage dropout linear regulator comprising:

[0008] The main circuit has a control end and an output end, wherein the control end is used to provide a control voltage, and the output end is used to provide an output voltage under the control of the control voltage;

[0009] An undershoot suppression circuit is connected to the control end and the output end of the main circuit, and is used to monitor the change of the output voltage and amplify the change of the output voltage. When the amplified voltage value is greater than the preset voltage value, the control voltage is reduced and the output voltage is increased to restore the output voltage.

[0010] In a possible embodiment of the present invention, the undershoot suppression circuit includes:

[0011] a response subcircuit, connected to the output terminal, for monitoring changes in the output voltage and amplifying the amount of change in the output voltage;

[0012] The control subcircuit is connected to the response subcircuit and is used to reduce the control voltage and increase the output voltage to restore the output voltage when the amplified voltage value is greater than a preset voltage value.

[0013] In a possible embodiment of the present invention, the response subcircuit includes: a voltage acquisition module, a voltage transfer module, and a voltage amplification module; wherein:

[0014] The voltage acquisition module is connected to the output end of the main circuit and is used to obtain the change in the output voltage;

[0015] The voltage transfer module is connected to the voltage acquisition module and the voltage amplification module, and is used to transfer the change in the output voltage to the voltage amplification module;

[0016] The voltage amplification module is used to amplify the variation of the output voltage.

[0017] In a possible embodiment of the present invention, the voltage acquisition module includes: a first PMOS transistor and a first NMOS transistor; wherein:

[0018] The source of the first PMOS transistor is connected to the output end, the gate of the first PMOS transistor is connected to the voltage transfer module and the drain of the first PMOS transistor, and the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor;

[0019] The gate of the first NMOS transistor is connected to the bias voltage input terminal, and the source of the first NMOS transistor is grounded.

[0020] In a possible embodiment of the present invention, the voltage transfer module includes: a second PMOS transistor and a second NMOS transistor; wherein:

[0021] The source of the second PMOS transistor is connected to the output end, the gate of the second PMOS transistor is connected to the voltage acquisition module, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor;

[0022] The drain of the second NMOS transistor is connected to the gate of the second NMOS transistor and the gate of the voltage amplifying module, and the source of the second NMOS transistor is grounded.

[0023] In a possible embodiment of the present invention, the voltage amplification module includes: a third PMOS transistor and a third NMOS transistor; wherein:

[0024] The source of the third PMOS transistor is connected to the reference voltage output terminal; the gate of the third PMOS transistor is connected to the voltage transfer module; the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor;

[0025] The gate of the third NMOS tube is connected to the voltage transfer module; the source of the third NMOS tube is grounded.

[0026] In a possible embodiment of the present invention, a gate length of the third NMOS transistor is greater than a gate length of the second NMOS transistor.

[0027] In a possible embodiment of the present invention, a size of the first PMOS transistor is smaller than a size of the third PMOS transistor, and a size of the third PMOS transistor is smaller than a size of the second PMOS transistor.

[0028] In a possible embodiment of the present invention, the control subcircuit includes: an inverter, a fifth PMOS transistor, and a fifth NMOS transistor; wherein:

[0029] The inverter is connected to the output end of the response subcircuit and is used to logically invert the amplified voltage value;

[0030] The gate of the fifth PMOS transistor is connected to the output end of the response sub-circuit, the source of the fifth PMOS transistor is connected to the power supply voltage output end, and the drain of the fifth PMOS transistor is connected to the output end;

[0031] The gate of the fifth NMOS transistor is connected to the output end of the inverter, the drain of the fifth NMOS transistor is connected to the control end, and the source of the fifth NMOS transistor is grounded.

[0032] In a possible embodiment of the present invention, the inverter includes: a fourth PMOS transistor and a fourth NMOS transistor; wherein:

[0033] The gate of the fourth PMOS transistor is connected to the response sub-circuit and the gate output terminal of the fourth NMOS transistor, the source of the fourth PMOS transistor is connected to the power supply voltage output terminal, and the drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor;

[0034] The source of the fourth NMOS transistor is grounded.

[0035] In a possible embodiment of the present invention, the main circuit includes: an error amplifier, a power tube, and a feedback network; wherein:

[0036] One input terminal of the error amplifier is connected to a reference voltage, and the other input terminal is connected to a feedback voltage; the output terminal of the error amplifier serves as a control terminal to provide a control voltage to the power tube; one end of the power tube serves as the output terminal to provide the output voltage; the feedback network is suitable for providing the feedback voltage.

[0037] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0038] By applying the solution of the present invention, an undershoot suppression circuit is set up. The undershoot suppression circuit can monitor the change of the output voltage of the main circuit and amplify the change of the output voltage of the main circuit. When the amplified voltage value is greater than the preset voltage value, the control voltage of the main circuit is reduced on the one hand, and the output voltage of the main circuit is increased on the other hand. In this way, on the basis of directly increasing the output voltage of the main circuit, the control voltage of the main circuit is indirectly reduced, so that the undershoot voltage can be reduced, and the undershoot amplitude is reduced, and the output voltage of the main circuit can be increased faster, thereby quickly restoring the output voltage of the main circuit to the level before the undershoot, so that the low voltage difference linear regulator quickly enters a steady state. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a schematic diagram of the circuit structure of an LDO;

[0040] Figure 2 1 is a schematic structural diagram of a low-dropout linear regulator according to an embodiment of the present invention;

[0041] Figure 3 1 is a schematic structural diagram of another low-dropout linear regulator according to an embodiment of the present invention;

[0042] Figure 4 1 is a schematic structural diagram of an undershoot suppression circuit according to an embodiment of the present invention;

[0043] Figure 5 1 is a schematic diagram of the circuit structure of an undershoot suppression circuit in an embodiment of the present invention;

[0044] Figure 6 for Figure 1 LDO and Figure 5 Schematic diagram of the comparison of simulation results of LDO in . DETAILED DESCRIPTION

[0045] Figure 1 This is a schematic diagram of the circuit structure of an existing LDO. Figure 1The LDO may include an error amplifier EA, a power transistor M1, and a feedback network consisting of a first resistor R1 and a second resistor R2. The error amplifier EA has one input connected to a reference voltage Vref and another input connected to a feedback voltage Vfb. The error amplifier EA amplifies the difference between the feedback voltage Vfb and the reference voltage Vref and outputs the amplified difference voltage as a control voltage VG for the power transistor M1. The first resistor R1 and the second resistor R2 divide the LDO output voltage Vout and provide the feedback voltage Vfb.

[0046] In actual applications, when the LDO output changes from no-load to heavy-load, because the load resistance Rload suddenly decreases, the LDO's output voltage Vout is limited by the bandwidth and loop, and cannot respond to the load change in a timely manner. Therefore, when the load current suddenly increases, the feedback network cannot immediately reduce the gate voltage VG of the power tube M1, resulting in the power tube M1 being unable to output sufficient current. At this time, the load capacitor Cload will release the stored charge to compensate for the insufficient output current. During the discharge time of the load capacitor Cload, the output voltage Vout will experience a large drop. This phenomenon is called undershoot, and the voltage value after the output voltage Vout undershoots is called the undershoot voltage.

[0047] At this point, the feedback voltage Vfb decreases as the output voltage Vout drops, reducing the output of the error amplifier EA. This reduces the control voltage VG of the power transistor M1, which in turn increases the gate-source voltage Vgs of the power transistor M1, causing the output voltage Vout to rise. The error amplifier EA then pulls the output voltage Vout back to its original value. This process of the output voltage Vout first falling and then rising requires feedback through the loop between the input and output of the error amplifier EA, which affects the response speed of the LDO.

[0048] Furthermore, undershoot is particularly pronounced when the loop gain is low, reducing the LDO's load regulation. The greater the rate of change in load current, the lower the undershoot voltage, the longer it lasts, and the slower the recovery. Excessively low output voltage can cause transient malfunctions in downstream circuits, while excessively long recovery times can reduce their reliability.

[0049] To address this problem, an embodiment of the present invention provides a low-voltage difference linear regulator, in which an undershoot suppression circuit is provided. When the amplified voltage value is greater than a preset voltage value, the undershoot suppression circuit can, on the one hand, directly increase the output voltage of the main circuit, and on the other hand, indirectly increase the output voltage of the main circuit by reducing the control voltage of the main circuit, thereby reducing the undershoot voltage, that is, reducing the undershoot amplitude, and allowing the output voltage of the main circuit to increase faster and the output voltage of the main circuit to recover quickly.

[0050] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0051] Reference Figure 2 , an embodiment of the present invention provides a low voltage dropout linear regulator, which may include: a main circuit 21 and an undershoot suppression circuit 22. Wherein:

[0052] The main circuit 21 has a control end and an output end, the control end is used to provide a control voltage VG, and the output end is used to provide an output voltage Vout under the control of the control voltage VG;

[0053] The undershoot suppression circuit 22 is connected to the control end and the output end of the main circuit, and is used to monitor the changes in the output voltage Vout and amplify the changes in the output voltage Vout. When the amplified voltage value is greater than the preset voltage value, the control voltage VG is reduced and the output voltage Vout is increased to restore the output voltage Vout.

[0054] In a specific implementation, the main circuit 21 may have a variety of circuit structures, including but not limited to Figure 1 Regardless of the circuit structure of the main circuit 21, as long as the main circuit 21 has a control terminal and an output terminal, and the control terminal can provide a control voltage, and the output terminal can provide an output voltage under the control of the control voltage, it will be sufficient.

[0055] The main circuit 21 adopts Figure 1 The circuit structure shown in the example is implemented as follows, Figure 3 The main circuit 21 may include an error amplifier EA, a power transistor M1, and a feedback network consisting of a first resistor R1 and a second resistor R2. The error amplifier EA has one input connected to a reference voltage Vref and the other input connected to a feedback voltage Vfb. The error amplifier EA amplifies the difference between the feedback voltage Vfb and the reference voltage Vref and outputs the amplified difference voltage as the control voltage VG of the power transistor M1. The first resistor R1 and the second resistor R2 divide the output voltage Vout of the LDO and provide the feedback voltage Vfb.

[0056] The undershoot suppression circuit 22 is connected to the control end and the output end of the main circuit 21, and can monitor the changes in the output voltage Vout and amplify the changes in the output voltage Vout. Once the amplified voltage value is greater than the preset voltage value, the control voltage VG is reduced and the output voltage Vout is increased to restore the output voltage Vout.

[0057] In a specific implementation, the undershoot suppression circuit 22 can be implemented using a variety of structures, which are not limited here.

[0058] In one embodiment, referring to Figure 4 The undershoot suppression circuit 22 may include: a response subcircuit 221 and a control subcircuit 222.

[0059] The response subcircuit 221 is connected to the output terminal and is used to monitor the change of the output voltage and amplify the change of the output voltage;

[0060] The control subcircuit 222 is connected to the response subcircuit 221 and is configured to reduce the control voltage and increase the output voltage to restore the output voltage when the amplified voltage value is greater than a preset voltage value.

[0061] In one embodiment, the response subcircuit 221 may include: a voltage acquisition module 2211, a voltage transfer module 2212, and a voltage amplification module 2213; wherein:

[0062] The voltage acquisition module 2211 is connected to the output end of the main circuit and is used to obtain the change in the output voltage;

[0063] The voltage transfer module 2212 is connected to the voltage acquisition module and the voltage amplification module, and is used to transfer the change in the output voltage to the voltage amplification module;

[0064] The voltage amplification module 2213 is used to amplify the variation of the output voltage.

[0065] In a specific implementation, the voltage acquisition module 2211, the voltage transfer module 2212 and the voltage amplification module 2213 can be implemented using a variety of circuit structures, which are not limited here.

[0066] In one embodiment of the present invention, referring to Figure 5 The voltage acquisition module 2211 may include: a first PMOS transistor PM1 and a first NMOS transistor NM1.

[0067] The source of the first PMOS transistor PM1 is connected to the output end, the gate of the first PMOS transistor PM1 is connected to the voltage transfer module 2212 and the drain of the first PMOS transistor PM1, and the drain of the first PMOS transistor PM1 is connected to the drain of the first NMOS transistor NM1;

[0068] A gate of the first NMOS transistor NM1 is connected to a bias voltage input terminal, and a source of the first NMOS transistor NM1 is grounded to AVSS.

[0069] Specifically, the gate and drain of the first PMOS transistor PM1 are connected to form a diode connection. The source of the first PMOS transistor PM1 is connected to the output voltage Vout. The bias voltage input terminal provides a bias voltage Vbias. The bias voltage input terminal can obtain the bias voltage Vbias by mirroring the bias current through another bias circuit. The gate voltage of the first PMOS transistor PM1 can be determined based on the magnitude of the bias current and the dimensions of the first PMOS transistor PM1 and the first NMOS transistor NM1.

[0070] When the gate-source voltage of the first PMOS transistor PM1 is less than the threshold voltage of the first PMOS transistor PM1, the first PMOS transistor PM1 is in the cut-off state, and when the gate-source voltage of the first PMOS transistor PM1 is greater than the threshold voltage of the first PMOS transistor PM1, the first PMOS transistor PM1 is in the on state. Thus, the change in the output voltage Vout is converted into the change in the gate voltage of the first PMOS transistor PM1 ΔVG through the first PMOS transistor PM1. PM1 .

[0071] In other embodiments, the first PMOS transistor PM1 and the first NMOS transistor NM1 can be replaced with other switching devices. For example, semiconductor devices such as insulated gate bipolar transistors (IGBTs) and bipolar junction transistors (BJTs) can be used to replace the first PMOS transistor PM1 and the first NMOS transistor NM1. When other semiconductor devices are used to replace the first PMOS transistor PM1 and the first NMOS transistor NM1, connections can be made according to the functions of the first PMOS transistor PM1 and the first NMOS transistor NM1.

[0072] In one embodiment of the present invention, referring to Figure 5 The voltage transfer module 2212 may include: a second PMOS transistor PM2 and a second NMOS transistor NM2.

[0073] The source of the second PMOS transistor PM2 is connected to the output terminal, the gate of the second PMOS transistor PM2 is connected to the voltage acquisition module 2211, and the drain of the second PMOS transistor PM2 is connected to the drain of the second NMOS transistor NM2;

[0074] The drain of the second NMOS transistor NM2 is connected to the gate of the second NMOS transistor NM2 and the gate of the voltage amplifying module 2213 , and the source of the second NMOS transistor NM2 is grounded to AVSS.

[0075] Specifically, the source of the second PMOS transistor PM2 is connected to the output voltage Vout. The gate of the second PMOS transistor PM2 is connected to the gate of the first PMOS transistor PM1, so that the second PMOS transistor PM2 and the first PMOS transistor PM1 form a P-type current mirror. The gate voltage of the second PMOS transistor PM2 changes with the change of the gate voltage of the first PMOS transistor PM1. When the change of the gate voltage of the first PMOS transistor PM1 is ΔVG PM1 When the gate voltage of the second PMOS transistor PM2 changes by ΔVG PM1 , thereby achieving the effect of voltage transmission.

[0076] The drain of the second PMOS transistor PM2 is connected to the second NMOS transistor NM2 in a diode-connected configuration. The bias branch formed by the second PMOS transistor PM2 and the second NMOS transistor NM2 can provide a bias voltage VA for the subsequent voltage amplifier module 2213. The magnitude of the bias voltage VA is determined by the size ratio between the second PMOS transistor PM2 and the first PMOS transistor PM1, as well as the size of the second NMOS transistor NM2. Thus, by varying the sizes of the second PMOS transistor PM2, the first PMOS transistor PM1, and the second NMOS transistor NM2, the magnitude of the bias voltage VA can be varied, thereby controlling the output voltage VB of the voltage amplifier module 2213.

[0077] In other embodiments, the second PMOS transistor PM2 and the second NMOS transistor NM2 can be replaced with other switching devices. For example, semiconductor devices such as IGBTs and BJTs can be used to replace the second PMOS transistor PM2 and the second NMOS transistor NM2. When other semiconductor devices are used to replace the second PMOS transistor PM2 and the second NMOS transistor NM2, connections can be made based on the functions of the second PMOS transistor PM2 and the second NMOS transistor NM2.

[0078] In one embodiment of the present invention, referring to Figure 5 The voltage amplification module 2213 may include: a third PMOS transistor PM3 and a third NMOS transistor NM3.

[0079] The source of the third PMOS transistor PM3 is connected to the reference voltage output terminal; the gate of the third PMOS transistor PM3 is connected to the voltage transfer module 2212; the drain of the third PMOS transistor PM3 is connected to the drain of the third NMOS transistor NM3;

[0080] The gate of the third NMOS transistor NM3 is connected to the voltage transfer module 2212 ; the source of the third NMOS transistor NM3 is grounded to AVSS.

[0081] Specifically, the source of the third PMOS transistor PM3 is connected to a reference voltage Vref, which provides a stable power supply voltage for the third PMOS transistor PM3, thereby reducing noise interference introduced by the power supply. The drain of the third PMOS transistor PM3 is connected to the drain of the third NMOS transistor NM3, thereby forming a simple single-stage amplifier.

[0082] The gate of the third PMOS transistor PM3 is connected to the gate of the first PMOS transistor PM1, thereby forming another P-type current mirror with the first PMOS transistor PM1. The gate voltage of the third PMOS transistor PM3 changes with changes in the gate voltage of the first PMOS transistor PM1. The gate of the third NMOS transistor NM3 is connected to the gate of the second NMOS transistor NM2, thereby forming an N-type current mirror with the second NMOS transistor NM2. The gate voltage of the third NMOS transistor NM3 changes with changes in the gate voltage of the second NMOS transistor NM2.

[0083] When the gate voltage of the first PMOS transistor PM1 changes by ΔVG PM1 When the gate voltage of the third PMOS transistor PM3 changes by ΔVG PM1 The gate voltage change is ΔVG PM1 After amplification by the single-stage amplifier composed of the third PMOS transistor PM3 and the third NMOS transistor NM3, an amplified voltage value VB is obtained. The amplified voltage value VB is a change of the gate voltage of the first PMOS transistor PM1 by ΔVG. PM1 The amplified voltage value may be output to the control sub-circuit 222 for rapid response.

[0084] In a specific implementation, the amplified voltage value VB can be adjusted to meet the requirement by adjusting a first size ratio between the second PMOS transistor PM2 and the first PMOS transistor PM1, a second size ratio between the third PMOS transistor PM3 and the first PMOS transistor PM1, and a third size ratio between the third NMOS transistor NM3 and the second NMOS transistor NM2. The first size ratio, the second size ratio, and the third size ratio refer to the width / length (ratio of width to length) of the two MOS transistors. For example, the first size ratio refers to the width / length ratio of the second PMOS transistor PM2 to the width / length of the first PMOS transistor PM1.

[0085] In a specific implementation, the size PM1 of the first PMOS transistor is smaller than the size of the third PMOS transistor PM3 , and the size of the third PMOS transistor PM3 is smaller than the size of the second PMOS transistor PM2 .

[0086] In one embodiment, the size ratio of the first PMOS transistor PM1 , the second PMOS transistor PM2 , and the third PMOS transistor PM3 may be 1:12:2.

[0087] In one embodiment, in order to make the single-stage amplifier have a larger gain, the output impedance of the third PMOS transistor PM3 and the third NMOS transistor NM3 needs to be larger. At the same time, in order to ensure that the node B meets the "low voltage under constant load", the gain of the third NMOS transistor NM3 can be increased to increase the gain of the single-stage amplifier.

[0088] Specifically, the intrinsic gain of the third NMOS transistor NM3 is described as follows:

[0089]

[0090] Among them, A represents the intrinsic gain of the third NMOS tube NM3, g nm3 represents the transconductance of the third NMOS tube NM3, r 0nm3 represents the output impedance of the third NMOS transistor NM3, W represents the width of the third NMOS transistor NM3, L represents the length of the third NMOS transistor NM3, u n represents the mobility of the third NMOS tube NM3, C ox Indicates the gate oxide capacitance of the third NMOS tube NM3, I D represents the leakage current of the third NMOS transistor NM3, and λ represents the channel length modulation coefficient of the third NMOS transistor NM3.

[0091] To increase the gain of a single-stage amplifier, it is necessary to increase the channel length of the third NMOS transistor NM3. As can be seen from formula (1), the influence of channel length on λ is greater than that on transconductance g. nm3 Therefore, the third NMOS transistor NM3 selects a gate length larger than that of the second NMOS transistor NM2, that is, the gate length of the third NMOS transistor NM3 is greater than the gate length of the second NMOS transistor NM2, thereby increasing the gain of the third NMOS transistor NM3.

[0092] In other embodiments, the third PMOS transistor PM3 and the third NMOS transistor NM3 may be replaced with other switching devices. For example, semiconductor devices such as IGBTs and BJTs may be used to replace the third PMOS transistor PM3 and the third NMOS transistor NM3. When other semiconductor devices are used to replace the third PMOS transistor PM3 and the third NMOS transistor NM3, connections may be made based on the functions of the third PMOS transistor PM3 and the third NMOS transistor NM3.

[0093] In a specific implementation, the control subcircuit 222 may have a variety of circuit structures, which are not limited here.

[0094] In one embodiment of the present invention, referring to Figure 5 The control sub-circuit 222 may include: an inverter 2221, a fifth PMOS transistor PM5 and a fifth NMOS transistor NM5.

[0095] The inverter 2221 is connected to the output end of the response sub-circuit 221 and is used to logically invert the amplified voltage value VB;

[0096] The gate of the fifth PMOS transistor PM5 is connected to the output terminal of the response sub-circuit 221, the source of the fifth PMOS transistor PM5 is connected to the power supply voltage output terminal, and the drain of the fifth PMOS transistor PM5 is connected to the output terminal;

[0097] The gate of the fifth NMOS transistor NM5 is connected to the output terminal of the inverter 2221 , the drain of the fifth NMOS transistor NM5 is connected to the control terminal, and the source of the fifth NMOS transistor NM5 is grounded to AVSS.

[0098] Specifically, refer to Figure 5 The source of the fifth PMOS transistor PM5 is connected to the power supply voltage output terminal AVDD, and the drain is connected to the output voltage Vout. The source of the fifth NMOS switch transistor NM5 is grounded, and the drain is connected to the control voltage VG. The gates of the fifth PMOS transistor PM5 and the fifth NMOS switch transistor NM5 are connected to the input and output terminals of the inverter 2221, forming a fast feedback loop between the output voltage Vout and the control voltage VG. With this connection, when the input of the inverter 2221 changes and causes the inverter 2221 to flip, the control voltage VG can be rapidly reduced and the output voltage Vout can be rapidly increased, achieving rapid recovery from the undershoot voltage.

[0099] In other embodiments, the fifth PMOS transistor PM5 and the fifth NMOS switch transistor NM5 may be replaced with other switching devices. For example, semiconductor devices such as IGBTs and BJTs may be used to replace the fifth PMOS transistor PM5 and the fifth NMOS switch transistor NM5. When other semiconductor devices are used to replace the fifth PMOS transistor PM5 and the fifth NMOS switch transistor NM5, connections may be made referring to the functions of the fifth PMOS transistor PM5 and the fifth NMOS switch transistor NM5.

[0100] In a specific implementation, the inverter 2221 can be implemented using a variety of circuit structures, which are not limited here.

[0101] In one embodiment of the present invention, referring to Figure 5 The inverter 2221 may include: a fourth PMOS transistor PM4 and a fourth NMOS transistor NM4; wherein:

[0102] The gate of the fourth PMOS transistor PM4 is connected to the response sub-circuit 221 and the gate output terminal of the fourth NMOS transistor NM4. The source of the fourth PMOS transistor PM4 is connected to the power supply voltage output terminal AVDD. The drain of the fourth PMOS transistor PM4 is connected to the drain of the fourth NMOS transistor NM4. The source of the fourth NMOS transistor NM4 is grounded to AVSS.

[0103] At this time, the preset voltage value is the larger one of the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5. When the amplified voltage value VB is greater than the preset voltage value, the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 are turned on to achieve voltage control.

[0104] In other embodiments, the fourth PMOS transistor PM4 and the fourth NMOS transistor NM4 may be replaced with other switching devices. For example, semiconductor devices such as IGBTs and BJTs may be used to replace the fourth PMOS transistor PM4 and the fourth NMOS transistor NM4. When other semiconductor devices are used to replace the fourth PMOS transistor PM4 and the fourth NMOS transistor NM4, connections may be made based on the functions of the fourth PMOS transistor PM4 and the fourth NMOS transistor NM4.

[0105] By adopting the control sub-circuit 222 , the change of the output voltage Vout can be fed back to the control voltage VG, thereby quickly reducing the undershoot peak and shortening the voltage recovery time.

[0106] Below Figure 5 Taking the circuit structure shown as an example, the working principle of the undershoot suppression circuit is described as follows:

[0107] When the output load of the LDO suddenly changes from a light load to a heavy load, an undershoot peak appears in the output voltage Vout. The change ΔVout of the output voltage Vout is converted into a change ΔVG of the gate voltage of the first PMOS transistor PM1 through the first PMOS transistor PM1. PM1 Since the gate of the first PMOS transistor PM1 is connected to the gate voltage of the second PMOS transistor PM2 and the third PMOS transistor PM3, the gate voltage of the second PMOS transistor PM2 and the third PMOS transistor PM3 are both reduced by ΔVG. PM1 .

[0108] The second PMOS transistor PM2 and the second NMOS transistor NM2 provide a bias voltage (ie, the voltage VA at the node A) for the third MOS transistor NM3. When the gate voltage of the third PMOS transistor PM3 drops instantaneously, the voltage at the node B rises instantaneously.

[0109] In actual application, the gate voltage of the third PMOS tube PM3 changes slightly, about one hundred millivolts, but due to the amplification effect of the single-stage amplifier, ΔVG PM1 The amplified output is sent to node B, where the voltage VB at node B may vary by several hundred millivolts.

[0110] When the voltage VB at node B reaches and exceeds the threshold voltages of the fourth MOS transistor NM4 and the fifth NMOS transistor NM5, the fifth NMOS transistor NM5 turns on, rapidly reducing the control voltage VG. Simultaneously, inverter 2221 flips, causing the gate voltage of the fifth PMOS transistor PM5 to transition from a high level to a low level. The fifth PMOS transistor PM5 then conducts, rapidly increasing the output voltage Vout. Due to the reduction in control voltage VG, the output voltage Vout increases more quickly and returns to its pre-undershoot voltage. At this point, the voltage VB at node B transitions from a high level to a low level, causing the fifth NMOS transistor NM5 to turn off. Simultaneously, inverter 2221 flips again, disconnecting the fifth PMOS transistor PM5, and the circuit enters a steady state.

[0111] Figure 6 for Figure 1 LDO and Figure 5 The simulation results of LDO are compared in Fig. 7, where curve 71 is the simulation result curve of the output voltage of LDO changing with time, and curve 72 is Figure 5 The simulation results curve of the LDO output voltage changing with time. The simulation conditions are: the LDO steady-state output is 1.56V, and the output current switches from 0.1mA to 6mA.

[0112] from Figure 6 It can be seen that the use of Figure 1In the case of the LDO, without the undershoot suppression circuit, the output voltage Vout of the LDO instantly undershoots to 1.33V (as shown at point C) at 5.3us, and it takes a long time to recover to the voltage corresponding to point F (6.1us, 1.48V). Figure 5 For the medium LDO, with the undershoot suppression circuit set, the output voltage Vout instantly overshoots to 1.41V at 5.3us, the undershoot peak is reduced by 80mV, and the time required to recover to the voltage corresponding to point E (5.5us, 1.48V) is relatively short.

[0113] Taking the voltage drop to 95% of the peak voltage as a benchmark, after using the undershoot suppression circuit of the present invention, the recovery time of the output voltage Vout is shortened by nearly 0.7 μs, and the overall recovery speed is increased by about 50%.

[0114] By using the low-dropout linear regulator in the embodiment of the present invention, when the output voltage has a large rate of change, the output voltage can be directly increased on the one hand, and the output voltage can be indirectly increased by reducing the control voltage on the other hand. This can quickly reduce the undershoot peak and shorten the voltage recovery time. Especially when the loop gain is not high, the load regulation rate of the LDO can be effectively increased.

[0115] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A low voltage dropout linear regulator, characterized in that: include: The main circuit has a control end and an output end, wherein the control end is used to provide a control voltage, and the output end is used to provide an output voltage under the control of the control voltage; An undershoot suppression circuit is connected to the control end and the output end of the main circuit, and is used to monitor the change of the output voltage and amplify the change of the output voltage. When the amplified voltage value is greater than the preset voltage value, the control voltage is reduced and the output voltage is increased to restore the output voltage.

2. The low-dropout linear regulator according to claim 1, wherein: The undershoot suppression circuit comprises: a response subcircuit, connected to the output terminal, for monitoring changes in the output voltage and amplifying the amount of change in the output voltage; The control subcircuit is connected to the response subcircuit and is used to reduce the control voltage and increase the output voltage to restore the output voltage when the amplified voltage value is greater than a preset voltage value.

3. The low-dropout linear regulator according to claim 2, wherein: The response subcircuit includes: a voltage acquisition module, a voltage transfer module and a voltage amplification module; wherein: The voltage acquisition module is connected to the output end of the main circuit and is used to obtain the change in the output voltage; The voltage transfer module is connected to the voltage acquisition module and the voltage amplification module, and is used to transfer the change in the output voltage to the voltage amplification module; The voltage amplification module is used to amplify the variation of the output voltage.

4. The low-dropout linear regulator according to claim 3, wherein: The voltage acquisition module includes: a first PMOS transistor and a first NMOS transistor; wherein: The source of the first PMOS transistor is connected to the output end, the gate of the first PMOS transistor is connected to the voltage transfer module and the drain of the first PMOS transistor, and the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor; The gate of the first NMOS transistor is connected to the bias voltage input terminal, and the source of the first NMOS transistor is grounded.

5. The low-dropout linear regulator according to claim 4, wherein: The voltage transfer module includes: a second PMOS transistor and a second NMOS transistor; wherein: The source of the second PMOS transistor is connected to the output end, the gate of the second PMOS transistor is connected to the voltage acquisition module, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor; The drain of the second NMOS transistor is connected to the gate of the second NMOS transistor and the gate of the voltage amplifying module, and the source of the second NMOS transistor is grounded.

6. The low-dropout linear regulator according to claim 5, wherein: The voltage amplification module includes: a third PMOS transistor and a third NMOS transistor; wherein: The source of the third PMOS transistor is connected to the reference voltage output terminal; the gate of the third PMOS transistor is connected to the voltage transfer module; the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor; The gate of the third NMOS tube is connected to the voltage transfer module; the source of the third NMOS tube is grounded.

7. The low-dropout linear regulator according to claim 6, wherein: The gate length of the third NMOS transistor is greater than the gate length of the second NMOS transistor.

8. The low-dropout linear regulator according to claim 6, wherein: The size of the first PMOS transistor is smaller than that of the third PMOS transistor, and the size of the third PMOS transistor is smaller than that of the second PMOS transistor.

9. The low-dropout linear regulator according to any one of claims 2 to 8, wherein: The control subcircuit includes: an inverter, a fifth PMOS transistor and a fifth NMOS transistor; wherein: The inverter is connected to the output end of the response subcircuit and is used to logically invert the amplified voltage value; The gate of the fifth PMOS transistor is connected to the output end of the response sub-circuit, the source of the fifth PMOS transistor is connected to the power supply voltage output end, and the drain of the fifth PMOS transistor is connected to the output end; The gate of the fifth NMOS transistor is connected to the output end of the inverter, the drain of the fifth NMOS transistor is connected to the control end, and the source of the fifth NMOS transistor is grounded.

10. The low-dropout linear regulator according to claim 9, wherein: The inverter includes: a fourth PMOS transistor and a fourth NMOS transistor; wherein: The gate of the fourth PMOS transistor is connected to the response sub-circuit and the gate output terminal of the fourth NMOS transistor, the source of the fourth PMOS transistor is connected to the power supply voltage output terminal, and the drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor; The source of the fourth NMOS transistor is grounded.

11. The low dropout linear regulator according to claim 1, wherein: The main circuit includes: an error amplifier, a power tube and a feedback network; wherein: One input terminal of the error amplifier is connected to a reference voltage, and the other input terminal is connected to a feedback voltage; the output terminal of the error amplifier serves as a control terminal to provide a control voltage to the power tube; one end of the power tube serves as the output terminal to provide the output voltage; the feedback network provides the feedback voltage.

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