Low noise voltage regulator and related method thereof

Abstract

The invention relates to a low-noise voltage regulator and a related method thereof. The low noise voltage regulator includes (i) an error amplifier configured to generate an error signal proportional to a difference between a voltage at a ground node and a voltage at a setup node, (ii) a reference resistor electrically coupled between an output power node and the setup node, (iii) a capacitor connected in parallel with the reference resistor, (iv) a reference current source electrically coupled to the capacitor, and (v) a control and power stage electrically coupled to the setup node, and (v) a control and power stage electrically coupled between an input power node and the output power node. The control and power stage is configured to convert an input voltage to an output voltage in response to the error signal to minimize a magnitude of the error signal.

Description

Technical Field

[0001] The present disclosure relates to low noise voltage regulators and related methods. Background Art

[0002] A voltage regulator is a power supply that provides a regulated output voltage. Voltage regulators are used in a variety of applications, such as supplying power to a load within a specified voltage range. Types of voltage regulators include switching voltage regulators and linear voltage regulators. Summary of the Invention

[0003] In one aspect of the present disclosure, a low noise voltage regulator is provided, comprising: an error amplifier configured to generate an error signal proportional to a difference between a voltage at a ground node and a voltage at a setting node; a reference resistor electrically coupled between an output power node and the setting node; a reference current source electrically coupled to the setting node; and a control and power stage electrically coupled between an input power node and the output power node, the control and power stage being configured to convert an input voltage into an output voltage in response to the error signal to minimize the magnitude of the error information, the input voltage being the voltage at the input power node, and the output voltage being the voltage at the output power node.

[0004] In another aspect of the present disclosure, a multi-output low-noise voltage regulator is provided, comprising: a first error amplifier configured to generate a first error signal, the first error signal being proportional to a difference between a voltage at a first ground node and a voltage at a first setting node; a first reference resistor electrically coupled between a first output power node and the first setting node; a first reference current source electrically coupled to the first setting node; a first control and power stage electrically coupled between a first input power node and the first output power node, the first control and power stage being configured to convert a first input voltage to a first output voltage in response to the first error signal to minimize a magnitude of the first error signal, the first input voltage being a voltage at the first input power node, and the first an output voltage being a voltage at the first output power node; a second error amplifier configured to generate a second error signal proportional to a difference between a voltage at a second ground node and a voltage at a second setting node; a second reference resistor electrically coupled between the second output power node and the second setting node; a second reference current source electrically coupled to the second setting node; and a second control and power stage electrically coupled between a second input power node and the second output power node, the second control and power stage configured to convert a second input voltage to a second output voltage in response to the second error signal to minimize a magnitude of the second error signal, the second input voltage being the voltage at the second input power node, and the second output voltage being the voltage at the second output power node.

[0005] In yet another aspect of the present disclosure, a method for controlling a low noise voltage regulator is provided, the method comprising: establishing a voltage having a first amplitude across a reference resistor electrically coupled between an output power node of the low noise voltage regulator and a setting node of the low noise voltage regulator, the first amplitude being a desired amplitude of an output voltage, the output voltage being the voltage at the output power node of the low noise voltage regulator; generating an error signal representing a difference between a voltage at the setting node of the low noise voltage regulator and a voltage at a ground node; and controlling a control and power stage electrically coupled between an input power node and the output power node in response to the error signal, the control and power stage being configured to convert an input voltage to an output voltage in response to the error signal so as to minimize the amplitude of the error signal, the input voltage being the voltage at the input power node. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 Figure 1 is a schematic diagram of a voltage regulator, where the voltage reference noise and error amplifier noise are obtained by the voltage divider in the voltage regulator.

[0007] Figure 2is a schematic diagram of a low noise voltage regulator according to an embodiment.

[0008] Figure 3 yes Figure 2 Schematic diagram of a low-noise voltage regulator, showing two noise sources.

[0009] Figure 4 yes Figure 2 Schematic diagram of an alternative embodiment of a low noise voltage regulator that is configured to produce a negative output voltage instead of a positive output voltage.

[0010] Figure 5 yes Figure 2 Schematic diagram of a low-noise voltage regulator, where the voltage source is implemented by a charge pump and a linear regulator.

[0011] Figure 6 yes Figure 4 Schematic diagram of a low-noise voltage regulator, where the voltage source is implemented by a linear regulator.

[0012] Figure 7 It has a boost topology Figure 2 Schematic diagram of an embodiment of a low noise voltage regulator.

[0013] Figure 8 It has a buck-boost topology Figure 4 Schematic diagram of an embodiment of a low noise voltage regulator.

[0014] Figure 9 It is a single-ended primary inductor converter (SEPIC) topology. Figure 2 Schematic diagram of an embodiment of a low noise voltage regulator.

[0015] Figure 10 It is a low dropout linear regulator topology. Figure 4 Schematic diagram of an embodiment of a low noise voltage regulator.

[0016] Figure 11 is a schematic diagram of a multi-output low noise voltage regulator according to an embodiment.

[0017] Figure 12 yes Figure 11 Schematic diagram of an embodiment of a low-noise voltage regulator in which each power stage is implemented by a linear regulator.

[0018] Figure 13 is a schematic diagram of another multi-output low noise voltage regulator according to an embodiment.

[0019] Figure 14 is composed of blocks that share a common input power node Figure 13 Schematic diagram of an embodiment of a low noise voltage regulator.

[0020] Figure 15 is comprised of blocks electrically coupled in series Figure 13 Schematic diagram of an embodiment of a low noise voltage regulator. DETAILED DESCRIPTION

[0021] Some voltage regulator applications require low electrical noise. In these applications, electrical noise on the voltage regulator output can cause the circuits powered by the voltage regulator to operate improperly. For example, noise on the output of a voltage regulator powering a precision measurement circuit can prevent the measurement circuit from discerning small changes in the measured parameter. As another example, noise on the output of a voltage regulator powering a linear amplifier can cause unwanted noise to appear at the linear amplifier's output.

[0022] However, a conventional voltage regulator may exhibit significant noise at its output due to noise amplification from the voltage regulator's voltage reference and noise amplification from the voltage regulator's error amplifier. For example, Figure 1 is a schematic diagram of a voltage regulator 100 in which the voltage reference noise and the error amplifier noise are amplified by the voltage regulator's voltage divider, i.e., the "gain." The voltage regulator 100 includes a control and power stage 102, an output capacitor 104, a first resistor 106, a second resistor 108, an error amplifier 110, a voltage reference 112, a resistor 114, and a capacitor 116. The control and power stage 102 is electrically coupled between an input power node 118 and an output power node 120. A load (not shown) may be connected to the output power node 120. The control and power stage 102 includes a power stage (not shown), such as a switching power converter power stage or a linear regulator power stage, and associated control circuitry (not shown). The output capacitor 104 is electrically coupled between the output power node 120 and a ground node 122. The control and power stage 102 converts an input voltage V in Converted to an output voltage V on the output power node 120 out .

[0023] Resistor 106 and resistor 108 together form a voltage divider that divides the voltage V out The voltage divided by the voltage divider is V div The error amplifier 110 is a transconductance amplifier configured to generate a voltage V div and the voltage V of the voltage reference 112 ref The current error signal I is proportional to the difference between ea The resistor 114 and the capacitor 116 together contribute to the current error signal I ea Integrate to generate a voltage error signal V ea, which signal is provided to the control and power stage 102. The control and power stage 102 regulates the output voltage V out To minimize the magnitude of the current error signal I ea The amplitude.

[0024] Output voltage V out The size of is determined by formula 1. 106 is the resistance of resistor 106, R 108 is the resistance of resistor 108. As is clear from Formula 1, the output voltage V out The magnitude of can be set by selecting resistors 106 and 108.

[0025]

[0026] While including resistors 106 and 108 in voltage regulator 100 facilitates setting the output voltage V out The resistor increases the amplitude flexibility, but also increases the amplitude of the electrical noise on the output power node 120. Specifically, Figure 1 Noise sources 128 and 130 are shown electrically coupled to respective inputs of error amplifier 110. Noise source 128 represents the noise V of voltage reference 112. rn , the noise source 130 represents the noise V of the error amplifier 110 ean Although noise sources 128 and 130 are shown as discrete components, it should be appreciated that noise sources 128, 130 are not physical components but represent noise generated internally by voltage reference 112 and error amplifier 110, respectively. Equation 2 below represents the feedback gain G implemented by resistors 106 and 108, and Equation 3 represents the noise V rn and noise V ea The noise V on the output power node 120 out_n As shown in Equation 3, the feedback gain G from resistors 106 and 108 adds the noise V of voltage reference 112 to the output power node 120. rn and the noise V of the error amplifier 110 ea Therefore, the voltage regulator 100 may not be suitable for applications requiring low power supply noise.

[0027]

[0028]

[0029] This document discloses a new low-noise voltage regulator and related methods that can at least partially overcome the aforementioned issues of conventional voltage regulators. For example, the new voltage regulator regulates the input port of the error amplifier to ground, eliminating the need for a voltage divider connected to the error amplifier input port. Consequently, certain embodiments of the new low-noise voltage regulator can operate without amplifying reference noise or error amplifier noise, which promotes low electrical noise at the voltage regulator's output power node. Furthermore, a capacitor is connected from the output port to the error amplifier input port to reduce output noise. Furthermore, certain embodiments of the new voltage regulator can operate over a wide range of input voltage amplitudes, for example, when the input voltage amplitude is less than or equal to the output voltage amplitude. Furthermore, in some embodiments, the minimum output voltage amplitude is not limited by the voltage reference voltage. Furthermore, certain embodiments can support negative output voltages. Furthermore, some embodiments can generate multiple output voltages. Thus, the new voltage regulator significantly advances the state of the art in low-noise voltage regulation.

[0030] Figure 2 FIG2 is a schematic diagram of a low-noise voltage regulator 200, which is one embodiment of the novel low-noise voltage regulator disclosed herein. Low-noise voltage regulator 200 includes a control and power stage 202, an output capacitor 204, a reference resistor 206, a reference capacitor 208, a reference current source 210, and an error amplifier 212. Control and power stage 202 is electrically coupled between an input power node 214 and an output power node 216. Output capacitor 204 is electrically coupled between output power node 216 and a ground node 218. In this document, a ground node is a reference electrical node that need not be the same as ground or chassis ground. Voltages in low-noise voltage regulator 200 are referenced to ground node 218, and therefore the voltage at ground node 218 is zero. Therefore, positive voltages in low-noise voltage regulator 200 have a higher potential than ground node 218, and negative voltages in low-noise current regulator 200 have a lower potential than ground node 218. A load (not shown) is optionally electrically coupled to the output power node 216 to be powered by the low noise voltage regulator 200. For example, the output capacitor 204 helps support transient loads on the output power node 216 and / or helps absorb ripple current (if any) generated by the control and power stage 202.

[0031] Each of the reference resistor 206 and the reference capacitor 208 is electrically coupled between the output power node 216 and the set node 220 such that the reference capacitor 208 is electrically coupled in parallel with the reference resistor 206. The reference current source 210 is electrically coupled to the set node 220. Figure 2Reference current source 210 is depicted as being electrically coupled between set node 220 and ground node 218, but reference current source 210 may alternatively be electrically coupled between set node 220 and one or more other nodes, in place of or in addition to ground node 218. Input port 222 of error amplifier 212 is connected to set node 220, and input port 224 of error amplifier 212 is connected to ground node 218. Output port 226 of error amplifier 212 is electrically coupled to control and power stage 202.

[0032] Input current I in The output current I out The input current I in and output current I out The low noise voltage regulator 200 has an input voltage V at the input power node 214. in , the output power node 216 has an output voltage V out Input voltage V in and the output voltage V out The polarity can be positive or negative, and in certain embodiments, the input voltage V in With the output voltage V out They do not need to be of the same polarity.

[0033] The input ports 222 and 224 of the error amplifier 212 both have high input impedances, so that the current flowing into these input ports can be ignored. ref is a direct current (DC) signal, so during the steady-state operation of the low-noise voltage regulator 200, the reference current signal I ref No significant amount of current will flow through the reference capacitor 208. Therefore, substantially all of the reference current signal I ref Both flow through the reference resistor 206, thereby establishing a voltage V across the reference resistor 206 according to the following formula 4 ref , where R ref is the resistance of the reference resistor 206 .

[0034] V ref =I ref ·R ref (Formula 4)

[0035] The error amplifier 212 is configured to generate an error signal E at its output port 226. rr , where the error signal E rrThe error signal E is proportional to the difference between the voltage at the set node 220 and the voltage at the ground node 218, and the voltage at the ground node 218 is zero because the voltage in the low noise voltage regulator 200 is referenced to the ground node 118. rr It can be a voltage signal or a current signal. For example, in an embodiment where the error amplifier 212 is a voltage amplifier, the error signal E rr It can be a voltage signal. In the embodiment where the error amplifier 212 is a transconductance amplifier, the error information E rr Alternatively, the error amplifier 212 may be configured such that the error signal E rr A signal other than an electrical signal, such as an optical signal or a radio frequency wireless signal.

[0036] The control and power stage 202 includes a power stage ( Figure 2 ), such as a switching power converter power stage or a linear regulator power stage, and optional associated control circuitry ( Figure 2 The control and power stage 202 is configured to respond at least in part to an error signal E generated by the error amplifier 212. rr , the input voltage V at the input power node 214 in Converted to an output voltage V at the output power node 216 out , to minimize the error signal E rr In other words, the control and power stage 202 are controlled to minimize the error signal E rr The output voltage V is controlled by the amplitude out In addition, the input port 224 of the error amplifier 212 is at zero voltage because the input port 224 is connected to the ground node 218. Therefore, the error amplifier 212 is connected to the ground node 218 via the error signal E. rr Control output voltage V out The magnitude of the voltage at the setting node 220 is adjusted to zero. Therefore, the output voltage V out The magnitude is equal to the voltage V across the reference resistor 206 ref , the low noise voltage regulator 200 indirectly regulates the output voltage V by adjusting the voltage amplitude on the setting node 220 to zero out Therefore, the output voltage V is set according to the above formula 4 out The desired amplitude is obtained by applying a reference current signal I to the reference resistor 206. ref To achieve the output voltage V out , to achieve the desired output voltage amplitude across the reference resistor 206. The reference capacitor 208 connected in parallel with the reference resistor 206 reduces the voltage noise across the reference resistor 206. Therefore, the output voltage Vout The magnitude can be adjusted by changing the resistance R of the reference resistor 206. ref and / or by changing the reference current signal I ref For example, the resistance R of the reference resistor 206 can be increased. ref and / or by increasing the reference current signal I ref The amplitude is used to increase the output voltage V out The amplitude.

[0037] Importantly, the configuration of the low noise voltage regulator 200 promotes low amplitude electrical noise on the output power node 216. For example, consider Figure 3 , which is a schematic diagram of the low noise regulator 200, showing the noise source 302 and the noise source 304 electrically coupled to the setting node 220. The noise source 302 represents the noise V ean , the noise source 304 represents the noise I of the reference current source 210 rn It should be noted that noise sources 302 and 304 are not physical components, but represent the noise generated internally by error amplifier 212 and reference current source 210, respectively. Figure 1 Compared to the voltage regulator 100, no noise V is obtained until the output power node 216 ean and noise I rn In contrast, the low noise voltage regulator 200 has a noise V with respect to the output power node 216. ean and noise I rn The reference resistor 206 is a resistor that is connected to the reference capacitor 208 and is therefore noise-free. Furthermore, the reference capacitor 208 helps filter noise across the reference resistor 206. Furthermore, the fact that the set node 220 is regulated to the ground node 218 (which is at zero voltage and therefore noise-free) also contributes to low noise. Therefore, the low noise voltage regulator 200 can have much lower noise on its output power node than a conventional voltage regulator with a similar error amplifier and reference noise amplitude.

[0038] In addition, the low noise voltage regulator 200 can achieve additional significant advantages. For example, some embodiments of the low noise voltage regulator 200 can be capable of outputting a voltage V out The amplitude is greater than or equal to the voltage V in As another example, the output voltage V out The minimum value of the amplitude voltage is not limited by the voltage reference amplitude. Instead, in certain embodiments, the minimum value of the amplitude voltage is limited by appropriately selecting the resistance R of the reference resistor 206. ref and the reference current signal I ref The amplitude of the output voltage V outAs another example, some embodiments of the low noise voltage regulator 200 can be configured to output voltage V out For negative voltages and when the output voltage V out Operates at positive voltage.

[0039] Reference again Figure 2 , the reference current source 210 is configured to generate a reference current signal I ref , so that the reference current signal I ref Flows out of the set node 220. Therefore, the output voltage V out is positive with respect to the ground node 218, or in other words, the output power node 216 is at a higher potential than the ground node 218. However, the reference current source 210 may be modified so that the reference current signal I ref have opposite polarity.

[0040] For example, Figure 4 is a schematic diagram of a low noise voltage regulator 400, which is a low noise current regulator 200 ( Figure 2 ), wherein the reference current source 210 is replaced by a reference current source 410. The reference current source 410 is configured to generate a reference current signal I ref , so that the reference current signal I ref flows toward the collection node 220, rather than away from the collection node 220. Therefore, the voltage V ref The polarity of the voltage V in the low noise regulator 200 ref As a result, in the low noise voltage regulator 400, the voltage V out It is negative with respect to the ground node 218 , or in other words, the potential of the output power node 216 is lower than the potential of the ground node 218 .

[0041] Some embodiments further include a current source 210 ( Figure 2 ) or current source 410 ( Figure 4 ) voltage sources in series. For example, Figure 5 is a schematic diagram of a low noise voltage regulator 500, which is Figure 2 The embodiment of the low noise voltage regulator 200 further includes a voltage source 530 electrically coupled in series with the current source 210. The voltage source 530 includes a charge pump (CP) 532, a linear regulator (LR) 534, and a capacitor 536. The charge pump 532 is configured to convert the positive input voltage V in Converted to a charge pump voltage V across capacitor 536 cp , where the voltage V cp The linear regulator 534 is configured to convert the charge pump voltage V cpConverted to the voltage V of the voltage source 530 530 In some alternative embodiments of the low noise voltage regulator 500, the linear regulator 534 is omitted and the voltage V 530 The voltage V generated by the charge pump 532 cp same.

[0042] As another example, Figure 6 is a schematic diagram of a low noise voltage regulator 600, which is Figure 4 The embodiment of the low noise voltage regulator 400 further includes a voltage source 630 electrically coupled in series with the current source 410. The voltage source 630 includes a linear regulator 632 configured to convert the positive input voltage V in Converted to positive voltage V of voltage source 630 630 .

[0043] Reference again Figure 2 As described above, in some embodiments, the control and power stage 202 includes a switching power converter stage or a linear regulator power stage. By way of example and not limitation, in some embodiments, the control and power stage 202 includes a buck switching power converter stage, a boost switching power converter stage, a buck-boost switching power conversion stage, a single-ended primary inductor converter (SEPIC) switching power converter, a Cock switching power converter, or a low dropout linear regulator power stage. Figure 7-10 Several example embodiments are shown for the control and power stage 202. However, it should be understood that the control and power stage 202 is not limited to these example embodiments.

[0044] Figure 7 is a schematic diagram of a low noise voltage regulator 700, which is a low noise voltage regulator 200 with a boost topology ( Figure 2 ) embodiment, so that the output voltage V out The amplitude is greater than or equal to the input voltage V in The control and power stage 202 of the low noise voltage regulator 200 is implemented by the control and power stage 702 in the low noise regulator 700, and the error amplifier 212 of the low noise regulator 200 is implemented by the error amplifier 712 in the low noise regulator 700. The error amplifier 712 is a transconductance amplifier, so the error amplifier 712 is configured to generate a current error signal I err , which is the error signal E of the low noise voltage regulator 200 rr An embodiment of .

[0045] The control and power stage 702 includes a current sense resistor 728, an inductor 730, a control switch device 732, a freewheeling switch device 734, a resistor 736, a capacitor 738, an oscillator 740, a slope compensation circuit 742, a summing circuit 744, a current sense amplifier 746, a comparator 748, an SR flip-flop 750, and logic 752. The inductor 730, the control switch device 732, and the freewheeling switch device 734 collectively form a boost switching power converter power stage. The current sense resistor 728 and the inductor 730 are electrically coupled in series between the input power node 214 and the switch node 754. The control switch device 732 is electrically coupled between the switch node 754 and the ground node 218, and the freewheeling switch device 734 is electrically coupled between the switch node 754 and the output power node 216. The control switch device 732 is controlled by a control signal Φ1 generated by the logic 752 (discussed below), and the freewheeling switch device 734 is controlled by a control signal Φ generated by the logic 752. Each of the control switch device 732 and the freewheeling switch device 734 includes, for example, one or more transistors (e.g., a field effect transistor (FET), a bipolar junction transistor (BJT), or an insulated gate bipolar junction transistor (IGBT)), and associated driver circuitry for the one or more transistors.

[0046] The current sense resistor 728, the resistor 736, the capacitor 738, the oscillator 740, the slope compensation circuit 742, the summing circuit 744, the current sense amplifier 746, the comparator 748, the SR flip-flop 750 and the logic 752 collectively form a control circuit for the control and power stage 702, which responds to the current error signal I err The duty cycle of the control switching device 732 is modulated to adjust the voltage amplitude at the setting node 220 to zero. Specifically, the resistor 736 and the capacitor 738 are electrically coupled in series between the output port 226 of the error amplifier 712 and the ground node 218, so the resistor 736 and the resistor 738 together have a positive effect on the current error signal I err Integrate to generate the corresponding voltage error signal V err The oscillator 740 periodically sends out a clock signal CLK at the switching frequency of the low noise voltage regulator 700, and the clock signal CLK is provided to the S input of the SR flip-flop 750 and the slope compensation circuit 742. The SR flip-flop 750 is accordingly set by the assertion of the clock signal CLK. The slope compensation circuit 742 generates a slope compensation signal SLOPE based on the clock signal CLK. The slope compensation signal SLOPE is, for example, a linear or nonlinear slope signal, such as a ramp signal. The summing circuit 744 adds the slope compensation signal SLOPE to the voltage error signal V err Added to generate the compensation signal V comp .

[0047] The current sense amplifier 746 is configured to amplify the voltage V across the current sense resistor 728. res , to generate a current I flowing through the inductor 730 L Proportional signal V cs The comparator 748 converts the current sensing signal V cs With the compensation signal V comp is compared, and when the current sensing information V cs The amplitude reaches the compensation signal V comp When the magnitude of the comparator 748 asserts the reset signal V reset . Reset signal V reset is provided to the R input terminal of the SR flip-flop 750, and the SR flip-flop 750 responds to the reset signal V reset The SR flip-flop 750 generates a control signal V at its output Q. ctrl When the SR flip-flop 750 is set, the control signal V ctrl is asserted, and when the SR flip-flop 750 is reset, the control information V ctrl is de-asserted. Therefore, the control signal V ctrl The current error signal I err The amplitude of the duty cycle of the PWM signal is minimized, thereby regulating the voltage at node 220 to zero. In this document, the duty cycle of the switching device of the low noise voltage regulator is the ratio of the on-time of the switching device to the switching period of the low noise voltage regulator.

[0048] Logic 752 is configured to be based on the control signal V ctrl Generate control signals Φ1 and Φ2. Specifically, when the control signal V ctrl is asserted, logic 752 asserts control signal Φ1, and when control signal V ctrl is de-asserted, then logic 752 de-asserts the control signal When the control signal Φ1 is asserted, the control switch device 732 operates in its conducting state (conducting state). When the control signal Φ2 is asserted, the freewheeling switch device 734 operates in its off state (non-conducting state). In addition, the logic 752 generates the control signal Φ2 so that it is complementary to the control signal Φ1. When the control signal Φ2 is asserted, the freewheeling switch device 734 operates in its on state (conducting state), and when the control signal When de-asserted, the device operates in its off-state (non-conducting state). When the control switch device 732 is in its off-state, the freewheeling switch device 734 provides a path for current to flow through the inductor 730. In some embodiments, the logic 752 inserts a dead time between the assertion of the control signal Φ1 and the assertion of the control signal Φ2, and / or vice versa, to help prevent the control switch device 732 and the freewheeling switch device 734 from operating simultaneously in their respective conductive states. In some alternative embodiments, the freewheeling switch device 734 is replaced by a diode. In these alternative embodiments, the logic 752 does not need to generate the control signal Φ2, or the logic 752 can be omitted.

[0049] Figure 8 is a schematic diagram of a low noise voltage regulator 800, which is a low noise voltage regulator 400 having a buck-boost topology ( Figure 4 ) embodiment. Therefore, the output voltage V out The amplitude can be greater than, equal to, or less than the input voltage V in However, the output voltage V out The polarity of the input voltage V in For example, if V in is a positive voltage, then V out is a negative voltage. Figure 8 It is assumed that the input voltage V in is a positive voltage and the output voltage V out is drawn for negative voltage.

[0050] The control and power stage 202 of the low noise voltage regulator 400 is implemented by the control and power stage 802 in the low noise voltage regulator 800, and the error amplifier 212 of the low noise voltage regulator 400 is implemented by the error amplifier 812 in the low noise voltage regulator 800. The error amplifier 812 is a transconductance amplifier, so the error amplifier 812 is configured to generate a current error signal I err , which is the error signal E of the low noise voltage regulator 400 rr An embodiment of .

[0051] The control and power stage 802 includes a current sense resistor 828, an inductor 830, a control switch device 832, a freewheeling diode 834, a resistor 836, a capacitor 838, an oscillator 840, a slope compensation circuit 842, a summing circuit 844, a current sense amplifier 846, a comparator 848, and an SR flip-flop 850. The inductor 830, the control switch device 832, and the freewheeling diode 834 collectively form a buck-boost switching power converter power stage. The current sense resistor 828 and the control switch device 832 are electrically coupled in series between the input power node 214 and the switch node 854. The inductor 830 is electrically coupled between the switch node 854 and the ground node 218, and the freewheeling diode 834 is electrically coupled between the switch node 854 and the output power node 216. The control switch device 832 is responsive to a control signal V generated by the SR flip-flop 850 (discussed below). ctrl Control. The control switching device 832 includes, for example, one or more transistors (eg, FETs, BJTs, or IGBTs) and associated driver circuitry for the one or more transistors.

[0052] The current sense resistor 828, the resistor 836, the capacitor 838, the oscillator 840, the slope compensation circuit 842, the summing circuit 844, the current sense amplifier 846, the comparator 848 and the SR flip-flop 850 collectively form a control circuit of the control and power stage 802, which responds to the current error signal I err The duty cycle of the control switching device 832 is modulated to adjust the voltage amplitude at the setting node 220 to zero. Specifically, the resistor 836 and the capacitor 838 are electrically coupled in series between the output port 226 of the error amplifier 812 and the ground node 218, so that the resistor 836 and the resistor 838 together contribute to the current error signal I err Integrate to generate the corresponding voltage error signal V err The oscillator 840 periodically emits a clock signal CLK at the switching frequency of the low noise voltage regulator 800, and the clock signal CLK is provided to the S input of the SR flip-flop 850 and the slope compensation circuit 842. The SR flip-flop 850 is accordingly set by the assertion of the clock signal CLK. The slope compensation circuit 842 generates a slope compensation signal SLOPE based on the clock signal CLK. The slope compensation signal SLOPE is, for example, a linear or nonlinear slope signal, such as a ramp signal. The summing circuit 844 sums the slope compensation signal SLOPE with the voltage error signal V err Added to generate the compensation signal V comp .

[0053] The current sense amplifier 846 is configured to amplify the voltage V across the current sense resistor 828 when the control switching device 832 is in its on-state. res, to generate a current I flowing through the inductor 830 L Proportional signal V cs The comparator 848 converts the current sensing signal V cs With the compensation signal V comp is compared, and when the current sensing information V cs The amplitude reaches the compensation signal V comp When the magnitude of the comparator 848 asserts the reset signal V reset . Reset signal V reset is provided to the R input terminal of the SR flip-flop 850, and the SR flip-flop 750 responds to the reset signal V reset The SR flip-flop 850 generates a control signal V at its output Q. ctrl When the SR flip-flop 850 is set, the control signal V ctrl is asserted, and when the SR flip-flop 850 is reset, the control information V ctrl is de-asserted. Therefore, the control signal V ctrl The current error signal I err The amplitude of the PWM signal minimizes the duty cycle, thereby setting the voltage at node 220 to zero.

[0054] The control switch device 832 is controlled by the control signal V ctrl Specifically, when the control signal V ctrl When asserted, the control switch device 832 operates in its conductive state (conductive state), and when the control signal V ctrl When the control switch device 832 is in its off state (non-conducting state), the freewheeling diode 834 is a current I L In some alternative embodiments, the freewheeling diode 834 is replaced by a freewheeling switching device, and the control and power stage 802 is modified to generate a control signal to control the freewheeling switching device.

[0055] Figure 9 is a schematic diagram of a low noise voltage regulator 900, which is a low noise voltage regulator 200 having a SEPIC topology ( Figure 2 ) embodiment. Therefore, the output voltage V out The amplitude can be greater than, equal to, or less than the input voltage V in The amplitude of Figure 8 Compared with the low noise voltage regulator, the output voltage V out The polarity of the input voltage V in The polarity is the same. Figure 9 It is assumed that the input voltage V inand the output voltage V out Each of them is drawn at a positive voltage.

[0056] The control and power stage 202 of the low noise voltage regulator 200 is implemented by the control and power stage 902 in the low noise voltage regulator 900, and the error amplifier 212 of the low noise voltage regulator 200 is implemented by the error amplifier 912 in the low noise voltage regulator 900. The error amplifier 912 is a transconductance amplifier, so the error amplifier 912 is configured to generate a current error signal I err , which is the error signal E of the low noise voltage regulator 200 rr An embodiment of .

[0057] The control and power stage 902 includes a current sense resistor 928, a first inductor 930, a control switch device 932, a capacitor 934, a second inductor 936, a diode 938, a resistor 940, a capacitor 942, an oscillator 944, a slope compensation circuit 946, a summing circuit 948, a current sense amplifier 950, a comparator 952, and an SR flip-flop 954. The first inductor 930, the control switch device 932, the capacitor 934, the second inductor 936, and the diode 938 collectively form a SEPIC switching power converter power stage. The current sense resistor 928 and the first inductor 930 are electrically coupled in series between the input power node 214 and a first switching node 956. The control switch device 932 is electrically coupled between the first switching node 956 and the ground node 218, and the capacitor 934 is electrically coupled between the second switching node 958 and the first switching node 956. The second inductor 936 is electrically coupled between the second switching node 958 and the ground node 218, and the diode 938 is electrically coupled between the first switching node 958 and the output power node 216. The switching device 932 is controlled by a control signal V generated by the SR flip-flop 954 (discussed below). ctrl Control. The control switching device 932 includes, for example, one or more transistors (eg, FETs, BJTs, or IGBTs) and associated driver circuitry for the one or more transistors.

[0058] The current sense resistor 928, the resistor 940, the capacitor 942, the oscillator 944, the slope compensation circuit 946, the summing circuit 948, the current sense amplifier 950, the comparator 952 and the SR flip-flop 954 collectively form a control circuit of the control and power stage 902, which responds to the current error signal I errThe duty cycle of the control switching device 932 is modulated to adjust the voltage amplitude at the setting node 220 to zero. Specifically, the resistor 940 and the capacitor 942 are electrically coupled in series between the output port 226 of the error amplifier 912 and the ground node 218, so that the resistor 940 and the resistor 942 jointly integrate the current error signal I err To generate the corresponding voltage error signal V err The oscillator 944 periodically sends out a clock signal CLK at the switching frequency of the low noise voltage regulator 900, and the clock signal CLK is provided to the S input of the SR flip-flop 954 and the slope compensation circuit 946. The SR flip-flop 954 is set accordingly by the assertion of the clock signal CLK. The slope compensation circuit 946 generates a slope compensation signal SLOPE based on the clock signal CLK. The slope compensation signal SLOPE is, for example, a linear or nonlinear slope signal, such as a ramp signal. The summing circuit 948 adds the slope compensation signal SLOPE to the voltage error signal V err Added to generate the compensation signal V comp .

[0059] The current sense amplifier 950 is configured to amplify the voltage V across the current sense resistor 928 when the control switching device 932 is in its on-state. res , to generate a current I flowing through the first inductor 930 L Proportional signal V cs The comparator 952 converts the current sensing signal V cs With the compensation signal V comp is compared, and when the current sensing information V cs The amplitude reaches the compensation signal V comp When the magnitude of the comparator 952 is greater than the reset signal V reset . Reset signal V reset is provided to the R input terminal of the SR flip-flop 954, and the SR flip-flop 954 responds to the reset signal V reset The SR flip-flop 954 generates a control signal V at its output Q. ctrl When the SR flip-flop 954 is set, the control signal V ctrl is asserted, and when the SR flip-flop 954 is reset, the control information V ctrl is de-asserted. Therefore, the control signal V ctrl The current error signal I err The amplitude of the PWM signal minimizes the duty cycle, thereby setting the voltage at node 220 to zero. The switching device 932 is controlled by the control signal V ctrl Specifically, when the control signal V ctrlWhen asserted, the control switching device 932 operates in its conductive state (conductive state), and when the control signal V ctrl When de-asserted, it operates in its off state (non-conducting state).

[0060] Figure 7 、 8 The control circuits of control stages 702, 802, and 902 of FIG. 9 may be modified. For example, any of control stage 702, power stage 802, and power stage 902 may be modified to remove current sensing circuitry and associated components to operate according to a voltage-mode control scheme rather than a current-mode control scheme. As another example, any of control stage 702, power stage 802, and power stage 902 may be modified to operate according to a current-mode control scheme other than peak current-mode control, such as average current mode or valley current mode control.

[0061] Figure 10 is a schematic diagram of a low noise voltage regulator 1000, which is a low noise voltage regulator 400 having a low dropout linear regulator topology ( Figure 4 ) embodiment. In the low noise voltage regulator 1000, the output voltage V out The polarity is negative, and the input voltage V in The polarity is positive. The control and power stage 202 of the low noise voltage regulator 400 is implemented by the control and power stage 1002 in the low noise voltage regulator 1000, and the error amplifier 212 of the low noise voltage regulator 400 is implemented by the error amplifier 1012 in the low noise voltage regulator 1000. The error amplifier 1012 is a voltage amplifier, so the error amplifier 1012 is configured to generate a voltage error signal V err , which is the error signal E of the low noise voltage regulator 400 rr An embodiment of .

[0062] The control and power stage 1002 includes a charge pump 1028, a capacitor 1030, and a transistor 1032. The charge pump 1028 is electrically coupled between the input power node 214 and the charge pump node 1034, and the capacitor 1030 is electrically coupled between the charge pump node 1034 and the ground node 218. The transistor 1032 is an N-channel enhancement type FET including a source (S), a drain (D), and a gate (S). The source S of the transistor 1032 is electrically coupled to the charge pump node 1034, and the drain D of the transistor 1032 is electrically coupled to the output power node 216. The gate G of the transistor 1032 is electrically coupled to the output port 226 of the error amplifier 1012, so that the gate G of the transistor 1032 is controlled by the voltage error signal V err drive.

[0063] Charge pump 1028 converts the positive voltage V in Converted to negative voltage V cp The transistor 1032 works as a variable resistor under the control of the error amplifier 1012 to convert the voltage V cp Converted to output voltage V out Specifically, the error amplifier 1012 generates a voltage error signal V err Control transistor 1032 to adjust the voltage amplitude at the set node 220 to zero, so that the output voltage V out is a negative voltage whose magnitude is the voltage V across the reference resistor 206 ref Transistor 1032 may be replaced with a different type of transistor, such as a different type of FET or BJT, with appropriate changes to error amplifier 1012 and / or control and power stage 1002 .

[0064] The novel low noise voltage regulator disclosed herein can have multiple outputs. For example, Figure 11 FIG1 is a schematic diagram of a multi-output low-noise voltage regulator 1100, which is another embodiment of the novel low-noise voltage regulator disclosed herein. The low-noise voltage regulator 1100 includes a first control and power stage 1102, a second control and power stage 1104, a first output capacitor 1106, a second output capacitor 1108, a first reference resistor 1110, a second reference resistor 1112, a first reference capacitor 1114, a second reference capacitor 1116, a first reference current source 1118, a second reference current source 1120, a first error amplifier 1122, and a second error amplifier 1124. The first control and power stage 1102 is electrically coupled between a first input power node 1126 and a first output power node 1128, and the second control and power stage 1104 is electrically coupled between a second input power node 1130 and a second output power node 1132. The first output capacitor 1106 is electrically coupled between the first output power node 1128 and the ground node 1134, and the second output capacitor 1108 is electrically coupled between the second output power node 1132 and the ground node 1134. The voltage in the low-noise voltage regulator 1100 is referenced to the ground node 1134, and thus the voltage at the ground node 1134 is zero. Therefore, a positive voltage in the low-noise voltage regulator 1100 has a higher potential than the ground node 1134, and a negative voltage in the low-noise voltage regulator 1100 has a lower potential than the ground node 1134.

[0065] The low noise voltage regulator 1100 has a positive first input voltage V at a first input power node 1126. in_1 , and the low noise voltage regulator 1100 has a positive first output voltage V at the first output power node 1128 out_1The first control and power stage 1102, the first output capacitor 1106, the first reference resistor 1110, the first reference capacitor 1114, the first reference current source 1118 and the first error amplifier 1122 are collectively configured to output a first voltage from a first input voltage V in_1 Generates a first output voltage V out_1 Specifically, each of the first reference resistor 1110 and the first reference capacitor 1114 is electrically coupled between the first output power node 1128 and the first setting node 1136. The first reference current source 1118 is electrically coupled to the first setting node 1136. Although Figure 11 A first reference current source 1118 is depicted as being electrically coupled between a first set node 1136 and a ground node 1134, but the first reference current source 1118 may alternatively be electrically coupled between the first set node 1136 and one or more other nodes in place of or in addition to the ground node 1134. An input port 1137 of the first error amplifier 1122 is connected to the first set node 1136, and an input port 1138 of the first error amplifier 1112 is connected to the ground node 1134. An output port 1140 of the first error amplifier 1122 is electrically coupled to the first control and power stage 1102.

[0066] Similar to the above Figure 2 The reference current signal I ref In the manner discussed, substantially all first reference current signals I ref_1 Both flow through the first reference resistor 1110, thereby establishing a voltage V across the first reference resistor 1100 according to the following formula 5 ref_1 , where R ref_1 is the resistance of the first reference resistor 1110 .

[0067] V ref_1 =I ref_1 ·R ref_1 (Formula 5)

[0068] The first error amplifier 1122 is configured to generate a first error signal E at its output port 1140. rr_1 , where the first error signal E rr_1 The first error signal E is proportional to the difference between the voltage at the first setting node 1136 and the voltage at the ground node 1134. rr_1 It can be a voltage signal, a current signal or other types of signals. The first control and power stage 1102 includes a power stage ( Figure 11 ), such as a switching power converter power stage or a linear regulator power stage, and optional associated control circuitry ( Figure 11 not shown), similar to Figure 2The first control and power stage 1102 is configured to respond at least in part to a first error signal E generated by a first error amplifier 1122. rr_1 , the first input voltage V in_1 Converted to the first output voltage V out_1 , to minimize the first error signal E rr_1 Therefore, the first error amplifier 1122 generates the first error signal E rr_1 Control the first output voltage V out_1 The amplitude of the first setting node 1136 is adjusted to zero. Therefore, the first output voltage V out_1 The magnitude is equal to the voltage V across the first reference resistor 1110 ref_1 , and the low noise voltage regulator 1100 indirectly adjusts the first output voltage V by adjusting the voltage amplitude on the first setting node 1136 to zero out_1 Therefore, according to the above formula 5, the first output voltage V out_1 The amplitude.

[0069] The low noise voltage regulator 1100 achieves low electrical noise at the first output power node 1128 for reasons similar to those discussed above with respect to Figure 2 For reasons discussed above with respect to the low noise voltage regulator 200, the low noise voltage regulator 1100 has a unity gain with respect to the first output power node 1128 due to the noise from the first error amplifier 1122 and the noise from the first reference current source 1118. As another example, the first reference capacitor 1114 helps filter the noise across the first reference resistor 1110.

[0070] The low noise voltage regulator 1100 has a negative second input voltage V at the second input power node 1130. in_2 , and the low noise voltage regulator 1100 has a negative second output voltage V at the first output power node 1132 out_2 The second control and power stage 1104, the second output capacitor 1108, the second reference resistor 1112, the second reference capacitor 1116, the second reference current source 1120 and the second error amplifier 1124 are collectively configured to output a voltage from the second input voltage V in_2 Generates the second output voltage V out_2 Specifically, each of the second reference resistor 1112 and the second reference capacitor 1116 is electrically coupled between the second output power node 1132 and the second setting node 1142. The second reference current source 1120 is electrically coupled to the second setting node 1142. Although Figure 11The second reference current source 1120 is depicted as being electrically coupled between a second set node 1142 and a ground node 1134, but the second reference current source 1120 may alternatively be electrically coupled between the second set node 1142 and one or more other nodes in place of, or in addition to, the ground node 1134. An input port 1144 of the second error amplifier 1124 is connected to the second set node 1142, and an input terminal 1146 of the second error processor 1124 is connected to the ground node 1134. An output port 1148 of the second error amplifier 1124 is electrically coupled to the second control and power stage 1104.

[0071] Similar to the above Figure 2 The reference current signal I ref In the manner discussed, basically all second reference current signals I ref_2 Both flow through the second reference resistor 1112, thereby establishing a voltage V across the second reference resistor 1112 according to the following formula 6: ref_2 , where R ref_2 is the resistance of the second reference resistor 1112 .

[0072] V ref_2 =I ref_2 ·R ref_2 (Formula 6)

[0073] The second error amplifier 1124 is configured to generate a second error signal E at its output port 1148. rr_2 , where the second error information E rr_2 The second error signal E is proportional to the difference between the voltage at the second setting node 1142 and the voltage at the ground node 1134. rr_2 It can be a voltage signal, a current signal or other types of signals. The second control and power stage 1104 includes a power stage ( Figure 11 ), such as a switching power converter power stage or a linear regulator power stage, and optional associated control circuitry ( Figure 11 not shown), similar to Figure 2 The second control and power stage 1104 is configured to respond at least in part to a second error signal E generated by a second error amplifier 1124. rr_2 , the second input voltage V in_2 Converted to the second output voltage V out_2 , to minimize the second error information E rr_2 Therefore, the second error amplifier 1124 generates the second error signal E rr_second Control the second output voltage V out_2The amplitude of the second setting node 1142 is adjusted to zero. Therefore, the second output voltage V out_2 The magnitude is equal to the voltage V across the second reference resistor 1112 ref_2 , and the low noise voltage regulator 1100 indirectly adjusts the second output current V by adjusting the voltage amplitude on the second setting node 1142 to zero out_2 Therefore, the second output voltage V is set according to the above formula 6. out_2 Amplitude

[0074] The low noise voltage regulator 1100 achieves low electrical noise at the second output power node 1132 for reasons similar to those discussed above with respect to Figure 2 For reasons discussed above with respect to the low noise voltage regulator 200, the low noise voltage regulator 1100 has a unity gain relative to the second output power node 1132 due to the noise from the second error amplifier 1124 and the noise from the second reference current source 1120. As another example, the second reference capacitor 1116 helps filter the noise across the second reference resistor 1112.

[0075] Figure 12 is a schematic diagram of a low noise voltage regulator 1200, which is a low noise voltage regulator 1100 ( Figure 11 ), wherein (a) the first control and power stage 1102 is implemented by a transistor 1202 configured as a linear regulator power stage, (b) the second control and power stage 1104 is implemented by a transistor 1204 configured as a linear regulator power stage, (c) the first error amplifier 1122 is implemented by a first error amplifier 1222, and (d) the second error amplifier 1124 is implemented by a second error amplifier 1224. The low noise voltage regulator 1200 also includes a voltage source 1252 electrically coupled in series with the first reference current source 1118 and a voltage source 1258 electrically coupled in series with the second reference current source 1120. The transistor 1202 is a P-channel enhancement type FET having a source S electrically coupled to a first input power node 1126, a drain D electrically coupled to a second output power node 1128, and a gate G electrically coupled to an output port 1140 of the error amplifier 1222. The first error amplifier 1222 is configured to generate a voltage first error signal V for driving the gate G of the transistor 1202. err_1 The transistor 1204 is an N-channel enhancement type FET, whose source S is electrically coupled to the second input power node 1130, the drain D is electrically coupled to the second output power node 1132, and the gate G is electrically coupled to the output port 1148 of the first error amplifier 1224. The second error amplifier 1224 is configured to generate a voltage second error signal V for driving the gate G of the transistor 1204. err_2 voltage amplifier.

[0076] Figure 13 1 is a schematic diagram of a multi-output low noise voltage regulator 1300, which is another embodiment of the novel low noise voltage regulator with multiple outputs disclosed herein. The low noise voltage regulator 1300 includes N blocks 1301, where N is an integer greater than 1. In this document, a specific instance of an item may be referred to by using a number in parentheses (e.g., block 1301 (1)), while a number without parentheses refers to any such item (e.g., block 1301). Each block 1301 includes a low noise voltage regulator 200 ( Figure 2 ) is an example of an element of . Therefore, the low noise voltage regulator 1300 has N output power nodes 216, wherein each output power node 216 has a respective output voltage V out Each block 1301 does not need to have the same configuration. For example, the polarity of the reference current source 210 can be changed between two or more blocks 1301 so that the output voltage V out The polarity of is changed between two or more blocks 1301. As another example, the configuration of the control and power stage 202 may vary between blocks 1301. For example, in one block 1301, the control and power stage 202 may include a switching power converter power stage, while in another block 1301, the control and power stage 202 may include a linear regulator power stage.

[0077] Although Figure 13 Blocks 1301 are depicted as discrete elements, but two or more blocks 1301 may share one or more nodes, or even one or more components. For example, in some embodiments, blocks 1301 share a common ground node 218 and / or a common input power node 214. For example, Figure 14 is a block diagram of a low noise voltage regulator 1400, which is an embodiment of the low noise voltage regulator 1300, wherein (i) N=4, (ii) all four blocks 1301 share a common input power node 214 and therefore have a common input voltage V in However, each block 1301 has a different corresponding output power node 216 and a corresponding output voltage V out To make it clear, Figure 14 The details of block 1301 are not shown.

[0078] As another example, in some alternative embodiments, two or more blocks 1301 share a common input power node 214 and a common power output node 216, such that the blocks 1301 are electrically coupled in parallel. In these alternative embodiments, the low-noise voltage regulator optionally further includes a current sharing circuit (not shown) to help achieve equal sharing of current between the blocks 1301.

[0079] Reference again Figure 13 In some embodiments, two or more blocks 1301 are electrically coupled in series. For example, Figure 15 is a block diagram of a low noise voltage regulator 1500, which is an embodiment of the low noise voltage regulator 1300, wherein (i) N=3 and (ii) blocks 1301 are electrically coupled in series. For clarity of illustration, Figure 15 The details of block 1301 are not shown in FIG. In the low noise voltage regulator 1500, the output power node 216(1) of block 1301(1) and the input power node 214(2) of block 1301(2) are the same node, so that the output voltage V out (1) and the input voltage V of block 1301 (2) in (2) are the same. In addition, the output power node 216 (2) of block 1301 (2) and the input power node 214 (3) of block 1301 (3) are the same node, so that the output voltage V out (2) and the input voltage V of block 1301 (3) in (3) Same.

[0080] Feature combination

[0081] The above features can be combined in various ways without departing from the scope of this document. The following examples illustrate some possible combinations.

[0082] (A1) A low noise voltage regulator comprising: (1) an error amplifier configured to generate an error signal proportional to a difference between a voltage at a ground node and a voltage at a set node, (2) a reference resistor electrically coupled between an output power node and the set node, (3) a reference current source electrically coupled to the set node, and (4) a control and power stage electrically coupled between an input power node and the output power node. The control and power stage is configured to convert an input voltage to an output voltage in response to the error signal to minimize a magnitude of the error signal, wherein the input voltage is a voltage at the input power node and the output voltage is a voltage at the output power node.

[0083] (A2) The low noise voltage regulator denoted as (A1) may further include a reference capacitor electrically coupled in parallel with the reference resistor.

[0084] (A3) In the low-noise voltage regulator represented as (A1) or (A2), (1) the first input port of the error amplifier can be connected to the setting node; and (2) the second input port of the error amplifier can be connected to the ground node.

[0085] (A4) Any of the low noise voltage regulators denoted as (A1) to (A3) may further include a voltage source electrically coupled in series with the reference current source.

[0086] (A5) In the low noise voltage regulator denoted as (A4), the voltage source may include a charge pump.

[0087] (A6) In the low noise voltage regulator denoted as (A4), (1) the voltage source may include a charge pump and a linear regulator, and (2) the linear regulator may be configured to convert a voltage generated by the charge pump into a voltage of the voltage source.

[0088] (A7) In any one of the low noise voltage regulators represented as (A1) to (A6), the reference current source can be configured to generate a reference current signal flowing out of the setting node so that the output voltage is positive relative to the ground node.

[0089] (A8) In any one of the low-noise voltage regulators represented as (A1) to (A6), the reference current source can be configured to generate a reference current signal flowing to the ground node so that the output voltage is negative relative to the ground point.

[0090] (A9) In any of the low noise voltage regulators denoted as (A1) to (A8), the control and power stage may include a switching power converter power stage.

[0091] (A10) In any of the low noise voltage regulators denoted as (A1) through (A8), the control and power stage may include a linear regulator power stage.

[0092] (A11) In any one of the low-noise voltage regulators denoted as (A1) to (A8), the low-noise voltage regulator may have a boost topology.

[0093] (A12) In any one of the low-noise voltage regulators denoted as (A1) to (A8), the low-noise voltage regulator may have a buck-boost topology.

[0094] (A13) In any one of the low noise voltage regulators denoted as (A1) to (A8), the low noise voltage regulator may have a single-ended primary inductor converter (SEPIC) topology.

[0095] (B1) A multi-output low-noise voltage regulator includes a first error amplifier, a first reference resistor, a first reference current source, a first control and power stage, a second error amplifier, a second reference resistor, a second reference current source, and a second control and power stage. The first error amplifier is configured to generate a first error signal proportional to the difference between a voltage at a first ground node and a voltage at a first setting node; the first reference resistor is electrically coupled between a first output power node and the first setting node; and the first reference current source is electrically coupled to the first setting node. The first control and power stage is electrically coupled between a first input power node and the first output power node, and the first control and power stage is configured to convert a first input voltage to a first output voltage in response to the first error signal to minimize the magnitude of the first error signal. The first input voltage is the voltage at the first input power node, and the first output voltage is the voltage at the first output power node. The second error amplifier is configured to generate a second error signal proportional to the difference between a voltage at a second ground node and a voltage at a second setting node; the second reference resistor is electrically coupled between a second output power node and the second setting node; and the second reference current source is electrically coupled to the second setting node. A second control and power stage is electrically coupled between a second input power node and a second output power node, and the second control and power stage is configured to convert a second input voltage to a second output voltage in response to the second error signal to minimize a magnitude of the second error signal. The second input voltage is the voltage at the second input power node, and the second output voltage is the voltage at the second output power node.

[0096] (B2) The multi-output low noise voltage regulator represented as (B1) may also include: (1) a first reference capacitor electrically coupled in parallel with the first reference resistor; and (2) a second reference capacitor electrically coupled in parallel with the second reference resistor.

[0097] (B3) In any one of the multi-output low noise voltage regulators represented as (B1) or (B2), (1) the first ground node and the second ground node can be a common ground node; (2) the first reference current source can be configured to generate a first reference current signal flowing out of the first setting node so that the first output voltage is positive relative to the common ground node; and (3) the second reference current source can be configured to generate a second reference current signal flowing to the second setting node so that the second output voltage is negative relative to the common ground node.

[0098] (C1) A method for controlling a low noise voltage regulator comprises: (1) establishing a voltage having a first amplitude across a reference resistor electrically coupled between an output power node of the low noise voltage regulator and a set node of the low noise voltage regulator, wherein the first amplitude is a desired amplitude of an output voltage and the output voltage is a voltage at the output power node of the low noise voltage regulator, (2) generating an error signal representing a difference between a voltage at the set node of the low noise voltage regulator and a voltage at a ground node, and (3) controlling a control and power stage electrically coupled between an input power node and the output power node in response to the error signal, wherein the control and power stage is configured to convert an input voltage to an output voltage in response to the error signal so as to minimize the amplitude of the error signal and the input voltage is the voltage at the input power node.

[0099] (C2) The method denoted as (C1) may further include filtering noise across the reference resistor using a capacitor electrically coupled in parallel with the reference resistor.

[0100] (C3) In the method denoted as (C1) or (C2), establishing the voltage having the first magnitude across the reference resistor may include applying a reference current signal to the reference resistor.

[0101] (C4) The method denoted as (C3) may further include generating the reference current signal using a linear regulator powered from the input power node.

[0102] Changes may be made to the methods, devices, and systems described above without departing from the scope of this disclosure. It should be noted, therefore, that the foregoing description and the accompanying drawings are to be interpreted as illustrative rather than restrictive. The following claims are intended to cover the generic and specific features described herein, as well as all statements of the scope of the methods and systems that, by definition, fall within the scope of the present disclosure.

Claims

1. A low-noise voltage regulator, comprising: an error amplifier configured to generate an error signal proportional to a difference between a voltage at a ground node and a voltage at a set node; a reference resistor electrically coupled between the output power node and the set node; a reference current source electrically coupled to the set node; and a control and power stage electrically coupled between an input power node and the output power node, the control and power stage configured to convert an input voltage to an output voltage in response to the error signal to minimize a magnitude of the error information, the input voltage being the voltage at the input power node and the output voltage being the voltage at the output power node. 2 . The low noise voltage regulator of claim 1 , further comprising a reference capacitor electrically coupled in parallel with the reference resistor.

3. The low noise voltage regulator according to claim 1 , wherein: The first input port of the error amplifier is connected to the set node; and The second input port of the error amplifier is connected to the ground node. 4 . The low noise voltage regulator of claim 1 , further comprising a voltage source electrically coupled in series with the reference current source.

5. The low noise voltage regulator of claim 4, wherein the voltage source comprises a charge pump.

6. The low noise voltage regulator according to claim 4, wherein: The voltage source includes a charge pump and a linear regulator; and The linear regulator is configured to convert the voltage generated by the charge pump into a voltage of the voltage source. 7 . The low noise voltage regulator of claim 1 , wherein the reference current source is configured to generate a reference current signal flowing out of the setting node such that the output voltage is positive with respect to the ground node. 8 . The low noise voltage regulator of claim 1 , wherein the reference current source is configured to generate a reference current signal flowing toward the ground node such that the output voltage is negative relative to the ground node.

9. The low noise voltage regulator of claim 1, wherein the control and power stage comprises a switching power converter power stage.

10. The low noise voltage regulator of claim 1, wherein the control and power stage comprises a linear regulator power stage.

11. The low noise voltage regulator of claim 1, wherein the low noise voltage regulator has a boost topology. 12 . The low noise voltage regulator of claim 1 , wherein the low noise voltage regulator has a buck-boost topology.

13. The low noise voltage regulator of claim 1, wherein the low noise voltage regulator has a single-ended primary inductor converter (SEPIC) topology.

14. A multi-output low-noise voltage regulator comprising: a first error amplifier configured to generate a first error signal proportional to a difference between a voltage at the first ground node and a voltage at the first set node; a first reference resistor electrically coupled between the first output power node and the first set node; a first reference current source electrically coupled to the first setting node; a first control and power stage electrically coupled between a first input power node and the first output power node, the first control and power stage configured to convert a first input voltage to a first output voltage in response to the first error signal to minimize a magnitude of the first error signal, the first input voltage being the voltage at the first input power node and the first output voltage being the voltage at the first output power node; a second error amplifier configured to generate a second error signal proportional to a difference between a voltage at the second ground node and a voltage at the second set node; a second reference resistor electrically coupled between the second output power node and the second set node; a second reference current source electrically coupled to the second setting node; and a second control and power stage electrically coupled between a second input power node and the second output power node, the second control and power stage being configured to convert a second input voltage to a second output voltage in response to the second error signal to minimize a magnitude of the second error signal, the second input voltage being the voltage at the second input power node, and the second output voltage being the voltage at the second output power node.

15. The multi-output low noise voltage regulator according to claim 14, further comprising: ； a first reference capacitor electrically coupled in parallel with the first reference resistor; and A second reference capacitor is electrically coupled in parallel with the second reference resistor.

16. The multi-output low noise voltage regulator according to claim 14, wherein: The first ground node and the second ground node are a common ground node; The first reference current source is configured to generate a first reference current signal flowing from the first setting node so that the first output voltage is positive relative to the common ground node; and The second reference current source is configured to generate a second reference current signal flowing to the second setting node such that the second output voltage is negative relative to the common ground node.

17. A method for controlling a low noise voltage regulator, the method comprising: establishing a voltage having a first magnitude across a reference resistor electrically coupled between an output power node of the low noise voltage regulator and a set node of the low noise voltage regulator, the first magnitude being a desired magnitude of an output voltage, the output voltage being the voltage at the output power node of the low noise voltage regulator; generating an error signal representing a difference between a voltage at a set node and a voltage at a ground node of the low noise voltage regulator; and In response to the error signal, controlling a control and power stage electrically coupled between an input power node and the output power node, the control and power stage being configured to convert an input voltage to an output voltage in response to the error signal to minimize a magnitude of the error signal, the input voltage being the voltage at the input power node.

18. The method of claim 17, further comprising filtering noise across the reference resistor using a capacitor electrically coupled in parallel with the reference resistor.

19. The method of claim 17, wherein establishing a voltage having the first magnitude across the reference resistor comprises applying a reference current signal to the reference resistor.

20. The method of claim 19, further comprising generating the reference current signal using a linear regulator powered from the input power node.

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