FPGA Code Similarity Detection Method and Apparatus Based on Weighted Directed Graph

Abstract

This invention discloses a method and apparatus for FPGA code similarity detection based on weighted directed graphs. The method includes: reading two FPGA hardware description language code modules to be detected; constructing corresponding directed graphs based on the data flow relationships within the two modules; weighting the edges of the directed graphs to obtain a weighted directed graph; obtaining the corresponding weighted adjacency matrix; performing same-dimensional processing on the weighted adjacency matrices of the two modules to obtain same-dimensional weighted adjacency matrices of the two modules; calculating the total feature value of the weighted adjacency matrices; subtracting the same-dimensional weighted adjacency matrices of the two modules and performing weighted processing to obtain the feature difference; and calculating the similarity between the two modules based on the feature difference and the total feature value. This method is easy to implement, can be easily automated by computer, has high detection efficiency, and can well meet the needs of the FPGA software testing industry for test case reuse.

Description

Technical Field

[0001] This invention belongs to the field of FPGA testing technology, and in particular, it is a method and apparatus for FPGA code similarity detection based on weighted directed graphs. Background Technology

[0002] Code similarity detection refers to the analysis of the similarity between software source codes using certain detection methods, and the quantification of the degree of similarity in the form of numerical values ​​or percentages, thereby supporting applications in fields such as code reuse, intellectual property protection, code component analysis, and security vulnerability discovery.

[0003] Currently, there are four main methods for code similarity detection: vector space method, token sequence method, abstract syntax tree method, and program dependency graph method. Vector space method uses operators, operands, capacity, etc., as features of the program, representing the program as feature vectors. It measures the similarity between programs by measuring the distance between any two vectors. This method is generally ineffective at measuring structural changes in programs. Token sequence representation analyzes the input source code using a lexical analyzer and converts it into a token sequence using certain rules. Then, it uses a matching algorithm to measure the similarity between programs. This method can detect code segments with different syntax but similar functions, but it often hides the program's organizational structure when measuring similarity. Abstract syntax trees (ASTs) are a commonly used intermediate representation method in program analysis. They measure program similarity by comparing the similarity between subtrees. However, this method is not very accurate in similarity calculation and has limited practicality. Program dependency graphs can represent the dependencies between data and control within code, enabling semantic analysis of the code. However, this method typically compares similarity based on traditional directed graphs, which is computationally intensive. Furthermore, program dependency graphs only focus on the differences in control flow and data flow, ignoring the differences in data transmitted within the code, which is unacceptable in some application areas.

[0004] In the field of FPGA software testing, testing is primarily accomplished through functional and timing simulations, which are extremely time-consuming. Therefore, test case reuse is highly valued in the FPGA software testing industry. Test case reuse requires finding historical code similar to the code under test and adaptively modifying the test cases of the historical code based on the differences between the current code under test and the historical code. The requirements for code similarity detection in test case reuse scenarios are not entirely the same as in traditional application scenarios. Test case reuse focuses on the similarity of code control flow and data flow. However, in FPGA software, because its code is executed in parallel, changes in control flow have a minimal impact on test cases; the focus is on data flow and differences in data flow bit width. Current code similarity detection methods cannot effectively reflect the differences in code data flow and data bit width simultaneously, and they suffer from high processing overhead, failing to meet the needs of rapid large-scale code similarity detection. Ji Zefan and Liu Hui of the Air Force Early Warning Academy of the Chinese People's Liberation Army proposed a code similarity comparison method based on frequent subgraph mining. Although this method is more efficient than previous methods, it is still too complex and time-consuming. Zou Juan, Wu Bing, and others from Xiangtan University proposed a code similarity detection method and system based on relational variables. This method only considers the data dependencies in the code, without considering the overall data flow or the differences in data transmitted in the data flow.

[0005] To address the need for code similarity detection in the FPGA software testing industry, there is an urgent need to propose a technical means that can quickly detect historical code that is most similar to the data flow and data bit width of the FPGA software code under test, thereby improving the effectiveness of FPGA software test case reuse and reducing the workload of FPGA software functional simulation and timing simulation. Summary of the Invention

[0006] The purpose of this invention is to address the problem that existing code similarity detection methods cannot adequately meet the needs of the FPGA software testing industry for test case reuse under current technological conditions. Based on the characteristics of FPGA software test case reuse, which mainly focuses on the differences in data flow and data flow bit width between tested codes, this invention proposes an FPGA code similarity detection method and apparatus based on weighted directed graphs. This method focuses on the differences in data flow and bit width between FPGA software codes, making it highly suitable for the needs of FPGA software test case reuse. Furthermore, it is easy to implement, readily automatable by computer, and has high detection efficiency, thus effectively meeting the needs of the FPGA software testing industry for test case reuse.

[0007] The technical solution to achieve the purpose of this invention is as follows: Firstly, this invention provides an FPGA code similarity detection method based on weighted directed graphs, comprising the following steps:

[0008] Step 1: Read the two FPGA hardware description language code modules to be tested, and construct the corresponding directed graph based on the data flow relationship between the two modules;

[0009] Step 2: Based on the signal bit width transmitted in the data streams within the two modules, weight the edges of the constructed directed graph to obtain the weighted directed graphs corresponding to the two modules.

[0010] Step 3: Based on the weighted directed graph of the two modules, obtain the corresponding weighted adjacency matrix;

[0011] Step 4: Perform same-dimensional processing on the weighted adjacency matrices of the two modules to obtain same-dimensional weighted adjacency matrices for the two modules.

[0012] Step 5: Calculate the total feature value of the weighted adjacency matrix based on the dimension of the weighted adjacency matrix and the set threshold. Then, subtract the weighted adjacency matrices of the same dimension corresponding to the two modules and perform weighted processing to obtain the feature difference. Calculate the similarity between the two modules based on the feature difference and the total feature value.

[0013] Secondly, the present invention provides an FPGA code similarity detection device based on a weighted directed graph, used to implement the method described in the first aspect, the device comprising:

[0014] The directed graph generation module is used to read the two FPGA hardware description language code modules to be tested and construct the corresponding directed graph based on the data flow relationship between the two modules.

[0015] The directed graph weighting module is used to weight the edges of the constructed directed graph according to the signal bit width transmitted in the data streams within the two modules, so as to obtain the weighted directed graphs corresponding to the two modules.

[0016] The adjacency matrix generation module is used to obtain the corresponding weighted adjacency matrix based on the weighted directed graph of the two modules, and to perform same-dimensional processing on the weighted adjacency matrices of the two modules to obtain the same-dimensional weighted adjacency matrix of the two modules.

[0017] The similarity calculation module is used to calculate the total feature value of the weighted adjacency matrix based on the dimension of the weighted adjacency matrix and the set threshold. Then, the corresponding weighted adjacency matrices of the two modules are subtracted and weighted to obtain the feature difference. The similarity between the two modules is calculated based on the feature difference and the total feature value.

[0018] Thirdly, the present invention provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the method described in the first aspect.

[0019] Fourthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in the first aspect.

[0020] Fifthly, the present invention provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method described in the first aspect.

[0021] Compared with the prior art, the beneficial effects of the present invention are: 1) The method can better detect the differences in data flow and bit width between codes, which is more suitable for the needs of test case reuse in the FPGA software industry; 2) The method is easy to implement by computer automation, has high detection efficiency, and is very practical.

[0022] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0023] Figure 1 This is a flowchart of the FPGA code similarity detection method based on weighted directed graphs proposed in this invention.

[0024] Figure 2 These are code examples for module A and module B.

[0025] Figure 3 It is a directed graph instance of module A and module B.

[0026] Figure 4 It is a weighted directed graph instance of module A and module B.

[0027] Figure 5 It is an instance of the adjacency matrix of module A and module B.

[0028] Figure 6 It is a numerical instance of the adjacent matrix elements of module A and module B.

[0029] Figure 7 It is an instance of the up-dimensional adjacency matrix of module A.

[0030] Figure 8 This is a schematic diagram of the FPGA code similarity detection device based on weighted directed graphs proposed in this invention. Detailed Implementation

[0031] Combination Figure 1 The present invention proposes an FPGA code similarity detection method based on weighted directed graphs, which specifically includes the following steps:

[0032] Step 1: Read the FPGA hardware description language code module A and module B to be tested, and construct the corresponding directed graph based on the data flow relationship inside module A and module B;

[0033] Step 2: Based on the signal bit width transmitted in the internal data streams of modules A and B, weight the edges of the constructed directed graph to obtain the weighted directed graphs corresponding to modules A and B.

[0034] Step 21: Traverse each directed edge of the directed graph corresponding to module A and module B, and find the data transfer relationship in the module corresponding to the directed edge;

[0035] Step 22: Perform bit width analysis on the data transmission relationship corresponding to each directed edge, and use the data transmission bit width as the weight of the directed edge to obtain the weighted directed graph of module A and module B.

[0036] Step 3: Based on the weighted directed graphs of module A and module B, obtain the corresponding weighted adjacency matrix;

[0037] Step 31: Traverse all nodes of the weighted directed graphs corresponding to module A and module B, and number each node sequentially. The numbering criteria used should ensure that the number of each node remains unchanged during each traversal.

[0038] Step 32: Construct a weighted adjacency matrix for module A and module B. and The elements in the square matrix and The value is equal to the value of the node in the weighted directed graph of module A and module B. To the node The weight of a directed edge, where elements and The value is set to 1. , .

[0039] Step 4: Perform same-dimensional processing on the weighted adjacency matrices of module A and module B to obtain same-dimensional weighted adjacency matrices of module A and module B.

[0040] Step 41: Calculate the weighted adjacency matrix and dimensional difference ,if If the value is zero, no same-dimensional processing is performed and step 4 ends; otherwise, steps 42-43 are executed for the two adjacent square matrices. and The adjacency square matrix with the smaller dimension (i.e., the smaller value among M and N) is used for... Dimensional upgrading and labeling. ;

[0041] Step 42: For the weighted adjacency matrix Choose any number The row is filled with zeros, and a row of all zeros is inserted before or after it. , and then in the Insert a column of all zeros at the same positions in the column to obtain a weighted adjacency matrix. Repeat the above processing for the k-th row and k-th column until the weighted adjacency matrix is ​​obtained. ;

[0042] Step 43: Repeat step 42 to obtain all Z possible weighted adjacency matrices after dimensionality increase. .

[0043] Step 5: Calculate the total feature value of the weighted adjacency matrix based on the dimension of the weighted adjacency matrix and the set threshold. Then, subtract the weighted adjacency matrices of the same dimension corresponding to module A and module B and perform weighted processing to obtain the feature difference. Calculate the similarity between module A and module B based on the feature difference and the total feature value.

[0044] Step 51: Set the bit width influence factor Q, where Q > 0. For application scenarios where the difference in data stream bit width is not considered during the module similarity comparison, set Q to 1; otherwise, set Q to the bit width of the signal with the largest bit width in the module.

[0045] Step 52: Calculate the total eigenvalue. , where T equals the maximum value of M and N;

[0046] Step 53: Connect the adjacent square matrix and Medium-dimensional large square matrices are respectively with Subtract the elements, take the absolute value of each element of the resulting square matrix, and then compare it with Q. If the absolute value is greater than Q, set it to Q.

[0047] Step 54: Add all elements of each subtracted square matrix after processing in Step 53, and take the smallest sum as the characteristic difference. ;

[0048] Step 55: According to the formula Obtain the similarity scores between modules A and B.

[0049] Based on the same inventive concept, this invention also provides an FPGA code similarity detection device based on a weighted directed graph, such as... Figure 8As shown, the device includes a directed graph generation module, a directed graph weighting module, an adjacency matrix generation module, and a similarity calculation module. The directed graph generation module reads the FPGA hardware description language code modules A and B to be tested, and constructs corresponding directed graphs based on the data flow relationships within modules A and B. The directed graph weighting module weights the edges of the constructed directed graphs according to the signal bit widths transmitted in the data flows of modules A and B, resulting in weighted directed graphs for modules A and B. The adjacency matrix generation module generates corresponding weighted adjacency matrices based on the weighted directed graphs of modules A and B, and further processes the weighted adjacency matrices of modules A and B to obtain weighted adjacency matrices of modules A and B with the same dimension. The similarity calculation module calculates the total feature value of the weighted adjacency matrix based on the dimension of the weighted adjacency matrix and a set threshold, then subtracts the weighted adjacency matrices of modules A and B with the same dimension and performs weighting to obtain the feature difference, and calculates the similarity between modules A and B based on the feature difference and the total feature value.

[0050] The specific implementation methods of the directed graph generation module, directed graph weighting module, adjacency matrix generation module and similarity calculation module are the same as those of the aforementioned detection method, and will not be repeated here.

[0051] The present invention will now be described in further detail with reference to the embodiments.

[0052] Example

[0053] The FPGA code similarity detection method based on weighted directed graphs proposed in this invention is applicable to all FPGA code. To better illustrate this invention with examples, two module examples are selected as the detection targets:

[0054] 1. Module A: As the basic module;

[0055] 2. Module B: Based on Module A, a new level of data stream is added and the data bit width of a certain level is modified.

[0056] The specific processing steps are as follows:

[0057] Step 1: Read the FPGA hardware description language code module A and module B to be tested, such as... Figure 2 As shown, a directed graph is constructed based on the data flow relationships within module A and module B, as follows: Figure 3 As shown;

[0058] Step 2: Based on the signal bit width transmitted in the internal data streams of modules A and B, weight the edges of the constructed directed graph to obtain the weighted directed graphs corresponding to modules A and B.

[0059] Step 21: Traverse each directed edge of the directed graph corresponding to module A and module B. Module A has a total of 6 directed edges corresponding to the data transfer relationships within the module, and module B has a total of 7 directed edges corresponding to the data transfer relationships within the module, such as... Figure 3 As shown;

[0060] Step 22: Perform bit-width analysis on the data transmission relationship corresponding to each directed edge in module A and module B, and use the data transmission bit-width as the weight of the directed edge to obtain the weighted directed graph of module A and module B, as shown below. Figure 4 As shown.

[0061] Step 3: Based on the weighted directed graphs of module A and module B, obtain the corresponding weighted adjacency matrix;

[0062] Step 31: Traverse all nodes of the weighted directed graphs corresponding to module A and module B, and number each node sequentially, such as... Figure 4 As shown;

[0063] Step 32: Construct a weighted adjacency matrix for module A and module B. and , of which elements and The values ​​are all set to 1, such as Figure 5 As shown, the adjacency matrix with specific weight values ​​is as follows: Figure 6 As shown.

[0064] Step 4: Perform same-dimensional processing on the weighted adjacency matrices of module A and module B to obtain same-dimensional weighted adjacency matrices of module A and module B.

[0065] Step 41: Calculate the weighted adjacency matrix. and dimensional difference Perform steps 42-43 on the weighted adjacency matrix with smaller dimension. Perform 1-dimensional upscaling;

[0066] Step 42: For the weighted adjacency matrix Select the first row and insert a row of all-zero data before it. Then, insert a column of all-zero data in the same position in the first column to obtain a weighted adjacency matrix. ;

[0067] Step 43: Repeat step 42 and select "before rows 2-6 and columns 2-6" and "after row 6 and column 6" as insertion positions in sequence to obtain 7 weighted adjacency matrices after dimensionality increase. ,like Figure 7 As shown.

[0068] Step 5: Calculate the total feature value of the weighted adjacency matrix based on the dimension of the weighted adjacency matrix and the set threshold. Then, subtract the weighted adjacency matrices of the same dimension corresponding to module A and module B and perform weighted processing to obtain the feature difference. Calculate the similarity between module A and module B based on the feature difference and the total feature value.

[0069] Step 51: The application scenario of this module needs to consider the bit width difference. Therefore, the bit width influence factor is set to the bit width of the signal with the largest bit width in the module. ;

[0070] Step 52: According to the formula for total eigenvalue ,in , The total value of the features is calculated. ;

[0071] Step 53: Connect the adjacent square matrix and Medium-dimensional square matrix respectively with Subtract, take the absolute value of each element of the subtracted matrix, and then multiply by the result. Compare values; values ​​greater than 32 are set to 32; otherwise, the actual value is used.

[0072] Step 54: Add all elements of each subtracted square matrix after step 53 to obtain 7 summations: , , , , , , Take the smallest sum of the two values. As the final feature difference ;

[0073] Step 55: According to the formula ,in , The similarity scores between modules A and B are calculated. .

[0074] The above description is merely a preferred embodiment of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention. All components not explicitly stated in this embodiment can be implemented using existing technology.

Claims

1. A method for FPGA code similarity detection based on weighted directed graphs, characterized in that, Includes the following steps: Step 1: Read the two FPGA hardware description language code modules to be tested, and construct the corresponding directed graph based on the data flow relationship between the two modules; Step 2: Based on the signal bit width transmitted in the data streams within the two modules, weight the edges of the constructed directed graph to obtain the weighted directed graphs corresponding to the two modules. Step 3: Based on the weighted directed graph of the two modules, obtain the corresponding weighted adjacency matrix; Step 4: Perform same-dimensional processing on the weighted adjacency matrices of the two modules to obtain same-dimensional weighted adjacency matrices for the two modules, including the following steps: Step 41: Calculate the weighted adjacency matrix and If the dimension difference D is zero, then no same-dimensional processing is performed and step 4 ends; otherwise, steps 42-43 are executed for the two adjacent square matrices. and Perform D-dimensional upsizing on the adjacency matrix with small mid-dimensionality and label it as... ; Step 42: For the weighted adjacency matrix Choose any number The row is filled with zeros, and a row of all zeros is inserted before or after it. , and then in the Insert a column of all zeros at the same positions in the column to obtain a weighted adjacency matrix. Repeat the above processing for the k-th row and k-th column until the weighted adjacency matrix is ​​obtained. ; Step 43: Repeat step 42 to obtain all Z possible weighted adjacency matrices after dimensionality increase. ; Step 5: Calculate the total feature value of the weighted adjacency matrix based on its dimension and a set threshold. Then, subtract the weighted adjacency matrices of the same dimension corresponding to the two modules and perform a weighted summation to obtain the feature difference. Calculate the similarity between the two modules based on the feature difference and the total feature value, including the following steps: Step 51: Set the bit width influence factor Q, where Q > 0. For application scenarios where the difference in data stream bit width is not considered during the module similarity comparison, set Q to 1; otherwise, set Q to the bit width of the signal with the largest bit width in the module. Step 52: Calculate the total eigenvalue. ,in equal and The maximum value in; Step 53: Connect the adjacent square matrix and Medium-dimensional large square matrices are respectively with Subtract the elements, take the absolute value of each element of the resulting square matrix, and then compare it with Q. If the absolute value is greater than Q, set it to Q. Step 54: Add all elements of each subtracted square matrix after processing in Step 53, and take the smallest sum as the characteristic difference. ; Step 55: According to the formula Obtain the similarity scores between module A and module B.

2. The FPGA code similarity detection method based on weighted directed graphs according to claim 1, characterized in that, In step 2, the edges of the constructed directed graph are weighted according to the signal bit width transmitted in the data streams within the two modules to obtain a weighted directed graph corresponding to the two modules, including the following steps: Step 21: Traverse each directed edge of the directed graph corresponding to module A and module B, and find the data transfer relationship in the module corresponding to the directed edge; Step 22: Perform bit width analysis on the data transmission relationship corresponding to each directed edge, and use the data transmission bit width as the weight of the directed edge to obtain the weighted directed graph of module A and module B.

3. The FPGA code similarity detection method based on weighted directed graphs according to claim 1, characterized in that, Step 3 yields the corresponding weighted adjacency matrix, including the following steps: Step 31: Traverse all nodes of the weighted directed graphs corresponding to module A and module B, and number each node sequentially. The numbering criteria used should ensure that the number of each node remains unchanged during each traversal. Step 32: Construct a weighted adjacency matrix for module A and module B. and The elements in the square matrix and The value is equal to the value of the node in the weighted directed graph of module A and module B. To the node The weight of a directed edge, where elements and The value is set to 1. , .

4. An FPGA code similarity detection device based on weighted directed graphs, characterized in that, The apparatus for implementing the method according to any one of claims 1 to 3 comprises: The directed graph generation module is used to read the two FPGA hardware description language code modules to be tested and construct the corresponding directed graph based on the data flow relationship between the two modules. The directed graph weighting module is used to weight the edges of the constructed directed graph according to the signal bit width transmitted in the data streams within the two modules, so as to obtain the weighted directed graphs corresponding to the two modules. The adjacency matrix generation module is used to obtain the corresponding weighted adjacency matrix based on the weighted directed graph of the two modules, and to perform same-dimensional processing on the weighted adjacency matrices of the two modules to obtain the same-dimensional weighted adjacency matrix of the two modules. The similarity calculation module is used to calculate the total feature value of the weighted adjacency matrix based on the dimension of the weighted adjacency matrix and the set threshold. Then, the corresponding weighted adjacency matrices of the two modules are subtracted and weighted to obtain the feature difference. The similarity between the two modules is calculated based on the feature difference and the total feature value.

5. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method as described in any one of claims 1-3.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps of the method as described in any one of claims 1-3.

7. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the steps of the method described in any one of claims 1-3.

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