A DFT ECO system and method

Abstract

This invention proposes a system and method for DFT ECO. The method receives a user-input DFT reference netlist as the first input information; this netlist is logically complete and can be detected by the ATPG tool. It also receives a user-input DFT pre-ECO netlist as the second input information; this pre-ECO netlist is the netlist whose DFT logic needs repair. The method extracts DFT-related structures and logic signals from the DFT reference netlist. Based on the extracted DFT structures and logic signals, it performs DFT DRC checks on the pre-ECO netlist to identify error types. Based on the check results, it repairs the DFT structures and DFT DRC violations in the pre-ECO netlist. It then performs ECO operations on the repaired netlist, including adding and removing links. Finally, it generates a repaired DFT netlist and provides a comparison report, significantly improving the efficiency of DFT ECO.

Description

Technical Field

[0001] This invention belongs to the field of ECO technology, specifically relating to a system and method for DFT ECO. Background Technology

[0002] In real-world projects, an ECO performed due to changes in circuit logic is called a Functional ECO. During a Functional ECO, it is inevitable that the Design For Test (DFT) logic will be altered or destroyed. In addition, modifications to logic functions, such as adding registers, will lead to a reduction in DFT coverage if the DFT logic is not updated accordingly, affecting product quality. In these application scenarios, it is necessary to repair and update the DFT logic, which is called a Design For Test (DFT) ECO.

[0003] Mainstream DFT tools do not inherently provide ECO functionality for DFT logic. However, specialized ECO tools now offer methods for repairing scan chains within the DFT: Simultaneous repair of DFT logic during Functional ECO leads to highly complex engineering implementations and poor practical results, failing to meet commercial requirements; Repairing DFT logic separately only reads one ECOed netlist, thus lacking complete DFT solution information and only capable of repairing simple DFT logic, unable to perform DFT DRC checks, requiring ATPG tools and complicating the design process; Existing tools cannot handle complex DFT logic, especially designs with multiple scan modes and compressors, exhibiting limitations in DFT logic ECO, where a violation might persist in one scan mode but remain in another. Summary of the Invention

[0004] This invention addresses the shortcomings of existing technologies by proposing a new, advanced DFT ECO system and method. It can not only independently perform more accurate and complete repairs on DFT logic, but also automatically check DFT DRC and report the differences before and after repair. It is a complete solution that can greatly improve engineering efficiency.

[0005] The solution of the present invention is as follows:

[0006] In a first aspect, the present invention provides a system for DFT ECO, the system comprising: a first input module, a second input module, a DFT structure extraction module, a DFT inspection module, a DFT repair module, a DFT ECO module, and an output module, wherein the first input module and the second input module are respectively connected to the DFT structure extraction module.

[0007] The first input module is used to receive a DFT reference netlist input by the user as the first input information. The DFT reference netlist is a netlist with complete DFT logic that can be detected by the ATPG tool.

[0008] The second input module is used to receive the DFT pre-ECO netlist to be ECO by the user as the second input information. The DFT pre-ECO netlist is the netlist that needs to repair the DFT logic.

[0009] The DFT structure extraction module is used to extract DFT-related structures and logic signals from the DFT reference netlist.

[0010] The DFT inspection module is connected to the DFT structure extraction module and is used to perform DFT DRC checks on the DFT pre ECO netlist based on the extracted DFT structure and logic signals to identify the error type.

[0011] The DFT repair module is connected to the DFT inspection module and is used to repair the DFT structure and DFT DRC violation in the DFT pre-ECO netlist according to the identified error type.

[0012] The DFT ECO module is connected to the DFT repair module and is used to perform ECO operations after adding or removing links based on the repaired netlist.

[0013] The output module is connected to the DFT ECO module and is used to generate the repaired DFT netlist and provide a comparison report.

[0014] Furthermore, the DFT-related structure includes a compression / decompression module and an on-chip clock management module, and the logic signals include a controllable clock signal, a controllable reset signal, and a scan enable signal.

[0015] Furthermore, the DFT inspection module performs DFT DRC checks including the following:

[0016] Check the DFT structure or logic signal connections; check the number of registers on the scan chain; check the drive signals of clock and reset signals of registers on the scan chain.

[0017] Furthermore, the DFT repair module repairs the network based on the inspection results, ensuring that the DFT logic in the repaired network list is consistent with the DFT logic in the DFT reference network list.

[0018] Furthermore, the DFT ECO module supports two operating modes: automatic ECO and user-command-based ECO.

[0019] Furthermore, the comparison report generated by the output module includes a scan chain length comparison, a count of the number of newly added / deleted registers, and DFT DRC check results.

[0020] Secondly, the present invention provides a method for DFT ECO, based on the system implementation of the first aspect, the method comprising the following steps:

[0021] Step S1: Receive the DFT reference netlist input by the user as the first input information. The DFT reference netlist is a netlist with complete DFT logic that can be detected by the ATPG tool.

[0022] Step S2: Receive the DFT pre-ECO netlist to be ECO by the user as the second input information. The DFT pre-ECO netlist is the netlist for which the DFT logic needs to be repaired.

[0023] Step S3: Extract the DFT-related structures and logic signals from the DFT reference netlist.

[0024] Step S4: Perform DFT DRC checks on the DFT pre ECO netlist based on the extracted DFT structure and logic signals to identify the error type.

[0025] Step S5: Repair the DFT structure and DFT DRC violations in the DFT pre-ECO netlist based on the inspection results.

[0026] Step S6: Perform the ECO operation after adding or removing links based on the repaired netlist.

[0027] Step S7: Generate the repaired DFT netlist and provide a comparison report.

[0028] Furthermore, the DFT-related structure includes a compression / decompression module and an on-chip clock management module, and the logic signals include a controllable clock signal, a controllable reset signal, and a scan enable signal.

[0029] Furthermore, the DFT DRC check includes: checking the DFT structure or logic signal connections; checking the number of registers on the scan chain; and checking the drive signals of clock and reset signals of the registers on the scan chain.

[0030] Furthermore, the repair operation ensures that the DFT logic in the repaired netlist is consistent with the DFT logic in the DFT reference netlist, and supports both automatic ECO and user-instruction-based ECO operation modes.

[0031] Compared with the prior art, the beneficial effects of this invention are:

[0032] This invention introduces a DFT reference netlist, which can completely obtain the original DFT scheme information, so that the DFT ECO has a standard reference document; the repair of DFT logic can be carried out entirely according to the implementation of the reference netlist, rather than other alternative schemes; built-in DFT DRC checks can be performed to verify the quality of test results without the need for third-party ATPG tools. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the DFT ECO system of the present invention;

[0034] Figure 2 This is a flowchart of the DFT ECO method of the present invention. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention are described clearly and completely below. Obviously, the described embodiments are only some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0036] Example 1

[0037] like Figure 1 The diagram shows a DFT ECO system according to the present invention. The system includes: a first input module, a second input module, a DFT structure extraction module, a DFT inspection module, a DFT repair module, a DFT ECO module, and an output module. The first input module and the second input module are respectively connected to the DFT structure extraction module.

[0038] The system employs a modular architecture. For example, the first and second input modules are connected to the DFT structure extraction module, respectively. Specifically, these two input modules utilize standard interface protocols, supporting various netlist input formats, including Verilog, VHDL, and Liberty formats. The connection mechanism uses asynchronous processing to ensure that no blocking occurs when processing large-scale netlists.

[0039] For example, in practical applications, when a user inputs a netlist file through a GUI interface or command-line tool, the system first performs file format verification and integrity checks. Assuming the user inputs a DFT reference netlist named "reference_design.v", the system will parse the file's syntax structure and extract key information such as port information, module hierarchy, and timing constraints. Simultaneously, for the netlist to be ECO'd, "pre_eco_design.v", the system will establish a mapping relationship with the reference netlist.

[0040] The first input module is used to receive a DFT reference netlist input by the user as the first input information. The DFT reference netlist is a netlist with complete DFT logic that can be detected by the ATPG tool.

[0041] The DFT reference netlist must meet several key conditions: First, it must contain a complete DFT logical structure, including all scan chains, compressors, decompressors, and related control logic; second, it must be able to pass the verification of the ATPG (Automatic Test Pattern Generation) tool, meaning that all fault points in the netlist can be effectively detected.

[0042] For example, suppose we have a 32-bit processor design whose DFT reference netlist should contain the following key elements: 8 scan chains, each containing approximately 500 flip-flops; an 8:1 compressor module to compress the outputs of the 8 scan chains into 1; a 1:8 decompressor module to distribute the test vectors to the 8 scan chains; complete clock control logic, including the switching mechanism between the test clock and the function clock; and reset control logic to ensure that all flip-flops are correctly reset in test mode.

[0043] In actual verification, this reference netlist needs to go through the complete test process of ATPG tools such as Synopsys TetraMAX or MentorTessent, including steps such as fault simulation, test vector generation, and fault coverage analysis. Only when the fault coverage reaches a preset threshold (usually above 95%) can the netlist be used as a valid reference standard.

[0044] The second input module is used to receive the DFT pre-ECO netlist to be ECO by the user as the second input information. The DFT pre-ECO netlist is the netlist that needs to repair the DFT logic.

[0045] The pre-ECO netlist for the DFT of an ECO is typically generated during the functional ECO process, and its DFT logic structure may have various problems. These problems mainly include: broken scan chains, incorrect insertion of newly added registers into the scan chain, timing violations caused by clock domain changes, and incorrect control signal connections.

[0046] For a specific example, suppose a cache control module containing 64 new registers is added to the original design. During a functional ECO, these registers are added directly to the design without updating the DFT logic accordingly. As a result, these 64 registers are not inserted into any scan chain, making them uncontrollable and unobservable during testing, thus reducing fault coverage.

[0047] Another typical example is the change of clock domain. Suppose that a module in the original design uses system_clk as its operating clock, but during the ECO process, due to performance optimization needs, the module is switched to use the high-frequency clock high_freq_clk. This change will affect the test clock distribution logic, which may cause the module's registers to fail to correctly receive the test clock signal in test mode.

[0048] The DFT structure extraction module is used to extract DFT-related structures and logic signals from the DFT reference netlist.

[0049] The DFT structure extraction module uses graph theory algorithms and pattern matching techniques to identify and extract DFT-related structural information. The workflow of this module includes steps such as netlist parsing, structure identification, signal tracing, and dependency analysis.

[0050] During the netlist resolution phase, the system establishes a complete design hierarchy diagram, including the connections between modules, port mappings, signal flow, and other information. For example, for a complex SoC design containing CPU cores, memory controllers, and peripheral interfaces, the system identifies the DFT structure of each module, including its respective scan chain configuration, clock domain partitioning, reset strategy, etc.

[0051] The structure recognition stage employs a feature-matching-based algorithm, which can automatically identify various DFT structure patterns. For example, the system can identify the serial scan chain structure: scan_in → FF1 → FF2 → FF3 → scan_out, and can distinguish between different types of scan chains, such as ordinary scan chains, clock-gated scan chains, and reset scan chains.

[0052] The signal tracing phase uses reverse and forward tracing algorithms to determine the source and destination of various control signals. For example, for the scan_enable signal, the system traces its complete path from the top-level port to each scan trigger, identifying all intermediate logic such as buffers, inverters, and multiplexers.

[0053] The DFT-related structure includes a compression / decompression module and an on-chip clock management module. The logic signals include a controllable clock signal, a controllable reset signal, and a scan enable signal.

[0054] Compression / decompression modules are used to reduce the amount of test data and test time. Compactors typically employ an XOR tree structure to compress the outputs of multiple scan chains into a smaller output signal. For example, an 8:1 compressor might use the following structure: a three-stage XOR gate; the first stage contains four XOR gates, corresponding to (chain0^chain1), (chain2^chain3), (chain4^chain5), and (chain6^chain7); the second stage contains two XOR gates, calculating the XOR of the results from the first stage; and the third stage contains one XOR gate, outputting the final compressed result.

[0055] The decompressor employs a linear feedback shift register (LFSR) or phase shifter structure to expand a small input signal into multiple scan chains. A typical 1:8 decompressor might contain: an 8-bit LFSR with a feedback polynomial of... Eight XOR gates are connected to different positions of the LFSR to generate pseudo-random test vectors for each scan chain.

[0056] The on-chip clock management module is responsible for switching the clock signal between functional mode and test mode. This module typically includes: a clock selector (Clock Mux), which selects the functional clock or the test clock under the control of the test_mode signal; clock gating logic, which disables unnecessary clock signals in test mode to reduce power consumption; and a clock divider, which provides different frequency clocks for different test requirements.

[0057] The management of controllable clock signals involves multiple levels: the top-level test clock (test_clk) is distributed to each module through the clock tree; the integrated clock gating (ICG) unit inside each module needs to be properly controlled in test mode; the synchronization logic of clock domain crossover needs to be specially handled during testing.

[0058] Controllable reset signals include: an asynchronous reset signal (async_reset) that initializes all triggers at the start of the test; a synchronous reset signal (sync_reset) that controls the state of specific triggers during the scan; and reset release logic that ensures all triggers are in a known state before the test vector is applied.

[0059] The DFT inspection module is connected to the DFT structure extraction module and is used to perform DFT DRC checks on the DFT pre ECO netlist based on the extracted DFT structure and logic signals to identify the error type.

[0060] The DFT checking module implements a complete Design Rule Check (DRC) system to ensure that the DFT logic in the netlist meets the test requirements. This module adopts a multi-level checking strategy: the structural layer checks and verifies the integrity and correctness of the DFT module; the connection layer checks and verifies the correctness of the signal connections; and the timing layer checks and verifies the rationality of the test timing.

[0061] During the structural layer check, the system verifies that the configuration of each compressor and decompressor is consistent with the reference netlist. For example, if an 8:1 compressor is defined in the reference netlist, the system checks if a compressor with the same configuration exists in the pre-ECO netlist, including the number of input ports, the number of output ports, and the internal logic structure. For any mismatches found, the system generates a detailed error report indicating the specific differences.

[0062] The connectivity layer check involves signal tracing and connectivity verification. The system checks the integrity of each scan chain to ensure that the signal path from scan_in to scan_out is not broken. For example, for a scan chain containing 100 flip-flops, the system verifies that the Q output of FF1 is correctly connected to the scan_in input of FF2, and so on; at the same time, the system also checks the connections of the clock and reset signals to ensure that each scan flip-flop receives the correct control signals.

[0063] Timing layer checks focus on the rationality of test timing. The system analyzes the propagation delay of the clock signal to ensure that there are no setup or hold time violations at the test frequency. For example, if the test clock frequency is 100MHz, the system calculates the propagation delay from the clock source to each flip-flop to ensure that the clock deviation is within an acceptable range.

[0064] The DFT inspection module performs DFT DRC checks, including the following:

[0065] Check the DFT structure or logic signal connections; check the number of registers on the scan chain; check the drive signals of clock and reset signals of registers on the scan chain.

[0066] The system will verify the correctness of the connection of each DFT signal one by one, including: whether the scan_enable signal is correctly connected to the enable terminal of all scan triggers; whether the scan_in signal is correctly connected to the first scan trigger; whether the scan output of each trigger is correctly connected to the scan input of the next trigger; and whether the scan_out signal is correctly connected to the output of the last scan trigger.

[0067] For example, suppose in a scan chain, the scan output of the 50th flip-flop is disconnected due to an error during the ECO process. The system will detect this breakpoint using a graph traversal algorithm and generate the following error report: "The scan_out signal of flip-flop FF_50 in Chain_0 is not connected to the scan_in signal of FF_51, causing the scan chain to break."

[0068] The scan chain register count check ensures that the length of each scan chain meets design requirements. The system counts the number of flip-flops in each scan chain and compares it with the reference netlist. For example, if Chain_0 in the reference netlist contains 128 flip-flops, while the pre-ECO netlist only contains 126, the system will identify the two missing flip-flops and report their specific locations and names.

[0069] Furthermore, the system also checks the balance of the scan chains. In designs with multiple scan chains, to optimize test time, it is usually required that the lengths of each scan chain be as balanced as possible. If the length of a scan chain differs from the average length by more than a preset threshold (e.g., 5%), the system will issue a warning and suggest rebalancing the scan chain distribution.

[0070] The drive signal checks for clock and reset signals involve several aspects. For clock signals, the system checks: whether the clock input of each scan flip-flop is connected to the correct clock domain; whether the fan-out load of the clock signal is within acceptable limits; and whether the logic depth of the clock signal meets timing requirements. For reset signals, the system checks: whether the polarity of the reset signal is correct; whether the release timing of the reset signal meets requirements; and whether the coverage of the reset signal is complete.

[0071] The DFT repair module is connected to the DFT inspection module and is used to repair the DFT structure and DFT DRC violation in the DFT pre-ECO netlist according to the identified error type.

[0072] For scan chain breakage issues, the repair module employs the following strategy: First, it identifies the location and cause of the break; then, based on the connection information in the reference netlist, it re-establishes the correct connections; finally, it verifies whether the repaired connections meet timing requirements. For example, when a disconnection is detected in the scan_out signal of FF_50, the system automatically adds a buffer or directly connects the Q output of FF_50 to the scan_in input of FF_51.

[0073] For the issue of newly added registers not being inserted into the scan chain, the repair module will use an intelligent insertion algorithm: analyze the location and function of the newly added register; determine the scan chain to which it should be inserted based on clock domain and reset domain information; select the optimal insertion position while maintaining scan chain balance; and update the relevant connection relationships.

[0074] For example, suppose 64 new registers are added to the cache control module, all using cpu_clk as the operating clock and async_reset as the reset signal. The repair module analyzes the existing eight scan chains and finds that Chain_2 and Chain_5 are relatively short. Therefore, it decides to insert 32 registers into Chain_2 and another 32 into Chain_5. During the insertion process, the system maintains the original scan order and ensures that all clock and reset connections are correct.

[0075] The DFT repair module repairs the network based on the inspection results, ensuring that the DFT logic in the repaired network list is consistent with the DFT logic in the DFT reference network list.

[0076] During structural consistency verification, the system compares each DFT component of the repaired netlist with the reference netlist one by one. For example, for the compressor module, the system verifies whether the number and names of the input ports are consistent; whether the number and names of the output ports are consistent; whether the connection relationships of the internal XOR logic are consistent; and whether the connections of the control signals are consistent.

[0077] Functional consistency verification uses formal verification methods to ensure logical equivalence. The system generates a series of test vectors, applies them to the reference netlist and the repaired netlist respectively, and compares their output responses. If any inconsistency is found in the output under any test vector, the system will report a functional mismatch error and provide detailed debugging information.

[0078] Extract timing information from the repaired netlist, including parameters such as setup time, hold time, and propagation delay, and compare it with the reference netlist. If the timing parameters are found to be outside the acceptable range, the system will automatically adjust the insertion of buffers or adjust the structure of the clock tree.

[0079] The DFT ECO module is connected to the DFT repair module and is used to perform ECO operations after adding or removing links based on the repaired netlist.

[0080] The DFT ECO module supports two operating modes: automatic ECO and user-command-based ECO.

[0081] The output module is connected to the DFT ECO module and is used to generate the repaired DFT netlist and provide a comparison report.

[0082] The comparison report generated by the output module includes a scan chain length comparison, a count of the number of newly added / deleted registers, and DFT DRC check results.

[0083] Example 2

[0084] like Figure 2 The diagram shown is a flowchart of the DFT ECO method of the present invention, which includes the following steps:

[0085] Step S1: Receive the DFT reference netlist input by the user as the first input information. The DFT reference netlist is a netlist with complete DFT logic that can be detected by the ATPG tool.

[0086] Step S1 includes several sub-processes: file format identification, syntax parsing, semantic analysis, and integrity verification. In the file format identification stage, the system supports various mainstream netlist formats, including Verilog, SystemVerilog, and VHDL. The system automatically identifies the format type based on the file extension and header information and calls the corresponding parser.

[0087] The syntax parsing phase employs a recursive descent parser, capable of handling complex syntax structures. For example, for Verilog netlists, the parser builds an Abstract Syntax Tree (AST) containing all syntax elements such as module definitions, port declarations, wire declarations, and instantiation statements. For netlists containing parameterized modules, the parser also handles parameter passing and module instantiation.

[0088] The semantic analysis phase includes type checking, name resolution, and scope analysis. The system establishes a complete symbol table, recording information such as the type, bit width, and scope of all signals. For hierarchical designs, the system creates a hierarchical symbol table, supporting cross-level signal references.

[0089] Integrity verification is a critical step in ensuring netlist quality. The system checks: whether all signals have a clearly defined driver; whether there are multiple drivers or driver conflicts; whether port connections are correct; and whether the clock signal distribution is reasonable.

[0090] For example, suppose the user inputs a reference netlist file named "cpu_core_with_dft.v", which is 50MB in size and contains 1 million logic gates. The system will first check the file's readability and format correctness, and then start a parallel parser for syntax analysis. During the semantic analysis phase, the system will identify the main modules included in the design: the CPU core module, the cache controller module, the bus interface module, etc., as well as their DFT structure configurations.

[0091] Step S2: Receive the DFT pre-ECO netlist to be ECO by the user as the second input information. The DFT pre-ECO netlist is the netlist for which the DFT logic needs to be repaired.

[0092] The processing strategy for receiving user-input DFT pre-ECO netlists needs to consider the special properties of these netlists, which typically contain incomplete or erroneous DFT logic. Therefore, fault-tolerant parsing techniques are required. The system employs a multi-level fault-tolerant mechanism: syntax-level fault tolerance handles syntax errors and incomplete statements; semantic-level fault tolerance handles type mismatches and undefined signals; and structural-level fault tolerance handles missing modules and connection errors.

[0093] Syntax-level fault tolerance employs an error recovery algorithm. When a syntax error is encountered, the system attempts various recovery strategies: skipping the erroneous statement and continuing parsing; inserting potentially missing syntax elements; and inferring the user's intent from the context. For example, if an incomplete module instantiation statement is encountered, the system will automatically complete the missing port connections based on the module definition.

[0094] Semantic-level fault tolerance involves type inference and signal reconstruction. When the system detects an undefined signal, it infers its type and bit width based on its usage context. For example, if a signal is used as a clock input, the system automatically labels it as a clock signal; if a signal is connected to the data input of multiple flip-flops, the system infers it as a data signal.

[0095] Structural-level fault tolerance is the most complex, involving module reconstruction and connection repair. The system maintains a module library containing standard implementations of common DFT modules. When a missing DFT module is detected, the system will select a suitable replacement module from the module library.

[0096] Step S3: Extract the DFT-related structures and logic signals from the DFT reference netlist.

[0097] The DFT-related structure includes a compression / decompression module and an on-chip clock management module. The logic signals include a controllable clock signal, a controllable reset signal, and a scan enable signal.

[0098] Extracting DFT-related structures and logic signals employs a pattern matching algorithm, requiring a large DFT structure template library that includes: various types of scan trigger templates (D triggers, JK triggers, SR triggers, etc.); compressor templates with different configurations (8:1, 16:1, 32:1, etc.); decompressor templates of different types (LFSR, phase shifter, hybrid type, etc.); and clock control logic templates (clock selectors, clock gates, clock dividers, etc.).

[0099] Each template contains a detailed structural description and matching rules. For example, for an 8:1 compressor template, the system will look for a structural pattern that contains 8 input ports, 1 output port, and 7 XOR gates.

[0100] The signal extraction process employs signal flow analysis techniques. The system starts from the identified DFT structure and traces the complete path of related signals. For example, starting with the scan_enable signal, the system traces its path to each scan trigger, recording all logic gates and connections along the way.

[0101] For a compressor, the system needs to identify its compression ratio, compression algorithm, input / output port configuration, and other information. Common compression algorithms include simple XOR compression, weighted XOR compression, and parity-checked compression. The system analyzes the compressor's internal structure to determine the specific algorithm used.

[0102] For example, for a 16:1 weighted XOR compressor, the system identifies 16 input ports (scan_out_0 to scan_out_15) and 1 output port (compressed_out). The internal structure contains 15 XOR gates, each with different input weights. The system extracts the complete weight matrix for reference in subsequent repair operations.

[0103] For a decompressor, the system needs to identify parameters such as its decompression ratio, seed value, and feedback polynomial. Taking an LFSR decompressor as an example, the system analyzes information such as the number of triggers, feedback connection method, and output tap position. For an 8-bit LFSR decompressor, the system extracts the feedback polynomial (e.g., Parameters such as initial seed value (e.g., 8'h5A) and output tap configuration (e.g., output from the 1st, 3rd, 5th, and 7th bits).

[0104] Extracting the on-chip clock management module requires analyzing clock domain partitioning and clock control logic. The system will identify all clock domains in the design, including: functional clock domains (such as cpu_clk, bus_clk, mem_clk, etc.); test clock domains (such as test_clk, scan_clk, etc.); and clock enable domains (such as various gated clocks). Simultaneously, the system will also analyze the clock switching logic, including the configuration of the clock selector and the control strategy for the clock enable signal.

[0105] The extraction of logic signals involves signal classification and attribute analysis. The extraction of controllable clock signals requires distinguishing between different types of clocks: the master clock signal comes directly from the clock source; derived clock signals are generated through frequency division or multiplication; and gated clock signals are affected by control signals. The system analyzes the frequency, duty cycle, phase relationship, and other characteristics of each clock signal.

[0106] Extracting controllable reset signals requires analyzing the reset tree structure and reset strategy. The system will identify: global reset signals affect the entire design; local reset signals affect only specific modules; and conditional reset signals are triggered based on specific conditions. It is necessary to trace the complete path of the scan_enable signal from the top-level port to each scan flip-flop, including: the signal's fan-out structure (one-to-many distribution); the signal's logical processing (inverting, AND, OR, etc.); and the signal's timing relationship (relative timing to the clock signal). For example, in a complex SoC design, the scan_enable signal may be distributed to tens of thousands of scan flip-flops through multi-level buffers. The system needs to build a complete signal distribution tree, recording the delay and load information of each branch.

[0107] Step S4: Perform DFT DRC checks on the DFT pre ECO netlist based on the extracted DFT structure and logic signals to identify the error type.

[0108] The DFT DRC check includes: checking the DFT structure or logic signal connections; checking the number of registers on the scan chain; and checking the drive signals of clock and reset signals of the registers on the scan chain.

[0109] The system maintains over 500 DFT design rules, covering everything from simple connection rules to complex timing constraints. For example, rule DFT_001 specifies that "each scan flip-flop must have explicit scan_in and scan_out connections"; rule DFT_075 specifies that "the number of compressor inputs must match the number of scan chains"; and rule DFT_156 specifies that "clock gating logic must be disabled in test mode".

[0110] The system represents the netlist as a directed graph, where nodes represent logic units and edges represent signal connections. Using Depth-First Search (DFS) and Breadth-First Search (BFS) algorithms, the system can detect: dangling nodes (nodes without input or output connections); loops (connections that could lead to combinational logic loops); unreachable nodes (nodes unreachable from the main input); and redundant connections (extra connections that do not affect functionality).

[0111] The corresponding error mode library contains various common DFT error modes and their characteristics. For example, the characteristic of a "scan chain break" error is that the scan_out signal of a certain flip-flop is not connected to the scan_in signal of the next flip-flop; the characteristic of a "clock domain error" is that the scan flip-flop uses an incorrect clock signal; and the characteristic of a "reset logic error" is that the reset signal of the scan flip-flop is connected incorrectly.

[0112] Step S5: Repair the DFT structure and DFT DRC violations in the DFT pre-ECO netlist based on the inspection results.

[0113] The repair operation ensures that the DFT logic in the repaired netlist is consistent with the DFT logic in the DFT reference netlist, and supports both automatic ECO and user-instruction-based ECO operation modes.

[0114] Step S6: Perform the ECO operation after adding or removing links based on the repaired netlist.

[0115] ECO operations on the top and bottom chains refer to the process of propagating the code upwards to the parent layer and downwards to the child layer after the current design layer has been repaired, in order to ensure the consistency of the entire design hierarchy.

[0116] The uppropagation (on-chain) operation handles the impact of modifications at the current level on the parent level; for example, if a new DFT port is added at the module level, a corresponding port connection needs to be added at the chip level. The system analyzes the hierarchy, identifies the parent module that needs modification, and automatically generates the corresponding modification instructions.

[0117] The specific on-chain operation process is as follows: The port change analysis system analyzes the port changes of the current module, including adding ports, deleting ports, renaming ports, etc.; the parent module positioning system locates all parent modules that instantiate the current module in the design level; the connection update system updates the instantiated connections of the current module in the parent module to ensure the correctness of the port connections; the constraint propagation system propagates the timing constraints, area constraints, etc. of the current module to the parent module.

[0118] The down-propagation (chain-down) operation handles the impact of modifications at the current level on sub-levels; for example, if the clock allocation strategy is modified, it needs to be ensured that all sub-modules use the correct clock signal. The system recursively analyzes all sub-modules and makes the corresponding modifications.

[0119] The specific offline operation process is as follows: The parameter transmission system transmits the modified parameters to all sub-modules, including clock frequency, reset polarity, scan mode, etc.; the interface update system updates the interface connection with the sub-modules to ensure the correctness of signal transmission; the constraint distribution system distributes the upper-level constraint requirements to the sub-modules, including timing requirements, power consumption requirements, etc.; the consistency check system checks whether the modifications of all sub-modules are consistent and whether there are any conflicts.

[0120] Step S7: Generate the repaired DFT netlist and provide a comparison report.

[0121] The report contains comparative information in several aspects: structural comparison shows the added, deleted, and modified DFT structures; connectivity comparison shows the changes in signal connections; performance comparison shows the performance differences before and after the repair; and quality comparison shows the improvement of the DRC inspection results.

[0122] This invention has been described through specific embodiments. Those skilled in the art will understand that various modifications and equivalent substitutions can be made to this invention without departing from its scope. Furthermore, various modifications can be made to this invention for specific situations or materials without departing from its scope. Therefore, this invention is not limited to the specific embodiments disclosed, but should include all embodiments falling within the scope of the claims.

Claims

1. A system for DFT ECO, characterized in that, The system includes: a first input module, a second input module, a DFT structure extraction module, a DFT inspection module, a DFT repair module, a DFT ECO module, and an output module. The first input module and the second input module are respectively connected to the DFT structure extraction module. The first input module is used to receive a DFT reference netlist input by the user as the first input information. The DFT reference netlist is a netlist with complete DFT logic that can be detected by the ATPG tool. The second input module is used to receive the DFT pre-ECO netlist to be ECO by the user as the second input information, wherein the DFT pre-ECO netlist is the netlist that needs to repair the DFT logic; The DFT structure extraction module is used to extract DFT-related structures and logic signals from the DFT reference netlist; the DFT-related structures include a compression / decompression module and an on-chip clock management module, and the logic signals include a controllable clock signal, a controllable reset signal, and a scan enable signal; The DFT inspection module is connected to the DFT structure extraction module and is used to perform DFT DRC inspection on the DFT pre ECO netlist based on the extracted DFT structure and logic signals to identify the error type. The DFT repair module is connected to the DFT inspection module and is used to repair the DFT structure and DFT DRC violation in the DFTpre ECO netlist according to the identified error type. The DFT ECO module is connected to the DFT repair module and is used to perform ECO operations after adding or removing links based on the repaired netlist. The output module is connected to the DFT ECO module and is used to generate the repaired DFT netlist and provide a comparison report.

2. The system for DFT ECO according to claim 1, characterized in that, The DFT inspection module performs DFTDRC checks on the following: DFT structure or logic signal connection check; Check the number of registers in the scan chain; Check the clock and reset signal drive signals of the registers on the scan chain.

3. The system for DFT ECO according to claim 2, characterized in that, The DFT repair module repairs the network based on the inspection results, ensuring that the DFT logic in the repaired network list is consistent with the DFT logic in the DFT reference network list.

4. The system for DFT ECO according to claim 3, characterized in that, The DFT ECO module supports two operating modes: automatic ECO and user-command-based ECO.

5. The system for DFT ECO according to claim 4, characterized in that, The comparison report generated by the output module includes a scan chain length comparison, a count of the number of newly added / deleted registers, and DFT DRC check results.

6. A method for DFT ECO, implemented based on the system described in any one of claims 1-5, characterized in that, The method includes the following steps: Step S1: Receive the DFT reference netlist input by the user as the first input information. The DFT reference netlist is a netlist with complete DFT logic that can be detected by the ATPG tool. Step S2: Receive the DFT pre-ECO netlist to be ECO from the user as the second input information. The DFT pre-ECO netlist is the netlist that needs to repair the DFT logic. Step S3: Extract the DFT-related structures and logic signals from the DFT reference netlist; Step S4: Perform DFT DRC checks on the DFT pre ECO netlist based on the extracted DFT structure and logic signals to identify the error type; Step S5: Repair the DFT structure and DFT DRC violations in the DFT pre-ECO netlist based on the inspection results; Step S6: Perform the ECO operation after adding or removing links based on the repaired netlist; Step S7: Generate the repaired DFT netlist and provide a comparison report.

7. The DFT ECO method according to claim 6, characterized in that, The DFT-related structure includes a compression / decompression module and an on-chip clock management module. The logic signals include a controllable clock signal, a controllable reset signal, and a scan enable signal.

8. The method for DFT ECO according to claim 7, characterized in that, The DFT DRC check includes: DFT structure or logic signal connection check; Check the number of registers in the scan chain; Check the clock and reset signal drive signals of the registers on the scan chain.

9. The method for DFT ECO according to claim 8, characterized in that, The repair operation ensures that the DFT logic in the repaired netlist is consistent with the DFT logic in the DFT reference netlist, and supports both automatic ECO and user-instruction-based ECO operation modes.

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