PCB automatic board splicing recognition method

Abstract

The application relates to the technical field of PCB plate matching, in particular to a PCB automatic plate matching method, which comprises the following steps: acquiring a layer file containing PCB frame information, wherein the frame information comprises line segment coordinates and lengths of the frame; taking a coordinate origin as a starting point, searching for a shortest closed path based on the frame information, and forming a first sub-plate frame in a region surrounded by the closed path; identifying the frame of all sub-plates in the substrate through a graphic matching algorithm according to the shape of the first sub-plate frame; and generating position information and rotation angle information of each sub-plate relative to the first sub-plate based on the matching result; the application directly processes frame layer data, eliminates manual intervention, avoids matching failure caused by wrong selection of a solder pad, automatically calculates a rotation angle, supports arbitrary angle plate matching and does not need to predefine parameters, reduces calculation amount through frame template matching based on geometric characteristics, avoids a trial and error process, preferentially identifies a physical frame structure, and solves a matching fault tolerance problem when a solder pad is missing or deformed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of PCB board matching, and particularly relates to a PCB automatic board matching method. BACKGROUND

[0002] The prior art calculates to pre-select the solder pad as a mark, judges whether it is a board by containing the solder pad as a mark in all solder pad information, and finally obtains all matching boards, such as CN110245412A and CN113239657A. However, for the method of manually specifying the solder pad as a mark, if the selected solder pad does not have enough mark, the board may not be calculated, or the correct board may not be matched in the case of insufficient solder pad information.

[0003] In view of this, the present application provides a PCB automatic board matching method to solve the existing problems. SUMMARY

[0004] The present application aims to provide a PCB automatic board matching method to solve the problems in the background.

[0005] To achieve the above object, the present application provides the following technical scheme: a PCB automatic board matching method, comprising:

[0006] Obtain a layer file containing PCB frame information, the frame information including line segment coordinates and lengths constituting the frame;

[0007] Take the coordinate origin as a starting point, search for a shortest closed path based on the frame information, and form a first sub-board frame in a region surrounded by the closed path;

[0008] According to the shape of the first sub-board frame, identify the frame of all sub-boards in the base plate through a graphic matching algorithm;

[0009] Generate position information and rotation angle information of each sub-board relative to the first sub-board based on the matching result.

[0010] Further, the searching for the shortest closed path includes traversing the path starting from the coordinate origin, and screening the closed path with the shortest length and the coincident starting point and ending point.

[0011] Further, the graphic matching algorithm includes extracting the geometric features of the first sub-board frame, matching the regions with the same geometric features in the base plate frame data, and performing affine transformation on the matching regions to calculate the translation amount and rotation angle thereof relative to the first sub-board.

[0012] Further, the layer file containing the PCB frame information is a GKO layer.

[0013] Further, after generating the position information of each sub-board, the method further comprises: extracting the pad set corresponding to the sub-board from the steel mesh pad data file according to the sub-board frame coordinates.

[0014] Further, the screening of the closed path comprises: modeling the end points of the line segment as the top points of the graph, modeling the line segment as the weighted edge, and constructing the adjacency matrix; starting from the coordinate origin vertex, performing hierarchical path search; and identifying all sub-board layouts through template matching based on the frame.

[0015] Further, the hierarchical path search comprises a first layer search and a second layer search, the first layer search uses the Dijkstra algorithm to generate a candidate closed loop set, and the second layer search applies the A* heuristic algorithm to screen the closed loop with the minimum total length from the candidate set, and takes the minimum closed loop as the first sub-board frame.

[0016] Further, the specific operation of the graph matching algorithm comprises: obtaining the vertex sequence of the first sub-board frame, performing Delaunay triangulation to generate a set of feature triangles, and calculating a geometric fingerprint for each feature triangle; in the base plate frame data, a candidate triangle set matching the geometric fingerprint is retrieved through local sensitive hash bucket, a direction chain code is calculated for the candidate area, and a difference operation is performed with the reference chain code, when the chain code difference value is less than a threshold value, it is determined as a matching sub-board; selecting the three non-collinear feature points with the highest matching degree, solving the affine transformation matrix, and extracting the translation amount and the rotation angle from the matrix parameters.

[0017] Further, the specific operation of extracting the pad set comprises: obtaining the sub-board frame coordinate set, generating a dynamic buffer boundary, and traversing the steel mesh pad data file.

[0018] Further, the dynamic buffer boundary comprises an inner buffer layer and an outer buffer layer.

[0019] Compared with the prior art, the present application has the following advantages:

[0020] The present application directly processes the frame layer data, eliminates manual intervention, avoids matching failure caused by selecting the wrong pad, automatically calculates the rotation angle, supports arbitrary angle splicing and does not need to predefine parameters, reduces the calculation amount based on the frame template matching of geometric features, avoids the trial and error process, and solves the matching fault tolerance problem when the pad is missing or deformed. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 It is a work flow diagram of a PCB automatic splicing recognition method of the present application. DETAILED DESCRIPTION

[0022] The technical solutions of the present application are further described below in combination with the drawings and specific embodiments. Embodiment one

[0023] As Figure 1 shown, a PCB automatic board recognition method, characterized in that, comprising:

[0024] Obtain a layer file containing PCB frame information, the frame information including line segment coordinates and length constituting the frame; wherein, the layer file containing PCB frame information is a GKO layer;

[0025] Take the coordinate origin as the starting point, search for the shortest closed path based on the frame information, and the area formed by the closed path forms the first sub-board frame; wherein, searching for the shortest closed path includes: traversing the path starting from the coordinate origin, and screening the closed path with the shortest length and the same starting point and end point;

[0026] According to the shape of the first sub-board frame, the frame of all sub-boards in the substrate is recognized by a pattern matching algorithm; wherein, the pattern matching algorithm includes: extracting the geometric features of the first sub-board frame; matching the areas with the same geometric features in the substrate frame data; performing affine transformation on the matching areas, and calculating the translation amount and rotation angle thereof relative to the first sub-board;

[0027] Based on the matching result, the position information and rotation angle information of each sub-board relative to the first sub-board are generated; after generating the position information of each sub-board, it further includes: extracting the pad set of the corresponding sub-board from the steel mesh pad data file according to the sub-board frame coordinates.

[0028] The working principle of a PCB automatic board recognition method based on embodiment one is:

[0029] The screening of the closed path includes: modeling the line segment endpoints as graph vertices, modeling the line segments as weighted edges, and constructing an adjacency matrix; starting from the coordinate origin vertex, performing hierarchical path search; identifying all sub-board layouts based on the frame through template matching.

[0030] Hierarchical path search includes first layer search and second layer search, the first layer search uses Dijkstra algorithm to generate a candidate closed loop set, and the second layer search applies A* heuristic algorithm to screen the closed loop with the smallest total length from the candidate set, and takes the smallest closed loop as the first sub-board frame.

[0031] The cost function of A* heuristic algorithm is: f(n)=g(n)+h(n), wherein, g(n) is the actual path length from the starting point to the current vertex, h(n) is the Euclidean distance from the current vertex to the origin multiplied by the weight coefficient α, 0.5≤α≤0.8.

[0032] Constructing the adjacency matrix includes: for any two vertices v i and v j , if there is a direct connection line segment, then the adjacency matrix element A ij = line segment length; otherwise Aij =∞; for obtuse vertex pairs with angle > 170°, set A ij =∞.

[0033] The first layer search includes dynamic pruning: when the current path length L current >2×L mincandidate , terminate the branch, where L mincandidate is the current shortest candidate closed loop length.

[0034] The screening of closed paths also includes closed loop verification: perform vector cross product operation on the screened minimum closed loop to verify whether it is a convex polygon; if there is a concave point, remove the loop from the candidate set and search again.

[0035] The specific operation of the pattern matching algorithm includes: obtaining the sequence of the first sub-plate frame vertex, performing Delaunay triangulation to generate a feature triangle set, and calculating the geometric fingerprint for each feature triangle; in the base plate frame data, retrieve the candidate triangle set matching the geometric fingerprint through local sensitive hash bucket, calculate the direction chain code for the candidate area, and perform difference operation with the reference chain code; when the chain code difference value is less than the threshold, it is determined that the matching sub-plate; select the three non-collinear feature points with the highest matching degree, solve the affine transformation matrix, and extract the translation and rotation angle from the matrix parameters.

[0036] The formula for calculating the geometric fingerprint of the i-th feature triangle is FP i =(r a ,r b ,cosθ c ), where r a and r b are normalized edge length ratios, r a =I min / I mid , r b =I mid / I max , I min is the length of the shortest edge of the triangle, I max is the length of the longest edge of the triangle, I mid is the length of the intermediate length edge of the triangle, and cosθ c is the maximum internal angle cosine value.

[0037] The formula for solving the affine transformation matrix is , where x and y are the horizontal and vertical coordinate values before affine transformation, x' and y' are the horizontal and vertical coordinate values after affine transformation, the translation is (c, f), and the rotation angle θ = arctan(d / a).

[0038] The generation of the direction chain code includes: converting the frame vertex sequence into a vector edge set, calculating the direction angle for each edge, and quantizing the direction angle to 8 intervals to generate the chain code.

[0039] The operation formula of chain code difference is wherein, is the i-th value in the reference chain code, is the i-th value in the direction chain code, the reference chain code and the direction chain code both have n values, and the threshold is 0.25.

[0040] Solving the affine transformation matrix comprises: selecting three groups of matching point pairs, and constructing an equation group: and adding an orthogonal constraint condition: a·d + b·e = 0; and solving the overdetermined equation group by using the least square method.

[0041] The specific operation of the graphic matching algorithm further comprises deformation compensation: when 0.3<ΔCC<0.6, a thin plate spline interpolation algorithm is started: interpolation points are dynamically inserted on the candidate frame, the matching degree is optimized through a bending energy function, and the transformation matrix parameters are updated.

[0042] The specific operation of extracting the pad set comprises: obtaining a sub-board frame coordinate set, generating a dynamic buffer boundary, and traversing a steel mesh pad data file.

[0043] The dynamic buffer boundary comprises an inner shrink buffer layer and an outer expansion buffer layer, and the sub-board frame coordinate set is B, the inner shrink buffer layer B in =Offset(B,-k1·δ), wherein δ=0.1mm, k1∈[0.8,1.2] is a steel mesh tension coefficient; and the outer expansion buffer layer B out =Offset(B,+k2·δ), k2=2.5k1.

[0044] In the traversal of the steel mesh pad data file, if the pad center is located in B, the current sub-board pad set is directly added; if the pad center is located between B in and B proj , the pad projection area ratio R=S pad / S proj is calculated, S pad is a pad projection area, and S out is a pad area itself, when R>0.7, it belongs to the current sub-board; if the pad center is located between B and B out , a cross-board arbitration is started: a sub-board with higher network connectivity is preferentially selected, and a sub-board with a shape similarity greater than 0.85 to the reference sub-board pad at the corresponding position is secondly selected.

[0045] The network connectivity calculation comprises: extracting a pad belonging to an electrical network Net i , counting the number N i of confirmed pads belonging to Net connected in the current sub-board, and calculating the proportion C i =Nconnected | Net i |.

[0046] The formula for calculating the shape similarity is Sim = ω1·IoU + ω2·e -|A-B| , wherein IoU is the intersection-over-union of the pad contours, A and B are Zernike moment feature vectors, ω1 = 0.6, and ω2 = 0.4.

[0047] The specific operation of extracting the pad set further includes process compensation: detecting whether the pad is located in the electroplating compensation area; if yes, correcting the coordinates according to a compensation formula: x' = x + α·Δx, y' = y + β·Δy, wherein α and β are substrate warping coefficients, and Δx and Δy are compensation vectors.

[0048] The compensation vector calculation includes: obtaining the historical offset data of the position, and predicting the current compensation amount through Gaussian process regression.

[0049] The above specific embodiments are only several preferred embodiments of the present application, and based on the technical solutions of the present application and the related inspirations of the above embodiments, those skilled in the art can make various alternative improvements and combinations on the above specific embodiments.

Claims

1. A PCB automatic panel recognition method, characterized in that: The method comprises the following steps: Obtain a layer file containing PCB frame information, the frame information including line segment coordinates and lengths constituting the frame; Search for the shortest closed path based on the frame information from the coordinate origin, and the area enclosed by the closed path forms the first sub-board frame; Identify the frame of all sub-boards in the substrate according to the shape of the first sub-board frame through a graphic matching algorithm; Generate the position information and rotation angle information of each sub-board relative to the first sub-board based on the matching result; The graphic matching algorithm comprises the following steps: extracting the geometric features of the first sub-board frame; matching the areas with the same geometric features in the substrate frame data; and performing affine transformation on the matching areas to calculate their translation and rotation angles relative to the first sub-board; The specific operation of the graphic matching algorithm comprises the following steps: obtaining the vertex sequence of the first sub-board frame, performing Delaunay triangulation to generate a feature triangle set, and calculating the geometric fingerprint of each feature triangle; in the substrate frame data, searching for a candidate triangle set matching the geometric fingerprint through local sensitive hash bucket retrieval, calculating the direction chain code of the candidate area, and performing difference operation with the reference chain code; when the chain code difference value is less than a threshold value, it is determined that it is a matching sub-board; selecting the three non-collinear feature points with the highest matching degree, solving the affine transformation matrix, and extracting the translation and rotation angle from the matrix parameters.

2. The PCB automatic panel recognition method according to claim 1, characterized in that, The search for the shortest closed path comprises the following steps: traversing the paths starting from the coordinate origin, and screening the closed path with the shortest length and the same starting point and ending point.

3. The PCB automatic panel recognition method of claim 1, wherein: The layer file containing the PCB frame information is a GKO layer.

4. The PCB automatic panel recognition method of claim 1, wherein, After generating the position information of each sub-board, the method further comprises the following steps: extracting the pad set of the corresponding sub-board from the steel mesh pad data file according to the sub-board frame coordinates.

5. The PCB automatic panel recognition method according to claim 2, wherein, The screening of the closed path comprises the following steps: modeling the line segment endpoints as graph vertices and the line segments as weighted edges to construct an adjacency matrix; starting from the coordinate origin vertex, performing hierarchical path search; and identifying all sub-board layouts through template matching based on the frame.

6. The PCB automatic panel recognition method according to claim 5, characterized in that: The hierarchical path search comprises first layer search and second layer search, the first layer search uses Dijkstra algorithm to generate a candidate closed loop set, and the second layer search applies A* heuristic algorithm to screen the closed loop with the smallest total length from the candidate set, and takes the smallest closed loop as the first sub-board frame.

7. The PCB automatic panel recognition method according to claim 4, characterized in that, The specific operation of extracting the pad set comprises the following steps: obtaining the sub-board frame coordinate set, generating a dynamic buffer boundary, and traversing the steel mesh pad data file.

8. The PCB automatic panel recognition method of claim 7, wherein: The dynamic buffer boundary comprises an inward buffer layer and an outward buffer layer.

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