LED display driving device

Abstract

There is provided an LED display driving apparatus including a master driver IC and a slave driver IC for driving a plurality of LEDs arranged in each of a plurality of display areas included in a display panel, where each display area includes a plurality of display units, each display unit including a plurality of light sources, each light source including a plurality of light sources, each light source including a plurality of light sources, each light source including a plurality of light sources, and each light source including a plurality of light sources. The main driver IC drives a first scan line group corresponding to a first display unit and a second display unit adjacent to each other in a first direction among the plurality of display units, and a first channel line group corresponding to a first display unit and a third display unit adjacent to each other in a second direction perpendicular to the first direction, and driving, from the driver IC, a second scan line group corresponding to a third display unit and a fourth display unit adjacent to each other in the first direction among the plurality of display units and a second channel line group corresponding to a second display unit and a fourth display unit adjacent to each other in the second direction.

Description

Technical Field

[0001] The present disclosure relates to an LED display driving device with reduced power consumption. Background Art

[0002] The display device can be implemented in various ways. For example, the display device can be classified as an LCD display device or an LED display device.

[0003] Mini LEDs or micro LED elements can be used in LED display devices. Therefore, the number of modular LED elements can be set as needed. Therefore, large-scale display devices such as signage can be easily realized.

[0004] However, since a plurality of LED modules are included in a display device, the number of required driver ICs may also be large. Therefore, it is crucial to reduce the power consumption of each driver IC.

[0005] In addition, as power consumption regulations in various countries become increasingly stringent, methods for reducing power consumption of display devices are becoming increasingly necessary. Summary of the Invention

[0006] The present disclosure is made in view of the above-mentioned problems, and an object thereof is to provide an LED display driving device with reduced power consumption.

[0007] Another object of the present disclosure is to provide an LED display driving device with reduced leakage current.

[0008] In addition to the objects of the present disclosure as described above, additional objects and features of the present disclosure will be clearly understood by those skilled in the art from the following description of the present disclosure.

[0009] According to one aspect of the present disclosure, the above and other purposes can be achieved by providing an LED display driving device, which includes a master driver IC and a slave driver IC, the master driver IC and the slave driver IC being used to drive multiple LEDs arranged in each of multiple display areas included in a display panel, wherein each display area includes multiple display units, the master driver IC drives a first scan line group corresponding to a first display unit and a second display unit adjacent to each other in a first direction among the multiple display units and a first channel line group corresponding to the first display unit and a third display unit adjacent to each other in a second direction perpendicular to the first direction, and the slave driver IC drives a second scan line group corresponding to the third display unit and a fourth display unit adjacent to each other in the first direction among the multiple display units and a second channel line group corresponding to the second display unit and the fourth display unit adjacent to each other in the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a view showing a configuration of an LED display device according to an embodiment of the present disclosure;

[0012] Figure 2 is a view showing a partial area of ​​a display panel according to an embodiment of the present disclosure;

[0013] Figure 3 is a view showing a configuration of a driver IC according to an embodiment of the present disclosure;

[0014] Figure 4 is a view showing a portion of an LED display driving device according to an embodiment of the present disclosure;

[0015] Figure 5 is an operation timing diagram of the LED display driving device according to an embodiment of the present disclosure;

[0016] Figure 6 is an operation timing diagram of the LED display driving device of the present disclosure in normal mode;

[0017] Figure 7 is an operation timing diagram of the LED display driving device of the present disclosure in low power mode;

[0018] Figure 8 is an operation timing diagram of the LED display driving device of the present disclosure in another low power mode; and

[0019] Figure 9 FIG. 4 is an operation timing diagram of the LED display driving device of the present disclosure in other low power modes. DETAILED DESCRIPTION

[0020] The advantages and features of the present disclosure and its implementation methods will be illustrated by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art. Furthermore, the present disclosure is limited only by the scope of the claims.

[0021] The shapes, sizes, ratios, angles, and quantities disclosed in the drawings used to describe the embodiments of the present disclosure are merely examples, and therefore, the present disclosure is not limited to the details shown. Throughout the specification, the same reference numerals refer to the same elements. In the following description, when it is determined that a detailed description of a related known function or configuration unnecessarily obscures the key points of the present disclosure, the detailed description will be omitted.

[0022] In the case where “including,” “having,” and “comprising” described in the present disclosure are used, other parts may be added unless “only to” is used. Unless otherwise specified, terms in the singular form may include plural forms.

[0023] When explaining an element, although not explicitly described, the element is interpreted as including an error band.

[0024] When describing a positional relationship, for example, when the positional relationship is described as "on," "over," "below," and "beside," one or more parts may be located between two other parts unless "only" or "directly" is used.

[0025] Spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to readily describe the relationship of one or more elements to another element or elements as shown in the figures. It should be understood that these terms are intended to encompass different orientations of a device in addition to the orientation of the device shown in the figures. For example, if the device shown in the figures were turned upside down, a device described as "below" or "beneath" another device could be positioned "above" the other device. Thus, the exemplary terms "below or below" can encompass both the orientations of "below or below" and "above." Similarly, the exemplary terms "above" or "on..." can encompass both the orientations of "above" and "below or below."

[0026] When describing a temporal relationship, for example, when a temporal order is described as "after," "subsequently," "next," and "before," discontinuous cases may be included unless "only" or "directly" is used.

[0027] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure.

[0028] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of a first element, a second element, and a third element" may include all combinations of two or more elements selected from the first element, the second element, and the third element, as well as each element of the first element, the second element, and the third element.

[0029] As will be fully appreciated by those skilled in the art, the features of the various embodiments of the present disclosure may be coupled or combined in part or in whole, and may interoperate and be technology-driven in various ways. The embodiments of the present disclosure may be performed independently of one another, or may be performed together in a mutually dependent relationship.

[0030] When adding reference numerals to elements of each of the drawings describing embodiments of the present disclosure, the same elements may have the same reference numerals as much as possible even though they are shown in different drawings.

[0031] Figure 1 1 is a view showing a configuration of an LED display device 10 according to an embodiment of the present disclosure.

[0032] According to an embodiment of the present disclosure, an LED display device 10 may include a display panel 101 and an LED display driver 100. Specifically, the LED display driver 100 may include a display controller 110, a data driver 120, and a gate driver 130. Although not shown, the LED display device 10 may further include a power supply circuit (not shown). The display panel 101, the display controller 110, the data driver 120, and the gate driver 130 will be described in detail below. The LED display driver 100 is configured to supply channel current to a plurality of LEDs and cause the plurality of LEDs to emit light.

[0033] According to an embodiment of the present disclosure, the display panel 101 performs a display function and may be implemented as an LED display. The display panel 101 of the present disclosure may also perform a touch sensing function.

[0034] According to an embodiment of the present disclosure, the display panel 101 may include a plurality of scan lines SL, a plurality of channel lines CL, and a plurality of pixels P.

[0035] According to an embodiment of the present disclosure, each of the plurality of pixels P may include a plurality of sub-pixels R, G, and B. For example, the pixel P may include a sub-pixel R representing red, a sub-pixel G representing green, and a sub-pixel B representing blue. However, the types of sub-pixels included in the pixel P are not limited to the above examples and may vary depending on the embodiment.

[0036] According to an embodiment of the present disclosure, each of the sub-pixels R, G, and B may include an LED. That is, the display panel 101 may be an LED display panel.

[0037] A plurality of pixels P may be connected to each other in the horizontal direction via scan lines SL. Furthermore, a plurality of pixels P may be connected to each other in the vertical direction via channel lines CL. The scan lines SL and the channel lines CL are positioned to intersect each other, thereby defining sub-pixels R, G, and B. Thus, a plurality of pixels P may be arranged to form a matrix. The display panel 101 includes a plurality of LEDs arranged in the plurality of sub-pixels R, G, and B where the plurality of channel lines CL and the plurality of scan lines SL intersect.

[0038] The plurality of pixels P may include a thin film transistor (not shown) connected to a scan line SL and a channel line CL adjacent to the thin film transistor; a pixel electrode (not shown) connected to the thin film transistor; and a storage capacitor (not shown) connected to the pixel electrode.

[0039] According to an embodiment of the present disclosure, the display controller 110 receives various signals from an external system (not shown) and generates a data control signal DCS to drive the data driver 120 and generates a gate control signal GCS to drive the gate driver 130. In addition, the display controller 110 may receive a vertical synchronization signal Vsync from the external system.

[0040] The display controller 110 may control the data driver 120 and the gate driver 130 .

[0041] The display controller 110 aligns the image data RGB received from the external system. Specifically, the display controller 110 aligns the image data RGB′ to conform to the structure and characteristics of the display panel 101. The display controller 110 transmits the aligned image data RGB′ to the data driver 120.

[0042] The data control signal DCS may include a source start pulse SSP, a source sampling clock SSC, a source output enable signal SOE, a PWM signal T PWM_R1 , channel disconnect signal T OFF_R1 The gate control signal GCS may include a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal and a scan signal T SCAN_ON1 .

[0043] According to an embodiment of the present disclosure, the data driver 120 converts the aligned image data RGB′ into a data signal according to the timing signal generated by the display controller 110. In detail, the data driver 120 converts the aligned image data RGB′ into a data signal according to the source start pulse, the source sampling clock, and the source output enable signal. The data driver 120 outputs the data signal for one horizontal line to the data line in each horizontal period in which the scan signal is supplied to the scan line SL. In this case, the data driver 120 receives a gamma voltage from a gamma voltage generator (not shown) and can convert the aligned image data RGB′ into a data signal by using the gamma voltage.

[0044] According to an embodiment of the present disclosure, the data driver 120 may include a plurality of channel stages 121 .

[0045] The plurality of channel levels 121 may include a first red channel level R[1], a first green channel level G[1], and a first blue channel level B[1]. Figure 1 Only the first red channel stage R[ 1 ], the first green channel stage G[ 1 ] and the first blue channel stage B[ 1 ] are shown in FIG, but the plurality of channel stages 121 may include more channel stages.

[0046] The plurality of channel stages 121 may supply LED power to the display panel 101 through the plurality of channel lines CL based on data signals.

[0047] Each of the plurality of channel stages 121 may be connected to an LED of the display panel 101 through one channel line CL. The plurality of channel stages 121 may be sequentially connected to the display panel 101 through one channel line CL in a horizontal direction.

[0048] According to an embodiment of the present disclosure, the gate driver 130 outputs a scan signal synchronized with a data signal generated by the data driver 120 to the scan line SL according to a timing signal generated by the display controller 110. In detail, the gate driver 130 outputs a scan signal synchronized with the data signal to the scan line SL according to a gate start pulse, a gate shift clock, and a gate output enable signal generated by the display controller 110.

[0049] The gate driver 130 may include a gate shift register circuit, a gate level shifter circuit, and the like.

[0050] According to an embodiment of the present disclosure, the gate driver 130 may include a plurality of output stages 131 .

[0051] The plurality of output stages 131 may include a first output stage SCAN[1], a second output stage SCAN[2], a third output stage SCAN[3], and a fourth output stage SCAN[4]. Figure 1 Only the first output stage SCAN[1], the second output stage SCAN[2], the third output stage SCAN[3] and the fourth output stage SCAN[4] are shown in FIG, but the plurality of output stages 131 may include more output stages.

[0052] The plurality of output stages 131 may provide driving power to the display panel 101 through the plurality of scan lines SL based on scan signals.

[0053] Each of the plurality of output stages 131 may be connected to an LED of the display panel 101 through a single scan line SL. The plurality of output stages 131 may be sequentially connected to the display panel 101 through a single scan line SL in a vertical direction.

[0054] The power supply circuit (not shown) generates various signals required for the data driver 120 and the gate driver 130. For example, the power supply circuit generates analog power and digital power by stepping up or down a system voltage.

[0055] Figure 2 is a view showing a partial area of ​​the display panel 101 according to an embodiment of the present disclosure.

[0056] According to an embodiment of the present disclosure, the display panel 101 may include a plurality of display areas 102. Figure 2 , multiple display areas 102 are arranged in a matrix form to constitute one display panel 101. The LED display device 10 of the present disclosure may be implemented as a single large display device such as a digital signage and an electronic display in which multiple display areas 102 are connected or assembled, or as a single small display device such as a monitor for a personal computer or a TV, but the present disclosure is not limited thereto.

[0057] Figure 2 Four display areas 102 constituting the display panel 101 are shown, but various numbers of display areas 102 may be coupled to each other to implement the display panel 101 .

[0058] According to an embodiment of the present disclosure, each display area 102 may include a plurality of display units 103. The plurality of display units 103 may include M+1 rows and M+1 columns, where M is a natural number greater than or equal to 1.

[0059] Figure 2 Four display units 103 constituting the display area 102 are shown, but nine display units 103 may be arranged in a 3×3 matrix.

[0060] In detail, Figure 2A first display unit 103a, a second display unit 103b, a third display unit 103c, and a fourth display unit 103d are arranged in the display panel. More specifically, in the first direction X, the first display unit 103a and the second display unit 103b are arranged adjacent to each other, and the third display unit 103c and the fourth display unit 103d are arranged adjacent to each other. In addition, in the second direction Y, the first display unit 103a and the third display unit 103c are arranged adjacent to each other, and the second display unit 103b and the fourth display unit 103d are arranged adjacent to each other.

[0061] According to an embodiment of the present disclosure, the LED display driving device 100 may include a driver IC 140. Specifically, the driver IC 140 may include a master driver IC 140a and a slave driver IC 140b. The master driver IC 140a may output a synchronization signal Sync to the slave driver IC 140b.

[0062] The main driver IC 140a may drive a first scan line group SL1 corresponding to the first and second display units 103a and 103b adjacent to each other in the first direction X and a first channel line group CL1 corresponding to the first and third display units 103a and 103c adjacent to each other in the second direction Y among the plurality of display units 103.

[0063] The slave driver IC 140B may drive a second scan line group SL2 corresponding to the third and fourth display units 103c and 103d adjacent to each other in the first direction X among the plurality of display units 103 and a second channel line group CL2 corresponding to the second and fourth display units 103b and 103d adjacent to each other in the second direction Y.

[0064] According to an embodiment of the present disclosure, the LED display driver apparatus 100 may include one master driver IC 140a and M slave driver ICs 140b for each display area 102. Specifically, when the display area 102 includes M+1 rows and M+1 columns of display cells 103, the LED display driver apparatus 100 may include M+1 driver ICs 140. In this case, among the M+1 driver ICs 140, the number of master driver ICs 140a is one, and the number of slave driver ICs 140b is M.

[0065] According to an embodiment of the present disclosure, the master driver IC 140a may be disposed in the 1st row and 1st column of the corresponding display area 102, and the slave driver IC 140b may be disposed in the Nth row and Nth column of the corresponding display area 102, where N is a natural number greater than 1 and less than or equal to M+1. Figure 2, the master driver IC 140a and the slave driver IC 140b may be disposed in parallel in a diagonal direction based on rows and columns, and the arrangement structure of the master driver IC 140a and the slave driver IC 140b of the present disclosure is not limited thereto.

[0066] Will be in Figure 3 and Figure 4 The configurations of the master driver IC 140a and the slave driver IC 140b are described in detail in FIG.

[0067] Figure 3 is a view showing a configuration of a driver IC 140 according to an embodiment of the present disclosure. Figure 4 is a view showing a portion of an LED display driving device 100 according to an embodiment of the present disclosure.

[0068] The configuration of the master driver IC 140a and the slave driver IC 140b is similar to Figure 3 The configurations of the driver ICs 140 shown are the same. The following description of the driver ICs 140 corresponds to the description of the master driver IC 140a and the slave driver IC 140b.

[0069] According to an embodiment of the present disclosure, the driver IC 140 may include a data driver 120, a gate driver 130, and a display controller 110. The data driver 120, the gate driver 130, and the display controller 110 of the driver IC 140 may correspond to Figure 1 The data driver 120, the gate driver 130 and the display controller 110 described in FIG.

[0070] According to an embodiment of the present disclosure, the driver IC 140 may include an interface 113, a data storage unit 114, a power reduction determination unit 111, a synchronization unit 112, a Vsync input terminal 115, a synchronization signal input terminal Sync_I, a synchronization signal output terminal Sync_O, a data input terminal DATA_I, a clock input terminal CLK_I, a data output terminal DATA_O and a clock output terminal CLK_O.

[0071] The interface 113 can input frame data input from the outside. Specifically, the interface 113 can be used to transfer the frame data input from the outside to the data storage unit 114. Specifically, data DATA and clock CLK can be output from the data input terminal DATA_I and the clock input terminal CLK_I to the data output terminal DATA_O and the clock output terminal CLK_O after passing through the interface 113. More specifically, data DATA and clock CLK can be transferred from the interface 113 provided in the master driver IC 140a to the interface 113 provided in the slave driver IC 140b after passing through the data output terminal DATA_O and the clock output terminal CLK_O.

[0072] Data input from the outside may include data DATA transmitted through the data input terminal DATA_I and a clock CLK transmitted through the clock input terminal CLK_I.

[0073] The data storage unit 114 may be used to store the frame data provided from the interface 113. The data storage unit 114 may include a first data storage unit 114a and a second data storage unit 114b.

[0074] The first data storage unit 114a and the second data storage unit 114b can store frame data in sequence. For example, after the first data storage unit 114a stores the first transmitted frame data, the second data storage unit 114b can store the second transmitted frame data. Figure 3 Only the first and second data storage units 114 a and 114 b are shown in FIG, but the present disclosure is not limited thereto and may include three or more data storage units.

[0075] The data storage unit 114 may transmit the stored frame data to the display controller 110 .

[0076] Description of display controller 110 Figure 1 The description is repeated and will therefore be omitted.

[0077] According to an embodiment of the present disclosure, the display controller 110 may include a power reduction determination unit 111 .

[0078] The power reduction determination unit 111 can be used to determine whether to operate in a low power mode or a normal mode based on the frame data transmitted from the data storage unit 114, which will be described below. Specifically, the power reduction determination unit 111 provided in each of the master driver IC 140a and the slave driver IC 140b can determine whether to operate the data driver 120 and the gate driver 130 of each of the master driver IC 140a and the slave driver IC 140b in the low power mode or in the normal mode.

[0079] Specifically, since the data input from the outside is transmitted to the corresponding power reduction determination unit 111 after passing through the interface 113 of each of the master driver IC 140a and the slave driver IC 140b, the master driver IC 140a and the slave driver IC 140b can know the data information of each other. Therefore, the power reduction determination unit 111 of each of the master driver IC 140a and the slave driver IC 140b can determine whether to operate each of the data driver 120 and the gate driver 130 in the low power mode or in the normal mode.

[0080] The synchronization unit 112 may output the synchronization signal Sync through the synchronization control signal SCS output from the display controller 110 .

[0081] The synchronization signal Sync may be output from the synchronization unit 112 of the master driver IC 140a and transmitted to the display controller 110 of the slave driver IC 140b through the synchronization signal output terminal Sync_O and the synchronization signal input terminal Sync_I of the slave driver IC 140b.

[0082] Based on the synchronization signal Sync output from the master driver IC 140a, the scanning signal of the master driver IC 140a can be synchronized with the scanning signal of the slave driver IC 140b. In detail, the synchronization signal Sync output from the master driver IC 140a includes scanning information corresponding to the master driver IC 140a. That is, the synchronization signal Sync transmits the scanning information corresponding to the master driver IC 140a to the slave driver IC 140b, so that the slave driver IC 140b can determine whether to perform a scanning operation.

[0083] Figure 4 1 is a view showing a portion of the driver IC 140 according to an embodiment of the present disclosure. In detail, Figure 4 is a view for explaining the principle of driving the driver IC 140 in the low power mode or the normal mode.

[0084] Each of the master driver IC 140a and the slave driver IC 140b can be driven in a low power mode or a normal mode. In detail, the data driver 120 and the gate driver 130 of each of the master driver IC 140a and the slave driver IC 140b can be driven in a low power mode or a normal mode.

[0085] Components for driving each of the master driver IC 140 a and the slave driver IC 140 b in the low power mode or the normal mode will be described in detail below.

[0086] The data driver 120 may include a plurality of first switches 151 connecting the plurality of channel stages 121 to the plurality of channel current sources 123 , respectively.

[0087] The plurality of first switches 151 can be switched according to the PWM signal T transmitted from the display controller 110. PWM_R1 Connect or disconnect.

[0088] The plurality of first switches 151 may be switches for controlling subsequent channel currents. For example, the plurality of first switches 151 may be PWM switches. The amount of channel current supplied through each channel line CL may be determined based on the time at which the plurality of first switches 151 are turned on. Thus, the brightness or color of the pixel P may be determined.

[0089] The plurality of channel current sources 123 may generate channel currents using an LED power source, and the channel current generated from each of the plurality of channel current sources 123 may be supplied to pixels P connected in a vertical direction through one channel line CL.

[0090] The data driver 120 may include a plurality of second switches 152 connecting the plurality of channel stages 121 to the plurality of amplifiers 122 , respectively.

[0091] The plurality of second switches 152 can be configured to be switched according to the channel cutoff signal T transmitted from the display controller 110. OFF_R1 Connect or disconnect.

[0092] Each of the plurality of amplifiers 122 may be connected to a supply channel cutoff voltage V OFF_R The plurality of amplifiers 122 can be based on the channel cutoff voltage V OFF_R Specifically, the amplifier 122 can control the channel cutoff voltage V output from the channel cutoff voltage source 124. OFF_R The difference between the voltage and the voltage fed back from the output stage is amplified, and the amplified value is output to the output stage.

[0093] The gate driver 130 may include a plurality of third switches 153 respectively connecting the plurality of output stages 131 to the plurality of scan offset voltage sources 132. Specifically, the plurality of scan offset voltage sources 132 may be connected to the plurality of LEDs through the plurality of third switches 153.

[0094] The plurality of third switches 153 can be switched according to the scan signal T transmitted from the display controller 110. SCAN_ON1 Connect or disconnect.

[0095] Each of the plurality of third switches 153 may be connected to a supply scan-off voltage V OFF_SCAN The scanning offset voltage source 132 is provided.

[0096] The gate driver 130 may include a plurality of scan transistors 154 having one end connected to the plurality of output stages 131 and the other end connected to the ground.

[0097] The plurality of scanning transistors 154 can be configured to be operable according to the scanning signal T transmitted from the display controller 110. SCAN_ON1 On or off.

[0098] That is, when the data driver 120 is driven in the low power mode, this means that all switches corresponding to some or all of the plurality of channel stages 121 in the data driver 120 are turned off. Figure 4 , when the first switch 151 and the second switch 152 corresponding to the first red channel level R[ 1 ] are turned off, it can be considered that the data driver 120 including the first red channel level R[ 1 ] is driven in the low power mode.

[0099] In addition, when the gate driver 130 is driven in the low power mode, this means that the third switches 153 corresponding to some or all of the plurality of output stages 131 in the gate driver 130 are kept in the on state and the scanning transistors 154 are kept in the off state. Figure 4 , when the third switch 153 corresponding to the first output stage SCAN[1] is maintained in the on state and the scan transistor 154 is maintained in the off state, it can be considered that the gate driver 130 including the first output stage SCAN[1] is driven in the low power mode.

[0100] Figure 5 FIG. 1 is an operation timing diagram of the LED display driving device 100 according to an embodiment of the present disclosure.

[0101] In detail, Figure 5 is a timing diagram showing a timing relationship between a vertical synchronization signal Vsync and a data signal DATA.

[0102] Frame data may refer to each image constituting an image, and one frame data may be composed of a plurality of segments.

[0103] One segment may be a unit for performing a scan operation for one cycle. The scan operation may be an operation performed when the third switch 153 included in the gate driver 130 is turned on and then turned off. One cycle of the scan operation may mean that a scan operation is sequentially performed once from the first output stage SCAN[1] to the last output stage SCAN

[36] . Although the last output stage is Figure 6 , it is shown as the 36th output stage, but the present disclosure is not limited thereto.

[0104] Reference Figure 5 , after activating the vertical synchronization signal Vsync, a new frame data starts.

[0105] Specifically, after the transmission of the (N)th frame data (N frame data) is completed, the vertical synchronization signal Vsync of the (N)th frame is activated. In addition, after the vertical synchronization signal Vsync of the (N)th frame is activated, the transmission of the (N+1)th frame data begins.

[0106] According to an embodiment of the present disclosure, after the transmission of the (N)-th frame data (N-frame data) is completed, as the vertical synchronization signal Vsync of the (N)-th frame is activated, the power reduction determination unit 111 can determine whether the master driver IC 140a and the slave driver IC 140b are operating in the low power mode or the normal mode. Specifically, the power reduction determination unit 111 of each of the master driver IC 140a and the slave driver IC 140b can determine whether the master driver IC 140a and the slave driver IC 140b are operating in the low power mode or the normal mode.

[0107] Figure 6 FIG. 1 is an operation timing diagram of the LED display driving device 100 of the present disclosure in a normal mode.

[0108] Figure 6 Graphs of a channel voltage V_CH1_Master applied to a first red channel stage R[1]_master corresponding to the master driver IC 140a and a channel voltage V_CH1_Slave applied to a first red channel stage R[1]_slave corresponding to the slave driver IC 140b are schematically shown.

[0109] In addition, Figure 6 1 and 2 show a scan signal T for controlling the third switch 153 connected to each of the first output stage SCAN[1]_Master to the 36th output stage SCAN

[36] _Master corresponding to the master driver IC 140a and the first output stage SCAN[1]_Slave to the 36th output stage SCAN

[36] _Slave corresponding to the slave driver IC 140b. SCAN_ON1 waveform.

[0110] According to an embodiment of the present disclosure, the first red channel stage R[1]_Master, the first green channel stage G[1]_Master, and the first blue channel stage B[1]_Master to the 40th red channel stage R

[40] _Master, the 40th green channel stage G

[40] _Master, and the 40th blue channel stage B

[40] _Master corresponding to the main driver IC 140a correspond to the first channel line group CL1, and the first output stage SCAN[1]_Master to the 36th output stage SCAN

[36] _Master correspond to the first scan line group SL1.

[0111] According to an embodiment of the present disclosure, the first red channel stage R[1]_slave, the first green channel stage G[1]_slave, and the first blue channel stage B[1]_slave to the 40th red channel stage R

[40] _slave, the 40th green channel stage G

[40] _slave, and the 40th blue channel stage B

[40] _slave corresponding to the slave driver IC 140b correspond to the second channel line group CL2, and the first output stage SCAN[1]_slave to the 36th output stage SCAN

[36] _slave correspond to the second scan line group SL2.

[0112] Reference Figure 6 , the graphs of the channel voltages V_CH1_Master and V_CH1_Slave may include an ON period and an OFF period.

[0113] According to an embodiment of the present disclosure, the channel voltages V_CH1_Master and V_CH1_Slave may represent channel voltages applied to the corresponding channel lines CL when channel currents are supplied to the channel lines CL corresponding to the first red channel stages R[1]_Master and R[1]_Slave. Figure 6 , the channel voltages applied to the channel lines corresponding to other channel stages are omitted.

[0114] According to an embodiment of the present disclosure, during the on-period, the first switch 151 can be turned on so that the channel current generated by the channel current source 123 can be supplied to the channel line CL. During the off-period, the first switch 151 can be turned off so that the channel current generated by the channel current source 123 can be blocked. The graphs of the channel voltages V_CH1_Master and V_CH1_Slave may include alternating on (ON) periods and off (OFF) periods. Although the off period is not shown in the drawings, the off period may be a period other than the period corresponding to the on period.

[0115] For example, the on period of the graphs of the channel voltages V_CH1_Master and V_CH1_Slave may indicate that the PWM signal T is received. PWM_R1 The disconnection period of the curves of the channel voltages V_CH1_Master and V_CH1_Slave may indicate that no PWM signal T is received. PWM_R1 In addition, during the on period, when the PWM signal T PWM_R1 When the PWM signal T is turned on and thus the channel current is supplied to the channel lines CL corresponding to the first red channel stages R[1]_Master and R[1]_Slave, the channel voltages V_CH1_Master and V_CH1_Slave applied to the corresponding channel lines CL may increase from a reference voltage level Voff higher than the ground GND level. PWM_R1 When the channels V_CH1_Master and V_CH1_Slave are disconnected and thus the supply of the channel current stops, the channel voltages V_CH1_Master and V_CH1_Slave may decrease to the reference voltage level Voff again.

[0116] According to an embodiment of the present disclosure, the reason for maintaining the channel voltages V_CH1_Master and V_CH1_Slave at the reference voltage level Voff higher than the ground GND level in the off period is to reduce the time taken for the channel voltages V_CH1_Master and V_CH1_Slave to increase to a maximum value according to the supply of the channel current.

[0117] According to an embodiment of the present disclosure, the normal mode may include a display period and a non-display period. In this case, the display period refers to an on-period of the graphs of the channel voltages V_CH1_Master and V_CH1_Slave, and the non-display period refers to an off-period of the graphs of the channel voltages V_CH1_Master and V_CH1_Slave.

[0118] According to an embodiment of the present disclosure, when the first switch 151 is turned off in the off period of the graph of the channel voltages V_CH1_Master and V_CH1_Slave, the second switch 152 may be turned on. In the off period, the first switch 151 is turned off and the second switch 152 is turned on, so that the channel-off voltage source 124 may generate the channel-off voltage V OFF_R .

[0119] Specifically, in the normal mode, when the first switch 151 is turned off, the second switch 152 may be turned on, and when the first switch 151 is turned on, the second switch 152 may be turned off.

[0120] Reference Figure 6 , scanning signal T SCAN_ON1The control period may include an on period and an off period. In the on period, the third switch 153 may be off and the scan transistor 154 may be on, so that the scan signal may be supplied to the scan line SL. In the off period, the third switch 153 may be on and the scan transistor 154 may be off, so that the scan offset voltage source 132 may supply the scan off voltage V OFF_SCAN Therefore, the scan offset voltage source 132 may output the precharge current to the output stage SCAN[1] after passing through the third switch 153. Although the off period is not shown in the drawings, the off period may be a period excluding the period corresponding to the on period.

[0121] Specifically, in the normal mode, when the third switch 153 is turned off, the scan transistor 154 may be turned on, and when the third switch 153 is turned on, the scan transistor 154 may be turned off.

[0122] According to an embodiment of the present disclosure, during the display period, the plurality of first switches 151 included in the master driver IC 140a and the slave driver IC 140b may be turned on, the plurality of second switches 152 may be turned off, the plurality of third switches 153 may be turned off, and the scan transistor 154 may be turned on. Thus, the LED may be turned on.

[0123] Specifically, in the display period, a plurality of channel current sources 123 corresponding to the first and second channel line groups CL1 and CL2 may supply channel currents to the corresponding channel lines CL, and a plurality of scan transistors 154 corresponding to the first and second scan line groups SL1 and SL2 may be turned on.

[0124] According to an embodiment of the present disclosure, the synchronization signal Sync is activated before the on period of the graphs of the channel voltages V_CH1_Master and V_CH1_Slave. Specifically, the PWM signal T may be input after the synchronization signal Sync is activated. PWM_R1 .

[0125] According to an embodiment of the present disclosure, the scan cut-off voltage V OFF_SCAN Can be greater than the channel cutoff voltage V OFF_R .

[0126] According to an embodiment of the present disclosure, when the first switch 151 is off and the scan transistor 154 is turned off in the non-display period, a period in which the second switch 152 and the third switch 153 are on may be referred to as a reverse voltage bias interval.

[0127] Specifically, in the non-display period, the plurality of channel-off voltage sources 124 corresponding to the first channel line group CL1 and the second channel line group CL2 may output the channel-off voltage V to the corresponding channel lines CL. OFF_R , and the plurality of scan offset voltage sources 132 corresponding to the first scan line group SL1 and the second scan line group SL2 can output the scan cut-off voltage V to the corresponding scan line SL OFF_SCAN .

[0128] The reverse voltage bias interval refers to the channel cutoff voltage V OFF_R and the scan cut-off voltage V OFF_SCAN The LED is maintained in a reverse voltage bias state during a period of time due to the voltage difference between the LED and the display. When the LED is maintained in a reverse voltage bias state, no current may flow to the LED. The LED display driver 100 of the present disclosure can reduce leakage current by maintaining the LED in a reverse voltage bias state for each non-display period in normal mode.

[0129] Figure 7 FIG. 1 is an operation timing diagram of the LED display driving device 100 of the present disclosure in the low power mode. Figure 8 FIG. 2 is an operation timing diagram of the LED display driving device 100 of the present disclosure in another low power mode. Figure 9 FIG. 2 is an operation timing diagram of the LED display driving device 100 of the present disclosure in other low power modes.

[0130] In detail, Figures 7 to 9 The left diagram of FIG. 1 is a view showing a partial area of ​​the display panel 101 according to an embodiment of the present disclosure. Figures 7 to 9 The left diagram shows a region with data "0" in a portion of the display panel 101. Specifically, the left diagram shows that regions with data "0" exist in multiple display cells 103. The fact that the data is "0" can mean that the first switch 151 and the second switch 152 of the channel stage 121 corresponding to the corresponding region are turned off. Specifically, the multiple channel current sources 123 and the multiple amplifiers 122 corresponding to the regions with data "0" are blocked from the corresponding channel lines CL.

[0131] According to an embodiment of the present disclosure, the data driver 120 and the gate driver 130 of each of the master driver IC 140 a and the slave driver IC 140 b may be driven in a low power mode or a normal mode.

[0132] For example, when the data driver 120 is driven in the low power mode, this means that all switches corresponding to some or all of the plurality of channel stages 121 in the data driver 120 are turned off. In addition, when the gate driver 130 is driven in the low power mode, this means that the third switches 153 corresponding to some or all of the plurality of output stages 131 in the gate driver 130 remain in the on state and the scan transistors 154 remain in the off state.

[0133] According to an embodiment of the present disclosure, the normal mode of the data driver 120 means that the data driver 120 does not include a channel stage 121 in which all switches corresponding to any channel stage 121 are turned off. Specifically, the normal mode of the data driver 120 may mean that there is no region in which data is 0 in the display unit 103 based on the second direction Y. In addition, the normal mode of the gate driver 130 means that the gate driver 130 does not include an output stage 131 in which the third switch 153 corresponding to any output stage 131 remains in the on state and the scan transistor 154 remains in the off state. Specifically, the normal mode of the gate driver 130 may mean that there is no region in which data is 0 in the display unit 103 based on the first direction X.

[0134] Reference Figure 7 When the first switches 151 and the second switches 152 corresponding to some of the plurality of channel stages 121 of the master driver IC 140a are disconnected, the data driver 120 of the master driver IC 140a may be driven in the low power mode, the gate driver 130 of the master driver IC 140a may be driven in the normal mode, the data driver 120 of the slave driver IC 140b may be driven in the normal mode, and the gate driver 130 of the slave driver IC 140b may be driven in the normal mode.

[0135] For example, the first switch 151 and the second switch 152 of the channel stage 121 corresponding to the region where the data is "0" in the data driver 120 of the master driver IC 140a are turned off. In this case, the channel voltage V_CH1_Master applied to the channel line CL corresponding to the region where the data is "0" may be the ground GND level.

[0136] For example, when there are areas with data "0" in the first display unit 103a and the third display unit 103c based on the second direction Y, the multiple channel current sources 123 and the multiple amplifiers 122 corresponding to the areas with data "0" in the first channel line group CL1 can be blocked from the corresponding channel lines CL, and the multiple channel current sources 123 corresponding to the second channel line group CL2 supply channel current to the corresponding channel lines CL, and the multiple scanning transistors 154 corresponding to the first scan line group SL1 and the second scan line group SL2 can be turned on.

[0137] Figure 7 The description of the synchronization signal Sync shown is the same as Figure 6 The description of the synchronization signal Sync shown is the same.

[0138] exist Figure 7 , for example, the first red channel level R[1]_Master is the channel level 121 corresponding to an area in which data is “0”.

[0139] Reference Figure 8 When the first switches 151 and the second switches 152 corresponding to some of the plurality of channel stages 121 of the slave driver IC 140 b are disconnected, the data driver 120 of the slave driver IC 140 b may be driven in the low power mode, the gate driver 130 of the slave driver IC 140 b may be driven in the normal mode, the data driver 120 of the master driver IC 140 a may be driven in the normal mode, and the gate driver 130 of the master driver IC 140 a may be driven in the normal mode.

[0140] For example, the first switch 151 and the second switch 152 of the channel stage 121 corresponding to the region where the data is "0" in the data driver 120 of the slave driver IC 140b are turned off. In this case, the channel voltage V_CH1_Slave applied to the channel line CL corresponding to the region where the data is "0" may be the ground GND level.

[0141] For example, when there are areas with data "0" in the second display unit 103b and the fourth display unit 103d based on the second direction Y, the multiple channel current sources 123 and the multiple amplifiers 122 corresponding to the areas with data "0" in the second channel line group CL2 can be blocked from the corresponding channel lines CL, and the multiple channel current sources 123 corresponding to the first channel line group CL1 supply channel current to the corresponding channel lines CL, and the multiple scanning transistors 154 corresponding to the first scan line group SL1 and the second scan line group SL2 can be turned on.

[0142] Figure 8 The description of the synchronization signal Sync shown is the same as Figure 6 and Figure 7 The description of the synchronization signal Sync shown is the same.

[0143] exist Figure 8 For example, the first red channel stage R[1]_Slave is the channel stage 121 corresponding to the region where the data is “0”.

[0144] Reference Figure 9 When the first switches 151 and the second switches 152 corresponding to all the channel stages 121 of the master driver IC 140a and the multiple channel stages 121 of the slave driver IC 140b are disconnected, the data driver 120 of the master driver IC 140a can be driven in the low power mode, the gate driver 130 of the master driver IC 140a can be driven in the low power mode, the data driver 120 of the slave driver IC 140b can be driven in the low power mode, and the gate driver 130 of the slave driver IC 140b can be driven in the low power mode.

[0145] For example, all switches in the data driver 120 of the master driver IC 140a and the slave driver IC 140b are turned off, the third switch 153 in the gate driver 130 is maintained in an on state, and the scan transistor 154 is maintained in an off state.

[0146] For example, when the first display unit 103a, the second display unit 103b, the third display unit 103c and the fourth display unit 104d are all areas with data "0", the multiple channel current sources 123 and the multiple amplifiers 122 of the first channel line group CL1 and the second channel line group CL2 can be blocked from the corresponding channel lines CL, and the multiple scan offset voltage sources 132 corresponding to the first scan line group SL1 and the second scan line group SL2 can be connected to the multiple LEDs corresponding thereto.

[0147] In this case, the channel voltages V_CH1_Master and V_CH1_Slave applied to the channel line CL corresponding to the region where data is “0” may be a ground GND level.

[0148] Reference Figure 9 , the synchronization signal Sync can be deactivated.

[0149] According to the present disclosure, the following advantageous effects can be obtained.

[0150] The LED display driving device according to an embodiment of the present disclosure may include a smaller number of driver ICs compared to the number of display units, thereby reducing power consumption.

[0151] An LED display driving apparatus according to another embodiment of the present disclosure may drive each of a master driver IC and a slave driver IC in a low power mode, thereby reducing power consumption.

[0152] An LED display driving device according to another embodiment of the present disclosure can maintain an LED in a reverse bias state in a normal mode, thereby reducing leakage current.

[0153] It will be apparent to those skilled in the art that the present disclosure is not limited to the above-described embodiments and drawings, and that various substitutions, modifications, and variations may be made in the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the scope of the present disclosure is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims are intended to fall within the scope of the present disclosure.

[0154] CROSS-REFERENCE TO RELATED APPLICATIONS

[0155] This application claims the benefit of Korean Patent Application No. 10-2024-0037399, filed on March 18, 2024, and Korean Patent Application No. 10-2025-0026392, filed on February 28, 2025, which are hereby incorporated by reference as if fully set forth herein.

Claims

1. An LED display driver, comprising: a master driver IC and a slave driver IC for driving a plurality of LEDs arranged in each of a plurality of display areas included in a display panel, Each display area includes multiple display units. The main driver IC drives a first scan line group corresponding to a first display unit and a second display unit adjacent to each other in a first direction among the plurality of display units, and a first channel line group corresponding to the first display unit and a third display unit adjacent to each other in a second direction perpendicular to the first direction among the plurality of display units, and The slave driver IC drives a second scan line group corresponding to the third display unit and the fourth display unit adjacent to each other in the first direction among the multiple display units, and a second channel line group corresponding to the second display unit and the fourth display unit adjacent to each other in the second direction among the multiple display units.

2. The LED display driving device according to claim 1, wherein: The main driver IC is disposed in a region corresponding to the first display unit, and The slave driver IC is disposed in a region corresponding to the fourth display unit.

3. The LED display driving device according to claim 1, wherein: Each of the master driver IC and the slave driver IC includes: a data driver configured to output a data signal corresponding to image data to a plurality of LEDs connected to each channel line through a plurality of channel lines extending in the second direction; a gate driver that selects an LED among the plurality of LEDs to emit light by outputting a scan signal synchronized with the data signal to a plurality of scan lines extending in the first direction; and A display controller controls the data driver and the gate driver.

4. The LED display driving device according to claim 3, wherein: Each of the master driver IC and the slave driver IC further includes a synchronization unit that outputs a synchronization signal by a synchronization control signal output from the display controller, and The scanning signal of the master driver IC is synchronized with the scanning signal of the slave driver IC based on the synchronization signal output from the master driver IC.

5. The LED display driving device according to claim 3, wherein: Each of the master driver IC and the slave driver IC further includes: Interfaces; and a power reduction determination unit that receives data from each interface, Data input from the outside is transmitted to the interface of the slave driver IC through the interface of the master driver IC, and The power reduction determination unit of each of the master driver IC and the slave driver IC determines whether to operate in a low power mode or a normal mode through data received from each interface.

6. The LED display driving device according to claim 3, wherein: The data driver includes: a plurality of channel current sources, the plurality of channel current sources supplying channel currents to corresponding channel lines among the plurality of channel lines; a plurality of channel-cutoff voltage sources, the plurality of channel-cutoff voltage sources outputting channel-cutoff voltages to corresponding channel lines among the plurality of channel lines; and a plurality of amplifiers that amplify a difference between the channel-off voltage output from the channel-off voltage source and a voltage fed back from an output stage and output the amplified value to the output stage, and The gate driver comprises: a plurality of scan offset voltage sources, the plurality of scan offset voltage sources outputting scan-off voltages to corresponding scan lines among the plurality of scan lines; and A plurality of scan transistors are turned on or off according to scan signals transmitted from the display controller, one end of the plurality of scan transistors being connected to the plurality of LEDs and the other end being grounded.

7. The LED display driving device according to claim 6, wherein: Each of the master driver IC and the slave driver IC operates in a normal mode or a low power mode, The normal mode includes a display period and a non-display period, and When each of the master driver IC and the slave driver IC is driven in the normal mode, during the display period, the multiple channel current sources corresponding to the first channel line group and the second channel line group supply channel currents to the corresponding channel lines, and the multiple scan transistors corresponding to the first scan line group and the second scan line group are turned on.

8. The LED display driving device according to claim 6, wherein: Each of the master driver IC and the slave driver IC operates in a normal mode or a low power mode, The normal mode includes a display period and a non-display period, and When each of the master driver IC and the slave driver IC is driven in the normal mode, the scan cut-off voltage is greater than the channel cut-off voltage, and in the non-display period, the multiple channel cut-off voltage sources corresponding to the first channel line group and the second channel line group output the channel cut-off voltage to the corresponding channel line, and the multiple scan offset voltage sources corresponding to the first scan line group and the second scan line group output the scan cut-off voltage to the corresponding scan line, so that the corresponding LED is maintained in a reverse voltage bias state.

9. The LED display driving device according to claim 6, wherein: When there is an area with data of 0 in the first display unit and the third display unit, A plurality of channel current sources and a plurality of amplifiers corresponding to regions where data in the first channel line group is 0 are blocked from the corresponding channel lines. A plurality of channel current sources corresponding to the second channel line group supply channel currents to corresponding channel lines, and A plurality of scan transistors corresponding to the first scan line group and the second scan line group are turned on.

10. The LED display driving device according to claim 6, wherein: When there is an area with data of 0 in the second display unit and the fourth display unit, A plurality of channel current sources and a plurality of amplifiers corresponding to regions where data in the second channel line group is 0 are blocked from the corresponding channel lines. A plurality of channel current sources corresponding to the first channel line group supply channel currents to corresponding channel lines, and A plurality of scan transistors corresponding to the first scan line group and the second scan line group are turned on.

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