Display device, driving method thereof, and electronic device including the display device

Abstract

The invention discloses a display device, a driving method thereof, and an electronic device including the display device. The display device includes: a display panel including a signal line connected to at least one pixel; at least one first output pad transmitting a first driving signal supplied to the signal line; at least one second output pad transmitting a second driving signal supplied to the signal line; a plurality of detection pads sensing each of the first driving signal and the second driving signal; an individual pad disposed adjacent to the at least one first output pad and the at least one second output pad; and a driving circuit generating an individual signal by analyzing a waveform of each of the first driving signal and the second driving signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0037566 filed on March 19, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a display device, a driving method thereof, and an electronic device including the display device. Background Art

[0004] The display device may include a display panel that outputs an image and a driving circuit that provides signals for driving the display panel. The driving circuit may be electrically connected to the display panel through one or more pads to provide a plurality of signals to the display panel. Summary of the Invention

[0005] Embodiments of the present disclosure provide a display device and an electronic device that can prevent or reduce a corrosion phenomenon occurring in a pad, which can improve the reliability of driving of the display device.

[0006] According to an embodiment of the present disclosure, a display device includes: a display panel including a plurality of signal lines connected to at least one pixel; at least one first output pad configured to transmit a first drive signal supplied to the signal line; at least one second output pad configured to transmit a second drive signal supplied to the signal line; a plurality of detection pads configured to sense each of the first drive signal and the second drive signal; a separate pad arranged adjacent to the at least one first output pad and the at least one second output pad; and a driving circuit configured to generate a separate signal by analyzing a waveform of each of the first drive signal and the second drive signal.

[0007] In an embodiment, the driving circuit supplies a separate signal to a separate pad in each of a plurality of predetermined driving cycles.

[0008] In an embodiment, the driving circuit includes: a calculation circuit configured to analyze a first waveform of the first driving signal and a second waveform of the second driving signal; and a generation circuit configured to output a separate signal based on each of the first waveform and the second waveform.

[0009] In an embodiment, the separate signal has a data value that is an average of the data value of the first drive signal and the data value of the second drive signal.

[0010] In an embodiment, any one of the first driving signal and the second driving signal has a high level data value during a first period included in each driving cycle. The separate signal is generated to have a high level data value during a second period smaller than the first period.

[0011] In an embodiment, the second period is half of the first period.

[0012] In an embodiment, the waveform of the separate signal has a form in which any one of the first waveform and the second waveform is shifted by a predetermined time interval.

[0013] In an embodiment, the waveform of the separate signal has a form in which any one of the first waveform and the second waveform is inverted.

[0014] In an embodiment, at least one first output pad includes a 1_1th output pad and a 1_2th output pad sequentially arranged in the first direction. At least one second output pad includes a 2_1th output pad and a 2_2nd output pad sequentially arranged in the first direction. A separate pad is provided between the 1_1th output pad and the 2_1th output pad.

[0015] In an embodiment, the detection pad includes a first sub-detection pad and a second sub-detection pad disposed between the 1_2 output pad and the 2_2 output pad. The first sub-detection pad is configured to sense the first driving signal, and the second sub-detection pad is configured to sense the second driving signal.

[0016] In an embodiment, the at least one first output pad further includes a 1_3rd output pad spaced apart from the 1_2nd output pad in the first direction, and the at least one second output pad further includes a 2_3rd output pad spaced apart from the 2_2nd output pad in the first direction.

[0017] In an embodiment, the detection pads include: a first detection pad disposed adjacent to the 1_2 output pad or the 1_3 output pad in a second direction intersecting the first direction; and a second detection pad disposed adjacent to the 2_2 output pad or the 2_3 output pad in a direction opposite to the second direction. The first detection pad is configured to sense a first drive signal, and the second detection pad is configured to sense a second drive signal.

[0018] In an embodiment, the driving circuit is provided on the display panel in a chip-on-pad manner.

[0019] In an embodiment, each predetermined driving period is a frame.

[0020] According to an embodiment of the present disclosure, a display device includes: a display panel including a plurality of signal lines connected to at least one pixel; at least one first output pad configured to transmit a first drive signal supplied to the signal line; at least one second output pad configured to transmit a second drive signal supplied to the signal line; a plurality of detection pads configured to sense each of the first drive signal and the second drive signal; a separate pad disposed adjacent to the at least one first output pad and the at least one second output pad; and a drive circuit configured to generate a separate signal based on a frequency of each of the first drive signal and the second drive signal. The drive circuit is further configured to supply the separate signal to the separate pad in each of a plurality of predetermined drive cycles.

[0021] According to an embodiment of the present disclosure, a method for driving a display device includes: applying a first drive signal to a first output pad electrically connected to a display panel; applying a second drive signal to a second output pad electrically connected to the display panel that is different from the first output pad; sensing each of the first drive signal and the second drive signal; generating a separate signal based on a waveform of each of the sensed first drive signal and the sensed second drive signal; and supplying the separate signal to a separate pad arranged adjacent to the first output pad and the second output pad in each drive cycle of a plurality of predetermined drive cycles.

[0022] In an embodiment, generating the separate signal includes: analyzing, by a calculation circuit, each of a first waveform of the first drive signal and a second waveform of the second drive signal; and outputting, by a generation circuit, the separate signal based on each of the first waveform and the second waveform.

[0023] In an embodiment, when generating the separate signal, the generating circuit outputs the separate signal having a data value having an average value of a data value of the first drive signal and a data value of the second drive signal.

[0024] In an embodiment, any one of the first drive signal and the second drive signal has a high-level data value during a first period included in each drive cycle. When generating a separate signal, the separate signal is generated to have a high-level data value during a second period smaller than the first period.

[0025] According to an embodiment of the present disclosure, an electronic device includes: a processor configured to provide input image data to a display device; and a display device configured to display an image based on the input image data. The display device includes: a display panel including a plurality of signal lines connected to at least one pixel; at least one first output pad configured to transmit a first drive signal supplied to the signal line; at least one second output pad configured to transmit a second drive signal supplied to the signal line; a plurality of detection pads configured to sense each of the first drive signal and the second drive signal; a separate pad disposed adjacent to the at least one first output pad and the at least one second output pad; a drive circuit configured to generate a separate signal by analyzing the waveform of each of the first drive signal and the second drive signal; and a printed circuit board disposed on the drive circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0027] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0028] Figure 2 It is shown in the figure Figure 1 A circuit diagram of an embodiment of any one of a plurality of pixels included in a display device shown in .

[0029] Figure 3 is a plan view of a display panel according to an embodiment of the present disclosure.

[0030] Figure 4 The diagram shows Figure 3 A plan view of a display panel showing the connection relationship between the pixels and the first pad area shown in FIG.

[0031] Figure 5 is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0032] Figure 6 The diagram shows the Figure 5 1 is a cross-sectional view of the structure of the first pad region and the second pad region taken along line II′ shown in FIG.

[0033] Figure 7 The diagram shows Figure 5 A plan view of an embodiment of a driving circuit is shown in FIG.

[0034] Figure 8 The diagram shows Figure 7 A plan view of an embodiment of the first region is shown in FIG.

[0035] Figure 9 The diagram shows Figure 7 , which is a block diagram of an embodiment of a driving circuit chip.

[0036] Figures 10 to 13 is a waveform diagram illustrating a first scan driving signal, a second scan driving signal, and a separate signal according to an embodiment of the present disclosure.

[0037] Figure 14 is a waveform diagram illustrating a first scan driving signal, a second scan driving signal, and a separate signal according to an embodiment of the present disclosure.

[0038] Figure 15 is a view illustrating an embodiment of data values ​​of separate signals according to frequencies of a first scan driving signal and a second scan driving signal.

[0039] Figure 16 The diagram shows Figure 5 A plan view of an embodiment of a driving circuit is shown in FIG.

[0040] Figure 17 The diagram shows Figure 16 A plan view of an embodiment of the second region is shown in FIG.

[0041] Figure 18 is a flowchart illustrating a method of driving a display device according to an embodiment of the present disclosure.

[0042] Figure 19 is a block diagram illustrating an electronic device including a display device according to an embodiment of the present disclosure.

[0043] Figure 20 The diagram shows Figure 19 1 is a perspective view of an example in which the electronic device shown in 1 is implemented as a tablet personal computer (PC). DETAILED DESCRIPTION

[0044] Hereinafter, embodiments of the present disclosure will be described more fully with reference to the accompanying drawings. Throughout the drawings, like reference numerals may refer to like elements.

[0045] It will be understood that when a component such as a film, region, layer, etc. is referred to as being "on," "connected to," "coupled to," or "adjacent" another component, it can be directly on, connected to, coupled to, or adjacent to the other component, or there may be intervening components. It will also be understood that when a component is referred to as being "between" two components, it can be the only component between the two components, or there may be one or more intervening components. Other words used to describe relationships between components should be interpreted in a similar manner.

[0046] It will be understood that when a component “includes” an element, unless otherwise described to the contrary, the component does not exclude another element but may further include another element. It will be understood that for the purposes of this disclosure, “at least one of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XY, YZ, XZ).

[0047] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, the "first" element discussed below may also be referred to as the "second" element without departing from the teachings of the present disclosure.

[0048] For ease of description, spatially relative terms such as "below" and "above" may be used herein to describe the relationship of one element to another element as illustrated in the figures. It will be understood that, in addition to the orientations described herein and depicted in the figures, the spatially relative terms and the illustrated configurations are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, an element described as "below" or "below" another element or feature will then be oriented as "above" the other element or feature. Thus, the exemplary term "above" can include both above and below orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0049] It should be understood that descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments, unless the context clearly dictates otherwise.

[0050] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0051] As used herein, the term "about" or "approximately" includes the stated value and means within an acceptable deviation range of the specified value determined by one of ordinary skill in the art, taking into account the measurement in question and errors associated with the measurement of the particular quantity (e.g., limitations of the measurement system). For example, "about" or "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0052] In a display device including a driving circuit, the driving circuit is electrically connected to a display panel of the display device by providing multiple signals to one or more pads of the display panel, and voltages with different amplitudes can be applied to the one or more pads. Due to the potential difference generated between adjacent pads, corrosion may occur in any of the pads. The corrosion phenomenon occurring in the pads may cause, for example, increased resistance, disconnection, short circuit and joint failure, and lead to degradation of the reliability of the drive of the display device. The embodiments of the present application described in detail below can reduce or prevent such degradation, and thus can improve the reliability of the drive of the display device.

[0053] Embodiments of the present disclosure provide a display device that can improve reliability by preventing or reducing corrosion in pads. The display device may include a display panel having multiple signal lines connected to at least one pixel and at least one first output pad that transmits a first drive signal to the signal line and at least one second output pad that transmits a second drive signal to the signal line. Multiple detection pads can sense both the first drive signal and the second drive signal. A separate pad can be placed adjacent to the at least one first output pad and the at least one second output pad. The drive circuit can generate a separate signal by analyzing the waveforms of both the first drive signal and the second drive signal. The implementation of the separate signal can manage the potential difference between the signals applied to the pads, which can reduce the risk of corrosion and improve the overall reliability of the display device.

[0054] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure. Figure 2 It is shown in the figure Figure 1 A circuit diagram of an embodiment of any one of a plurality of pixels included in a display device shown in .

[0055] refer to Figure 1 , the display device 100 may include a display panel 110 , a scan driver 120 , an emission driver 130 , a data driver 140 , and a timing controller 150 .

[0056] The display panel 110 may include one or more pixels PX. The one or more pixels PX may be arranged in an orthogonal matrix. Figure 1 , the pixel PX is shown to have a quadrilateral shape. However, the present disclosure is not limited thereto. For example, according to embodiments, the shape of the pixel PX may be variously changed to have shapes such as other polygonal shapes, circular shapes, and elliptical shapes.

[0057] The scan driver 120 may be configured to supply scan signals to scan lines GL, for example, a plurality of scan lines GL1 to GLn (where n is an integer greater than or equal to 1). In some embodiments, the scan driver 120 may be configured to sequentially supply scan signals to the plurality of scan lines GL1 to GLn, but the present disclosure is not limited thereto. The scan driver 120 may receive a scan drive signal SCS and supply the scan signals to the plurality of scan lines GL1 to GLn in synchronization with a timing sequence. For example, in some embodiments, the scan driver 120 may receive a scan drive signal SCS and coordinate the supply of the scan signals to the scan lines GL1 to GLn according to a predetermined timing sequence.

[0058] The emission driver 130 may be configured to supply emission signals to the emission lines EL, for example, a plurality of emission lines EL1 to ELn (where n is an integer greater than or equal to 1). In some embodiments, the emission driver 130 may be configured to sequentially supply the emission signals to the plurality of emission lines EL1 to ELn, but the present disclosure is not limited thereto. The emission driver 130 may receive the emission drive signal ECS and supply the emission signals to the plurality of emission lines EL1 to ELn in synchronization with a timing sequence. For example, in some embodiments, the emission driver 130 may coordinate the supply of the emission signals to the emission lines EL1 to ELn according to a predetermined timing sequence.

[0059] The data driver 140 may be configured to supply (e.g., apply or output) a data voltage to the data lines DL, such as a plurality of data lines DL1 to DLm (where m is an integer greater than or equal to 1). The data driver 140 may receive a data drive signal DCS and second image data DATA2 and supply a data voltage corresponding to the image data to the plurality of data lines DL1 to DLm in synchronization with a timing sequence. For example, in some embodiments, the data driver 140 may coordinate the supply of the data voltage to the data lines DL1 to DLm according to a predetermined timing sequence.

[0060] The timing controller 150 may receive a control signal CS and first image data DATA1 from outside the timing controller 150 (e.g., from a processor). The timing controller 150 may output a data drive signal DCS, a scan drive signal SCS, an emission drive signal ECS, and second image data DATA2 based on the received control signal CS and the received first image data DATA1. For example, the timing controller 150 may convert the received first image data DATA1 into second image data DATA2. The timing controller 150 may then transmit the second image data DATA2 to the data driver 140.

[0061] refer to Figure 2 , the pixel PXij may include a light emitting element, at least one transistor and at least one capacitor. Figure 2The pixel PXij shown in Figure 1 The pixels PX shown in FIG are the same. For example, Figure 2 The pixel PXij shown in can be Figure 1 Pixels located on an i-th (where i is an integer greater than or equal to 1) pixel row and a j-th (where j is an integer greater than or equal to 1) pixel column among the pixels PX shown in .

[0062] In the following, it is assumed that transistors M1 and M2 are implemented using N-type transistors (e.g., n-channel metal oxide semiconductor (NMOS) transistors). However, the present disclosure is not limited thereto. For example, in some embodiments, transistors M1 and M2 may be implemented using P-type transistors (e.g., p-channel metal oxide semiconductor (PMOS) transistors), or a combination of N-type and P-type transistors.

[0063] A gate electrode of the first transistor M1 may be connected to the i-th scan line GLi. One electrode of the first transistor M1 may be connected to the first node N1. The other electrode of the first transistor M1 may be connected to the j-th data line DLj. The first transistor M1 may be referred to as a switching transistor. However, the present disclosure is not limited thereto.

[0064] A gate electrode of the second transistor M2 may be connected to the first node N1. One electrode of the second transistor M2 may be connected to the first power line ELVDDL to which the first power voltage ELVDD is applied. The other electrode of the second transistor M2 may be connected to the second node N2.

[0065] One electrode of the storage capacitor Cst may be connected to the first node N1, and the other electrode of the storage capacitor Cst may be connected to the second node N2.

[0066] The anode of the light-emitting element LD can be connected to the second node N2. The cathode of the light-emitting element LD can be connected to the second power line ELVSSL to which the second power supply voltage ELVSS is applied. The light-emitting element LD can be configured as a light-emitting diode. For example, the light-emitting element LD can be an organic light-emitting diode. However, the present disclosure is not limited thereto. For example, as described above, in some embodiments, the light-emitting element LD can be a quantum dot light-emitting diode.

[0067] Figure 3 is a plan view of a display panel according to an embodiment of the present disclosure. Figure 4 The diagram shows Figure 3 A plan view of a display panel showing the connection relationship between the pixels and the first pad area shown in FIG. Figure 5 is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0068] Figure 3 The display panel DP shown in FIG. Figure 1 The display panel 110 shown in FIG is the same. Hereinafter, for convenience of explanation, repeated description will be omitted.

[0069] refer to Figure 3 The display panel DP may be an emissive display panel. In some embodiments, the display panel DP may be an organic light-emitting display panel or a quantum dot light-emitting display panel. When the display panel DP is an organic light-emitting display panel, the light-emitting layer may include an organic light-emitting material. When the display panel DP is a quantum dot light-emitting display panel, the light-emitting layer may include quantum dots and quantum rods. Hereinafter, for ease of description, the display panel DP is described as being implemented as an organic light-emitting display panel.

[0070] The display panel DP may include a display area DA and a non-display area NDA disposed adjacent to the display area DA. The non-display area NDA may be an area where no image is displayed. In an example, the display area DA may be defined as an area where pixels PX are disposed to provide image information to a user. The non-display area NDA is a peripheral area of ​​the display area DA and may surround the display area DA. For example, the non-display area NDA may be defined as an area where wires and electronic components for driving the pixels PX are disposed.

[0071] The non-display area NDA may include a first pad area PDA-DP. A plurality of pads may be arranged in the first pad area PDA-DP along the first direction DR1. The display panel DP may receive an electrical signal from outside the display panel DP through the plurality of pads.

[0072] refer to Figure 4 , each of the pixels PX can be connected to the first pad area PDA-DP via a plurality of signal lines SL. Each of the pixels PX can be connected to any one of the signal lines SL. For example, each of the pixels PX can be connected to any one of the emission lines EL, the data lines DL, and the scan lines GL. Therefore, each of the pixels PX can receive multiple signals and / or voltages.

[0073] refer to Figure 5 , the display device DD may include a display panel DP, a driving circuit DDI and a printed circuit board FPCB.

[0074] The display panel DP may include a substrate that supports the display panel DP. In some embodiments, the substrate may be a rigid substrate made of glass. The substrate may be a flexible substrate that is bendable, foldable, and rollable. The substrate may include an insulating material, such as a polymer resin such as polyimide.

[0075] According to an embodiment, the substrate may include a silicon wafer substrate formed using a semiconductor process. The substrate may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon-germanium. The substrate may be provided by, for example, a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer.

[0076] The drive circuit DDI may be provided on the display panel DP. For example, the drive circuit DDI may be provided on the aforementioned substrate. In other words, the drive circuit DDI may be provided on the display panel DP (or substrate) in a chip-on-pad (COP) manner. However, the present disclosure is not limited thereto. For example, in some embodiments, the drive circuit DDI may be provided on the display panel DP in a chip-on-film (COF) manner or a chip-on-glass (COG) manner.

[0077] The driving circuit DDI may include a second pad area PDA-DDI (see Figure 7 For example, the driving circuit DDI may include a second pad area PDA-DDI including a plurality of pads.

[0078] The first pad area PDA-DP and the second pad area PDA-DDI may overlap each other. The pads of the first pad area PDA-DP and the second pad area PDA-DDI may contact each other. Therefore, the driving circuit DDI may be electrically connected to the display panel DP through a plurality of pads.

[0079] The driving circuit DDI may include a driving circuit chip DIC (see Figure 7 ). The driving circuit chip DIC can supply multiple signals to the second pad area PDA-DDI. For example, the driving circuit chip DIC can provide various voltages and / or various signals. Therefore, the driving circuit chip DIC can sequentially supply voltages and / or signals to the signal line SL via the second pad area PDA-DDI and the first pad area PDA-DP.

[0080] refer to Figure 1 and Figure 5 The driving circuit DDI may include a scan driver 120 (see Figure 1 ), transmit driver 130 (see Figure 1 ), data driver 140 (see Figure 1 ) and timing controller 150 (see Figure 1). For example, two or more of the scan driver 120, the emission driver 130, the data driver 140, and the timing controller 150 may be mounted in one integrated circuit. For example, two or more of the scan driver 120, the emission driver 130, the data driver 140, and the timing controller 150 may be mounted in a driver circuit chip (DIC). However, the present disclosure is not limited thereto.

[0081] In some embodiments, the scan driver 120 included in the drive circuit DDI may sequentially supply scan signals to the scan lines GL via the second pad area PDA-DDI and the first pad area PDA-DP. Furthermore, the emission driver 130 included in the drive circuit DDI may sequentially supply emission signals to the emission lines EL via the second pad area PDA-DDI and the first pad area PDA-DP. According to an embodiment, the data driver 140 included in the drive circuit DDI may sequentially supply data voltages (or data signals) to the data lines DL via the second pad area PDA-DDI and the first pad area PDA-DP.

[0082] In some embodiments, the drive circuit DDI may include a power generation circuit that supplies power for driving the display panel DP. For example, the power generation circuit may supply a predetermined power source to the scan driver 120. Thus, the scan driver 120 may generate scan signals using the supplied power source. However, the present disclosure is not limited thereto. For example, in some embodiments, the display device DD may be supplied with power from a power source external to the display device DD.

[0083] The printed circuit board FPCB may be disposed on the driving circuit DDI. However, the present disclosure is not limited thereto. For example, in some embodiments, the printed circuit board FPCB may be disposed on the display panel DP (or the substrate of the display panel DP).

[0084] The printed circuit board FPCB may be a flexible printed circuit board. Therefore, the printed circuit board FPCB may be bent in the second direction DR2. However, the present disclosure is not limited thereto.

[0085] The printed circuit board FPCB may transmit a signal received from the outside of the display panel DP. For example, the printed circuit board FPCB may be electrically connected to the display panel DP and the driving circuit DDI to supply the received signal.

[0086] Figure 6 The diagram shows the Figure 5 1 is a cross-sectional view of the structure of the first pad region and the second pad region taken along line II′ shown in FIG. Figure 7 The diagram shows Figure 5 A plan view of an embodiment of a driving circuit is shown in FIG. Figure 8 The diagram shows Figure 7 A plan view of an embodiment of the first region is shown in FIG.

[0087] refer to Figure 6 The input pad PD-DP may be provided on the display panel DP. For example, the input pad PD-DP may be provided on the substrate of the display panel DP.

[0088] In addition, the output pad PD-DDI may be provided on the driving circuit DDI. For example, the output pad PD-DDI may be provided on the substrate of the driving circuit DDI.

[0089] The conductive adhesive film ACF can bond the display panel DP and the drive circuit DDI to each other. For example, the conductive adhesive film ACF can be disposed between the input pads PD-DP and the output pads PD-DDI to bond the display panel DP and the drive circuit DDI to each other. In some embodiments, the conductive adhesive film ACF can be a conductive adhesive member, such as an anisotropic conductive film. However, the present disclosure is not limited thereto.

[0090] The conductive adhesive film ACF may include one or more conductive balls BL and an insulating adhesive member RN. However, the present disclosure is not limited thereto.

[0091] Each of the conductive balls BL may be a conductive particle. The conductive particles are particles capable of conducting electricity and may be, for example, conductive particles such as metals or metal oxides, or particles in which a metal or metal oxide is coated on the surface using an insulating material as a core. The metal contained in the conductive balls BL may include, for example, nickel (Ni), iron (Fe), copper (Cu), aluminum (Al), tin (Sn), zinc (Zn), chromium (Cr), cobalt (Co), silver (Ag), and gold (Au). However, the present disclosure is not limited thereto.

[0092] The insulating adhesive member RN may include an insulating polymer. For example, epoxy resin, acrylic resin, etc. may be used as the insulating polymer. However, this is merely exemplary, and the insulating adhesive member RN may include other insulating polymers.

[0093] refer to Figure 7 , the driving circuit DDI may include a second pad area PDA-DDI and a driving circuit chip DIC.

[0094] The second pad area PDA-DDI may be a portion of an area on the rear surface of the driving circuit DDI. For example, the second pad area PDA-DDI may be a portion of an area on the rear surface of the driving circuit DDI that is adjacent to the first pad area PDA-DP (see FIG. Figure 4 ) part of the area that overlaps.

[0095] The second pad area PDA-DDI may include a plurality of output pads PD-DDI. The plurality of output pads PD-DDI may include first to k-th pads PD1 to PDk (where k is an integer greater than or equal to 1) spaced apart from each other in the first direction DR1 and each arranged in the third direction DR3.

[0096] Each of the first to k-th pads PD1 to PDk may be configured as three rows of pads. For example, the first pad PD1 may include a 1_1 pad PD1_1, a 1_2 pad PD1_2, and a 1_3 pad PD1_3 sequentially arranged in the opposite direction of the third direction DR3. In addition, the second pad PD2 may include a 2_1 pad PD2_1, a 2_2 pad PD2_2, and a 2_3 pad PD2_3 sequentially arranged in the opposite direction of the third direction DR3. Furthermore, the k-th pad PDk may include a k_1 pad PDk_1, a k_2 pad PDk_2, and a k_3 pad PDk_3 sequentially arranged in the opposite direction of the third direction DR3. However, this is merely exemplary, and the present disclosure is not limited thereto.

[0097] The first area A1 may include a first pad PD1 , a second pad PD2 , an individual pad OPD, and a detection pad DPD.

[0098] The driving circuit chip DIC can supply at least one signal and / or at least one voltage to a plurality of output pads PD-DDI provided in the second pad area PDA-DDI. For example, the driving circuit chip DIC can supply a driving signal DS to any one of the first pad PD1 to the kth pad PDk provided in the second pad area PDA-DDI. In some embodiments, the driving signal DS may include a scan driving signal SCS. However, the present disclosure is not limited thereto. For example, in some embodiments, the driving signal DS may include an emission driving signal ECS and / or a data driving signal DCS. The driving signal DS may be transmitted to the display panel DP (see FIG. 1 ) via the first pad PD1 to the kth pad PDk. Figure 5 ) of the signal line SL (see Figure 5 )

[0099] refer to Figure 7 and Figure 8, each of the first pads PD1 can be supplied with a first scan drive signal SCS1 from the drive circuit chip DIC. In addition, each of the second pads PD2 can be supplied with a second scan drive signal SCS2 from the drive circuit chip DIC. Therefore, the drive circuit chip DIC can transmit the first scan drive signal SCS1 and the second scan drive signal SCS2 via the first pad PD1 and the second pad PD2, respectively. For example, the first pad PD1 and the second pad PD2 can each be connected to the input pad PD-DP (see Figure 6 ). Therefore, the drive circuit chip DIC can transmit the first scan drive signal SCS1 to the display panel DP via the corresponding one of the first pad PD1 and the input pad PD-DP. In addition, the drive circuit chip DIC can transmit the second scan drive signal SCS2 to the display panel DP via the corresponding one of the second pad PD2 and the input pad PD-DP.

[0100] The detection pad DPD may be disposed between the first pad PD1 and the second pad PD2. For example, the first detection pad DPD1 may be disposed between the 1st_2nd pad PD1_2 and the 2nd_2nd pad PD2_2. Furthermore, the second detection pad DPD2 may be disposed between the 1st_3rd pad PD1_3 and the 2nd_3rd pad PD2_3. However, the present disclosure is not limited thereto.

[0101] The detection pads DPD can sense the scan drive signal SCS. For example, the first detection pad DPD1 can be electrically connected to the 1_2 pad PD1_2. Therefore, the first detection pad DPD1 can sense the first scan drive signal SCS1 from the 1_2 pad PD1_2. In addition, the second detection pad DPD2 can be electrically connected to the 2_3 pad PD2_3. The second detection pad DPD2 can sense the second scan drive signal SCS2 from the 2_3 pad PD2_3.

[0102] The individual pad OPD may be disposed between the first pad PD1 and the second pad PD2. For example, the individual pad OPD may be disposed between the 1_1st pad PD1_1 and the 2_1st pad PD2_1. However, the present disclosure is not limited thereto.

[0103] The individual pads OPD may be supplied with the individual signals OS. For example, the individual pads OPD may receive the individual signals OS from the driving circuit chip DIC.

[0104] refer to Figures 6 to 8, when the driving circuit DDI applies the driving signal DS to the output pad PD-DDI, the plurality of conductive balls BL may be oxidized and / or reduced. In other words, when a signal having a positive voltage is applied to any one of the output pads PD-DDI, the metal (e.g., nickel (Ni)) contained in the plurality of conductive balls BL may be oxidized. For example, when the potential difference between the signal applied to any one of the output pads PD-DDI and another output pad PD1-DDI disposed adjacent to the above-mentioned output pad is large, the oxidized metal may not be reduced. Therefore, as the metal contained in the conductive ball BL disappears, the resistance of the conductive ball BL or the output pad PD-DDI may increase. Therefore, the driving circuit DDI may not supply at least one of the plurality of signals to the display panel DP, and the display device DD (see Figure 5 )'s drive reliability is degraded.

[0105] According to an embodiment of the present disclosure, the drive circuit chip DIC can supply a separate signal OS generated by considering the waveform of the drive signal DS to the separate pad OPD. For example, the separate pad OPD can be set between the 1_1 pad PD1_1 and the 2_1 pad PD2_1. The separate signal OS can be generated based on the waveforms of the first scan drive signal SCS1 and the second scan drive signal SCS2 applied to the 1_1 pad PD1_1 and the 2_1 pad PD2_1, respectively. Therefore, the potential difference between the signal applied to the separate pad OPD and the 1_1 pad PD1_1 (or the 2_1 pad PD2_1) can be relatively reduced, and the reliability of the drive of the display device DD can be improved.

[0106] Figure 9 The diagram shows Figure 7 , which is a block diagram of an embodiment of a driving circuit chip.

[0107] refer to Figure 9 , the driving circuit chip DIC may include a calculation circuit CT and a generation circuit GT.

[0108] The calculation circuit CT may receive a scan driving signal SCS from the detection pad DPD. For example, the calculation circuit CT may receive a first scan driving signal SCS1 from the first detection pad DPD1 and may receive a second scan driving signal SCS2 from the second detection pad DPD2.

[0109] The calculation circuit CT may receive the first scanning drive signal SCS1 and the second scanning drive signal SCS2 in each of a plurality of predetermined driving cycles. For example, the calculation circuit CT may receive the first scanning drive signal SCS1 and the second scanning drive signal SCS2 in each frame. However, the present disclosure is not limited thereto.

[0110] The calculation circuit CT may determine the waveform of the received scan driving signal SCS. For example, the calculation circuit CT may determine the first waveform of the first scan driving signal SCS1 and the second waveform of the second scan driving signal SCS2.

[0111] The calculation circuit CT may generate sensing data SD based on the waveform of the scan drive signal SCS. For example, the calculation circuit CT may generate sensing data SD including information about the determined first waveform and the determined second waveform. Thus, the calculation circuit CT may transmit the sensing data SD to the generation circuit GT.

[0112] The generating circuit GT may generate the separate signal OS based on the sensing data SD. For example, the generating circuit GT may generate the separate signal OS based on the first waveform and the second waveform, which is described in further detail below.

[0113] The generating circuit GT may generate a separate signal OS in each predetermined driving cycle. For example, the generating circuit GT may generate and output a separate signal OS in each frame. However, the present disclosure is not limited thereto.

[0114] Figures 10 to 13 is a waveform diagram illustrating a first scan driving signal, a second scan driving signal, and a separate signal according to an embodiment of the present disclosure.

[0115] refer to Figure 8 and Figures 10 to 13 The first scan drive signal SCS1 may be transmitted to the scan line GL via the 1_1 pad PD1_1 (see Figure 5 ) signal. In addition, the second scan driving signal SCS2 may be a signal transmitted to the scan line GL via the 2_1-th pad PD2_1. The individual signal OS may be a signal transmitted to the individual pad OPD.

[0116] refer to Figure 10 During the first period P1, the first scan drive signal SCS1 may have a data value of a first scan high level SCSH1. During the first period P1, the second scan drive signal SCS2 may have a data value of a second scan low level SCSL2. During the first period P1, the individual signal OS may have a data value of an individual ground level OSG.

[0117] At the first time T1, the second scan drive signal SCS2 may be changed to have a data value of the second scan high level SCSH2. In addition, during the second period P2, the first scan drive signal SCS1 may have a data value of the first scan high level SCSH1. During the second period P2, the individual signal OS may have a data value of the individual high level OSH.

[0118] At the second time T2, the second scan driving signal SCS2 may be changed to have a data value of a second scan low level SCSL2. In a period between the second time T2 and a third time T3, the individual signal OS may have a data value of an individual ground level OSG.

[0119] At the third time T3, the first scan drive signal SCS1 may be changed to have a data value of the first scan low level SCSL1. Subsequently, during the third period P3, the first scan drive signal SCS1 may have a data value of the first scan low level SCSL1. During the third period P3, the individual signal OS may have a data value of the individual low level OSL.

[0120] At the fourth time T4, the second scan driving signal SCS2 may be changed to have a data value of a second scan high level SCSH2. During the fourth period P4, the individual signal OS may have a data value of an individual ground level OSG.

[0121] At the fifth time T5, the first scan drive signal SCS1 may be changed to a data value having a first scan high level SCSH1. At the fifth time T5, the second scan drive signal SCS2 may be changed to a data value having a second scan low level SCSL2. During a fifth period P5 including the fifth time T5, the individual signal OS may have a data value having an individual ground level OSG.

[0122] In an embodiment of the present disclosure, the generating circuit GT may generate a separate signal OS having an average value of the data value of the first scanning driving signal SCS1 and the data value of the second scanning driving signal SCS2 .

[0123] refer to Figures 11 to 13 , the second scan driving signal SCS2 may have a data value of a second scan low level SCSL2. For ease of description, the second scan driving signal SCS2 is shown to maintain the data value of the second scan low level SCSL2 during one frame. However, the present disclosure is not limited thereto.

[0124] refer to Figure 11 During the first period P1, the first scan driving signal SCS1 may have a data value of a first scan low level SCSL1. During the first period P1, the individual signal OS may have a data value of an individual low level OSL.

[0125] During the first sub-period SP1, the individual signal OS may have a data value of an individual low level OSL. Subsequently, during the second sub-period SP2, the individual signal OS may have a data value of an individual high level OSH. Therefore, the output pad PD-DDI (see Figure 7 ) along with the resistance of the conductive ball BL (see Figure 6 ) disappears and increases. For example, during the first sub-period SP1, the first scan driving signal SCS1 having a high level may be applied to the 1_1 th pad PD1_1 (see Figure 8 ). In addition, during the first sub-period SP1, the individual signal OS having a low level may be applied to the individual pad OPD (see Figure 8 ). Therefore, during the first sub-period SP1, the 1_1st pad PD1_1 may have a positive voltage compared to the individual pad OPD, and the metal contained in the conductive ball BL disposed adjacent to the 1_1st pad PD1_1 may disappear. During the second sub-period SP2, the individual signal OS having a high level may be applied to the individual pad OPD. Therefore, during the second sub-period SP2, the metal contained in the conductive ball BL disposed adjacent to the 1_1st pad PD1_1 may not disappear. In other words, the period in which the 1_1st pad PD1_1 has a positive voltage relative to the individual pad OPD adjacent thereto may be relatively shortened.

[0126] For example, during the first sub-period SP1, the individual signal OS may have a data value of an individual low level OSL. Subsequently, during the second sub-period SP2, the individual signal OS may have a data value of an individual high level OSH. As a result, the conductive ball BL (see FIG. 2 ) may be prevented from being Figure 6 ) caused by the disappearance of the metal in the output pad PD-DDI (see Figure 7 For example, during the first sub-period SP1, the first scan driving signal SCS1 having a high level may be applied to the 1_1 th pad PD1_1 (see Figure 8 ). In addition, during the first sub-period SP1, the individual signal OS having a low level may be applied to the individual pad OPD (see Figure 8 ). Therefore, during the first sub-period SP1, the 1_1th pad PD1_1 may have a positive voltage relative to the individual pad OPD, and the metal in the conductive ball BL disposed adjacent to the 1_1th pad PD1_1 may disappear. During the second sub-period SP2, when the individual signal OS having a high level is applied to the individual pad OPD, the metal in the conductive ball BL disposed adjacent to the 1_1th pad PD1_1 will not disappear. In other words, the duration in which the 1_1th pad PD1_1 has a positive voltage relative to the individual pad OPD can be relatively shortened.

[0127] In an embodiment of the present disclosure, a separate signal OS having a data value of a different level may be applied to the separate pad OPD during the second period P2. Therefore, a period in which the metal contained in the conductive ball BL disposed adjacent to the output pad PD-DDI disappears may be relatively shortened, and the display device DD (see FIG. 1 ) may be relatively improved. Figure 5) drive reliability.

[0128] The length of the second sub-period SP2 may be less than the length of the second period P2. In some embodiments, the length of the second sub-period SP2 may be half the length of the second period P2. However, the present disclosure is not limited thereto. For example, in some embodiments, the length of the second sub-period SP2 may be greater than half the length of the second period P2.

[0129] At the third time T3, the first scan drive signal SCS1 may be changed to have a data value of the first scan low level SCSL1. During the third period P3, the first scan drive signal SCS1 may have a data value of the first scan low level SCSL1. During the third period P3, the individual signal OS may have a data value of the individual low level OSL.

[0130] At the fourth time T4, the first scan drive signal SCS1 may be changed to a data value having a first scan high level SCSH1. During the fourth period P4, the first scan drive signal SCS1 may have a data value having a first scan high level SCSH1. During the third sub-period SP3, the individual signal OS may have a data value having a separate low level OSL. Subsequently, at the fifth time T5, the individual signal OS may be changed to a data value having a separate high level OSH. In other words, during the fourth sub-period SP4, the individual signal OS may have a data value having a separate high level OSH. During the fourth sub-period SP4, the metal contained in the conductive ball BL disposed adjacent to the 1_1th pad PD1_1 may not disappear. Therefore, the risk that the resistance of any one of the output pads PD-DDI to which the first scan drive signal SCS1 is applied (e.g., the 1_1th pad PD1_1) will increase can be relatively reduced.

[0131] At the sixth time T6, the first scan driving signal SCS1 may be changed to have a data value of a first scan low level SCSL1. In addition, at the sixth time T6, the individual signal OS may be changed to have a data value of an individual low level OSL.

[0132] During the fifth period P5 , the first scan driving signal SCS1 may have a data value of a first scan low level SCSL1 . Also, during the fifth period P5 , the individual signal OS may have a data value of an individual low level OSL.

[0133] refer to Figure 12During the first period P1, the first scan drive signal SCS1 may have a data value of a first scan low level SCSL1. During a period before the first time T1 in the first period P1, the individual signal OS may have a data value of an individual high level OSH. At the first time T1, the individual signal OS may be changed to have a data value of an individual low level OSL.

[0134] At the second time T2, the first scan drive signal SCS1 may be changed to a data value having a first scan high level SCSH1. During the second period P2, the first scan drive signal SCS1 may have a data value having a first scan high level SCSH1. During the period before the third time T3 in the second period P2, the individual signal OS may have a data value having an individual low level OSL. At the third time T3, the individual signal OS may be changed to a data value having an individual high level OSH.

[0135] According to an embodiment of the present disclosure, the separate signal OS may have a waveform obtained by shifting the waveform of the first scan drive signal SCS1 by the first offset period S1. For example, the third time T3 may be a time shifted by the first offset period S1 from the second time T2 at which the first scan drive signal SCS1 is changed to a data value having the first scan high level SCSH1. At the third time T3, the separate signal OS may be changed to a data value having the separate high level OSH. Therefore, during the period between the third time T3 and the fourth time T4, the 1_1 pad PD1_1 (see FIG. 1 ) to which the first scan drive signal SCS1 is applied is not connected. Figure 8 ) The metal contained in the conductive ball BL disposed adjacent thereto may not disappear. In other words, the 1_1-th pad PD1_1 is located adjacent to the single pad OPD (see FIG. Figure 8 ) has a positive voltage can be relatively shortened. Therefore, a period in which metal included in the conductive ball BL disposed adjacent to the 1_1-th pad PD1_1 disappears can be relatively shortened.

[0136] At the fourth time T4, the first scan drive signal SCS1 may be changed to a data value having a first scan low level SCSL1. During the third period P3, the first scan drive signal SCS1 may have a data value having a first scan low level SCSL1. During the period before the fifth time T5 in the third period P3, the individual signal OS may have a data value having an individual high level OSH. At the fifth time T5, the individual signal OS may be changed to a data value having an individual low level OSL.

[0137] At the sixth time T6, the first scan drive signal SCS1 may be changed to a data value having a first scan high level SCSH1. During the fourth period P4, the first scan drive signal SCS1 may have a data value having a first scan high level SCSH1. During the period before the seventh time T7 in the fourth period P4, the individual signal OS may have a data value having an individual low level OSL. At the seventh time T7, the individual signal OS may be changed to a data value having an individual high level OSH.

[0138] According to an embodiment of the present disclosure, the independent signal OS may have a waveform obtained by shifting the waveform of the first scan drive signal SCS1 by the second offset period S2. For example, the seventh time T7 may be a time that is shifted by the second offset period S2 from the sixth time T6 at which the first scan drive signal SCS1 changes to a data value having the first scan high level SCSH1. At the seventh time T7, the independent signal OS may be changed to a data value having the independent high level OSH. Therefore, the risk that the resistance of the 1_1th pad PD1_1, to which the first scan drive signal SCS1 is applied, will increase can be relatively reduced.

[0139] The first offset period S1 and the second offset period S2 may have substantially the same length. However, the present disclosure is not limited thereto. For example, in some embodiments, the first offset period S1 may be a relatively longer period than the second offset period S2.

[0140] At the eighth time T8, the first scan drive signal SCS1 may be changed to a data value having a first scan low level SCSL1. During the fifth period P5, the first scan drive signal SCS1 may have a data value having a first scan low level SCSL1. During the period before the ninth time T9 in the fifth period P5, the individual signal OS may have a data value having a single high level OSH. At the ninth time T9, the individual signal OS may be changed to a data value having a single low level OSL. During the period after the ninth time T9 in the fifth period P5, the individual signal OS may have a data value having a single low level OSL.

[0141] refer to Figure 13 At the first time T1, the first scan driving signal SCS1 may be changed to have a data value of the first scan low level SCSL1. During a period between the first time T1 and the second time T2, the first scan driving signal SCS1 may have a data value of the first scan low level SCSL1.

[0142] At the first time T1 , the individual signal OS may be changed to have a data value of an individual high level OSH. During a period between the first time T1 and the second time T2 , the individual signal OS may have a data value of an individual high level OSH.

[0143] At the second time T2, the first scan driving signal SCS1 may be changed to have a data value of the first scan high level SCSH1. During a period between the second time T2 and the third time T3, the first scan driving signal SCS1 may have a data value of the first scan high level SCSH1.

[0144] At the second time T2 , the individual signal OS may be changed to have a data value of an individual low level OSL. During a period between the second time T2 and a third time T3 , the individual signal OS may have a data value of an individual low level OSL.

[0145] At the third time T3 , the first scan driving signal SCS1 may be changed to have a data value of the first scan low level SCSL1 . During a period between the third time T3 and the fourth time T4 , the first scan driving signal SCS1 may have a data value of the first scan low level SCSL1 .

[0146] At the third time T3 , the individual signal OS may be changed to have a data value of an individual high level OSH. During a period between the third time T3 and a fourth time T4 , the individual signal OS may have a data value of an individual high level OSH.

[0147] At the fourth time T4, the first scan driving signal SCS1 may be changed to have a data value of the first scan high level SCSH1. During a period between the fourth time T4 and the fifth time T5, the first scan driving signal SCS1 may have a data value of the first scan high level SCSH1.

[0148] At the fourth time T4 , the individual signal OS may be changed to have the data value of the individual low level OSL. During a period between the fourth time T4 and the fifth time T5 , the individual signal OS may have the data value of the individual low level OSL.

[0149] According to an embodiment of the present disclosure, the waveform of the separate signal OS may have a form in which the waveform of the first scan drive signal SCS1 is inverted in the vertical direction. For example, at the first time T1, the separate signal OS may be changed to a data value having a separate high level OSH, which corresponds to the first scan drive signal SCS1 being changed to a data value having a first scan low level SCSL1. During the period between the first time T1 and the second time T2, the 1_1st pad PD1_1 may be used as a separate pad OPD (see Figure 8 ) compared to the output pad PD-DDI with a relatively negative voltage (see Figure 8 ). Therefore, during the period between the first time T1 and the second time T2, the 1_1st pad PD1_1 (see Figure 8) adjacent conductive balls BL (see Figure 6 ) may not be oxidized. Therefore, a risk that the resistance of the 1_1 th pad PD1_1 to which the first scan driving signal SCS1 is applied will increase may be relatively reduced.

[0150] Figure 14 is a waveform diagram illustrating a first scan driving signal, a second scan driving signal, and a separate signal according to an embodiment of the present disclosure. Figure 15 is a view illustrating an embodiment of data values ​​of separate signals according to frequencies of a first scan driving signal and a second scan driving signal.

[0151] refer to Figure 14 At the first time T1, the first scan driving signal SCS1 may be changed to have a data value of the first scan low level SCSL1. Subsequently, during a period between the first time T1 and the second time T2, the first scan driving signal SCS1 may have a data value of the first scan low level SCSL1.

[0152] At the second time T2, the first scan driving signal SCS1 may be changed to have the data value of the first scan high level SCSH1. Subsequently, during a period between the second time T2 and the third time T3, the first scan driving signal SCS1 may have the data value of the first scan high level SCSH1.

[0153] At the third time T3 , the first scan driving signal SCS1 may be changed to have the data value of the first scan low level SCSL1 . Subsequently, during a period between the third time T3 and the fourth time T4 , the first scan driving signal SCS1 may have the data value of the first scan low level SCSL1 .

[0154] At the fourth time T4, the first scan driving signal SCS1 may be changed to have the data value of the first scan high level SCSH1. Subsequently, during a period between the fourth time T4 and the fifth time T5, the first scan driving signal SCS1 may have the data value of the first scan high level SCSH1.

[0155] During the period between the first time T1 and the fifth time T5, the second scan drive signal SCS2 may have a data value of the second scan low level SCSL2. In other words, the frequency of the second scan drive signal SCS2 may be relatively low compared to the first scan drive signal SCS1. For example, the driving period of the first scan drive signal SCS1 may correspond to the period between the first time T1 and the second time T2. On the other hand, the driving period of the second scan drive signal SCS2 may correspond to the period between the first time T1 and the fifth time T5. Therefore, the first scan drive signal SCS1 may be a signal having a high frequency HF compared to the second scan drive signal SCS2. In addition, the second scan drive signal SCS2 may be a signal having a low frequency LF compared to the first scan drive signal SCS1. During the period between the first time T1 and the fifth time T5, the separate signal OS may have a data value of the separate ground level OSG. However, the present disclosure is not limited to this.

[0156] refer to Figure 14 and Figure 15 , the first scan driving signal SCS1 may be a signal having a high frequency HF, and the second scan driving signal SCS2 may also be a signal having a high frequency HF. The individual signal OS may have a data value of an individual high level OSH.

[0157] According to an embodiment, the first scan driving signal SCS1 may be a signal having a high frequency HF, and the second scan driving signal SCS2 may be a signal having a low frequency LF.The individual signal OS may have a data value of an individual ground level OSG.

[0158] According to an embodiment, the first scan driving signal SCS1 may be a signal having a low frequency LF, and the second scan driving signal SCS2 may be a signal having a high frequency HF.The individual signal OS may have a data value of an individual ground level OSG.

[0159] According to an embodiment, the first scan driving signal SCS1 may be a signal having a low frequency LF, and the second scan driving signal SCS2 may be a signal having a low frequency LF. The individual signal OS may have a data value of an individual low level OSL.

[0160] In other words, the voltage applied to the individual pads OPD (see Figure 8 ) may vary according to the frequencies of the first scan driving signal SCS1 and the second scan driving signal SCS2.

[0161] Figure 16 The diagram shows Figure 5 A plan view of an embodiment of a driving circuit is shown in FIG. Figure 17 The diagram shows Figure 16A plan view of an embodiment of the second region is shown in FIG.

[0162] refer to Figure 16 , the driving circuit DDI′ may include a second pad area PDA-DDI′ and a driving circuit chip DIC.

[0163] The second pad area PDA-DDI' may be a portion of an area on the rear surface of the driving circuit DDI'. For example, the second pad area PDA-DDI' may be a portion of an area on the rear surface of the driving circuit DDI' that is adjacent to the first pad area PDA-DP (see FIG. Figure 4 ) part of the area that overlaps.

[0164] The second pad area PDA-DDI' may include a plurality of output pads PD-DDI'. The plurality of output pads PD-DDI' may include first to k-th pads PD1' to PDk' (where k is an integer greater than or equal to 1) spaced apart from each other in the first direction DR1 and each arranged in the third direction DR3.

[0165] Each of the first to k-th pads PD1' to PDk' may be configured as two rows of pads. For example, the first pad PD1' may include a 1_1th pad PD1_1' and a 1_2th pad PD1_2' sequentially arranged in the opposite direction of the third direction DR3. In addition, the second pad PD2' may include a 2_1st pad PD2_1' and a 2_2nd pad PD2_2' sequentially arranged in the opposite direction of the third direction DR3. In addition, the k-th pad PDk' may include a k_1th pad PDk_1' and a k_2nd pad PDk_2' sequentially arranged in the opposite direction of the third direction DR3.

[0166] The second area A2 may include a first pad PD1 ′, a second pad PD2 ′, an individual pad OPD′, and a detection pad DPD′.

[0167] The driving circuit chip DIC may supply at least one signal and / or at least one voltage to a plurality of output pads PD-DDI′ disposed in the second pad area PDA-DDI′. Figure 16 The driver circuit chip DIC shown in the figure can be used with Figure 7 The driving circuit chip DIC shown in FIG is described identically. Hereinafter, for convenience of explanation, repeated descriptions will be omitted or simplified.

[0168] In addition, if Figure 16 The 1_1st pad PD1_1′, the 1_2nd pad PD1_2′, the 2_1st pad PD2_1′, the 2_2nd pad PD2_2′, the k_1st pad PDk_1′, the k_2nd pad PDk_2′ and the individual pad OPD′ shown in FIG. Figure 71_1th pad PD1_1, 1_2th pad PD1_2, 2_1th pad PD2_1, 2_2th pad PD2_2, k_1th pad PDk_1, k_2th pad PDk_2, and individual pad OPD shown in FIG are identically described.

[0169] refer to Figure 16 and Figure 17 , the detection pad DPD′ may include a first sub-detection pad SDPD1 and a second sub-detection pad SDPD2.

[0170] The first sub-detection pad SDPD1 and the second sub-detection pad SDPD2 may have an area smaller than that of either the first pad PD1' or the second pad PD2' on a plane. For example, the area obtained by adding the area of ​​the first sub-detection pad SDPD1 and the area of ​​the second sub-detection pad SDPD2 may be smaller than the area of ​​the 1_1st pad PD1_1'. However, the present disclosure is not limited thereto.

[0171] The first sub-detection pad SDPD1 may be disposed adjacent to the 1_2 th pad PD1_2 ′. In addition, the second sub-detection pad SDPD2 may be disposed adjacent to the 2_2 th pad PD2_2 ′.

[0172] The detection pad DPD' can sense the scan drive signal SCS. For example, the first sub-detection pad SDPD1 can be electrically connected to the 1_2 th pad PD1_2'. Therefore, the first sub-detection pad SDPD1 can sense the first scan drive signal SCS1 from the 1_2 th pad PD1_2'. In addition, the second sub-detection pad SDPD2 can be electrically connected to the 2_2 th pad PD2_2'. The second sub-detection pad SDPD2 can sense the second scan drive signal SCS2 from the 2_2 th pad PD2_2'.

[0173] refer to Figure 16 and Figure 17 , the drive circuit chip DIC can supply the individual signal OS' to the individual pad OPD'. For example, the drive circuit chip DIC can generate the individual signal OS' based on the first scan drive signal SCS1 and the second scan drive signal SCS2 transmitted from the first sub-detection pad SDPD1 and the second sub-detection pad SDPD2, respectively. Therefore, the drive circuit chip DIC can transmit the individual signal OS' to the individual pad OPD'.

[0174] Figure 18 is a flowchart illustrating a method of driving a display device according to an embodiment of the present disclosure.

[0175] refer to Figure 18According to an embodiment of the present disclosure, a method 1800 for driving a display device may include an operation S1810 of applying a first driving signal to a first output pad, an operation S1820 of applying a second driving signal to a second output pad different from the first output pad, an operation S1830 of sensing each of the first driving signal and the second driving signal, an operation S1840 of generating a separate signal based on a waveform of each of the sensed first driving signal and the sensed second driving signal, and an operation S1850 of supplying a separate signal to a separate pad disposed adjacent to the first output pad and the second output pad in each predetermined driving cycle.

[0176] refer to Figure 7 、 Figure 8 and Figure 18 In operation S1810 of applying the first driving signal to the first output pad, the driving circuit chip DIC may transmit the driving signal DS to any one of the output pads PD-DDI. For example, the driving circuit chip DIC may supply the first scan driving signal SCS1 to the 1_1th pad PD1_1.

[0177] refer to Figure 7 、 Figure 8 and Figure 18 In operation S1820 of applying the second drive signal to a second output pad different from the first output pad, the drive circuit chip DIC may transmit a different drive signal DS to another of the output pads PD-DDI. For example, the drive circuit chip DIC may supply the second scan drive signal SCS2 to the 2_1st pad PD2_1.

[0178] refer to Figures 7 to 9 as well as Figure 18 In operation S1830 of sensing each of the first drive signal and the second drive signal, the detection pad DPD may sense the drive signal DS. For example, the first detection pad DPD1 may sense the first scan drive signal SCS1. Furthermore, the second detection pad DPD2 may sense the second scan drive signal SCS2. The first detection pad DPD1 and the second detection pad DPD2 may respectively sense the first scan drive signal SCS1 and the second scan drive signal SCS2 in each frame. However, the present disclosure is not limited thereto.

[0179] The calculation circuit CT may generate sensing data SD including information about the waveform of each of the first scan drive signal SCS1 and the second scan drive signal SCS2. The calculation circuit CT may transmit the sensing data SD to the generation circuit GT. In some embodiments, the calculation circuit CT may generate the sensing data SD every frame.

[0180] Reference Figures 8 to 13 as well as Figure 18 In operation S1840 of generating a separate signal based on the waveform of each of the sensed first drive signal and the sensed second drive signal, the generation circuit GT may generate the separate signal OS based on the first waveform of the first scan drive signal SCS1 and the second waveform of the second scan drive signal SCS2. For example, the generation circuit GT may generate the separate signal OS having the average value of the data value of the first scan drive signal SCS1 and the data value of the second scan drive signal SCS2 based on the sensed data SD. However, this is merely exemplary, and the generation circuit GT may generate the separate signal OS according to various embodiments as described above.

[0181] Reference Figure 7 、 Figure 8 and Figure 18 In operation S1850 of supplying a separate signal to a separate pad disposed adjacent to the first output pad and the second output pad in each predetermined driving cycle, the drive circuit chip DIC may supply the separate signal OS to the separate pad OPD in each predetermined driving cycle. For example, the drive circuit chip DIC may supply the separate signal OS to the separate pad OPD in each frame. However, the present disclosure is not limited thereto.

[0182] Figure 19 is a block diagram illustrating an electronic device including a display device according to an embodiment of the present disclosure. Figure 20 The diagram shows Figure 19 1 is a perspective view of an example in which the electronic device shown in 1 is implemented as a tablet personal computer (PC).

[0183] refer to Figure 19 and Figure 20 The electronic device ED may include a processor PRC, a memory device MEM, a storage device SRD, an input / output (I / O) device IO, a power supply PS, and a display device 1900. The display device 1900 may be Figure 5 According to an embodiment, the electronic device ED may further include several ports capable of communicating with, for example, a video card, a sound card, a memory card, a USB device, etc. or with other systems. In an embodiment, as shown in FIG. Figure 20 As shown in FIG, the electronic device ED may be implemented as a tablet PC 2000. However, this is merely exemplary, and the electronic device ED is not limited thereto. For example, in some embodiments, the electronic device ED may be implemented as a mobile phone, a video phone, a smart tablet, a smart watch, a car navigation system, a computer monitor, a notebook computer, or a head-mounted display device.

[0184] The processor PRC can perform specific calculations or tasks. In some embodiments, the processor PRC can be, for example, a microprocessor, a central processing unit, or an application processor. The processor PRC can be connected to other components via, for example, an address bus, a control bus, and a data bus. In some embodiments, the processor PRC can be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0185] The memory device MEM may store data used for the operation of the electronic device ED. For example, the memory device MEM may include a non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, or a volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, or a mobile DRAM device.

[0186] The storage device SRD may include, for example, a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, and the like.

[0187] The I / O device 10 may include an input device such as a keyboard, a keypad, a touch screen, or a mouse, and an output device such as a speaker or a printer. In some embodiments, the display device 1900 may be included in the I / O device 10.

[0188] The power supply PS may supply power for the operation of the electronic device ED. For example, the power supply PS may be a power management integrated circuit (PMIC).

[0189] The display device 1900 can display an image corresponding to the visual information of the electronic device ED. The display device 1900 can be, for example, an organic light-emitting display device or a quantum dot light-emitting display device, but the present disclosure is not limited thereto. The display device 1900 can be connected to other components via a bus or another communication link.

[0190] refer to Figure 20 , driving reliability of the tablet PC 2000 including the display device according to the embodiment of the present disclosure may be improved.

[0191] According to the embodiments of the present disclosure, it is possible to provide a display device and an electronic device that can prevent a corrosion phenomenon from occurring in a pad, thereby improving driving reliability.

[0192] According to the convention in the field of the present disclosure, the embodiments are described in terms of functional blocks, units and / or modules and are illustrated in the accompanying drawings. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc. that can be formed using semiconductor-based manufacturing technology or other manufacturing technology. In the case where blocks, units and / or modules are implemented by microprocessors etc., they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. Alternatively, each block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) that performs other functions.

[0193] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the claims.

Claims

1. A display device, comprising: A display panel including a plurality of signal lines connected to at least one pixel; at least one first output pad configured to transmit a first driving signal supplied to the signal line; at least one second output pad configured to transmit a second driving signal supplied to the signal line; a plurality of detection pads configured to sense each of the first drive signal and the second drive signal; a separate pad disposed adjacent to the at least one first output pad and the at least one second output pad; as well as The driving circuit is configured to generate a separate signal by analyzing a waveform of each of the first driving signal and the second driving signal.

2. The display device according to claim 1, wherein The driving circuit is configured to supply the individual signal to the individual pad in each of a plurality of predetermined driving cycles.

3. The display device according to claim 2, wherein: The driving circuit includes: a calculation circuit configured to analyze a first waveform of the first drive signal and a second waveform of the second drive signal; and A generating circuit is configured to output the separate signal based on each of the first waveform and the second waveform.

4. The display device according to claim 2, wherein The separate signal has a data value that is an average of the data value of the first drive signal and the data value of the second drive signal.

5. The display device according to claim 2, wherein Any one of the first driving signal and the second driving signal has a data value of a high level during a first period included in each driving cycle, and The separate signal is generated to have the data value of the high level during a second period that is smaller than the first period. The display device according to claim 5 , wherein: The second period is half of the first period.

7. The display device according to claim 3, wherein: The waveform of the separate signal has a form in which any one of the first waveform and the second waveform is shifted by a predetermined time interval.

8. The display device according to claim 3, wherein: The waveform of the separate signal has a form in which any one of the first waveform and the second waveform is inverted.

9. The display device according to claim 1, wherein The at least one first output pad includes a 1_1th output pad and a 1_2th output pad sequentially arranged in the first direction, wherein the at least one second output pad includes a 2_1st output pad and a 2_2nd output pad sequentially arranged in the first direction, and The separate pad is disposed between the 1_1 th output pad and the 2_1 th output pad.

10. The display device according to claim 9, wherein The detection pad includes a first sub-detection pad and a second sub-detection pad disposed between the 1_2 output pad and the 2_2 output pad, and The first sub-detection pad senses the first driving signal, and the second sub-detection pad senses the second driving signal.

11. The display device according to claim 9, wherein The at least one first output pad further includes a 1_3th output pad spaced apart from the 1_2th output pad in the first direction, and The at least one second output pad further includes a 2_3 th output pad spaced apart from the 2_2 th output pad in the first direction.

12. The display device according to claim 11, wherein The detection pad includes: a first detection pad, disposed adjacent to the 1_2 output pad or the 1_3 output pad in a second direction intersecting the first direction; and The second detection pad is arranged adjacent to the 2_2 output pad or the 2_3 output pad in the opposite direction of the second direction. The first detection pad is configured to sense the first driving signal, and the second detection pad is configured to sense the second driving signal.

13. The display device according to claim 1, wherein The driving circuit is arranged on the display panel in a chip-on-pad manner.

14. The display device according to claim 2, wherein: Each predetermined driving period is a frame.

15. A display device comprising: A display panel including a plurality of signal lines connected to at least one pixel; at least one first output pad configured to transmit a first driving signal supplied to the signal line; at least one second output pad configured to transmit a second driving signal supplied to the signal line; a plurality of detection pads configured to sense each of the first drive signal and the second drive signal; a separate pad disposed adjacent to the at least one first output pad and the at least one second output pad; as well as a drive circuit configured to generate a separate signal based on a frequency of each of the first drive signal and the second drive signal, The driving circuit is further configured to supply the individual signal to the individual pad in each of a plurality of predetermined driving cycles.

16. A method for driving a display device, the method comprising: applying a first driving signal to a first output pad electrically connected to the display panel; applying a second driving signal to a second output pad electrically connected to the display panel and different from the first output pad; sensing each of the first drive signal and the second drive signal; generating a separate signal based on a waveform of each of the sensed first drive signal and the sensed second drive signal; as well as The individual signal is supplied to an individual pad disposed adjacent to the first output pad and the second output pad in each of a plurality of predetermined driving cycles.

17. The method according to claim 16, wherein: Generating the separate signal comprises: analyzing, by a calculation circuit, each of a first waveform of the first drive signal and a second waveform of the second drive signal; and The separate signal is output by a generating circuit based on each of the first waveform and the second waveform.

18. The method according to claim 17, wherein When generating the individual signal, the generation circuit outputs the individual signal having a data value that is an average of a data value of the first drive signal and a data value of the second drive signal.

19. The method according to claim 17, wherein Any one of the first driving signal and the second driving signal has a data value of a high level during a first period included in each driving cycle, and When the separate signal is generated, the separate signal is generated to have the data value of the high level during a second period that is smaller than the first period.

20. An electronic device comprising: a processor configured to provide input image data to a display device according to any one of claims 1 to 15; as well as The display device is configured to display an image based on the input image data, Wherein, the display device further comprises: A printed circuit board is arranged on the driving circuit.

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