Power management circuit, circuit system and wearable device

Abstract

The invention provides a power management circuit, a circuit system and wearable equipment. The power management circuit comprises a power switching module, an input detection module, an input comparison module, a driving control module and a switch switching module. And the power supply switching module internally connects the port of the positive electrode of the external power supply to the power supply output end of the equipment and internally connects the port of the external grounding end to the power supply ground end of the equipment, so that reverse connection prevention of power supply input is realized. When the input detection module detects that the voltage at the power supply output end is smaller than or equal to the communication threshold voltage, the input detection module outputs a first driving signal group to the driving control module, and the driving control module outputs a comparison signal according to the comparison signal output by the comparison module. And different switch signal groups are output to control the switch switching module to internally connect the first external port or the second external port to a signal communication end of a rear-end circuit, so that communication connection between the rear-end circuit and external communication equipment is established, and reverse connection prevention of communication input is realized at the same time.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and in particular to a power management circuit, a circuit system, and a wearable device. Background Art

[0002] In wearable devices, two pins or contacts of a single interface are usually provided as input interfaces for an external power supply. To prevent damage to the wearable device caused by reverse connection of the external power supply, an anti-reverse connection structure is often provided inside the device in the prior art.

[0003] However, the input interface of the wearable device in the prior art cannot realize two-way communication between the back-end circuit of the device and the external input device while realizing the reverse connection protection of the power input. Summary of the Invention

[0004] The technical problem solved by the present invention is: on the basis of realizing the reverse connection protection of external power input, communication with an external input device is achieved through the same external connection port.

[0005] To solve the above technical problems, the technical solution of the present invention provides a power management circuit, comprising: A power switching module, the power switching module being configured to: if the first external port is externally connected to the ground terminal, connect the second external port internally to the power output terminal, and connect the first external port internally to the power ground terminal; if the second external port is externally connected to the ground terminal, connect the first external port internally to the power output terminal, and connect the second external port internally to the power ground terminal; an input detection module, configured to output a first drive signal group when a voltage at the power output terminal is less than or equal to a communication threshold voltage; an input comparison module, configured to output a first comparison signal if a first voltage at the first external port is greater than a second voltage at the second external port; and output a second comparison signal if the first voltage is less than the second voltage; a drive control module, configured to: output a first switch signal group according to the first drive signal group and a first comparison signal; or output a second switch signal group according to the first drive signal group and a second comparison signal; A switch switching module, the switch switching module is used to: connect the first external port internally to the signal communication terminal and connect the second external port internally to the power ground terminal according to the first switch signal group; or connect the second external port internally to the signal communication terminal and connect the first external port internally to the power ground terminal according to the second switch signal group.

[0006] Optionally, the switch switching module includes a first switch and a second switch; A first end of the first switch is connected to the first external port, a second end of the first switch is connected to the signal communication end, and a third end of the first switch is connected to the power ground end. The first switch controls the connection between its first end and its second end according to the first switch signal group, and further controls the connection between its first end and its third end according to the second switch signal group. The first end of the second switch is connected to the second external port, the second end of the second switch is connected to the signal communication end, and the third end of the second switch is connected to the power ground end. The second switch controls its first end to connect to its third end according to the first switch signal group, and the second switch also controls its first end to connect to its second end according to the second switch signal group.

[0007] Optionally, the power switching module includes a first switching PMOS transistor, a second switching PMOS transistor, a first switching NMOS transistor, a second switching NMOS transistor, a third switching NMOS transistor and a fourth switching NMOS transistor; The drain of the first switching PMOS transistor, the gate of the second switching PMOS transistor, and the source of the first switching NMOS transistor are all connected to the second external port, the drain of the second switching PMOS transistor, the gate of the first switching PMOS transistor, and the source of the second switching NMOS transistor are all connected to the first external port, and the drain of the first switching NMOS transistor, the drain of the second switching NMOS transistor, the source of the first switching PMOS transistor, and the source of the second switching PMOS transistor are all connected to the power output terminal; The drain of the third switching NMOS tube and the gate of the fourth switching NMOS tube are both connected to the second external port, the gate of the third switching NMOS tube and the drain of the fourth switching NMOS tube are both connected to the first external port, and the source of the third switching NMOS tube and the source of the fourth switching NMOS tube are both connected to the power ground.

[0008] Optionally, the power management circuit further includes a linear voltage regulator module, a unidirectional conducting PMOS tube, a power supply capacitor and a first comparator; The linear voltage stabilization module is used to convert the voltage at the power output end into a supply voltage and output the voltage; The drain of the unidirectional conducting PMOS tube is connected to the output end of the linear voltage regulator module, and the source of the unidirectional conducting PMOS tube is connected to the power supply voltage end; The non-inverting input terminal of the first comparator is connected to the source of the unidirectional conducting PMOS transistor, the inverting input terminal of the first comparator is connected to the drain of the unidirectional conducting PMOS transistor, and the output terminal of the first comparator is connected to the gate of the unidirectional conducting PMOS transistor; The first end of the power supply capacitor is also connected to the power supply voltage end, and the second end of the power supply capacitor is connected to the power ground end.

[0009] Optionally, the power management circuit further includes a power channel NMOS transistor, wherein the drain of the power channel NMOS transistor is connected to the power output terminal, and the source of the power channel NMOS transistor is connected to the power terminal of the back-end circuit; The input detection module is further configured to: output a second drive signal group if the voltage at the power output terminal is greater than or equal to an overvoltage threshold voltage, and the overvoltage threshold voltage is greater than the communication threshold voltage; and output a third drive signal group if the voltage at the power output terminal is less than the overvoltage threshold voltage and greater than the communication threshold voltage; The drive control module is further configured to: output a first drive voltage to the gate of the power channel NMOS transistor according to the second drive signal group to turn off the power channel NMOS transistor; and output a second drive voltage and a third drive voltage to the gate of the first switching NMOS transistor and the gate of the second switching NMOS transistor, respectively, to turn off the gates of the first switching NMOS transistor and the second switching NMOS transistor; or, output a fourth drive voltage to the gate of the power channel NMOS transistor according to the third drive signal group and the first comparison signal to turn on the power channel NMOS transistor; output a fifth drive voltage to the gate of the second switching NMOS transistor to turn on the second switching NMOS transistor; and output a sixth drive voltage to the gate of the first switching NMOS transistor to turn off the first switching NMOS transistor; or, output a fourth drive voltage to the gate of the power channel NMOS transistor according to the third drive signal group and the second comparison signal to turn on the power channel NMOS transistor; output a seventh drive voltage to the gate of the second switching NMOS transistor to turn off the second switching NMOS transistor; and output an eighth drive voltage to the gate of the first switching NMOS transistor to turn on the first switching NMOS transistor.

[0010] Optionally, the input detection module includes: a first voltage-dividing resistor, a second voltage-dividing resistor, a second comparator, and a third comparator; A first end of the first voltage-dividing resistor is connected to the power supply output end, and a second end of the first voltage-dividing resistor is respectively connected to the non-inverting input end of the second comparator, the non-inverting input end of the third comparator, and the first end of the second voltage-dividing resistor; The second end of the second voltage-dividing resistor is connected to the power ground; The inverting input terminal of the second comparator is connected to the overvoltage threshold voltage, and the output terminal of the second comparator is connected to the drive control module; the inverting input terminal of the third comparator is connected to the communication threshold voltage, and the output terminal of the third comparator is connected to the drive control module; The high level output by the second comparator and the high level output by the third comparator constitute the second driving signal group; The low level output by the second comparator and the high level output by the third comparator constitute the third driving signal group; The low level output by the second comparator and the low level output by the third comparator constitute the first driving signal group.

[0011] Optionally, the drive control module includes a control unit and a charge pump; The control unit is configured to: output a first switching signal group according to the first drive signal group and the first comparison signal; or output a second switching signal group according to the first drive signal group and the second comparison signal; The charge pump is used to: output the first drive voltage, the second drive voltage and the third drive voltage according to the first drive signal group and the second drive signal group; or, output the fourth drive voltage, the fifth drive voltage and the sixth drive voltage according to the third drive signal group and the first comparison signal; or, output the fourth drive voltage, the seventh drive voltage and the eighth drive voltage according to the third drive signal group and the second comparison signal.

[0012] Optionally, the input comparator module includes a fourth comparator, the inverting input of the fourth comparator is connected to the first external port, the non-inverting input of the fourth comparator is connected to the second external port, and the output of the fourth comparator is connected to the drive control module.

[0013] Optionally, the hysteresis voltage of the fourth comparator is greater than or equal to 300 mV.

[0014] The technical solution of the present invention further provides a circuit system, including the power management circuit.

[0015] The technical solution of the present invention also provides a wearable device, including the circuit system.

[0016] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects: The power management circuit provided by the technical solution of the present invention has the following characteristics: if the first external port and the second external port are externally connected to the positive power supply and the ground terminal, then regardless of which port is connected to the ground terminal, the power switching module can internally connect the port connected to the external positive power supply to the power output terminal of the device and the port connected to the external ground terminal to the power ground terminal of the device, thereby preventing the power input from being reversed. When the input detection module detects that the voltage at the power output terminal is less than or equal to the communication threshold voltage, it outputs a first drive signal group to the drive control module to indicate that the external device is a communication device. Therefore, the drive control module outputs different switch signal groups based on the comparison signal output by the comparison module to control the switch switching module to internally connect the first external port or the second external port to the signal communication terminal of the back-end circuit to establish a communication connection between the back-end circuit and the external communication device. Because the comparison signal is used to represent the voltage level of each of the first and second external ports, the switch switching module internally connects the external port with a higher port voltage to the signal communication terminal and the external port with a lower port voltage to the power ground terminal according to different switch signal groups, thereby preventing the communication input from being reversed.

[0017] Furthermore, when the first switching NMOS transistor or the second switching NMOS transistor is turned on under the conditions met, its parallel connection with the first switching PMOS transistor or the second switching PMOS transistor significantly reduces the resistance of the power path, thereby significantly reducing the transmission loss of the power path during current input. Furthermore, because the volume of an NMOS transistor is significantly smaller than that of a PMOS transistor at the same impedance, the impact of parallel NMOS transistors on circuit integration is extremely limited.

[0018] In addition, the first switching PMOS tube, the second switching PMOS tube, the third switching NMOS tube and the fourth switching NMOS tube can all be automatically turned on and off according to the external pins of the first external port and the second external port, thereby realizing automatic anti-reverse connection of the power input.

[0019] Finally, the first switching PMOS transistor and the second switching PMOS transistor can also be turned on when the external input device is a communication device, thereby enabling the normal operation of the power management circuit. Furthermore, when the first switching PMOS transistor or the second switching PMOS transistor is turned on, the voltage difference between the first external port and the second external port is losslessly transmitted to the input detection module via the first switching PMOS transistor or the second switching PMOS transistor, thereby improving the input detection module's detection accuracy of the voltage at the power output terminal.

[0020] Furthermore, when the external input device is a communication device, there is no need to draw power from the system (such as an internal battery) through the linear voltage regulator module, the first comparator, the unidirectional conduction PMOS tube and the power supply capacitor, thereby further reducing the system power consumption when the circuit enters the communication mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Schematic diagram of the circuit structure of the power management circuit provided by the embodiment of the present invention Figure 1 ; Figure 2 Schematic diagram of the circuit structure of the power management circuit provided by the embodiment of the present invention Figure 2 . DETAILED DESCRIPTION

[0022] As described in the background art, the input interface of the wearable device in the prior art cannot simultaneously realize two-way communication between the back-end circuit of the device and the external input device while realizing the protection against reverse connection of the power input.

[0023] An embodiment of the present invention provides a new power management circuit, including a power switching module, an input detection module, an input comparison module, a drive control module, and a switch switching module. If the first external port and the second external port are externally connected to the positive pole of the power supply and the ground terminal, no matter which port is connected to the ground terminal, the power switching module can connect the port of the external positive pole of the power supply to the power output terminal of the device, and connect the port of the external ground terminal to the power ground terminal of the device, thereby realizing the anti-reverse connection of the power input. When the input detection module detects that the voltage at the power output terminal is less than or equal to the communication threshold voltage, it outputs a first drive signal group to the drive control module to indicate that the external device is a communication device. Therefore, the drive control module will output different switch signal groups according to the comparison signal output by the comparison module to control the switch switching module to connect the first external port or the second external port to the signal communication terminal of the back-end circuit to establish a communication connection between the back-end circuit and the external communication device. Since the comparison signal is used to represent the voltage size of the first external port and the second external port, the switch switching module connects the port with a larger port voltage to the signal communication terminal and connects the port with a smaller port voltage to the power ground terminal according to different switch signal groups, thereby achieving anti-reverse connection of the communication input.

[0024] To make the above-mentioned objectives, features, and beneficial effects of the present invention more readily apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. It should be understood that the described embodiments are only some, and not all, of the embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention. The terms "first," "second," "third," "fourth," and so on (if any) in the specification and claims of the present invention and the accompanying drawings are used to distinguish similar items and are not necessarily used to describe a specific order or precedence. It should be understood that such terms are interchangeable where appropriate, such that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "including," "comprising," and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, product, or apparatus.

[0025] Figure 1 Schematic diagram of the circuit structure of the power management circuit provided by the embodiment of the present invention Figure 1 . Figure 2 Schematic diagram of the circuit structure of the power management circuit provided by the embodiment of the present invention Figure 2 .

[0026] The power management circuit provided in this embodiment is used to manage and control the input power or input signal of the first external port Po1 and the second external port Po2.

[0027] Please refer to Figure 1 The power management circuit includes a power switching module 10 , an input detection module 20 , an input comparison module 40 , a drive control module 30 and a switch switching module 50 .

[0028] The power switching module 10 is configured to connect the second external port Po2 internally to the power output terminal RECT and the first external port Po1 internally to the power ground terminal GND when the first external port Po1 is externally connected to the ground. The power switching module 10 is further configured to connect the first external port Po1 internally to the power output terminal RECT and the second external port Po2 internally to the power ground terminal GND when the second external port Po2 is externally connected to the ground, so that regardless of whether the positive pole of the external input power source is connected to the first external port Po1 or the second external port Po2, the positive pole of the power source is connected to the power output terminal RECT inside the circuit and the ground pole is connected to the power ground terminal GND inside the circuit, thereby preventing the external input power from being reversely connected.

[0029] It should be noted that when the external input device is a power supply, if one external port is connected to the ground, the other end is connected to the positive pole of the power supply. This is common knowledge in the art and will not be elaborated here.

[0030] Please refer to Figure 1 and Figure 2 In this embodiment, the power switching module 10 includes a first switching PMOS transistor P1, a second switching PMOS transistor P2, a first switching NMOS transistor N1, a second switching NMOS transistor N2, a third switching NMOS transistor N3 and a fourth switching NMOS transistor N4.

[0031] The drain of the first switching PMOS transistor P1, the gate of the second switching PMOS transistor P2, and the source of the first switching NMOS transistor N1 are all connected to the second external port Po2, the drain of the second switching PMOS transistor P2, the gate of the first switching PMOS transistor P1, and the source of the second switching NMOS transistor N2 are all connected to the first external port Po1, and the drain of the first switching NMOS transistor N1, the drain of the second switching NMOS transistor N2, the source of the first switching PMOS transistor P1, and the source of the second switching PMOS transistor P2 are all connected to the power output terminal RECT.

[0032] The drain of the third switching NMOS transistor N3 and the gate of the fourth switching NMOS transistor N4 are both connected to the second external port Po2, the gate of the third switching NMOS transistor N3 and the drain of the fourth switching NMOS transistor N4 are both connected to the first external port Po1, and the source of the third switching NMOS transistor N3 and the source of the fourth switching NMOS transistor N4 are both connected to the power ground GND.

[0033] When the first external port Po1 is connected to the positive power supply and the second external port Po2 is connected to the ground, the power supply voltage at the first external port Po1 acts on the gate of the third switching NMOS transistor N3, turning on the third switching NMOS transistor N3 and internally connecting the second external port Po2 to the power ground GND. The ground voltage at the second external port Po2 acts on the gate of the second switching PMOS transistor P2, turning on the second switching PMOS transistor P2 and internally connecting the first external port Po1 to the power output terminal RECT. Furthermore, when the second switching PMOS transistor P2 is turned on and the external power supply voltage is less than the overvoltage value, the second switching NMOS transistor N2 is also turned on.

[0034] When the first external port Po1 is externally connected to the ground terminal and the second external port Po2 is externally connected to the positive power supply, the power supply voltage at the second external port Po2 acts on the gate of the fourth switching NMOS transistor N4, turning on the fourth switching NMOS transistor N4, thereby internally connecting the first external port Po1 to the power ground terminal GND. The ground voltage at the first external port Po1 acts on the gate of the first switching PMOS transistor P1, turning on the first switching PMOS transistor P1, thereby internally connecting the second external port Po2 to the power output terminal RECT. In addition, when the first switching PMOS transistor P1 is turned on and the external power supply voltage is less than the overvoltage value, the first switching NMOS transistor N1 is also turned on.

[0035] The principle of turning on the second switching NMOS transistor N2 and the first switching NMOS transistor N1 will be described later and will not be repeated here.

[0036] First, since the first switching PMOS transistor P1, the second switching PMOS transistor P2, the third switching NMOS transistor N3 and the fourth switching NMOS transistor N4 can be automatically turned on and off according to the external pins of the first external port Po1 and the second external port Po2, automatic reverse connection protection of the power input is achieved.

[0037] Furthermore, when the first switching NMOS transistor N1 or the second switching NMOS transistor N2 is turned on under the conditions met, its parallel connection with the first switching PMOS transistor P1 or the second switching PMOS transistor P2 significantly reduces the resistance in the power path, thereby significantly reducing transmission losses in the power path during current input. Furthermore, because the volume of an NMOS transistor is significantly smaller than that of a PMOS transistor at the same impedance, the impact of parallel NMOS transistors on circuit integration is extremely limited.

[0038] Finally, the first switching PMOS transistor P1 and the second switching PMOS transistor P2 can also be turned on when the external input device is a communication device, thereby enabling the normal operation of the power management circuit. At the same time, when the first switching PMOS transistor P1 or the second switching PMOS transistor P2 is turned on, the voltage difference between the first external port and the second external port is losslessly transmitted to the input detection module through the first switching PMOS transistor P1 or the second switching PMOS transistor P2, thereby improving the input detection module's detection accuracy of the voltage at the power output terminal.

[0039] For example, during communication, when the external input device transmits a logic-high signal, the voltage difference between the first external port Po1 and the second external port Po2 is 1.7V, and the first switching PMOS transistor P1 or the second switching PMOS transistor P2 is turned on. Unless the external input device inputs a logic-low signal, the first switching PMOS transistor P1 or the second switching PMOS transistor P2 is not turned on.

[0040] It should be noted that if the external input device is an external power supply, the voltage difference between the first external port Po1 and the second external port Po2 will be greater than 3.6V, so the first switching PMOS transistor P1 or the second switching PMOS transistor P2 will definitely be turned on.

[0041] Please continue to refer to Figure 1 and Figure 2 The input detection module 20 is used to output a first drive signal group when the voltage at the power output terminal RECT is less than or equal to the communication threshold voltage UOV.

[0042] The input comparison module 40 is configured to output a first comparison signal vc1 when a first voltage at the first external port Po1 is greater than a second voltage at the second external port Po2 ; and to output a second comparison signal vc2 when the first voltage is less than the second voltage.

[0043] The drive control module 30 is configured to output a first switching signal group according to the first drive signal group and the first comparison signal vc1 . The drive control module 30 is also configured to output a second switching signal group according to the first drive signal group and the second comparison signal vc2 .

[0044] The switch switching module 50 is configured to internally connect the first external port Po1 to the signal communication terminal COMM and internally connect the second external port Po2 to the power ground terminal GND according to the first switch signal group. The switch switching module 50 is further configured to internally connect the second external port Po2 to the signal communication terminal COMM and internally connect the first external port Po1 to the power ground terminal GND according to the second switch signal group.

[0045] The first drive signal group output by the input detection module 20 is used to indicate that the external device is a communication device. Therefore, the drive control module 30 will output different switch signal groups based on the comparison signal output by the input comparison module 40 to control the switch switching module 50 to connect the first external port Po1 or the second external port Po2 to the signal communication terminal COMM of the back-end circuit to establish a communication connection between the back-end circuit and the external communication device. Since the comparison signal is used to represent the voltage level of the first external port Po1 and the second external port Po2, the switch switching module 50 will connect the external port with a larger port voltage to the signal communication terminal COMM and the external port with a smaller port voltage to the power ground terminal GND based on different switch signal groups, thereby achieving anti-reverse connection of the communication input.

[0046] Of course, in addition to detecting whether the external input device is a communication device, the input detection module 20 can also detect whether the external input device is a power supply device and whether the power input is overvoltage. Please continue to refer to Figure 1 and Figure 2 In this embodiment, the input detection module 20 is further configured to output a second drive signal group when the voltage at the power output terminal RECT is greater than or equal to an overvoltage threshold voltage OV. The overvoltage threshold voltage OV is greater than the communication threshold voltage UOV. The overvoltage threshold voltage OV indicates that the external input voltage exceeds the upper voltage limit of the back-end circuit, and therefore, the voltage at the power output terminal RECT needs to be isolated. For example, the overvoltage threshold voltage OV is 5.5V, and the communication threshold voltage UOV is 3.6V.

[0047] It can be understood that, while 3.6V was originally used as the undervoltage threshold for the external power input, this embodiment uses 3.6V not only as the undervoltage threshold for the external power input, but also as the overvoltage threshold for the external signal input. Therefore, 3.6V serves as the critical threshold for the power management circuit to determine the external power input and external communication input. Of course, the overvoltage threshold voltage OV and the communication threshold voltage UOV can be adjusted according to actual applications and are not limited here.

[0048] The input detection module 20 is further configured to output a third drive signal group when the voltage at the power output terminal RECT is less than the overvoltage threshold voltage OV and greater than the communication threshold voltage UOV, indicating that the external input voltage is within the withstand voltage range of the back-end circuit and is used to charge the back-end circuit.

[0049] Please continue to refer to Figure 1 and Figure 2In this embodiment, the input detection module 20 includes: a first voltage-dividing resistor R1, a second voltage-dividing resistor R2, a second comparator D2, and a third comparator D3.

[0050] A first end of the first voltage-dividing resistor R1 is connected to the power output terminal RECT, and a second end of the first voltage-dividing resistor R1 is respectively connected to the non-inverting input terminal of the second comparator D2, the non-inverting input terminal of the third comparator D3, and the first end of the second voltage-dividing resistor R2. A second end of the second voltage-dividing resistor R2 is connected to the power ground terminal GND.

[0051] The inverting input of the second comparator D2 is connected to the overvoltage threshold voltage OV; the inverting input of the third comparator D3 is connected to the communication threshold voltage UOV, and the output of the second comparator D2 and the output of the third comparator D3 are both connected to the drive control module 30.

[0052] Based on the structure of the above-mentioned input detection module 20 , the high level output by the second comparator D2 and the high level output by the third comparator D3 constitute the second driving signal group.

[0053] The low level output by the second comparator D2 and the high level output by the third comparator D3 constitute the third driving signal group.

[0054] The low level output by the second comparator D2 and the low level output by the third comparator D3 constitute the first driving signal group.

[0055] Please continue to refer to Figure 1 and Figure 2 In this embodiment, the power management circuit further includes a power channel NMOS tube, the drain of the power channel NMOS tube is connected to the power output terminal RECT, and the source of the power channel NMOS tube is connected to the power terminal of the back-end circuit.

[0056] The drive control module 30 is further configured to output a first drive voltage G3, a second drive voltage G2, and a third drive voltage G1, respectively, based on the second drive signal group. The first drive voltage G3 acts on the gate of the power channel NMOS transistor to shut down the power channel NMOS transistor, thereby isolating the power output terminal RECT from the back-end circuit to provide overvoltage protection for the back-end circuit. The second drive voltage G2 and the third drive voltage G1 act on the gate of the second switching NMOS transistor N2 and the gate of the first switching NMOS transistor N1, respectively, to shut down the gates of the second switching NMOS transistor N2 and the first switching NMOS transistor N1.

[0057] The drive control module 30 is further configured to output a fourth drive voltage G3, a fifth drive voltage G2, and a sixth drive voltage G1, respectively, based on the third drive signal group and the first comparison signal vc1. The fourth drive voltage G3 is applied to the gate of the power channel NMOS transistor to turn on the power channel NMOS transistor. The fifth drive voltage G2 is applied to the gate of the second switching NMOS transistor N2 to turn on the second switching NMOS transistor N2. The sixth drive voltage G1 is applied to the gate of the first switching NMOS transistor N1 to turn off the first switching NMOS transistor N1.

[0058] The drive control module 30 is further configured to output a fourth drive voltage G3, a seventh drive voltage G2, and an eighth drive voltage G1, respectively, based on the third drive signal group and the second comparison signal vc2. The fourth drive voltage G3 is applied to the gate of the power channel NMOS transistor to turn on the power channel NMOS transistor. The seventh drive voltage G2 is applied to the gate of the second switching NMOS transistor N2 to turn off the second switching NMOS transistor N2. The eighth drive voltage G1 is applied to the gate of the first switching NMOS transistor N1 to turn on the first switching NMOS transistor N1.

[0059] It should be noted that the drive control module 30 is also used to output the first drive voltage G3, the second drive voltage G2 and the third drive voltage G1 respectively according to the first drive signal group, so as to turn off the power channel NMOS tube, the first switching NMOS tube N1 and the second switching NMOS tube N2 respectively when the external input device is a communication device.

[0060] Please continue to refer to Figure 1 and Figure 2 In this embodiment, the driving control module 30 includes a control unit 31 and a charge pump 32 .

[0061] The control unit 31 is configured to output a first switching signal group according to the first drive signal group and the first comparison signal vc1. The control unit 31 is also configured to output a second switching signal group according to the first drive signal group and the second comparison signal vc2.

[0062] The charge pump 32 is configured to output the first drive voltage G3, the second drive voltage G1, and the third drive voltage G2 based on the first drive signal group and the second drive signal group. The charge pump 32 is further configured to output the fourth drive voltage G3, the fifth drive voltage G2, and the sixth drive voltage G1 based on the third drive signal group and the first comparison signal vc1. The charge pump 32 is further configured to output the fourth drive voltage G3, the seventh drive voltage G2, and the eighth drive voltage G1 based on the third drive signal group and the second comparison signal vc2.

[0063] When the external input device is a communication device, the voltage difference between the first external port Po1 and the second external port Po2 is less than 3.6V, so the input detection module 20 outputs the first drive signal group to the control unit 31 and the charge pump 32. The control unit 31 outputs a corresponding switch signal group based on the first drive signal group according to the comparison signal input by the input comparison module 40.

[0064] When the external input device is a power supply device but the input voltage exceeds the overvoltage threshold voltage OV, the input detection module 20 outputs a second drive signal group to the control unit 31 and the charge pump 32 .

[0065] The charge pump 32 outputs the first drive voltage G3, the second drive voltage G1, and the third drive voltage G2 based on the second drive signal group and the first drive signal group. After the charge pump 32 turns off the first switching NMOS transistor N1, the second switching NMOS transistor N2, and the power channel NMOS transistor, the control unit 31 disables the charge pump 32, thereby reducing the power consumption of the drive control module 30, and further reducing the circuit power consumption in communication mode and the circuit power consumption when the circuit is overvoltage.

[0066] When the external input device is a power supply device and the input voltage is between the communication threshold voltage UOV and the overvoltage threshold voltage OV, the input detection module 20 outputs a third drive signal group to the control unit 31 and the charge pump 32. The charge pump 32 outputs a corresponding drive voltage to the first switching NMOS tube N1, the second switching NMOS tube N2 and the power channel NMOS tube according to the corresponding comparator signal based on the third drive signal group, so as to turn on the power channel NMOS tube, the first switching NMOS tube N1 or the second switching NMOS tube N2.

[0067] Furthermore, taking the example of the first external port Po1 being connected to the positive power supply, the second switching PMOS transistor P2 is turned on by the ground terminal connected to the second external port Po2, and the power supply voltage at the positive power supply terminal is input to the charge pump 32. Based on the power supply voltage, the charge pump 32 outputs the fifth drive voltage G2, which is greater than the power supply voltage, to the gate of the second switching NMOS transistor N2, thereby turning on the second switching NMOS transistor N2. The driving principle of the first switching NMOS transistor N1 when the second external port Po2 is connected to the positive power supply terminal is the same as when the first external port Po1 is connected to the positive power supply terminal, and is not further described here.

[0068] Please continue to refer to Figure 1 and Figure 2 In this embodiment, the switch switching module 50 includes a first switch SW1 and a second switch SW2.

[0069] The first end A1 of the first switch SW1 is connected to the first external port Po1, the second end A2 of the first switch SW1 is connected to the signal communication end COMM, and the third end A3 of the first switch SW1 is connected to the power ground end GND. The first switch SW1 controls its first end A1 to connect to its second end A2 according to the first switch signal group. The first switch SW1 also controls its first end A1 to connect to its third end A3 according to the second switch signal group.

[0070] The first end B1 of the second switch SW2 is connected to the second external port Po2, the second end B2 of the second switch SW2 is connected to the signal communication end COMM, and the third end B3 of the second switch SW2 is connected to the power ground end GND. The second switch SW2 controls its first end B1 to connect to its third end B3 according to the first switch signal group. The second switch SW2 also controls its first end B1 to connect to its second end B2 according to the second switch signal group.

[0071] It should be supplemented that the control unit 31 further outputs a third switch signal group to the first switch SW1 and the second switch SW2 according to the second drive signal group and the third drive signal group.

[0072] Specifically, the first switch signal group, the second switch signal group, and the third switch signal group are all composed of a first enable signal E1, a second enable signal E2, a first switching signal S1, and a second switching signal S2.

[0073] In the first switch signal group, the first enable signal E1 and the second enable signal E2 are both at a high level, so that the first switch SW1 and the second switch SW2 both operate normally. The first switching signal S1 acts on the first switch SW1, and the first switching signal S1 is at a low level, so that the first end A1 of the first switch SW1 is connected to its second end A2. The second switching signal S2 acts on the second switch SW2, and the second switching signal S2 is at a low level, so that the first end B1 of the second switch SW2 is connected to its third end B3. It can be understood that the first external port Po1 is externally connected to a logic high level, and the second external port Po2 is externally connected to the reference ground terminal, so that the first external port Po1 is internally connected to the signal communication terminal COMM, and the second external port Po2 is internally connected to the power ground terminal GND.

[0074] In the second switch signal group, the first enable signal E1 and the second enable signal E2 are both at a high level, so that the first switch SW1 and the second switch SW2 both operate normally. The first switching signal S1 acts on the first switch SW1, and the first switching signal S1 is at a high level, so that the first terminal A1 of the first switch SW1 is connected to its third terminal A3. The second switching signal S2 acts on the second switch SW2, and the second switching signal S2 is at a high level, so that the first terminal B1 of the second switch SW2 is connected to its second terminal B2. It can be understood that the second external port Po2 is externally connected to a logic high level, and the first external port Po1 is externally connected to the reference ground terminal, so that the second external port Po2 is internally connected to the signal communication terminal COMM, and the first external port Po1 is internally connected to the power ground terminal GND.

[0075] Therefore, no matter whether the first external port Po1 is connected to a logic high level or the second external port Po2 is connected to a logic high level, it can ensure that the logic high level is internally connected to the signal communication terminal COMM, thereby achieving communication between the external communication device and the back-end circuit regardless of whether the external input signal is connected positively or reversely.

[0076] In the third switch signal group, both the first enable signal E1 and the second enable signal E2 are at a low level. In this case, regardless of whether the first switching signal S1 and the second switching signal S2 are at a high level, the first switch SW1 and the second switch SW2 are both disabled. This indicates that the external input device is a power supply used to charge the back-end circuitry rather than for communication. Therefore, the first switch SW1 and the second switch SW2 are disabled to prevent damage to low-voltage communication components in the back-end circuitry.

[0077] Please continue to refer to Figure 1 and Figure 2 In this embodiment, the power management circuit further includes a linear voltage regulator module 60, a unidirectional conducting PMOS transistor P3, a power supply capacitor C1 and a first comparator D1.

[0078] The linear voltage stabilization module 60 is used to convert the voltage at the power output terminal RECT into a power supply voltage VREG and output the converted voltage. Specifically, the linear voltage stabilization module 60 includes a linear voltage stabilizer.

[0079] The drain of the unidirectional conducting PMOS transistor P3 is connected to the output end of the linear voltage regulator module 60 , and the source of the unidirectional conducting PMOS transistor P3 is connected to the power supply voltage end VDD.

[0080] The non-inverting input of the first comparator D1 is connected to the source of the unidirectional conducting PMOS transistor P3 , the inverting input of the first comparator D1 is connected to the drain of the unidirectional conducting PMOS transistor P3 , and the output of the first comparator D1 is connected to the gate of the unidirectional conducting PMOS transistor P3 .

[0081] A first end of the power supply capacitor C1 is also connected to the power supply voltage terminal VDD, and a second end of the power supply capacitor C1 is connected to the power ground terminal GND.

[0082] The linear voltage regulator module 60 converts the voltage at the power output terminal RECT into a supply voltage VREG and outputs it. When the supply voltage VREG is greater than the voltage at the supply voltage terminal VDD, the first comparator D1 outputs a low level to the gate of the unidirectional conduction PMOS transistor P3, turning on the unidirectional conduction PMOS transistor P3 and indirectly powering the various devices via the voltage at the first external port Po1 or the second external port Po2. Simultaneously, while powering the various devices, the supply voltage VREG also charges the power supply capacitor C1. When the supply voltage VREG is less than the voltage at the supply voltage terminal VDD, the first comparator D1 outputs a high level to the gate of the unidirectional conduction PMOS transistor P3, turning off the unidirectional conduction PMOS transistor P3 to prevent the voltage at the supply voltage terminal VDD from flowing back into the linear voltage regulator module 60 and powering the various devices via the power supply capacitor C1.

[0083] When the external input device is a power supply, regardless of whether the positive power supply terminal of the external input device is connected to the first external port Po1 or the second external port Po2, the power supply voltage is input to the linear voltage regulator module 60. The linear voltage regulator module 60 converts the power supply voltage into a low voltage suitable for power supply, namely the supply voltage VREG. Since the supply voltage VREG is greater than the voltage at the supply voltage terminal VDD, the first comparator D1 outputs a low level to the gate of the unidirectional conduction PMOS transistor P3, thereby turning on the unidirectional conduction PMOS transistor P3. While the supply voltage VREG provides power to the various functional modules in the circuit, it also charges the power supply capacitor C1 until the voltage at the supply voltage terminal VDD and the supply voltage VREG are substantially equal.

[0084] When the external input device is a communication device, the voltage difference between the first external port Po1 and the second external port Po2 when transmitting a logic zero signal will be significantly lower than the power supply voltage VREG generated when the external input communication device transmits a logic high signal. For example, when the external input communication device transmits a logic high signal, the voltage difference between the first external port Po1 and the second external port Po2 is 3.3V. This 3.3V will charge C1, so the voltage at the power supply voltage terminal VDD is equal to or close to the voltage given to V when the external input communication device transmits a logic high level. The voltage of REG is 3.3V. When the external input communication device transmits a logic-zero signal, the voltage difference between the first external port Po1 and the second external port Po2 is 0V. Therefore, the supply voltage VREG output by the linear voltage regulator module 60 is 0V, which is lower than the voltage at the supply voltage terminal VDD, which is 3.3V or close to 3.3V. The first comparator D1 outputs a high level to the unidirectional PMOS transistor P3, shutting off the unidirectional PMOS transistor P3 and preventing the linear voltage regulator module 60 from releasing the energy stored in the power supply capacitor C1. Transmitting a logic-high signal charges C1, while transmitting a logic-zero signal prevents C1 from discharging energy in the VREG direction. This cycle repeats based on the logic high and low of the communication signal. Therefore, when the external input device is a communication device, no power is required from the system (e.g., an internal battery), further reducing system power consumption when the circuit enters communication mode.

[0085] Of course, the above power supply circuit is only a specific implementation method, and each functional module can also be powered by an internal power supply, which is not limited here.

[0086] Please continue to refer to Figure 1 and Figure 2In this embodiment, the input comparison module 40 includes a fourth comparator D4. The inverting input of the fourth comparator D4 is connected to the first external port Po1, the non-inverting input of the fourth comparator D4 is connected to the second external port Po2, and the output of the fourth comparator D4 is connected to the drive control module 30. The hysteresis voltage of the fourth comparator D4 is greater than or equal to 300mV, thereby ensuring that when the external input device is a communication device, the output of the fourth comparator D4 remains unchanged when the input signal transitions from a logic high level to a logic low level. For example, when the first external port Po1 is connected to a logic high level and the second external port Po2 is connected to a reference ground, the fourth comparator D4 outputs a low level, i.e., the first comparison signal vc1. When the logic low level jumps to a logic low level, the hysteresis voltage of the fourth comparator D4 ensures that the fourth comparator D4 still outputs a low level until the first external port Po1 is externally connected to the reference ground terminal and the second external port Po2 is externally connected to a logic high level. Then, the fourth comparator D4 outputs a high level, i.e., the second comparison signal vc2.

[0087] In addition to being output to the drive control module 30 , the output signal of the fourth comparator D4 may also be output to a system processor in the circuit, so that the system can know whether the external input device is reversely connected.

[0088] In summary, the power management circuit provided in this embodiment and the power switching module enable the positive pole of the external input power supply to be connected to the power output terminal inside the circuit and the ground terminal to be connected to the power ground terminal inside the circuit regardless of whether the positive pole of the power supply is connected to the first external port or the second external port, thereby preventing the external input power from being reversely connected.

[0089] When the input detection module detects that the voltage at the power output terminal is less than or equal to the communication threshold voltage, the input detection module outputs a first drive signal group to the drive control module. Based on the comparison signal output by the comparison module, the drive control module outputs different switch signal groups to control the switch switching module to internally connect the first external port or the second external port to the signal communication terminal of the back-end circuit, thereby establishing a communication connection between the back-end circuit and the external communication device, and simultaneously preventing reverse connection of the communication input.

[0090] Furthermore, when the first switching NMOS transistor N1 or the second switching NMOS transistor N2 is turned on under the conditions met, its parallel connection with the first switching PMOS transistor P1 or the second switching PMOS transistor P2 significantly reduces the resistance of the power path, thereby significantly reducing the transmission loss of the power path during current input. Furthermore, because the volume of an NMOS transistor is significantly smaller than that of a PMOS transistor at the same impedance, the impact of parallel NMOS transistors on circuit integration is extremely limited.

[0091] In addition, the first switching PMOS tube, the second switching PMOS tube, the third switching NMOS tube and the fourth switching NMOS tube can all be automatically turned on and off according to the external pins of the first external port and the second external port, thereby realizing automatic anti-reverse connection of the power input.

[0092] Finally, the first switching PMOS transistor and the second switching PMOS transistor can also be turned on when the external input device is a communication device, thereby enabling the normal operation of the power management circuit. Furthermore, when the first switching PMOS transistor or the second switching PMOS transistor is turned on, the voltage difference between the first external port and the second external port is losslessly transmitted to the input detection module via the first switching PMOS transistor or the second switching PMOS transistor, thereby improving the input detection module's detection accuracy of the voltage at the power output terminal.

[0093] Furthermore, when the external input device is a communication device, there is no need to draw power from the system (such as an internal battery) through the linear voltage regulator module, the first comparator, the unidirectional conduction PMOS tube and the power supply capacitor, thereby further reducing the system power consumption when the circuit enters the communication mode.

[0094] An embodiment of the present invention further provides a circuit system including the power management circuit.

[0095] An embodiment of the present invention further provides a wearable device including the circuit system.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power management circuit, characterized in that: include: A power switching module, the power switching module being configured to: if the first external port is externally connected to the ground terminal, connect the second external port internally to the power output terminal, and connect the first external port internally to the power ground terminal; if the second external port is externally connected to the ground terminal, connect the first external port internally to the power output terminal, and connect the second external port internally to the power ground terminal; an input detection module, configured to output a first drive signal group when a voltage at the power output terminal is less than or equal to a communication threshold voltage; an input comparison module, configured to output a first comparison signal if a first voltage at the first external port is greater than a second voltage at the second external port; and output a second comparison signal if the first voltage is less than the second voltage; a drive control module, configured to: output a first switch signal group according to the first drive signal group and a first comparison signal; or output a second switch signal group according to the first drive signal group and a second comparison signal; A switch switching module, the switch switching module is used to: connect the first external port internally to the signal communication terminal and connect the second external port internally to the power ground terminal according to the first switch signal group; or connect the second external port internally to the signal communication terminal and connect the first external port internally to the power ground terminal according to the second switch signal group.

2. The power management circuit according to claim 1, wherein: The switch switching module includes a first switch and a second switch; A first end of the first switch is connected to the first external port, a second end of the first switch is connected to the signal communication end, and a third end of the first switch is connected to the power ground end. The first switch controls the connection between its first end and its second end according to the first switch signal group, and further controls the connection between its first end and its third end according to the second switch signal group. The first end of the second switch is connected to the second external port, the second end of the second switch is connected to the signal communication end, and the third end of the second switch is connected to the power ground end. The second switch controls its first end to connect to its third end according to the first switch signal group, and the second switch also controls its first end to connect to its second end according to the second switch signal group.

3. The power management circuit according to claim 1, wherein: The power switching module includes a first switching PMOS transistor, a second switching PMOS transistor, a first switching NMOS transistor, a second switching NMOS transistor, a third switching NMOS transistor and a fourth switching NMOS transistor; The drain of the first switching PMOS transistor, the gate of the second switching PMOS transistor, and the source of the first switching NMOS transistor are all connected to the second external port, the drain of the second switching PMOS transistor, the gate of the first switching PMOS transistor, and the source of the second switching NMOS transistor are all connected to the first external port, and the drain of the first switching NMOS transistor, the drain of the second switching NMOS transistor, the source of the first switching PMOS transistor, and the source of the second switching PMOS transistor are all connected to the power output terminal; The drain of the third switching NMOS tube and the gate of the fourth switching NMOS tube are both connected to the second external port, the gate of the third switching NMOS tube and the drain of the fourth switching NMOS tube are both connected to the first external port, and the source of the third switching NMOS tube and the source of the fourth switching NMOS tube are both connected to the power ground.

4. The power management circuit according to claim 1 or 3, characterized in that: The power management circuit further includes a linear voltage regulator module, a unidirectional conducting PMOS tube, a power supply capacitor and a first comparator; The linear voltage stabilization module is used to convert the voltage at the power output end into a supply voltage and output the voltage; The drain of the unidirectional conducting PMOS tube is connected to the output end of the linear voltage regulator module, and the source of the unidirectional conducting PMOS tube is connected to the power supply voltage end; The non-inverting input terminal of the first comparator is connected to the source of the unidirectional conducting PMOS transistor, the inverting input terminal of the first comparator is connected to the drain of the unidirectional conducting PMOS transistor, and the output terminal of the first comparator is connected to the gate of the unidirectional conducting PMOS transistor; The first end of the power supply capacitor is also connected to the power supply voltage end, and the second end of the power supply capacitor is connected to the power ground end.

5. The power management circuit according to claim 3, wherein: The power management circuit further includes a power channel NMOS transistor, the drain of the power channel NMOS transistor is connected to the power output terminal, and the source of the power channel NMOS transistor is connected to the power terminal of the back-end circuit; The input detection module is further configured to: output a second drive signal group if the voltage at the power output terminal is greater than or equal to an overvoltage threshold voltage, and the overvoltage threshold voltage is greater than the communication threshold voltage; and output a third drive signal group if the voltage at the power output terminal is less than the overvoltage threshold voltage and greater than the communication threshold voltage; The drive control module is further configured to: output a first drive voltage to the gate of the power channel NMOS transistor according to the second drive signal group to turn off the power channel NMOS transistor; further outputting a second driving voltage and a third driving voltage to the gate of the first switching NMOS transistor and the gate of the second switching NMOS transistor, respectively, to turn off the gate of the first switching NMOS transistor and the gate of the second switching NMOS transistor; or outputting a fourth driving voltage to the gate of the power channel NMOS transistor based on the third driving signal group and the first comparison signal, to turn on the power channel NMOS transistor; outputting a fifth driving voltage to the gate of the second switching NMOS transistor to turn on the second switching NMOS transistor; outputting a sixth driving voltage to the gate of the first switching NMOS transistor to turn off the first switching NMOS transistor; or outputting a fourth driving voltage to the gate of the power channel NMOS transistor to turn on the power channel NMOS transistor based on the third driving signal group and the second comparison signal; outputting a seventh driving voltage to the gate of the second switching NMOS transistor to turn off the second switching NMOS transistor; An eighth driving voltage is output to the gate of the first switching NMOS transistor to turn on the first switching NMOS transistor.

6. The power management circuit according to claim 5, characterized in that: The input detection module includes: a first voltage-dividing resistor, a second voltage-dividing resistor, a second comparator, and a third comparator; A first end of the first voltage-dividing resistor is connected to the power supply output end, and a second end of the first voltage-dividing resistor is respectively connected to the non-inverting input end of the second comparator, the non-inverting input end of the third comparator, and the first end of the second voltage-dividing resistor; The second end of the second voltage-dividing resistor is connected to the power ground; The inverting input terminal of the second comparator is connected to the overvoltage threshold voltage, and the output terminal of the second comparator is connected to the drive control module; the inverting input terminal of the third comparator is connected to the communication threshold voltage, and the output terminal of the third comparator is connected to the drive control module; The high level output by the second comparator and the high level output by the third comparator constitute the second driving signal group; The low level output by the second comparator and the high level output by the third comparator constitute the third driving signal group; The low level output by the second comparator and the low level output by the third comparator constitute the first driving signal group.

7. The power management circuit according to claim 5, wherein: The drive control module includes a control unit and a charge pump; The control unit is configured to: output a first switching signal group according to the first drive signal group and the first comparison signal; or output a second switching signal group according to the first drive signal group and the second comparison signal; The charge pump is configured to: output the first drive voltage, the second drive voltage, and the third drive voltage according to the first drive signal group and the second drive signal group; or output the fourth drive voltage, the fifth drive voltage, and the sixth drive voltage according to the third drive signal group and the first comparison signal; Alternatively, the fourth driving voltage, the seventh driving voltage, and the eighth driving voltage are output according to the third driving signal group and the second comparison signal.

8. The power management circuit according to claim 1, wherein: The input comparator module includes a fourth comparator, an inverting input end of the fourth comparator is connected to the first external port, a non-inverting input end of the fourth comparator is connected to the second external port, and an output end of the fourth comparator is connected to the drive control module.

9. The power management circuit according to claim 8, wherein: The hysteresis voltage of the fourth comparator is greater than or equal to 300 mV.

10. A circuit system, characterized in that: The power management circuit comprises the power management circuit according to any one of claims 1 to 9.

11. A wearable device, characterized in that: A circuit system comprising the circuit system of claim 10.

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