Seven-level inverter and modulation method thereof

Abstract

This invention discloses a seven-level inverter and its modulation method. The seven-level inverter includes: first to third DC voltage sources with the same voltage at the load end; a first switch between the positive terminal of the second DC voltage source and the negative terminal of the third DC voltage source; a second switch between the positive terminal of the first DC voltage source and the negative terminal of the second DC voltage source; a third switch between the positive terminal of the third DC voltage source and the negative terminal of the first DC voltage source; a fourth switch between the positive terminal of the third DC voltage source and the positive terminal of the load end; a fifth switch between the positive terminal of the first DC voltage source and the negative terminal of the load end; a sixth switch between the negative terminal of the second DC voltage source and the positive terminal of the load end; and a seventh switch between the negative terminal of the first DC voltage source and the negative terminal of the load end. By configuring the switching on and off states of the switches under different voltage levels, the number of switches is reduced while ensuring multi-level output and stable operation of the inverter. Using a low-frequency modulation method can ensure excellent characteristics of the inverter's output voltage and reduce switching losses.

Description

Technical Field

[0001] This invention relates to a seven-level inverter and its modulation method, belonging to the field of power electronics application technology. Background Technology

[0002] Multilevel inverters are widely used in many fields due to their advantages such as flexible control, low switching stress, and high output voltage waveform quality, especially in the field of new energy where they have great development prospects.

[0003] The inverter topology directly affects the output voltage waveform quality and system performance. In the field of multilevel inverters, mainstream topologies have significant technical bottlenecks: NPC (Neutral Point Clamped) topologies suffer from structural complexity and topology scalability limitations, facing challenges in DC capacitor voltage equalization; FC (Flying Capacitor) topologies require multiple energy storage capacitors, while also facing difficulties in voltage equalization control and increased costs due to additional pre-charging circuits; CHB (Cascaded H-Bridge) architectures suffer from device redundancy, significantly increasing system losses and size. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a seven-level inverter and its modulation method, which reduces the number of switching transistors while avoiding the use of switching capacitors.

[0005] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0006] A seven-level inverter includes: a load terminal on the AC side and a first to a third DC voltage source on the DC side, wherein the voltages of the first, second and third DC voltage sources are equal.

[0007] The seven-level inverter further includes: first to seventh switching transistors; the source of the first switching transistor is connected to the negative terminal of the third DC voltage source, and the drain is connected to the positive terminal of the second DC voltage source; the source of the second switching transistor is connected to the negative terminal of the second DC voltage source, and the drain is connected to the positive terminal of the first DC voltage source; the source of the third switching transistor is connected to the negative terminal of the first DC voltage source, and the drain is connected to the positive terminal of the third DC voltage source; the source of the fourth switching transistor is connected to the positive terminal of the load, and the drain is connected to the positive terminal of the third DC voltage source; the source of the fifth switching transistor is connected to the negative terminal of the load, and the drain is connected to the positive terminal of the first DC voltage source; the source of the sixth switching transistor is connected to the negative terminal of the second DC voltage source, and the drain is connected to the positive terminal of the load; the source of the seventh switching transistor is connected to the negative terminal of the first DC voltage source, and the drain is connected to the negative terminal of the load.

[0008] Compared with the prior art, the present invention, employing the above technical solution, has the following technical effects:

[0009] 1. This invention simplifies the topology by optimizing the inverter design, while ensuring circuit stability and output voltage quality, reducing the number of switching transistors and avoiding the use of switching capacitors.

[0010] 2. The present invention uses a low-frequency modulation method, which can ensure the excellent characteristics of the inverter output voltage and reduce switching losses. Attached Figure Description

[0011] Figure 1 This is a circuit topology diagram of the seven-level inverter of the present invention;

[0012] Figure 2 These are the operating mode diagrams of the seven-level inverter of the present invention under different output levels, wherein the output levels corresponding to (a)-(h) are +3E, +2E, +E, 0, 0, -E, -2E and -3E, respectively;

[0013] Figure 3 This is a schematic diagram showing the relationship between the switch conduction angle and the output level in the inverter modulation method.

[0014] Figure 4(a) is a waveform diagram of the load voltage and current at the inverter output terminal, Figure 4(b) is a spectrum diagram of the load voltage, and Figure 4(c) is a spectrum diagram of the load current.

[0015] Figure 5 This is a dynamic performance diagram of the inverter output. Detailed Implementation

[0016] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0017] like Figure 1 As shown, this invention proposes a seven-level inverter, comprising: an AC-side load output, three DC-side inputs of equal voltage sources E1, E2, and E3 (E1 = E2 = E3 = E), and seven switching transistors; the positive terminal of DC voltage source E2 is connected to the negative terminal of E3 via switching transistor S1, the positive terminal of DC voltage source E1 is connected to the negative terminal of E2 via switching transistor S2, the positive terminal of DC voltage source E3 is connected to the negative terminal of E1 via switching transistor S3, the positive terminal of DC voltage source E3 is connected to the positive terminal of the load via switching transistor S4, the positive terminal of DC voltage source E1 is connected to the negative terminal of the load via switching transistor S5, the negative terminal of DC voltage source E2 is connected to the positive terminal of the load via switching transistor S6, and the negative terminal of DC voltage source E1 is connected to the negative terminal of the load via switching transistor S7. Switches S1, S2, S3, S4, S5, S6, and S7 are all insulated-gate bipolar transistors (IGBTs).

[0018] like Figure 2As shown in (a)-(h), by controlling the on / off state of the switching transistor, three different power supply combinations—E1, E2+E3, and E1+E2+E3—can be achieved, resulting in seven different output levels at the load terminal: 0, ±E, ±2E, and ±3E. The switching state also differs for different output levels, as shown in Table 1.

[0019] Table 1

[0020]

[0021]

[0022] In the table, 1 indicates that the switch is on and 0 indicates that the switch is off.

[0023] The inverter output voltage is modulated using SHEPWM low-frequency modulation technology to eliminate specified harmonics; the seven-point flat inverter topology has 3 degrees of freedom, and 2 specified harmonics can be eliminated by establishing 3 nonlinear equations, usually prioritizing the elimination of the 5th and 7th harmonics;

[0024] In modulation methods, the expression for the modulated wave is:

[0025]

[0026] In the formula, V r The signal is a modulated wave, where ω is the fundamental angular frequency and t is the time variable. The initial phase angle;

[0027] The three switching angles are determined using three nonlinear equations:

[0028]

[0029] In the formula, α1, α2, and α3 are three switch conduction angles, expressed in radians, and 0 < α1 ≤ α2 ≤ α3 < π / 2, M a For the modulation scheme, i and j represent the i-th and j-th harmonics to be eliminated, respectively, and both i and j are odd numbers greater than 1;

[0030] Six comparison potentials are determined based on three switch conduction angles:

[0031]

[0032] In the formula, +V1 and -V1 represent the first set of comparison potentials with opposite values, +V2 and -V2 represent the second set of comparison potentials with opposite values, and +V3 and -V3 represent the third set of comparison potentials with opposite values.

[0033] When V r When >+V3, U o=3E, the control signals of switching transistors S1, S2, S4, and S7 are high level, and the control signals of switching transistors S3, S5, and S6 are low level;

[0034] When V r When <-V3, U o =-3E, the control signals of switching transistors S1, S3, S5, and S6 are high level, and the control signals of switching transistors S2, S4, and S7 are low level;

[0035] When +V2 < V r When ≤+V3, U o =2E, the control signals of switching transistors S1, S2, S4, and S5 are high level, and the control signals of switching transistors S3, S6, and S7 are low level;

[0036] When -V3≤V r When <-V2, U o =-2E, the control signals of switching transistors S1, S3, S6, and S7 are high level, and the control signals of switching transistors S2, S4, and S5 are low level;

[0037] When +V1 < V r When ≤+V2, U o =E, the control signals of switching transistors S2, S6, and S7 are high level, and the control signals of switching transistors S1, S3, S4, and S5 are low level;

[0038] When -V2≤V r When <-V1, U o =-E, the control signals of switching transistors S3, S4, and S5 are high level, and the control signals of switching transistors S1, S2, S6, and S7 are low level;

[0039] When -V1≤V r ≤+V1, and V r When the value of U decreases o In the first zero-level state, the control signals of switches S2, S5, and S6 are high, and the control signals of switches S1, S3, S4, and S7 are low.

[0040] When -V1≤V r ≤+V1, and V r As the value of U increases, o In the second zero-level state, the control signals of switches S3, S4, and S7 are high, while the control signals of switches S1, S2, S5, and S6 are low.

[0041] Based on the above modulation method, the output voltage U o It will exhibit a stepped wave shape, and its relationship with the three switch conduction angles α1, α2, and α3 is as follows: Figure 3 As shown.

[0042] Example

[0043] The seven-level inverter was simulated in MATLAB / Simulink, with the DC voltage source in the simulation model set to 12V. For the operating state of the seven-level inverter, the system load resistance was set to 10Ω and the load inductance to 5mH. The modulation method adopted was the low-frequency modulation technique SHEPWM, with a modulation frequency of 50Hz. In this embodiment, the 5th and 7th harmonics in the output voltage were eliminated.

[0044] Figures 4(a)-4(c) The steady-state performance of the inverter is demonstrated. When the modulation index is 1, the three switching angles are obtained by solving the nonlinear equations: α1 = 0.2039°, α2 = 0.5442°, and α3 = 1.0224°. Figure 4(a) shows the waveforms of the load voltage and current at the inverter output terminal under this modulation parameter, Figure 4(b) shows the spectrum of the load voltage, and Figure 4(c) shows the spectrum of the load current. It can be seen that the inverter output voltage is a symmetrical seven-level stepped wave, realizing the basic function of this topology; the voltage spectrum does not contain the 5th and 7th harmonics, and the fundamental component amplitude of the output voltage is approximately 36V, consistent with the theoretical analysis; the load inductor acts as a filter, reducing the harmonic distortion rate of the load current.

[0045] Figure 5 The dynamic performance of the inverter's output voltage and current at the load side is demonstrated. Between 0s and 0.05s, the modulation index is 0.6, the modulation frequency is 50Hz, the load resistance is 130Ω, and the load inductance is 5mH. At the end of 0.05s, a load transition occurs, so between 0.05s and 0.1s, the modulation index remains at 0.6, the modulation frequency remains at 50Hz, the load resistance becomes 30Ω, and the load inductance becomes 5.5mH. At the end of 0.1s, another modulation index transition occurs, so between 0.1s and 0.15s, the modulation index becomes 1, the modulation frequency remains at 50Hz, the load resistance remains at 30Ω, and the load inductance remains at 5.5mH. At the end of 0.15s, a modulation frequency transition occurs, so between 0.15s and 0.2s, the modulation index remains at 1, the modulation frequency becomes 150Hz, the load resistance remains at 30Ω, and the load inductance remains at 5.5mH. It is evident that this inverter possesses excellent dynamic characteristics and can promptly adapt to changes in instantaneous disturbances.

[0046] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. A seven-level inverter, characterized in that, The seven-level inverter includes: a load terminal on the AC side and a first to a third DC voltage source on the DC side, wherein the voltages of the first, second and third DC voltage sources are equal. The seven-level inverter further includes: first to seventh switching transistors; the emitter of the first switching transistor is connected to the negative terminal of the third DC voltage source, and the collector is connected to the positive terminal of the second DC voltage source; the emitter of the second switching transistor is connected to the negative terminal of the second DC voltage source, and the collector is connected to the positive terminal of the first DC voltage source; the emitter of the third switching transistor is connected to the negative terminal of the first DC voltage source, and the collector is connected to the positive terminal of the third DC voltage source; the emitter of the fourth switching transistor is connected to the positive terminal of the load, and the collector is connected to the positive terminal of the third DC voltage source; the emitter of the fifth switching transistor is connected to the negative terminal of the load, and the collector is connected to the positive terminal of the first DC voltage source; the emitter of the sixth switching transistor is connected to the negative terminal of the second DC voltage source, and the collector is connected to the positive terminal of the load; the emitter of the seventh switching transistor is connected to the negative terminal of the first DC voltage source, and the collector is connected to the negative terminal of the load.

2. The seven-level inverter according to claim 1, characterized in that, The first to seventh switching transistors are all insulated gate bipolar transistors.

3. The seven-level inverter according to claim 1, characterized in that, The voltages of the first, second, and third DC voltage sources are all E. By controlling the on / off state of the first to seventh switching transistors, seven different voltage levels are achieved at the load end. The seven voltage levels output at the load end are: U o ={0, ±E, ±2E, ±3E}.

4. The seven-level inverter according to claim 3, characterized in that, Different output levels correspond to different switching states of the transistor. The corresponding levels and switching states are as follows: U o When =3E, the first, second, fourth, and seventh switches are turned on, and the third, fifth, and sixth switches are turned off; U o When =2E, the first, second, fourth and fifth switches are turned on, and the third, sixth and seventh switches are turned off; U o When =E, the second, sixth, and seventh switches are turned on, and the first, third, fourth, and fifth switches are turned off; U o When the value is -E, the third, fourth, and fifth switches are turned on, while the first, second, sixth, and seventh switches are turned off. U o When the voltage is -2E, the first, third, sixth, and seventh switches are turned on, while the second, fourth, and fifth switches are turned off. U o When the value is -3E, the first, third, fifth, and sixth switches are turned on, while the second, fourth, and seventh switches are turned off. U o When =0, there are two different switching states, which occur during the two processes when the output voltage changes from positive to negative and from negative to positive. The first state is that the second, fifth, and sixth switches are turned on, while the first, third, fourth, and seventh switches are turned off. This state occurs during the process of the output voltage changing from positive to negative. The second state is that the third, fourth, and seventh switches are turned on, while the first, second, fifth, and sixth switches are turned off. This state occurs during the process of the output voltage changing from negative to positive.

5. A modulation method for a seven-level inverter according to any one of claims 1-4, characterized in that, The inverter output voltage is subjected to SHEPWM low-frequency modulation technology to eliminate specified harmonics, as detailed below: The seven-level inverter has 3 degrees of freedom, and 2 specified harmonics are eliminated by establishing 3 nonlinear equations; The expression for the modulating wave in the modulation method is: ， In the formula, For modulated waves, Let t be the fundamental angular frequency, and t be the time variable. The initial phase angle; The three switching conduction angles in the modulation method are determined by the following nonlinear equations: ， In the formula, , , It has 3 switch conduction angles, and , For the modulation scheme, i and j represent the i-th and j-th harmonics to be eliminated, respectively, and both i and j are odd numbers greater than 1; The six comparison potentials in the modulation method are determined by three switch conduction angles: ， In the formula, and This represents the first set of comparison potentials whose values ​​are opposites. and This represents the second set of comparison potentials with opposite values. and This represents the third set of comparison potentials whose values ​​are opposite.

6. The modulation method according to claim 5, characterized in that, The specific control signals for the switching transistors corresponding to different output levels are as follows: when At that time, U o =3E, the control signals for the first, second, fourth and seventh switches are high level, and the control signals for the third, fifth and sixth switches are low level; when At that time, U o =-3E, the control signals for the first, third, fifth and sixth switches are high level, and the control signals for the second, fourth and seventh switches are low level; when At that time, U o =2E, the control signals for the first, second, fourth and fifth switching transistors are high level, and the control signals for the third, sixth and seventh switching transistors are low level; when At that time, U o =-2E, the control signals for the first, third, sixth and seventh switches are high level, and the control signals for the second, fourth and fifth switches are low level; when At that time, U o =E, the control signals for the second, sixth, and seventh switches are high, and the control signals for the first, third, fourth, and fifth switches are low; when At that time, U o =-E, the control signals for the third, fourth and fifth switches are high, and the control signals for the first, second, sixth and seventh switches are low; when ,and When the value of U decreases o =0, the control signals of the second, fifth and sixth switches are high level, and the control signals of the first, third, fourth and seventh switches are low level; when ,and As the value of U increases, o =0, the control signals of the third, fourth and seventh switches are high level, and the control signals of the first, second, fifth and sixth switches are low level.

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