Data acquisition device and power line communication chip for power line communication

Abstract

This invention discloses a data acquisition device and a power line communication chip for power line communication, belonging to the field of power line communication technology. The data acquisition device is applied to a power line communication chip containing a receiving link and includes: a node register for storing node identifiers written by a central processing unit; a multiplexer connected to the node register for selecting signal data output by a target node based on the node identifier and transmitting the signal data to a data acquisition control module; and a data acquisition control module connected to the multiplexer for receiving the signal data output by the target node and writing the signal data into system memory for the central processing unit to read the signal data and perform anomaly localization on the receiving link. This invention is applicable to scenarios such as fault debugging, link anomaly tracing, and performance verification in power line communication chips under complex interference environments, improving chip debugging efficiency and maintainability.

Description

Technical Field

[0001] This invention belongs to the field of power line communication technology, and particularly relates to a data acquisition device and a power line communication chip for power line communication. Background Technology

[0002] Power line communication (PLC), a communication method that utilizes existing power lines for data transmission, is widely used in smart grids, building automation, and remote meter reading. With the increasing level of intelligence, communication chips in PLC systems are undertaking more and more functions such as data reception, signal processing, and protocol control, significantly increasing their integration and complexity. In actual deployment and debugging, analyzing the status and data flow of different signal processing nodes in the internal receiving link of the communication chip has become one of the key means to improve communication stability and quickly locate faults.

[0003] In related technologies, the analysis of communication link status mainly relies on peripheral interface acquisition or indirect acquisition of communication results at the software level. For example, some systems collect the data stream output by the chip by setting up a logic analyzer or debug port outside the communication chip, and then perform reconstruction analysis in conjunction with protocol parsing tools.

[0004] However, the above methods mostly rely on the final output of the communication link or external monitoring methods, making it difficult to perform fine-grained analysis of the internal processing path of the communication chip. Especially in complex receiving links involving multiple processing nodes, it is often difficult to locate which level of node is causing the abnormality once a data anomaly or synchronization failure occurs. Summary of the Invention

[0005] This invention aims to at least solve one of the technical problems existing in related technologies. To this end, this invention proposes a data acquisition device and a power line communication chip for power line communication, enabling flexible acquisition and efficient analysis of output data from any signal processing node in the power line communication chip's receiving link, thereby improving the efficiency of communication anomaly location and debugging capabilities.

[0006] In a first aspect, the present invention provides a data acquisition device for power line communication, applied in a power line communication chip including a receiving link, the receiving link including multiple signal processing nodes, the data acquisition device comprising:

[0007] A node register is used to store a node identifier written by the central processing unit. The node identifier is used to indicate the target node in the receiving link for collecting data.

[0008] A multiplexer, connected to the node register, is used to select the signal data output by the target node according to the node identifier, and transmit the signal data to the data acquisition and control module.

[0009] The data acquisition and control module, connected to the multiplexer, is used to receive signal data output by the target node and write the signal data into the system memory so that the central processing unit can read the signal data and perform anomaly location on the receiving link.

[0010] The data acquisition device for power line communication provided by this invention, by introducing a data acquisition device consisting of a node register, a multiplexer, and a data acquisition control module into the power line communication chip, enables flexible acquisition of the output signal of any signal processing node in the receiving link. The node register is used by the central processing unit to dynamically configure the target node to be acquired, and in conjunction with the multiplexer, it selects and switches the output channels of different nodes. This allows the signal data of the target node to be guided to the data acquisition control module for centralized acquisition and processing without relying on additional observation pins. The acquired data is written to the system memory for further reading and analysis by the central processing unit, thereby enabling visual observation and fault tracing of the processing status of each node in the receiving link, effectively improving the chip's response speed and diagnostic accuracy for anomalies in actual power communication environments. Simultaneously, this structure possesses good flexibility and configurability, suitable for various scenarios such as debugging and verification, fault location, and dynamic monitoring, significantly enhancing the maintainability and field testing capabilities of the power line communication chip.

[0011] Secondly, the present invention provides a data acquisition method for power line communication, the method comprising:

[0012] The node identifier written by the central processing unit is stored in the node register to indicate the target node for the data to be collected in the receiving link;

[0013] Based on the node identifier, the multiplexer is controlled to select the output signal data of the target node and transmit the signal data to the data acquisition and control module.

[0014] The data acquisition and control module receives the output signal data of the target node and writes the signal data into the system memory so that the central processing unit can read the signal data and locate the anomaly in the receiving link.

[0015] The data acquisition method for power line communication provided by this invention introduces a node-identification-based multi-channel acquisition mechanism into the power line communication chip, enabling flexible selection and acquisition of output data from any processing node in the receiving link. This avoids the problems of strong dependence on external pins and limited debugging coverage in traditional solutions. Simultaneously, the acquired data can be directly written into system memory for real-time analysis by the central processing unit, thereby improving the chip's problem-solving capabilities and debugging efficiency in complex communication environments, and enhancing maintainability and reliability during mass production.

[0016] Thirdly, the present invention provides a power line communication chip, the power line communication chip comprising:

[0017] The receiving link contains multiple signal processing nodes for processing communication signals received through the power line, and each processing node outputs corresponding signal data.

[0018] The data acquisition device as described in any of the first aspects is configured to acquire signal data output by any processing node according to the configuration and write it into the system memory so that the central processing unit can read the signal data and perform anomaly location on the receiving link.

[0019] The power line communication chip provided by this invention, based on conventional power line communication capabilities, integrates an optional node data acquisition mechanism, enabling the chip to acquire and analyze in-situ link status. This breaks the limitations of traditional methods that rely on external pin observation or evaluation of processing status through coarse-grained read-only registers. It allows for real-time acquisition and analysis of output data from any processing node in a field communication environment. Especially under conditions of limited mass production packaging, complex interference environments, and tight fault location cycles, it can quickly locate abnormal nodes, significantly improving chip maintainability and engineering verification efficiency. Simultaneously, chip-level integration avoids pin waste and excessive area increase, possessing high reliability and product value, making it suitable for next-generation high-robustness, high-transparency power line communication systems.

[0020] Fourthly, the present invention provides a signal receiving device, the signal receiving device comprising a data acquisition device for power line communication as described in the first aspect, or comprising a power line communication chip as described in the third aspect.

[0021] Fifthly, the present invention provides a signal receiving device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the data acquisition method for power line communication as described in the second aspect above.

[0022] In a sixth aspect, the present invention provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the data acquisition method for power line communication as described in the second aspect above.

[0023] In a seventh aspect, the present invention provides a computer program product, including a computer program that, when executed by a processor, implements the data acquisition method for power line communication as described in the second aspect above.

[0024] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0025] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0026] Figure 1 This is a schematic diagram of the structure of a data acquisition device for power line communication provided in some embodiments of the present invention;

[0027] Figure 2 This is a schematic diagram of the data acquisition system architecture of the power line communication chip receiver provided in some embodiments of the present invention;

[0028] Figure 3 This is a schematic diagram of a simplified power line communication chip receiving link data acquisition architecture provided in some embodiments of the present invention;

[0029] Figure 4 This is a flowchart illustrating a data acquisition method for power line communication provided in some embodiments of the present invention;

[0030] Figure 5 This is a schematic diagram of the structure of a signal receiving device provided in some embodiments of the present invention. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the present invention.

[0032] Unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains; the terminology used in the specification of this application is for the purpose of describing particular embodiments only and is not intended to limit the invention; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings are used to distinguish different objects, not to describe a particular order or hierarchy.

[0033] In this invention, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this invention can be combined with other embodiments.

[0034] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "attachment" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0035] In this invention, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, in this invention, the character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0036] In this invention, "multiple" refers to two or more (including two), similarly, "multiple groups" refers to two or more (including two groups), and "multiple pieces" refers to two or more (including two pieces).

[0037] When performing die-back verification on high performance line communication (HPLC) chips, especially during the testing of the functionality and performance of their receiver (RX) link, it is usually necessary to collect and analyze data from multiple signal processing nodes in the RX link in order to determine the location of communication anomalies and achieve precise problem localization.

[0038] In practical engineering, to obtain data from each processing node, a common practice is to directly bring out the nodes in the analog signal path to the external pins of the chip for testing, while the digital path provides some key status information for the CPU to read and analyze through read-only registers.

[0039] However, the above approach has certain drawbacks: for the analog part, engineering batch chips are usually packaged in large packages, and the corresponding observation pins are packaged out. However, because the packaged chips for commercial use are smaller, the observation pins cannot be fully packaged out, which makes it impossible to perform data analysis on mass-produced chips. For the digital part, considering the area, the state machine and key information are stored only through read-only registers, resulting in missing analysis data and making it impossible to analyze the link data more intuitively.

[0040] Furthermore, the aforementioned problems are particularly prominent in power line carrier communication scenarios. Power line communication chips are typically deployed in power grid environments, where the signal is prone to severe attenuation due to the resistance, inductance, and capacitance effects of the cables. Simultaneously, they are frequently subjected to various interferences such as impulse noise, periodic noise, and white noise, and the communication channel characteristics are unstable. These complex interference factors can lead to sudden anomalies or performance fluctuations in the receiving link. When communication anomalies occur, real-time on-site analysis of the receiving link processing data within the chip is required to pinpoint the root cause. However, current technologies can only observe register states or waveforms of some nodes, failing to directly obtain intermediate processing data from the link, severely impacting the efficiency of problem tracing and the controllability of debugging.

[0041] Therefore, to address the limitations of analog observation and the untraceability of digital link data, especially the inability to effectively analyze communication anomalies in complex field environments of power line communication, this invention provides a data acquisition device and a power line communication chip for power line communication. Without increasing chip area or relying on external pins, it adds a data acquisition control module inside the chip and reuses system memory. It simultaneously supports the acquisition of analog and digital signal nodes, and combined with configurable triggering mechanisms and mode control, enables real-time acquisition, reconstruction, and problem analysis of RX link data at communication anomaly sites. This solves the problem of missing data analysis in traditional methods, thereby effectively locating anomalies and improving problem location efficiency.

[0042] The data acquisition device and power line communication chip for power line communication provided in this invention will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0043] In some embodiments, the data acquisition device is integrated into the receiver (RX) link of the power line communication chip to internally sample and store the output data of each signal processing node in the receiver link, so as to realize link status monitoring and anomaly tracing.

[0044] Among them, power line communication chips (hereinafter referred to as communication chips) are system-level integrated chips used for bidirectional communication in low-voltage power line environments. They have functions such as analog reception, digital processing, and protocol parsing, and are suitable for scenarios such as smart meters and building controllers. Due to the complexity of power line communication channels, such as strong interference, high noise, and impedance mismatch, the receiving link of this type of chip is usually composed of multiple series-connected signal processing nodes, each of which is responsible for a specific function of the receiving link.

[0045] Figure 1 This is a schematic diagram of the structure of a data acquisition device for power line communication provided in some embodiments of the present invention. For example... Figure 1 As shown, the receiving link includes multiple signal processing nodes 110, and the data acquisition device 10 includes:

[0046] Node register 120 is used to store the node identifier written by the central processing unit. The node identifier is used to indicate the target node in the receiving link to collect data.

[0047] Multiplexer 130 is connected to node register 120 and is used to select the signal data output by the target node according to the node identifier and transmit the signal data to data acquisition and control module 140.

[0048] The data acquisition and control module 140 is connected to the multiplexer 130 and is used to receive the signal data output by the target node and write the signal data into the system memory so that the central processing unit can read the signal data and locate the anomaly in the receiving link.

[0049] For example, a signal processing node may include the following key types:

[0050] Signal receiving node: For example, the node where the low noise amplifier (LNA) is located is used to receive weak signals on the power line. Its gain and noise figure directly determine the signal quality.

[0051] Signal filtering nodes: such as the nodes where bandpass filters (BPF) are located, are used to filter out interference signals that are not in the target frequency band, and are a key link in improving signal purity;

[0052] Signal conversion nodes: such as the nodes where analog-to-digital converters (ADCs) are located, are used to accurately convert analog signals into digital signals, and are the interface between the analog and digital domains;

[0053] Digital front-end nodes: such as the nodes where decision feedback equalizers (DFE) are located, are used to eliminate severe inter-symbol interference in power lines and improve bit error rate performance;

[0054] Baseband processing node: For example, the node where the baseband processing module (BBP) is located is used to complete the core communication functions in power line communication, such as modulation and demodulation, synchronization, error correction, encryption and decryption.

[0055] In a power line carrier communication environment, the data from some nodes not only needs to participate in real-time communication processing, but also needs to be monitored, collected, and analyzed in real time during the communication process in order to cope with dynamic interference and link anomalies on site.

[0056] Typical nodes that require real-time monitoring and analysis include:

[0057] LNA node: Its output signal reflects the power and noise status of the amplified signal, and can be used to determine whether the receiving sensitivity meets the standard.

[0058] BPF node: Its output spectrum reflects the filtering accuracy and passband shape, and can be used to verify interference suppression capability;

[0059] ADC node: Its output is digital waveform data, which reflects the conversion accuracy, dynamic range, and whether there is distortion;

[0060] DFE node: Its output can be used to evaluate the effect of equalization algorithm and reflect whether inter-symbol interference has been effectively suppressed;

[0061] BBP node: Its output information includes indicators such as synchronization accuracy, frame structure judgment and decoding success rate, which are key reference data for debugging higher-level protocols.

[0062] To address the aforementioned data acquisition requirements, the data acquisition device proposed in this invention comprises the following three core components:

[0063] A node register is a data register that can be accessed and written to by the central processing unit (CPU) via software. It is primarily used to store the node identifier, which indicates the currently selected target node. The node identifier can be a uniquely coded node address or number, used for selection control of the multiplexer during subsequent data acquisition.

[0064] A multiplexer (MUX) is a signal channel switching module with multiple inputs and a single output. Its inputs are connected to the outputs of multiple signal processing nodes, and its outputs are connected to a data acquisition and control module. The selection input of the MUX is provided by the node register. Once the node identifier is written, the MUX can select the output signal of the corresponding node.

[0065] The data acquisition and control module is a hardware unit used to receive, buffer, and write data to system memory. It is connected to the MUX and is used to acquire the output signal data of the target node and write it to system memory via the on-chip internal bus. System memory is an addressable general-purpose storage area in the communication chip that can be read and parsed by the CPU.

[0066] In the above structure, when the CPU detects a communication anomaly or requires debugging, it can write the target node's identifier to the node register via software, indicating the location of the node to be acquired. Subsequently, the MUX completes the node output channel selection at the hardware layer, and the data acquisition control module begins to receive the signal data of that channel and writes it to system memory. The CPU can then read the acquired signal data from system memory and perform anomaly localization analysis in conjunction with the link structure and processing status.

[0067] With this structural design, the communication chip can flexibly select any node output for real-time data capture during operation without adding external pins or large-capacity storage. This enables visualization and problem tracking of the entire process from analog processing and analog-to-digital conversion to digital demodulation, and is suitable for the typical field debugging and mass production maintenance needs of power line communication chips.

[0068] The following, in conjunction with the accompanying drawings, provides scenario-based embodiments for five key nodes (LNA, TIA, BPF, DFE, BBP) in the power line communication chip to illustrate the data acquisition device provided by the present invention.

[0069] (1) Observation and anomaly analysis of LNA nodes

[0070] In the receiving link of a power line communication chip, the LNA node is a front-end module responsible for primary amplification of the weak analog signals received from the power line. Its performance directly affects the signal-to-noise ratio and subsequent processing effect of the entire receiving link.

[0071] When a communication system is deployed in an industrial environment with strong inductive load interference (such as welding machines or frequent motor switching), and issues such as degraded reception performance and abnormal signal identification occur, the central processing unit (CPU) writes instructions to the node register, writing the node identifier value representing the LNA node, indicating that the target node to be acquired is the LNA node. This node identifier value in the node register is transmitted to a multiplexer (MUX). The MUX selects the signal channel connected to the LNA node's output based on this identifier, thus completing the selection of the target node's signal path. Since the LNA node output is an analog signal, this analog signal is converted to a digital signal by an analog-to-digital converter (ADC) module connected to the MUX, providing a digital signal for subsequent acquisition. The digital signal enters the data acquisition control module. After receiving the signal data, the data acquisition control module automatically writes the acquired data into system memory according to the sampling length setting in the length configuration register.

[0072] After the data is written, the CPU can read the collected LNA node output signal data from the system memory and compare and analyze it with the node data of the upstream and downstream of the link to determine whether the current anomaly is caused by abnormal signal amplification of the LNA node, such as distortion or saturation.

[0073] (2) Observation and anomaly analysis of TIA nodes

[0074] In the receiving link of a power line communication chip, the TIA node is mainly used to convert the current signal output by the LNA node into a voltage signal and further amplify it. It is suitable for precise processing of extremely small current signals, such as deployment scenarios with frequent carrier jumps or signal distortion caused by aging coupling devices.

[0075] In this embodiment, the target node is a TIA node. The CPU writes a instruction to the node register, writing the node identifier value representing the TIA node into it, indicating that the target node to be acquired subsequently is a TIA node. The node identifier value in the node register is transmitted to a multiplexer (MUX). The MUX selects the signal channel connected to the output of the TIA node based on the identifier, thus completing the selection of the target node signal path. Since the output of the TIA node is an analog signal, it is converted into a digital signal by the ADC module, then received by the data acquisition control module, and written to the system memory according to the set length.

[0076] After the CPU reads the signal data, it can determine whether the conversion gain is stable, whether there is drift or nonlinear distortion in the output, and thus help determine whether the TIA parameter settings are reasonable, or whether they are affected by interference from the previous stage signal, etc.

[0077] (3) Observation and anomaly analysis of BPF nodes

[0078] In residential buildings or scenarios where multiple devices are used simultaneously, periodic carrier interference or low-frequency noise superposition can easily occur, affecting communication quality. BPF is used to extract communication signals within a specified frequency range and filter out high-frequency spike interference and low-frequency power noise.

[0079] In this embodiment, the target node is a BPF node. The CPU sets the target node as a BPF node through the node register. The acquisition path is the same as the aforementioned node, that is, after the output signal data is selected by the multiplexer, it is acquired and written to memory by the data acquisition control module. After the CPU analyzes the data of the BPF node, it can evaluate whether the filter has effectively suppressed common power frequency interference and periodic noise on power lines, whether the signal bandwidth meets the design requirements, and thus determine whether there are problems such as filter parameter drift or interference leakage.

[0080] (4) Observation and anomaly analysis of DFE nodes

[0081] In this embodiment, the target node is the DFE node. The CPU sets the target node as the DFE node through the node register. The acquisition path is the same as the aforementioned nodes, that is, after the output signal data is selected by the multiplexer, it is acquired and written to memory by the data acquisition control module. After analyzing the data of the DFE node, the CPU can determine whether the equalizer is working correctly, whether there is inter-symbol interference (ISI), etc. Combining the data differences between upstream and downstream nodes can help identify interference sources or equalization parameter misalignment problems.

[0082] (5) Observation and anomaly analysis of BBP nodes

[0083] In this embodiment, the target node is a BBP node. The CPU sets the target node as a BBP node through the node register. The acquisition path is the same as the aforementioned node, that is, after the output signal data is selected by the multiplexer, it is acquired by the data acquisition control module and written to memory. The CPU can perform synchronization point detection, packet header analysis, or error correction statistics based on the raw frame data output by the BBP, thereby tracing potential asynchrony, bit errors, or frame loss in the protocol processing link.

[0084] Through the above process, the data acquisition device provided by this invention can acquire signals from each signal processing node within the chip without the need for external pin observation, and store the signal data in system memory for subsequent analysis. Compared to related technologies that only support leading the signal data output by each signal processing node to the test pin via a MUX, and are essentially only applicable to the engineering verification stage, this invention supports the acquisition of signal data output by each signal processing node within the mass production stage, effectively enhancing the chip's self-diagnostic capabilities in complex power communication environments.

[0085] It should be noted that the nodes and corresponding processing flows illustrated above are merely illustrative and do not constitute a limitation of the present invention. Without departing from the inventive concept of the present invention, nodes in the receiving link can be equivalently replaced or combined and modified.

[0086] The data acquisition device provided in this invention can select any node and realize real-time acquisition and analysis of data processed within the link. Its core is to achieve fine-grained data access within the link without relying on external pins or introducing a large area of ​​storage.

[0087] Based on this inventive concept, in order to further improve the data acquisition efficiency of each signal processing node in the receiving link, the data acquisition device can also be expanded to support parallel acquisition of multiple nodes.

[0088] Therefore, in some embodiments, the data acquisition device further includes at least one parallel channel group, each parallel channel group including: multiple node registers, each used to store node identifiers written by the central processing unit to indicate different target nodes to be acquired in the receiving link; multiple multiplexers, each connected to a parallel node register, used to select the signal data output by each indicated target node according to the multiple node identifiers, and transmit each signal data to the data acquisition control module respectively; multiple data acquisition control modules, each connected to a parallel multiplexer, used to receive the signal data output by each target node, and write each signal data into the system memory respectively.

[0089] Specifically, at least one parallel channel group is added to the existing acquisition channels. Each parallel channel group includes an independent node register, a multiplexer, and an acquisition path, allowing multiple target nodes to be selected simultaneously, forming a parallel acquisition link. The central processing unit can write different target node identifiers to each node register, thereby controlling multiple multiplexers to select the signal data output by multiple nodes in parallel. Multiple data acquisition control modules receive the signal data of their respective target nodes and write them to different address segments of the system memory.

[0090] To avoid resource conflicts, a data acquisition task scheduling logic module can be further configured to uniformly manage the acquisition time window, system memory mapping address, and bus bandwidth usage of each channel, ensuring that the acquisition actions of each channel do not interfere with each other and that data is stored consistently. Therefore, the data acquisition device further includes an acquisition scheduling logic module, used to uniformly manage the acquisition time window, system memory mapping address, and bus bandwidth usage of each target node for each data acquisition control module, to avoid resource conflicts and ensure that the data writing process of each channel does not interfere with each other and that data is stored consistently. For example, in actual operation, the central processing unit first configures the target node identifier to be acquired in each parallel node register and allocates a dedicated system memory address segment to each data acquisition control module to avoid data write conflicts between different channels. Furthermore, to prevent bandwidth congestion on the system bus when multiple acquisition tasks are performed simultaneously, the acquisition scheduling logic module can also pre-set the acquisition time window for each channel. For example, the acquisition time of parallel channel A can be set to the first half of a certain system clock cycle, and channel B to the second half, thus creating a staggered acquisition rhythm. For system architectures that support Direct Memory Access (DMA), this module can also dynamically coordinate DMA channel allocation and priorities to ensure the real-time requirements of high-priority nodes.

[0091] Through the above mechanism, even in high-interference, high-concurrency debugging scenarios, the system can stably acquire real-time data from multiple signal processing nodes and ensure the integrity of the data written to memory, thereby improving the chip's ability to respond to and analyze link anomalies in complex communication environments. This parallel architecture is particularly suitable for dynamic debugging scenarios of power line communication chips in complex interference environments, such as simultaneously analyzing the response status of multiple processing nodes during high noise bursts, which helps to quickly locate the source of abnormal waveforms and link bottlenecks.

[0092] In some embodiments, signal processing nodes include two types: analog signal processing nodes and digital signal processing nodes. To enable observation and acquisition of analog signal processing nodes, the data acquisition device further includes: an analog-to-digital converter connected to a multiplexer, used to convert the analog signal data output by the target node into digital signal data when the target node is an analog signal processing node, so that the multiplexer can transmit it to the data acquisition control module.

[0093] The analog signal processing node refers to the functional unit that performs front-end processing on the received power line analog signal, such as gain amplification and noise filtering. Examples include low-noise amplifiers (LNAs), transimpedance amplifiers (TIAs), and bandpass filters (BPFs). These nodes typically output continuous analog waveform signals, which cannot be directly processed by the subsequent digital acquisition module. They must first be converted into digital signals by an analog-to-digital converter (ADC) before being transmitted to the data acquisition and control module for further writing processing.

[0094] In practical applications, when the target node written to the node register is the aforementioned analog signal processing node, the multiplexer selects the corresponding analog signal channel based on the node identifier. This channel is first connected to the analog-to-digital converter (ADC), which converts the analog signal into the corresponding digital signal. The digital signal is then transmitted to the data acquisition and control module via the digital signal channel and finally written to the system memory. The ADCs in this path typically employ a multiplexing design to save chip resources and avoid the area and power consumption overhead caused by configuring an independent ADC for each analog node.

[0095] By introducing an analog-to-digital converter between the analog processing node and the data acquisition control module, the conversion of analog signals to digital signals can be automatically completed when the target acquisition node is an analog signal processing node. This enables unified acquisition of key signals in the analog signal path, improves the observability of signals inside the chip, facilitates debugging and fault diagnosis, and is especially suitable for application scenarios with complex channel noise in power line communication.

[0096] In some embodiments, to facilitate the central processing unit in accurately determining the boundary range of the currently acquired signal data, the data acquisition device further includes a length configuration register connected to the data acquisition control module, used to store the data length value written by the central processing unit, so as to control the data acquisition control module to stop writing after the data length written to the system memory reaches the data length value.

[0097] The data length value indicates the maximum data length of the acquired signal data when it is written to the system memory.

[0098] In practical applications, the CPU first writes a preset data length value to the length configuration register. The data acquisition control module then continuously counts the amount of data written to system memory during the acquisition of signal data output from the target node. When the cumulative amount of written data reaches the specified length value, the data acquisition control module automatically terminates the current writing process to prevent write overflow or data misalignment.

[0099] By setting a length configuration register, the data acquisition device can achieve controllability and boundary constraints in the data writing process, effectively avoiding overflow errors or invalid data redundancy caused by memory overwrite. Simultaneously, the length value is configured by the CPU, possessing good adjustability and adaptability, allowing for flexible adjustment of the data length for different communication scenarios, node types, or sampling requirements, improving the system's testing accuracy and resource utilization efficiency. This mechanism enhances the flexibility and robustness of the acquisition system in complex scenarios involving power line communication chips, such as on-demand sampling and rapid anomaly location.

[0100] In addition, when used in conjunction with the address latch register, it can also realize the dynamic identification and packet parsing of the first and last addresses of the acquired data, thereby improving the processing efficiency of the upper-layer debugging software on the data content.

[0101] Therefore, in some embodiments, the data acquisition control module is also used to store the system memory write address at the end of the data after the signal data is written according to the configured data length value; in order to realize boundary management and start and end address identification of the acquired data, the data acquisition device further includes: an address latch register, connected to the data acquisition control module, used to receive the system memory write address transmitted by the data acquisition control module, and latch the system memory write address so that the central processing unit can determine the end position of the signal data.

[0102] The system memory write address at the end of the data, combined with the data length value preset by the central processing unit, can be used to deduce the starting address, thereby achieving complete location and identification of the data block.

[0103] Specifically, during the signal data writing process, the data acquisition control module continuously updates the currently written memory address. Once the acquisition and writing process is complete according to the target data length stored in the length configuration register, the data acquisition control module sends the final written system memory address to the address latch register for latching and storage. The central processing unit can read the contents of the address latch register at any time and deduce the complete sampled data segment based on the sampling length, enabling subsequent correct unpacking, analysis, and processing of the target node data.

[0104] By introducing an address latch register, the endpoint address of the memory write can be automatically recorded after signal data acquisition, providing boundary markers for subsequent data reading and parsing by the central processing unit and avoiding problems such as data misreading and segment confusion. Compared to the traditional method that relies on the CPU to track the memory pointer alone, this structure provides a hardware-level address latching mechanism, improving the automation capability and timing stability of the sampling system. It is especially suitable for link status monitoring and fault location under high concurrency and high interference conditions in power line communication chips.

[0105] To enable dynamic control over the activation and deactivation of data acquisition, in some embodiments, the data acquisition device further includes an acquisition switch register. This register is connected to the data acquisition control module and is used to receive control commands written by the central processing unit to enable or disable the output channel of the data acquisition control module, thereby controlling whether the data acquisition control module writes the signal data output by the target node into the system memory.

[0106] When the central processing unit detects that the communication link is in a debugging, sampling, or testing state, it can configure the acquisition switch register to the "on" state (e.g., the stored value is "1") via software, triggering the data acquisition control module to acquire the output signal of the target node and write the data to the system memory. Conversely, during non-testing periods, or when the communication status is stable and monitoring is not required, the central processing unit can configure the register to the "off" state (e.g., the stored value is "0"), preventing the data acquisition control module from continuing to write, thereby avoiding redundant data accumulation, saving memory resources, and preventing expired sampled data from interfering with system operation.

[0107] By configuring the data acquisition switch register, the central processing unit can flexibly control data acquisition behavior as needed. This not only avoids wasting memory resources caused by data writing during unnecessary periods but also enhances the system's adaptability in various scenarios. For example, disabling acquisition in normal operation mode and enabling acquisition during debugging or anomaly detection effectively supports the long-term reliable operation and rapid troubleshooting of power line communication chips. This mechanism provides a fine-grained and convenient hardware-software collaboration method, particularly suitable for communication chip application environments with limited resources and high reliability requirements.

[0108] To enable automatic triggering of data acquisition, the data acquisition device further includes a trigger source selection register. This trigger source selection register is connected to the data acquisition control module and is used to store the trigger source type configured by the central processing unit, that is, to indicate at which link processing stage the acquisition operation is triggered.

[0109] The trigger source type includes at least one of the following: receive enable signal, synchronization start signal, or synchronization completion signal.

[0110] Accordingly, the data acquisition and control module is also used to write the signal data output by the target node into the system memory when it receives a trigger signal generated by the communication state control logic in the receiving link that corresponds to the trigger source type.

[0111] The data acquisition control module is connected to the communication state control logic (such as the state machine control module) in the communication link. This communication state control logic can generate trigger signals after key nodes in the receiving link complete specific processing flows, such as receive enable (rx_enable), synchronization start (sync_begin), and frame synchronization complete (frame_synced). The data acquisition control module continuously monitors whether it receives a trigger signal that matches the trigger source type. Once a corresponding trigger event is detected, it immediately starts the acquisition operation of the output data of the target node and writes the acquisition results into the system memory for subsequent CPU review and analysis.

[0112] By linking the trigger source selection register with the communication status control logic, the data acquisition control module can automatically initiate data acquisition at critical moments during link operation, realizing an event-driven data acquisition mechanism. This acquisition method features high real-time performance and low interference, and can capture data after the processing of key communication nodes without manual intervention. This avoids problems such as improper acquisition timing or missed data, and improves the reliability and automation of power line communication chips in anomaly detection, functional verification, and dynamic link analysis. It is particularly suitable for intelligent data acquisition needs in power communication scenarios with strong interference and severe link fluctuations.

[0113] In some embodiments, to ensure that the acquisition trigger action has sufficient link status basis, the data acquisition device further includes at least one status register for storing the status flag values ​​of each signal processing node (e.g., DFE, BBP, etc.) in the receiving link after processing is completed.

[0114] Each status register corresponds one-to-one with a type of trigger source in the communication link. For example, the status register used for receiving enable events can be written with a specific value when the link enters the receive state, indicating that the receive initialization has been completed. This status flag value can be automatically written into the status register by the communication status control logic after the node has finished processing.

[0115] The data acquisition and control module is connected to the aforementioned status register and can continuously monitor the status flag value stored in the status register that matches the trigger source type configured in the trigger source selection register. When a change in the corresponding status flag value is detected, it is considered that the trigger event has been met (e.g., from "0" to "1"), and then the module controls the writing of the signal data of the target node into the system memory.

[0116] By introducing a status register synchronized with the status of each processing node and combining it with a trigger source selection mechanism, the data acquisition control module can detect status changes at the first moment of changes in the status of processing nodes within the link, and determine whether the acquisition trigger conditions are met based on this. Compared with fixed-sequence acquisition or external command triggering methods, this solution has higher time accuracy and context awareness, and can capture the precise status of key processing stages during the operation of the communication link, avoiding invalid acquisition and missed acquisition problems, significantly improving data analysis quality and debugging efficiency. It is particularly suitable for scenarios in power line communication where the link dynamic fluctuations are significant and the debugging timing requirements are strict.

[0117] In some embodiments, to further refine the data acquisition triggering timing and improve the accuracy and flexibility of acquisition, the data acquisition device also includes a trigger source edge selection register, which is connected to the data acquisition control module and is used to configure the trigger edge type by the central processing unit, that is, to indicate that acquisition should be started when the rising edge or falling edge of the status signal occurs.

[0118] Here, "rising edge" refers to the process of the status flag value changing from 0 to 1; "falling edge" refers to the process of the status flag value changing from 1 to 0. This mechanism is particularly suitable for complex link scenarios in communication protocols where synchronous start-up or processing completion signal edge triggering exists.

[0119] Based on the status flag values ​​of the aforementioned status registers, the data acquisition control module monitors whether the value of the corresponding status register changes edgewise (i.e., from low to high, or vice versa) according to the trigger source type configured in the trigger source selection register. When the monitored status flag value changes in the configured edge direction, the data acquisition control module triggers the writing of the target node's signal data into the system memory, ensuring that the data acquisition operation is precisely initiated only at critical event boundaries.

[0120] By setting the trigger source edge selection register, precise determination of signal state change edges is achieved. This enables data acquisition not only to respond to state changes but also to precisely control the specific timing of those changes, significantly improving the time alignment accuracy of data acquisition. This is beneficial for analyzing data behavior near link state transition points and is particularly suitable for analyzing edge-sensitive power line communication scenarios such as frame synchronization start points and sampling window start points. In power line communication scenarios, due to the large timing fluctuations of the link, the edge triggering mechanism can significantly enhance the system's responsiveness to minute state changes, thereby improving debugging accuracy and problem reproducibility.

[0121] In some embodiments, to adapt to different testing requirements and data capture strategies, the data acquisition device further includes a data acquisition mode configuration register, which stores the acquisition mode type written by the central processing unit.

[0122] The acquisition mode refers to the data acquisition control module's processing strategy for historical data during the data writing process. Acquisition mode types can include either cyclic overwrite mode or single acquisition mode, and the acquisition behavior of the data acquisition control module will be differentiated according to this configuration. Cyclic overwrite mode allows repeated updates within the same memory area, saving space; single acquisition mode ensures that each acquired data is completely retained, facilitating the analysis of complete waveforms or abnormal windows.

[0123] Specifically, when configured in cyclic overlay mode, the data acquisition control module can continuously overwrite previously stored old data when writing the signal data of the target node into the system memory, thereby achieving real-time acquisition in a ring-buffered manner, which is suitable for link stability monitoring in a continuous operating environment.

[0124] When configured in single-acquisition mode, the data acquisition control module automatically stops after completing one signal data writing operation, and only resumes acquisition when the conditions for triggering a new round of acquisition are met (such as a change in the edge of the flag value in the status register). This is suitable for capturing sample data under specific states or event triggers.

[0125] By configuring the data acquisition mode register, the data acquisition device possesses a flexible and adjustable operating mode, supporting both a cyclic coverage mode for long-term observation and a single-acquisition mode for capturing specific events. Compared to fixed-strategy data acquisition mechanisms, this significantly improves the system's adaptability to different link debugging scenarios. Particularly in power line communication, due to the complex and diverse types of interference and the uncertain occurrence of some abnormal events, which may only appear briefly at a certain moment, the single-acquisition mode can accurately pinpoint the problem. For long-term monitoring, a cyclic mode can be enabled for continuous sampling, reducing storage pressure. Overall, this mechanism enhances the breadth and depth of the chip's abnormal event detection, improving the system's availability during mass production debugging and dynamic monitoring phases.

[0126] Figure 2 This is a schematic diagram of the data acquisition system architecture of the power line communication chip receiver provided in some embodiments of the present invention. For example... Figure 2 As shown, the power line communication chip is used to receive and process actual link signals from the field communication link. The overall receiving link includes analog end processing, digital end processing, and a data acquisition system with multi-level control capabilities.

[0127] In the analog processing section, the receiving link sequentially includes a low-noise amplifier (LNA), a transimpedance amplifier (TIA), and a bandpass filter (BPF). These are used to amplify the input signal with low noise, perform current-to-voltage conversion, and bandpass filtering, respectively. The resulting analog signal is converted into a digital signal by an analog-to-digital converter (ADC) and then enters the digital processing module. The digital processing module includes a decision feedback equalizer (DFE) and a baseband processing unit (BBP). The former is used to eliminate inter-symbol interference, while the latter is responsible for core communication processing operations such as modulation, synchronization, and error correction. Finally, the results are written to system memory for the CPU to read.

[0128] exist Figure 2 Based on the conventional link shown, this invention introduces a complete data acquisition path. Multiple signal processing nodes (such as LNA output, TIA output, ADC output, DFE output, and BBP output, labeled as nodes 1 to 5) are connected to a multiplexer (MUX). The channel selection of the MUX is configured by the CPU through the target register. The MUX output is connected to the data acquisition module to transmit the output signal of the selected target node to the system memory.

[0129] To achieve flexible and controllable data acquisition, Figure 2 It also includes several function registers connected to the data acquisition module, including an acquisition switch register, a trigger source selection register and a trigger edge selection register, a related status register, a length configuration register, and an address latch register.

[0130] After the CPU is configured with the acquisition target, trigger type, edge, and acquisition length, the data acquisition module starts acquisition when it receives a valid edge change from the communication link status register, writes the data of the target node into memory, automatically stops when the set length is filled, and latches the address to form complete traceable data.

[0131] To further improve the application flexibility and debugging efficiency of the above system, the present invention also provides a simplified acquisition architecture that is oriented towards the debugging needs of specific nodes and is suitable for simulated link debugging or resource-constrained scenarios.

[0132] Figure 3This is a schematic diagram of a simplified power line communication chip receiving link data acquisition architecture provided in some embodiments of the present invention. For example... Figure 3 As shown, this architecture is mainly used to realize signal acquisition and observation of key nodes in the analog signal processing path.

[0133] The communication chip receives the actual link signal from the field communication link. The signal first passes through the analog processing module, which includes a low-noise amplifier (LNA), a transimpedance amplifier (TIA), and a bandpass filter (BPF) to perform amplification, transformation, and filtering. The processed analog signal is then converted into a digital signal by the ADC for subsequent system processing and written into system memory. The CPU can read the final processing result from the system memory.

[0134] In this simplified architecture, to facilitate the acquisition of output signals from nodes such as LNA, TIA, and BPF, Figure 3 A MUX (Multiple-Selector) is provided, with its inputs connected to the outputs of multiple key nodes in the analog path and its outputs connected to an externally observable path. The control input of the MUX is set by the "channel register" configured by the CPU, which is used to select the target node signal to be acquired or observed.

[0135] The data stream output by the MUX can be sent to external test equipment, or connected to a data acquisition module and further written into system memory, thereby enabling on-chip or off-chip observation and recording.

[0136] compared to Figure 2 structure, Figure 3 More suitable for scenarios with limited resources and package pins, but still requiring the observation of specific analog nodes, and can also be used as Figure 2 The partial implementation of the solution is embedded in the entire data acquisition system to form a layered architecture, supporting flexible debugging and data verification.

[0137] Based on the same inventive concept, the present invention also provides a data acquisition method for power line communication, applied to a power line communication chip, the power line communication chip including a receiving link, the receiving link including multiple signal processing nodes.

[0138] For example, the power line communication chip is deployed in a power line carrier communication system for dynamic observation and anomaly localization of link processing data in test or field environments.

[0139] Figure 4 This is a flowchart illustrating a data acquisition method for power line communication provided in some embodiments of the present invention. For example... Figure 4 As shown, the method includes:

[0140] Step 410: Store the node identifier written by the central processing unit into the node register to indicate the target node for data to be collected in the receiving link.

[0141] Step 420: Based on the node identifier, control the multiplexer to select the output signal data of the target node and transmit the signal data to the data acquisition and control module.

[0142] Step 430: The data acquisition and control module receives the output signal data of the target node and writes the signal data into the system memory so that the central processing unit can read the signal data and locate the anomaly in the receiving link.

[0143] Specifically, the central processing unit (CPU) first writes the target node's identifier into the node register via software configuration. The node identifier indicates the current data processing location that is to be observed. The multiplexer (MUX) then connects to the corresponding target node's output based on this node identifier.

[0144] Subsequently, the multiplexer transmits the acquired target node output signal data to the data acquisition and control module. During this process, if the target node output is an analog signal, it can be converted using an analog-to-digital converter (ADC) before transmission. The data acquisition and control module buffers the received target node signal data and writes it into system memory for subsequent CPU analysis.

[0145] For example, in a communication test, the CPU set the node identifier to the DFE node and completed the acquisition of DFE processing output data through the above process. The CPU then analyzed the data stored in the system memory and found that there were intermittent data jumps in the DFE output. It was initially judged that this might be caused by a deviation in the sampling rate configuration of the front-end ADC or a mismatch in the DFE equalization parameters. Therefore, the configuration parameters were adjusted in a targeted manner and the test was repeated.

[0146] The data acquisition method for power line communication provided in this invention introduces a node-identification-based multi-channel acquisition mechanism into the power line communication chip, enabling flexible selection and acquisition of output data from any processing node in the receiving link. This avoids the problems of strong dependence on external pins and limited debugging coverage in traditional solutions. Simultaneously, the acquired data can be directly written into system memory for real-time analysis by the central processing unit, thereby improving the chip's problem-solving capabilities and debugging efficiency in complex communication environments, and enhancing the maintainability and reliability of the product during mass production.

[0147] Based on the same inventive concept, this invention also provides a power line communication chip. This chip includes a receiving link, which is a continuous processing path that receives signals from a power line and performs demodulation, decision-making, synchronization, and other processing. The communication chip integrates a data acquisition device as described in any of the foregoing embodiments or combinations thereof, enabling it to perform real-time acquisition and analysis of the operating status of key processing nodes in the receiving link while performing power line communication tasks.

[0148] This communication chip can be deployed in power line carrier communication systems for stable data reception under complex interference conditions. When the system detects a deterioration in communication performance (such as increased bit error rate, synchronization failure, response timeout, etc.), the central processing unit can configure node registers to select a target node and use the data acquisition control module to write its output data into the system memory. Subsequently, through acquisition length configuration, trigger source control, and state edge monitoring, the abnormal handling process can be accurately traced. Its acquisition range can cover multiple processing links such as analog front-end (e.g., LNA, TIA, BPF) and digital back-end (e.g., ADC, DFE, BBP), possessing high adaptability and configurability.

[0149] The power line communication chip provided by this invention, based on conventional power line communication capabilities, integrates an optional node data acquisition mechanism, enabling the chip to acquire and analyze in-situ link status. This breaks through the limitations of traditional methods that rely on external pin observation or coarse-grained read-only registers to assess processing status. It allows for real-time acquisition and analysis of output data from any processing node in a field communication environment. Especially under conditions of limited mass production packaging, complex interference environments, and tight fault location cycles, it can quickly locate abnormal nodes, significantly improving chip maintainability and engineering verification efficiency. Simultaneously, chip-level integration avoids pin waste and excessive area increase, possessing high reliability and product value, making it suitable for next-generation, highly robust, and highly transparent power line communication systems.

[0150] This invention also provides a signal receiving device that integrates the data acquisition device for power line communication provided in the foregoing embodiments.

[0151] This invention also provides a signal receiving device that integrates the power line communication chip provided in the foregoing embodiments.

[0152] Figure 5 This is a schematic diagram of the structure of a signal receiving device provided in some embodiments of the present invention. In some embodiments, such as... Figure 5As shown, this embodiment of the invention also provides a signal receiving device 500, including a processor 501, a memory 502, and a computer program stored in the memory 502 and executable on the processor 501. When the program is executed by the processor 501, it implements the various processes of the above method embodiments and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0153] This invention also provides a non-transitory computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the various processes of the above-described data acquisition method embodiments for power line communication and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0154] The processor is the processor in the computer device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0155] This invention also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described data acquisition method for power line communication.

[0156] The processor is the processor in the computer device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0157] This invention also provides a chip, which includes a processor and a communication interface. The communication interface and the processor are coupled. The processor is used to run programs or instructions to implement the various processes of the above-described data acquisition method embodiments for power line communication, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0158] It should be understood that the chip mentioned in the embodiments of the present invention may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0159] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of the present invention is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0160] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the related technology, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0161] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.

[0162] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0163] Unless otherwise specified, all embodiments and optional embodiments of the present invention can be combined with each other to form new technical solutions.

[0164] Unless otherwise specified, all technical features and optional technical features of this invention can be combined to form new technical solutions.

[0165] Unless otherwise specified, all steps of the present invention may be performed sequentially or randomly, preferably sequentially. For example, the method includes steps (a) and (b), indicating that the method may include steps (a) and (b) performed sequentially, or it may include steps (b) and (a) performed sequentially. For example, the mention that the method may also include step (c) indicates that step (c) may be added to the method in any order; for example, the method may include steps (a), (b), and (c), or it may include steps (a), (c), and (b), or it may include steps (c), (a), and (b), etc.

[0166] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A data acquisition device for power line communication, characterized in that, Applied in a power line communication chip that includes a receiving link, the receiving link comprising multiple signal processing nodes, the data acquisition device includes: A node register is used to store a node identifier written by the central processing unit. The node identifier is used to indicate the target node in the receiving link for collecting data. A multiplexer, connected to the node register, is used to select the signal data output by the target node according to the node identifier, and transmit the signal data to the data acquisition and control module. The data acquisition and control module is connected to the multiplexer and is used to receive the signal data output by the target node and write the signal data into the system memory so that the central processing unit can read the signal data and perform anomaly location on the receiving link. A trigger source selection register, connected to the data acquisition control module, is used to store the trigger source type configured by the central processing unit; the trigger source type includes at least one of a receive enable signal, a synchronization start signal, or a synchronization completion signal; The data acquisition and control module is also used to write the signal data output by the target node into the system memory when it receives a trigger signal generated by the communication state control logic in the receiving link and corresponding to the trigger source type.

2. The data acquisition device for power line communication according to claim 1, characterized in that, The signal processing node includes at least one analog signal processing node; the data acquisition device further includes: An analog-to-digital converter, connected to the multiplexer, is used to convert the analog signal data output by the target node into digital signal data when the target node is an analog signal processing node, so that the multiplexer can transmit it to the data acquisition and control module.

3. The data acquisition device for power line communication according to claim 1, characterized in that, The data acquisition device also includes: A length configuration register, connected to the data acquisition control module, is used to store the data length value written by the central processing unit, so as to control the data acquisition control module to stop writing after the data length written to the system memory reaches the data length value.

4. The data acquisition device for power line communication according to claim 1 or 3, characterized in that, The data acquisition control module is further configured to store the system memory write address of the data tail after writing the signal data according to the configured data length value; the data acquisition device also includes: The address latch register is connected to the data acquisition control module and is used to receive the system memory write address transmitted by the data acquisition control module and latch the system memory write address so that the central processing unit can determine the end position of the signal data.

5. The data acquisition device for power line communication according to claim 1, characterized in that, The data acquisition device also includes: The acquisition switch register, connected to the data acquisition control module, is used to turn on or off the output channel of the data acquisition control module according to the control instructions written by the central processing unit, so as to control whether the data acquisition control module writes the signal data output by the target node into the system memory.

6. The data acquisition device for power line communication according to claim 1, characterized in that, The data acquisition device also includes: At least one status register is connected to the data acquisition control module and is used to store the status flag value automatically written when each signal processing node in the receiving link completes processing; wherein, each status register corresponds one-to-one with each trigger source type; The data acquisition and control module is also used to monitor the change of the status flag value of the status register corresponding to the trigger source type based on the trigger source selection register, so as to trigger the writing of the signal data into the system memory.

7. The data acquisition device for power line communication according to claim 6, characterized in that, The data acquisition device also includes: A trigger source edge selection register, connected to the data acquisition control module, is used to store the trigger edge type configured by the central processing unit; wherein, the trigger edge type includes either a rising edge or a falling edge; The data acquisition and control module is also used to monitor the change of the status flag value in the status register corresponding to the trigger source type based on the trigger source type configured in the trigger source selection register, and write the signal data output by the target node into the system memory when the status flag value changes along the trigger edge type.

8. The data acquisition device for power line communication according to claim 1, characterized in that, The data acquisition device also includes: A data acquisition mode configuration register, connected to the data acquisition control module, is used to store the acquisition mode type configured by the central processing unit; wherein, the acquisition mode type includes either a cyclic coverage mode or a single acquisition mode; The data acquisition control module is configured as follows: When the acquisition mode type is cyclic overwrite mode, the original data is overwritten when the signal data output by the target node is written to the system memory; When the acquisition mode type is single acquisition mode, it stops after writing one signal data until the conditions for a new round of acquisition are triggered. The acquisition start condition includes at least the following: the status flag value stored in the monitored status register changes along the trigger edge type configured by the central processing unit.

9. A power line communication chip, characterized in that, The power line communication chip includes: The receiving link contains multiple signal processing nodes for processing communication signals received through the power line, and each processing node outputs corresponding signal data. The data acquisition device for power line communication as described in any one of claims 1 to 8 is configured to acquire signal data output by any processing node according to a configuration and write it into system memory so that the central processing unit can read the signal data and perform anomaly location on the receiving link.

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