Serial communication protocol analysis method and system based on mixed state machine architecture

Abstract

The invention discloses a serial communication protocol analysis method based on a mixed state machine architecture, which comprises the following steps that: a main state machine receives and detects serial data in a detection state, and identifies an instruction type of the serial data; the main state machine analyzes and verifies the serial data based on the instruction type to generate a trigger signal; and the response state machine performs response assembly after receiving the trigger signal, and outputs response data after obtaining the response data. The invention also discloses a serial communication protocol analysis system based on the hybrid state machine architecture, computer equipment and a storage medium. The method has the advantages that the main state machine and the response state machine work in parallel, communication delay is reduced, the bit error rate and maintenance cost are reduced, and microsecond-level response is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of protocol analysis, and in particular to a serial communication protocol analysis method and system based on a hybrid state machine architecture. Background Art

[0002] The Modbus protocol, a commonly used serial communication protocol in industrial communications, is widely used in fields such as intelligent manufacturing and automated control. Its core function is to implement data frame parsing, command execution, and response between master and slave devices. Traditional solutions often use a single state machine design, mixing logic such as data reception, protocol parsing, and response generation within the same state machine. This results in a complex code structure and poor readability. Adding new features or modifying logic can easily lead to communication failures, resulting in high maintenance costs and significant communication delays. This is especially true when multiple devices are communicating concurrently, making it difficult to meet the microsecond-level response requirements of industrial scenarios. Summary of the Invention

[0003] The technical problem to be solved by the embodiments of the present invention is to provide a serial communication protocol parsing method and system based on a hybrid state machine architecture, which adopts the main state machine and the response state machine to work in parallel, reduce communication delays, lower bit error rates and maintenance costs, and achieve microsecond-level response.

[0004] In order to solve the above technical problems, the present invention provides a serial communication protocol parsing method based on a hybrid state machine architecture, comprising:

[0005] The main state machine receives and detects the serial data in the detection state, and identifies the instruction type of the serial data;

[0006] The main state machine parses and verifies the serial data based on the instruction type and generates a trigger signal;

[0007] The response state machine performs response assembly after receiving the trigger signal, and outputs the response data after obtaining it.

[0008] In a feasible implementation, the main state machine receives and detects the serial data in the detection state, and identifies the instruction type of the serial data, including:

[0009] It is determined whether the main state machine can detect a valid frame header within a set time period. If so, the instruction type is output; if not, the main state machine is reset to the detection state.

[0010] In a feasible implementation, parsing and verifying the serial data based on the instruction type to generate the trigger signal includes:

[0011] Determine, based on the instruction type, to perform a corresponding data operation on the serial data, and obtain a local check code by calculation;

[0012] The received target check code is compared with the local check code. If the comparison results are consistent, the trigger signal is generated and the data in the shared data buffer is updated. If the comparison results are inconsistent, the main state machine is reset to the detection state.

[0013] In a feasible implementation, the determining, based on the instruction type, to perform a corresponding data operation on the serial data includes:

[0014] When the instruction type is a read instruction, the main state machine enters a read data state to extract the target data length; or,

[0015] When the instruction type is a single write instruction, the main state machine enters a single data write state to write a single data; or,

[0016] When the instruction type is a multi-write instruction, the main state machine enters a multi-data amount extraction state to extract multiple data lengths, and then enters a multi-data writing state to perform multi-data cyclic writing.

[0017] In a feasible implementation, the shared data buffer includes a readable and writable area for storing dynamic data and a read-only area for storing static data.

[0018] In a feasible implementation, the response state machine performs response assembly after receiving the trigger signal and outputs the response data after obtaining the response data, including:

[0019] The response state machine detects the trigger signal in an idle state;

[0020] generating a corresponding response frame header based on the trigger signal;

[0021] Generate a response data frame based on the response frame header;

[0022] Performing a checksum calculation on the response data frame to generate an additional checksum;

[0023] The additional check code is added to the end of the response data frame to obtain the response data.

[0024] In a feasible implementation, the response state machine obtains the response data and outputs it through a data buffer module, and the data buffer module outputs the response data to the physical layer interface in a first-in-first-out queue order.

[0025] Accordingly, the present invention also provides a serial communication protocol parsing system based on a hybrid state machine architecture, comprising:

[0026] The main state machine is used to receive and parse serial data and generate trigger signals;

[0027] The response state machine is used to receive and assemble a response according to the trigger signal and output response data.

[0028] Accordingly, the present invention also provides a computer device, comprising at least one processor and at least one memory; wherein, at least one of the memories is used to store computer instructions, and at least one of the processors is used to execute at least part of the computer instructions to implement the steps of the described method.

[0029] Accordingly, the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed, the steps of the method described are implemented.

[0030] The implementation of the present invention has the following beneficial effects:

[0031] The main state machine and the response state machine work in parallel to reduce communication delays, lower bit error rates and maintenance costs, and achieve microsecond-level response.

[0032] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application, and do not constitute an improper limitation on the present application.

[0034] Figure 1 It is a step diagram of the serial communication protocol parsing method based on the hybrid state machine architecture of the present invention;

[0035] Figure 2 This is a diagram showing the specific steps of parsing and verifying serial data according to the present invention;

[0036] Figure 3 This is a diagram of the steps of the response state machine of the present invention performing response assembly after receiving a trigger signal;

[0037] Figure 4 It is an architectural diagram of a serial communication protocol parsing system based on a hybrid state machine architecture of the present invention;

[0038] Figure 5 It is a state transition flow chart of the main state machine of the present invention;

[0039] Figure 6 It is a state transition flow chart of the response state machine of the present invention. DETAILED DESCRIPTION

[0040] To make the above-mentioned objects, features, and advantages of the present invention more readily apparent, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. The following description sets forth numerous specific details to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art may make similar modifications without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0041] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly attached to the other element or there may be an intermediate element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0043] The present invention provides a serial communication protocol parsing method based on a hybrid state machine architecture, referring to Figure 1 ,include,

[0044] Step S100: The main state machine 1 receives and detects serial data in the detection state, and identifies the instruction type of the serial data;

[0045] Step S200: The main state machine 1 parses and verifies the serial data based on the instruction type and generates a trigger signal;

[0046] Step S300: After receiving the trigger signal, the response state machine 2 performs response assembly and outputs the response data after obtaining it.

[0047] Specifically, the present invention provides a serial communication protocol parsing method based on a hybrid state machine architecture, which adopts a main state machine 1 and a response state machine 2 to work in parallel, reduce communication delay, lower bit error rate and maintenance cost, and achieve microsecond-level response.

[0048] In a feasible implementation, the main state machine 1 receives and detects serial data in the detection state, and identifies the instruction type of the serial data, including:

[0049] Determine whether the main state machine 1 can detect a valid frame header within a set time period. If yes, output the instruction type. If not, reset the main state machine 1 to the detection state.

[0050] Specifically, a timeout counter (time_cnt) monitors the idle interval between characters, complying with the physical layer frame start rules of the Modbus RTU protocol. If the master state machine 1 times out and fails to detect a frame header, it resets, preventing invalid data from occupying resources and ensuring that the master state machine 1 is always in the ready state.

[0051] In a feasible implementation, serial data is parsed and verified based on the instruction type, and a trigger signal is generated. Figure 2 ,include,

[0052] Step S201, determining to perform a corresponding data operation on the serial data based on the instruction type, and obtaining a local check code by calculation;

[0053] Step S202 , the received target check code is compared with the local check code. If the comparison results are consistent, a trigger signal is generated and the data in the shared data buffer 3 is updated. If the comparison results are inconsistent, the main state machine 1 is reset to the detection state.

[0054] Specifically, differentiated processing of different instructions is achieved through state transfer of the main state machine 1 (such as S_R_NUM, S_W_DATA_S), and the hardware parallel characteristics ensure fast response to multiple instructions.

[0055] The CRC (Cyclic Redundancy Check) verification mechanism is used to calculate the CRC value of valid data (frame header, address, data, etc.), compare it with the received check code, and use mathematical redundancy check to detect transmission errors.

[0056] CRC checking reduces bit error rates to extremely low levels, ensuring the integrity of instructions and data executed by the slave device. FPGA (Field-Programmable Gate Array) hardware logic handles instruction parsing and verification in parallel, avoiding the serial latency of traditional MCUs and achieving microsecond-level response times.

[0057] In one feasible implementation, determining to perform a corresponding data operation on the serial data based on the instruction type includes:

[0058] When the instruction type is a read instruction, the main state machine 1 enters the read data state to extract the target data length; or,

[0059] When the instruction type is a single write instruction, the main state machine 1 enters the single data write state to write single data; or,

[0060] When the instruction type is a multi-write instruction, the main state machine 1 enters the multi-data amount extraction state to extract the multi-data length, and then enters the multi-data writing state to perform multi-data cyclic writing.

[0061] Specifically, refer to Figure 5 S_START is the starting state, used to monitor the data input from the RS485 interface and detect whether there is a valid frame header (Frame_header). If a valid frame header is detected, it enters the S_STYE state. If a valid frame header is not detected within the specified time (determined to have timed out, as determined by time_cnt), or if an invalid command is received, it remains in the S_START state and continues to detect.

[0062] S_STYE is the instruction type identification state. After entering this state, the main state machine 1 parses the received data frame containing the frame header to identify whether the instruction type is a read instruction or a write instruction. After the identification is completed, the state machine enters the S_ADDR0 state.

[0063] S_ADDR0 is the address resolution state, in which the target address information in the data frame is extracted to determine the operation object. At the same time, further branch processing is performed according to the instruction type:

[0064] Read instruction situation: If it is recognized as a read instruction (Frame_read), it enters the S_R_NUM state.

[0065] Single write instruction case: If it is a single write instruction (Frame_write_s), it enters the S_W_DATA_S state.

[0066] Multiple write instruction situation: If it is a multiple write instruction (Frame_write_m), it enters the S_W_NUM state.

[0067] S_R_NUM is the read instruction data length extraction state. For read instructions, this state extracts the data length to be read (S_Frame_rd_num). After the extraction is completed, the state enters the S_CRC state.

[0068] S_W_DATA_S is the single write instruction data write state. For a single write instruction, data is written to the specified location in this state. The written data is S_Frame_wr_s_data. After the write operation is completed, the state enters S_CRC.

[0069] S_W_NUM is the state for extracting the data length of the multi-write instruction. When it is a multi-write instruction, this state extracts the length of the multi-data to be written (S_Frame_wr_m_num). After the extraction is completed, it enters the S_W_DATA_M state.

[0070] S_W_DATA_M is the data writing state of the multi-write instruction. For the multi-write instruction, a cyclic writing operation of multiple data is performed. After the data writing is completed, it enters the S_CRC state.

[0071] S_CRC is the CRC check state. It receives the CRC check code in the data frame and performs a CRC check calculation on the valid part of the previously received data frame (excluding the CRC check code). If the calculated CRC value is consistent with the received CRC check code (crc_out = 0), it means that the CRC check is successful and the state enters S_check; if they are inconsistent (crc_out ≠ 0), it means that the CRC check failed and the state returns to S_START to restart the detection.

[0072] S_check is the check success confirmation state. This state confirms that the CRC check is successful, indicating that the data frame is complete and has not been tampered with. Subsequent processing, such as updating the shared data buffer 3, can be performed. After completing the corresponding processing, the main state machine 1 can continue to wait for receiving new data frames or perform other related operations as needed.

[0073] Each of these states is equipped with a timeout counter to reset to the initial state after a timeout, preventing deadlock. The entire main state machine 1, through the orderly transition and processing of these states, implements the complete flow of Modbus data frames, from reception, command recognition, address resolution, data processing, to CRC verification. This ensures that only valid data frames that pass verification are further processed, guaranteeing the reliability and accuracy of communication.

[0074] In a feasible implementation, the shared data buffer 3 includes a readable and writable area for storing dynamic data and a read-only area for storing static data.

[0075] Specifically, on the one hand, the shared data buffer 3 is used to store data that has passed the CRC check of the main state machine 1, and the response state machine 2 can also read data from the shared data buffer 3. On the other hand, the data generated by the main state machine 1 during the process of executing data detection, address resolution, CRC check, etc. can be temporarily stored in the shared data buffer 3.

[0076] More specifically, dynamic data and static data are stored separately, and master-slave state machine data synchronization is achieved through the mb_Frame_data_update flag to avoid read and write conflicts.

[0077] The readable and writable area is 0-511 bytes, and the read-only area is 512-768 bytes. The size of the readable and writable area can be dynamically adjusted to meet the data storage requirements of different instructions (such as batch data of multiple write instructions).

[0078] The read-only nature of static data reduces the loss of frequent reads and writes, while the dynamic data area supports rapid updates, improving data interaction efficiency. The partition design reduces the risk of data confusion, especially in scenarios with multiple concurrent instructions, ensuring data consistency.

[0079] In a feasible implementation, the response state machine 2 receives the trigger signal and performs response assembly, and outputs the response data after obtaining the response data. Figure 3 ,include,

[0080] Step S301, the response state machine 2 detects a trigger signal in the idle state;

[0081] Step S302: Generate a corresponding response frame header based on the trigger signal;

[0082] Step S303, generating a response data frame based on the response frame header;

[0083] Step S304, performing a check calculation on the response data frame to generate an additional check code;

[0084] Step S305: Add the additional check code to the end of the response data frame to obtain response data.

[0085] Specifically, refer to Figure 6 rt_state0 represents the idle state, waiting for the trigger signal. After receiving the read request trigger signal (mb_Frame_rd_req) or write request trigger signal (mb_Frame_wr_req) sent by the main state machine 1, it enters different branch processes respectively.

[0086] Read request branch: rt_state_r_head generates a read response frame header, which contains information such as the slave device address and function code. This provides the basis for subsequent data reading and the construction of a complete response frame. The frame header is the beginning of the response frame and clarifies the basic attributes of the response. After completion, it enters rt_state1.

[0087] rt_state1 is used to complete data reading. Based on the read request, data is read from the shared data buffer 3 data_buffer according to the address (rt_rd_addr_max). The data content requested by the master device is obtained, and the response frame contains valid data information, and then enters the rt_state3 state.

[0088] Write request branch: rt_state_w_head is used to generate a write response frame header, which contains information such as the slave device address and function code, indicating the response attributes of the write operation. It determines the basic format and identification of the write response, providing the prerequisite for subsequent packaging confirmation information. After completion, it enters rt_state2.

[0089] rt_state2 is the state of encapsulated confirmation information, such as the flag of write success or failure, etc. The result information of the write operation is integrated into the response frame so that the master device can understand the execution status of the write operation, and then enters rt_state3.

[0090] rt_state3 performs a CRC check on the data portion of a read or write response (including the frame header, read data, or confirmation information), generates a CRC checksum (rt_crc_out), and appends it to the end of the response frame. This ensures the integrity of the response frame during transmission and prevents data tampering. The state then enters rt_state4.

[0091] rt_state4 is used to send a complete response frame including the CRC check code through the RS485 interface, so that the master device receives the response information from the slave device, completing a communication interaction, and then enters rt_state5.

[0092] rt_state5 is the return to idle state. Response state machine 2 returns to the initial idle state and waits for the next trigger signal. It is ready for the next response request and can respond to the new trigger signal sent by main state machine 1 at any time.

[0093] A timeout counter is set in each of the above states to reset to the initial state after timeout to avoid deadlock.

[0094] In a feasible implementation, after the response state machine 2 obtains the response data, it outputs it through the data buffer module, and the data buffer module outputs the response data to the physical layer interface 4 in the order of the first-in-first-out queue.

[0095] Specifically, the response state machine 2 works in parallel with the main state machine 1. When the main state machine 1 processes a new frame, the response state machine 2 can synchronously send the previous response, using the parallel characteristics of the FPGA to improve throughput.

[0096] The data buffer module is a FIFO hardware queue that ensures response frames are sent in first-in, first-out order, complying with the serial transmission requirements of the Modbus RTU protocol and avoiding bus conflicts. A dual-state machine processes requests and responses in parallel, supporting high-concurrency communications in multi-device polling scenarios.

[0097] A serial communication protocol parsing system based on a hybrid state machine architecture, referring to Figure 4 ,include,

[0098] Main state machine 1, used to receive and parse serial data and generate trigger signals;

[0099] The response state machine 2 is used to receive and assemble responses according to the trigger signal and output response data.

[0100] Specifically, the present invention provides a serial communication protocol parsing system based on a hybrid state machine architecture. The system includes a master state machine 1 (responsible for parsing) and a response state machine 2 (responsible for responding). The system is implemented using a hardware description language (such as Verilog) on ​​an FPGA chip. The master state machine 1 focuses on protocol parsing, while the response state machine 2 focuses on data transmission, decoupling complex logic and reducing maintenance complexity.

[0101] The main state machine 1 and the response state machine 2 work in parallel to reduce communication delay, lower bit error rate and maintenance cost, and achieve microsecond-level response.

[0102] Leveraging the gate-level parallelism of FPGAs, this approach replaces the traditional MCU's software serial processing, breaking through CPU resource bottlenecks. Its modular design allows adding new features (such as custom function codes) by simply expanding independent state machines without modifying the core logic. Dynamic allocation of logic resources (such as optimizing circuits for 03 / 06 / 16 function codes) adapts to the needs of diverse industrial scenarios.

[0103] A computer device includes at least one processor and at least one memory; wherein the at least one memory is used to store computer instructions, and the at least one processor is used to execute at least part of the computer instructions to implement the steps of a method.

[0104] A computer-readable storage medium stores a computer program, which implements the steps of the method when the computer program is executed.

[0105] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0106] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A serial communication protocol parsing method based on a hybrid state machine architecture, characterized in that: include, The main state machine receives and detects the serial data in the detection state, and identifies the instruction type of the serial data; The main state machine parses and verifies the serial data based on the instruction type and generates a trigger signal; The response state machine performs response assembly after receiving the trigger signal, and outputs the response data after obtaining it.

2. The serial communication protocol parsing method based on the hybrid state machine architecture according to claim 1, characterized in that: The main state machine receives and detects the serial data in the detection state, and identifies the instruction type of the serial data, including: It is determined whether the main state machine can detect a valid frame header within a set time period. If so, the instruction type is output; if not, the main state machine is reset to the detection state.

3. The serial communication protocol parsing method based on a hybrid state machine architecture according to claim 1, characterized in that: said parsing and verifying the serial data based on the instruction type to generate the trigger signal, include, Determine, based on the instruction type, to perform a corresponding data operation on the serial data, and obtain a local check code by calculation; The received target check code is compared with the local check code. If the comparison results are consistent, the trigger signal is generated and the data in the shared data buffer is updated. If the comparison results are inconsistent, the main state machine is reset to the detection state.

4. The serial communication protocol parsing method based on a hybrid state machine architecture according to claim 3, characterized in that: The determining, based on the instruction type, to perform a corresponding data operation on the serial data includes: When the instruction type is a read instruction, the main state machine enters a data read state to extract the target data length; or, When the instruction type is a single write instruction, the main state machine enters a single data write state to write a single data; or, When the instruction type is a multi-write instruction, the main state machine enters a multi-data amount extraction state to extract multiple data lengths, and then enters a multi-data writing state to perform multi-data cyclic writing.

5. The serial communication protocol parsing method based on a hybrid state machine architecture according to claim 3, characterized in that: The shared data buffer includes a readable and writable area for storing dynamic data and a read-only area for storing static data.

6. The serial communication protocol parsing method based on a hybrid state machine architecture according to claim 1, characterized in that: The response state machine performs response assembly after receiving the trigger signal and outputs the response data after obtaining the response data, including: The response state machine detects the trigger signal in an idle state; generating a corresponding response frame header based on the trigger signal; Generate a response data frame based on the response frame header; Performing a checksum calculation on the response data frame to generate an additional checksum; The additional check code is added to the end of the response data frame to obtain the response data.

7. The serial communication protocol parsing method based on a hybrid state machine architecture according to claim 1, characterized in that: After receiving the response data, the response state machine outputs the response data through a data buffer module. The data buffer module outputs the response data to the physical layer interface in a first-in-first-out queue order.

8. A serial communication protocol parsing system based on a hybrid state machine architecture, characterized in that: include, The main state machine is used to receive and parse serial data and generate trigger signals; The response state machine is used to receive and assemble a response according to the trigger signal and output response data.

9. A computer device, characterized in that: The system comprises at least one processor and at least one memory; wherein at least one of the memories is used to store computer instructions, and at least one of the processors is used to execute at least part of the computer instructions to implement the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The storage medium stores a computer program, which, when executed, implements the steps of the method according to any one of claims 1 to 7.

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