Interference signal generation system and method based on PXIe bus

Abstract

The invention discloses an interference signal generation system and method based on a PXIe bus, and belongs to the technical field of wireless communication testing. According to the invention, the problems of transmission bandwidth bottleneck, incapability of generating intelligent interference associated with communication signals in real time, large size of interference source equipment and poor configuration flexibility in the traditional method are solved. The method can be used for generating conventional interference and also can be used for generating aperiodic intelligent interference, and complex aperiodic intelligent interference associated with communication signals is generated in real time in dynamic scene simulation. And the PXIe system supports various operating systems and programming languages, so that a user can freely select a proper development environment to develop and test the upper computer, and a larger transmission bandwidth can be obtained based on the PXIe bus. Multi-channel emission can be realized by arranging a plurality of PXIe interference generation modules in the PXIe case, and the flexibility of system configuration is greatly improved. The method can be applied to the field of interference signal generation.

Description

Technical Field

[0001] The present invention belongs to the technical field of wireless communication testing, and in particular relates to an interference signal generation system and a generation method based on a PXIe bus. Background Art

[0002] With the rapid development of technologies like 5G / 6G communications and satellite internet, modern wireless devices face increasingly complex electromagnetic interference environments. According to the 3GPP TS 37.104 standard, 5G base stations must maintain normal communication within an adjacent channel leakage ratio (ACLR ≤ -45dBc). This requires the use of high-performance interference sources to generate interference signals to complete preliminary testing. However, traditional periodic interference struggles with frequency-hopping communications. Aperiodic interference, on the other hand, dynamically matches the frequency hopping pattern and suppresses key communication nodes. Therefore, aperiodic intelligent interference generation technology is crucial for effectively addressing frequency-hopping communications.

[0003] However, the prior art still has the following defects:

[0004] (1) Traditional interference sources are mostly based on universal buses such as USB or LAN. The theoretical bandwidth of USB 3.0 is less than 5Gbps (often less than 3Gbps in practice), and the theoretical bandwidth of Gigabit Ethernet is less than 1Gbps (often less than 800Mbps in practice). Therefore, traditional interference sources have a transmission bandwidth bottleneck.

[0005] (2) In dynamic scenario simulations, it is often necessary to generate intelligent interference associated with communication signals in real time (such as AI-based cognitive interference waveforms). The generation of intelligent interference requires the synchronous control of multiple parameters such as frequency, power, and modulation mode, which is obviously impossible with traditional interference sources.

[0006] (3) Traditional interference source equipment is large in size and has poor configuration flexibility. The cost of channel expansion increases exponentially (each additional channel requires the purchase of an additional complete machine, which increases the cost significantly), and it is impossible to achieve sub-nanosecond trigger synchronization between multiple devices. Summary of the Invention

[0007] The purpose of the present invention is to solve the problems of traditional methods such as transmission bandwidth bottleneck, inability to generate intelligent interference associated with communication signals in real time, large size of interference source equipment and poor configuration flexibility, and propose an interference signal generation system and generation method based on PXIe bus.

[0008] The technical solution adopted by the present invention to solve the above technical problems is:

[0009] An interference signal generation system based on a PXIe bus, the system comprising a main control module, a PXIe interference generation module and a data acquisition module;

[0010] The PXIe interference generation module includes a signal generation submodule, a radio frequency front-end submodule and a memory;

[0011] The signal generation submodule includes an XDMA core, an instruction parsing unit, an interference signal generation unit, a memory interface unit, a read control unit, and a DAC driver unit; the RF front-end submodule includes a DAC chip and an analog conditioning circuit;

[0012] When you need to generate periodic interference:

[0013] The main control module sets the interference type, frequency, power, and trigger control parameters through the configuration interface of the host computer. After encoding the set parameters into a configuration frame, the configuration frame is sent to the PXIe interference generation module through the XDMA_user channel.

[0014] The XDMA core is used to perform mapping conversion on the configuration frame, and the instruction parsing unit is used to parse the configuration parameters in the configuration frame after mapping conversion and send the configuration parameters to the interference signal generating unit;

[0015] The interference signal generating unit is used to generate a baseband interference signal according to the configuration parameters, and forward the baseband interference signal and the radio frequency parameters of the baseband interference signal to the DAC driving unit;

[0016] The DAC driver unit is used to provide an interface for the DAC chip to transmit baseband interference signals and radio frequency information. The DAC chip is used to perform digital-to-analog conversion and up-conversion processing on the received baseband interference signals according to the radio frequency information. The up-converted signal then passes through the analog conditioning circuit, and the output of the analog conditioning circuit is output to the outside.

[0017] When you need to generate non-periodic interference:

[0018] The data acquisition module is used to collect spectrum information of the communication signal and send the collected spectrum information to the main control module;

[0019] The main control module calls the intelligent interference generation algorithm through the host computer to generate the baseband signal waveform data of the interference signal and the configuration frame containing the frequency and power information of the interference signal in real time. The host computer sends the configuration frame containing the frequency and power information of the interference signal to the XDMA core, and the host computer sends the baseband signal waveform data of the interference signal to the memory;

[0020] The XDMA core is used to map and convert the configuration frame, and the instruction parsing unit is used to parse the mapped configuration frame to obtain radio frequency information including the frequency and power of the interference signal, and send the radio frequency information to the DAC driving unit;

[0021] The memory interface unit is used to implement storage and reading of data in the memory;

[0022] The DAC driving unit reads data from the memory through the read control unit. The DAC driving unit is used to provide an interface for the DAC chip to transmit baseband interference signals and radio frequency information. The DAC chip is used to perform digital-to-analog conversion and up-conversion processing on the received baseband interference signal according to the radio frequency information. The signal after up-conversion processing then passes through the analog conditioning circuit, and the output of the analog conditioning circuit is output to the outside.

[0023] A method for generating an interference signal based on a PXIe bus, the method specifically comprising the following steps:

[0024] Step 1: The user selects the non-periodic interference type in the configuration interface of the host computer and triggers it to start;

[0025] Step 2: The host computer calls the intelligent interference generation algorithm to generate the baseband signal waveform data of the interference signal and the configuration frame containing the interference parameters of the interference signal in real time according to the communication signal spectrum information collected by the data acquisition module;

[0026] Step 3: The host computer sends the configuration frame to the XDMA core through the XDMA_user channel. After the configuration frame is converted by the XDMA core, the instruction parsing unit is used to parse the converted configuration frame to obtain the RF information of the interference signal.

[0027] The host computer caches the baseband signal waveform data of the interference signal into the memory through the XDMA_dma channel;

[0028] Step 4. When the system is running, the DAC driver unit reads the baseband signal waveform data from the asynchronous FIFO read port of the read control unit at the DAC interface rate, and sends the baseband signal waveform data to the DAC chip. The DAC chip then performs digital-to-analog conversion and up-conversion processing on the baseband signal waveform data in sequence. The up-converted signal then passes through the analog conditioning circuit, and the analog conditioning circuit uses the analog conditioning circuit to filter and amplify the up-converted signal before outputting it to the outside.

[0029] A method for generating an interference signal based on a PXIe bus, the method specifically comprising the following steps:

[0030] Step 1: Parameter setting:

[0031] After the user enters the host computer main interface, he or she can set the interference signal type, frequency, power and trigger control parameters in the host computer configuration interface;

[0032] Step 2: Generate configuration frame:

[0033] The host computer generates a configuration frame based on the user's configuration parameters. Each field in the configuration frame corresponds to a configuration parameter.

[0034] Step 3: Configure frame sending:

[0035] The host computer sends the configuration frame to the XDMA core in the PXIe interference generator module through the XDMA_user channel. The instruction parsing unit then parses the configuration frame after the XDMA core mapping conversion to obtain the configuration parameters corresponding to each field in the configuration frame.

[0036] The parsed configuration parameters are then sent to the interference signal generation unit in the PXIe interference generation module, and the baseband digital interference signal is synthesized in the interference signal generation unit according to the configuration parameters;

[0037] Step 4: Digital-to-analog conversion and amplification:

[0038] The interference signal generation unit sends the synthesized baseband digital interference signal and RF parameters to the DAC driving unit. After the DAC driving unit sends the baseband digital interference signal and RF parameters to the DAC chip, the DAC chip is used to perform digital-to-analog conversion and up-conversion processing on the received baseband interference signal in sequence. The up-converted signal then passes through the analog conditioning circuit, and the analog conditioning circuit is used to filter and amplify the signal before outputting it to the outside.

[0039] The beneficial effects of the present invention are:

[0040] (1) The present invention is a programmable broadband intelligent interference generation system based on the PXIe architecture. Data transmission is based on the PCIe 2.0 / 3.0 protocol, with a high transmission rate of 500MB / Lane and above. Compared with traditional solutions, the transmission rate of the present invention is significantly improved, multiple parameters can be configured simultaneously, and the interference parameter reconfiguration time is reduced from seconds to milliseconds.

[0041] (2) The broadband intelligent interference generation system based on the PXIe bus of the present invention has the characteristics of strong software compatibility. The PXIe system supports various operating systems and programming languages, allowing users to freely select the appropriate development environment for host computer development and testing. The PXIe bus can obtain a larger transmission bandwidth.

[0042] The method can be used to generate both conventional and aperiodic intelligent jamming, enabling real-time generation of complex aperiodic intelligent jamming associated with communication signals in dynamic scenario simulations. Dynamic adjustment of jamming parameters allows for precise suppression to maximize the jamming effect, resulting in a 30% to 50% improvement in bit error rate compared to conventional jamming.

[0043] (3) The arbitrary waveform generator based on the PXIe architecture of the present invention has good scalability compared with traditional interference signal generators. Multiple PXIe interference generation modules can be arranged in a PXIe chassis. The PXIe_CLK100 precision clock (jitter less than 50ps) can be used to synchronize multiple devices and realize 2 to 8 channel transmission. The interference source device is small in size and has good configuration flexibility. It also has broad application prospects in the fields of phased array radar and millimeter waves. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 This is a hardware topology diagram of an interference signal generation system based on a PXIe bus of the present invention;

[0045] Figure 2 This is the internal structure diagram of the FPGA of the signal generation unit;

[0046] Figure 3 This is a flow chart for generating conventional periodic interference;

[0047] Figure 4 It is a flow chart for generating complex non-periodic intelligent interference. DETAILED DESCRIPTION

[0048] Specific implementation method 1: Combination Figure 1 and Figure 2 This embodiment describes a PXIe bus-based interference signal generation system, which includes a main control module, a PXIe interference generation module, and a data acquisition module;

[0049] The PXIe interference generation module includes a signal generation submodule, a radio frequency front-end submodule and a memory (DDR3);

[0050] The signal generation submodule includes an XDMA core, an instruction parsing unit, an interference signal generation unit, a memory interface unit, a read control unit, and a DAC driver unit; the RF front-end submodule includes a DAC chip and an analog conditioning circuit;

[0051] When you need to generate periodic interference:

[0052] The main control module sets the interference type, frequency, power, and trigger control parameters through the configuration interface of the host computer. After encoding the set parameters into a configuration frame, the configuration frame is sent to the PXIe interference generation module through the XDMA_user channel.

[0053] The XDMA core implements the PCIe endpoint logic and is used to map and convert the configuration frame, that is, to convert the PCIe physical layer data packet to the AXI4 memory mapping. The instruction parsing unit has an AXI4-Lite slave interface and is used to parse the configuration parameters in the configuration frame after mapping and conversion and send the configuration parameters to the interference signal generation unit.

[0054] The interference signal generation unit contains multiple modulation engines. The interference signal generation unit is used to generate a baseband interference signal according to the configuration parameters, and forward the baseband interference signal and the RF parameters of the baseband interference signal (including frequency and power) to the DAC driver unit;

[0055] The DAC driver unit is used to provide an interface for the DAC chip to transmit baseband interference signals and radio frequency information. The DAC chip is used to perform digital-to-analog conversion and up-conversion processing on the received baseband interference signals according to the radio frequency information. The up-converted signal then passes through the analog conditioning circuit, and the output of the analog conditioning circuit is output to the outside.

[0056] When you need to generate non-periodic interference:

[0057] The data acquisition module is used to collect spectrum information of the communication signal and send the collected spectrum information to the main control module;

[0058] The main control module calls the intelligent interference generation algorithm through the host computer to generate the baseband signal waveform data of the interference signal and the configuration frame containing the frequency and power information of the interference signal in real time. The host computer sends the configuration frame containing the frequency and power information of the interference signal to the XDMA core, and the host computer sends the baseband signal waveform data of the interference signal to the memory;

[0059] The XDMA core is used to map and convert the configuration frame, and the instruction parsing unit is used to parse the mapped configuration frame to obtain radio frequency information including the frequency and power of the interference signal, and send the radio frequency information to the DAC driving unit;

[0060] The memory interface unit is used to implement storage and reading of data in the memory;

[0061] The DAC driving unit reads data from the memory through the read control unit. The DAC driving unit is used to provide an interface for the DAC chip to transmit baseband interference signals and radio frequency information. The DAC chip is used to perform digital-to-analog conversion and up-conversion processing on the received baseband interference signal according to the radio frequency information. The signal after up-conversion processing then passes through the analog conditioning circuit, and the output of the analog conditioning circuit is output to the outside.

[0062] The specific hardware model selection in the present invention is:

[0063] (1) The main control module of the present invention uses a PXIe-8880 controller to run the host computer software. It has an eight-core Intel Xeon processor with a base frequency of 2.3GHz.

[0064] (2) The signal generation submodule within the PXIe interference generation module of the present invention is implemented based on an FPGA, and the FPGA model selected is XC7K325T-2FFG900I. The memory uses a DDR3 chip with a 64-bit data width, a 2GB storage depth, and a read and write speed of 1600Mtps.

[0065] PXIe (PCI eXtensions for Instrumentation Express) is a high-performance modular instrument bus featuring high transmission rates, modular expansion, and strong software compatibility. Using the PXIe bus for interference signal generation effectively addresses the shortcomings of traditional interference sources. The PXIe bus offers up to 12 GB / s of transmission bandwidth. The PXIe bus allows users to flexibly program host applications to implement complex intelligent interference generation algorithms. Users can expand the number of channels by arranging multiple modules within the PXIe chassis. The PXIe_Timer hardware timing module is also supported for sub-nanosecond synchronization.

[0066] (3) The RF front-end submodule of the present invention includes an AD9361 high-speed DAC chip and an analog conditioning circuit, which has a 16-bit bit width, an output frequency range of 100 MHz to 6 GHz, and an output power range of -120 dBm to +20 dBm (digital attenuator step 0.1 dB).

[0067] Specific embodiment 2: This embodiment differs from specific embodiment 1 in that the main control module is connected to the PXIe interference generation module via a PXIe chassis backplane signal line. The PXIe interference generation module occupies a single slot width.

[0068] Other steps and parameters are the same as those in the first embodiment.

[0069] Specific embodiment three: This embodiment differs from specific embodiment one or two in that the analog conditioning circuit is used to sequentially filter and amplify the up-conversion processing result.

[0070] Other steps and parameters are the same as those in the first or second embodiment.

[0071] Specific embodiment 4: This embodiment differs from any one of specific embodiments 1 to 3 in that when generating non-periodic interference, the host computer sends a configuration frame containing the interference signal frequency and power information to the XDMA core through the XDMA_user channel.

[0072] The other steps and parameters are the same as those in the first to third embodiments.

[0073] Specific embodiment five: This embodiment differs from any one of specific embodiments one to four in that when generating aperiodic interference, the host computer sends the baseband signal waveform data of the interference signal to the memory via the XDMA_dma channel.

[0074] The other steps and parameters are the same as those in the first to fourth embodiments.

[0075] Specific embodiment six: This embodiment differs from any one of specific embodiments one to five in that the PXIe interference generation module also includes an XDMA interrupt control unit. After the XDMA interrupt control unit sends an XDMA interrupt request to the XDMA core, the memory receives the baseband signal waveform data of the interference signal through the XDMA_dma channel.

[0076] The other steps and parameters are the same as those in the first to fifth embodiments.

[0077] Specific implementation method seven: combination Figure 4 This embodiment describes a method for generating interference signals based on a PXIe bus. By analyzing electromagnetic environment data in real time to automatically identify characteristics such as the spectrum occupancy and modulation mode of the target communication system, intelligent interference associated with the communication signal can be generated. The specific process of the method is as follows:

[0078] Step 1: The user selects the non-periodic interference type in the configuration interface of the host computer and triggers it to start;

[0079] Step 2: The host computer calls the intelligent interference generation algorithm to generate the baseband signal waveform data of the interference signal and the configuration frame containing the interference parameters of the interference signal in real time based on the communication signal spectrum information collected by the data acquisition module (PXIe-4499);

[0080] Intelligent jamming generation algorithm achieves precise suppression by dynamically adjusting jamming parameters (such as frequency and power) to maximize jamming effect;

[0081] Step 3: The host computer sends the configuration frame to the XDMA core through the XDMA_user channel. After the configuration frame is converted by the XDMA core, the instruction parsing unit is used to parse the converted configuration frame to obtain the RF information of the interference signal.

[0082] The host computer caches the baseband signal waveform data of the interference signal into the memory through the XDMA_dma channel. The memory interface uses the MIG (Memory Interface Generator) IP core. The memory interface unit is used to access the waveform data sent by the host computer in the memory when complex non-periodic interference occurs.

[0083] Step 4. When the system is running, the DAC driver unit reads the baseband signal waveform data from the asynchronous FIFO read port of the read control unit at the DAC interface rate, and sends the baseband signal waveform data to the DAC chip. The DAC chip then performs digital-to-analog conversion and up-conversion processing on the baseband signal waveform data in sequence. The up-converted signal then passes through the analog conditioning circuit, and the analog conditioning circuit uses the analog conditioning circuit to filter and amplify the up-converted signal before outputting it to the outside.

[0084] Whenever the amount of baseband data in the asynchronous FIFO is insufficient (less than a certain number of sampling points), the read DMA of the read control unit generates an AXI4 read timing to read the baseband data from the memory into the asynchronous FIFO.

[0085] The intelligent interference generation module of the present invention is loaded with an interference generation program based on the Q-Learning algorithm. The system cooperates with the data acquisition module PXIe-4499 to collect electromagnetic environment data. The host computer runs the interference generation program based on the Q-Learning algorithm based on the data collected by the data acquisition module PXIe-4499 to generate baseband interference waveforms in real time. It also generates configuration frames in real time to adjust radio frequency parameters such as power and frequency. The host computer sends configuration frames in real time through the XDMA_user channel and sends large batches of baseband interference waveforms to the memory of the signal generation submodule through the XDMA_dma channel.

[0086] Verified in QPSK and 16QAM modulation scenarios, the complex non-periodic intelligent interference generated by the present invention based on the Q-Learning algorithm can improve the communication bit error rate by 50% compared with the fixed-power AWGN broadband noise interference.

[0087] Specific embodiment eight: This embodiment differs from specific embodiment seven in that the memory is divided into two storage areas of equal size to implement double buffering. The two storage areas are respectively denoted as BANK1 and BANK2;

[0088] The working process of the memory is:

[0089] Step 1: When the data in the storage area BANK1 of the memory is read out, the read control unit shifts the read address to the first address of the storage area BANK2 of the memory, and the read control unit simultaneously generates a flag signal to the XDMA interrupt control unit;

[0090] Step 2: After receiving the flag signal, the XDMA interrupt control unit sends an XDMA interrupt request to the XDMA core;

[0091] Step 3: The XDMA core sends a PCIe MSI interrupt message to the host computer. After receiving the PCIe MSI interrupt message, the host computer rewrites the baseband signal waveform data of the interference signal into the storage area BANK1 that has been read out.

[0092] Step 4: When the data in the storage area BANK2 of the memory is read out, the read control unit shifts the read address to the first address of the storage area BANK1 of the memory, and the read control unit simultaneously generates a flag signal to the XDMA interrupt control unit;

[0093] Step 5: After receiving the flag signal, the XDMA interrupt control unit sends an XDMA interrupt request to the XDMA core;

[0094] Step 6: The XDMA core sends a PCIe MSI interrupt message to the host computer. After receiving the PCIe MSI interrupt message, the host computer rewrites the baseband signal waveform data of the interference signal into the storage area BANK2 that has been read out.

[0095] Return to step 1.

[0096] Other steps and parameters are the same as those in the seventh embodiment.

[0097] The read control unit of the present invention internally includes an asynchronous FIFO and a read DMA. The read DMA is responsible for reading baseband data from the memory and writing it into the asynchronous FIFO according to the AXI4 bus timing. The read channel of the asynchronous FIFO is connected to the DAC driver unit, and data is continuously read out at the DAC interface rate. The present invention divides the area within the memory into two equal-sized storage areas, BANK1 and BANK2, each with a storage space of 1GB. The storage areas BANK1 and BANK2 within the memory perform a double-buffered ping-pong operation, and the read control unit and the host computer alternately read and write the two storage areas of the memory. When either storage area is read, the XDMA interrupt control unit pulls high the interrupt request signal connected to the XDMA core. The XDMA core sends an interrupt message to the host computer, which responds to the interrupt message and sends a data transmission. The host computer then sends a response signal to the XDMA interrupt control unit via the XDMA core, and the XDMA interrupt control unit pulls low the interrupt request signal. Combining PCIe MSI interrupt control with the double-buffer mechanism can achieve continuous transmission of interference signals.

[0098] Specific embodiment 9: This embodiment differs from specific embodiment 7 or 8 in that the intelligent interference generation algorithm is a Q-Learning algorithm.

[0099] Other steps and parameters are the same as those in the seventh or eighth embodiment.

[0100] Specific implementation method ten: Combination Figure 3 This embodiment describes a method for generating an interference signal based on a PXIe bus, and the specific process of the method is as follows:

[0101] Step 1: Parameter setting:

[0102] After the user enters the host computer main interface, he or she can set the interference signal type, frequency, power and trigger control parameters in the host computer configuration interface;

[0103] Step 2: Generate configuration frame:

[0104] The host computer generates a configuration frame based on the user's configuration parameters. Each field in the configuration frame corresponds to a configuration parameter. The configuration frame consists of: 2 bytes of interference type + 4 bytes of frequency + 2 bytes of power control + 1 byte of trigger control.

[0105] Step 3: Configure frame sending:

[0106] The host computer sends the configuration frame to the XDMA core in the PXIe interference generator module through the XDMA_user channel. The instruction parsing unit then parses the configuration frame after the XDMA core mapping conversion to obtain the configuration parameters corresponding to each field in the configuration frame.

[0107] The parsed configuration parameters are then sent to the interference signal generation unit in the PXIe interference generation module, and the baseband digital interference signal is synthesized in the interference signal generation unit according to the configuration parameters;

[0108] Step 4: Digital-to-analog conversion and amplification:

[0109] The interference signal generation unit sends the synthesized baseband digital interference signal and RF parameters to the DAC driver unit. After the DAC driver unit sends the baseband digital interference signal and RF parameters to the DAC chip, the DAC chip is used to perform digital-to-analog conversion and up-conversion processing on the received baseband interference signal in sequence. The up-converted signal then passes through the analog conditioning circuit, and the analog conditioning circuit uses the signal to filter and amplify (amplify to the required power level by the RF amplifier) ​​before outputting it to the outside.

[0110] The present invention needs to be powered on before executing step 1, and the software and hardware initialization is completed after powering on:

[0111] Check if a PCIe device (XDMA hardware) is inserted: Check the device nodes (user, dma, event) that XDMA should be enabled. If not all XDMA device nodes are found, a "initialization failed" prompt window will pop up; if the device is detected, perform another link read and write test;

[0112] Verify under all available user channels and DMA channels (including H2C channels and C2H channels): whether the data written to a certain address of the device matches the data read from the address. If they match, the system enters the host computer main interface; if not, a "Data Link Error" prompt window pops up.

[0113] The above examples are merely illustrative of the calculation model and process of the present invention and are not intended to limit the embodiments of the present invention. Persons skilled in the art will readily appreciate that other variations or modifications based on the above description are possible. This list of embodiments is not exhaustive; however, any obvious variations or modifications derived from the technical solution of the present invention remain within the scope of protection of the present invention.

Claims

1. The interference signal generation system based on PXIe bus is characterized by: The system includes a main control module, a PXIe interference generation module and a data acquisition module; The PXIe interference generation module includes a signal generation submodule, a radio frequency front-end submodule and a memory; The signal generation submodule includes an XDMA core, an instruction parsing unit, an interference signal generation unit, a memory interface unit, a read control unit, and a DAC driver unit; the RF front-end submodule includes a DAC chip and an analog conditioning circuit; When you need to generate periodic interference: The main control module sets the interference type, frequency, power, and trigger control parameters through the configuration interface of the host computer. After encoding the set parameters into a configuration frame, the configuration frame is sent to the PXIe interference generation module through the XDMA_user channel. The XDMA core is used to perform mapping conversion on the configuration frame, and the instruction parsing unit is used to parse the configuration parameters in the configuration frame after mapping conversion and send the configuration parameters to the interference signal generating unit; The interference signal generating unit is used to generate a baseband interference signal according to the configuration parameters, and forward the baseband interference signal and the radio frequency parameters of the baseband interference signal to the DAC driving unit; The DAC driver unit is used to provide an interface for the DAC chip to transmit baseband interference signals and radio frequency information. The DAC chip is used to perform digital-to-analog conversion and up-conversion processing on the received baseband interference signals according to the radio frequency information. The up-converted signal then passes through the analog conditioning circuit, and the output of the analog conditioning circuit is output to the outside. When you need to generate non-periodic interference: The data acquisition module is used to collect spectrum information of the communication signal and send the collected spectrum information to the main control module; The main control module calls the intelligent interference generation algorithm through the host computer to generate the baseband signal waveform data of the interference signal and the configuration frame containing the frequency and power information of the interference signal in real time. The host computer sends the configuration frame containing the frequency and power information of the interference signal to the XDMA core, and the host computer sends the baseband signal waveform data of the interference signal to the memory; The XDMA core is used to map and convert the configuration frame, and the instruction parsing unit is used to parse the mapped configuration frame to obtain radio frequency information including the frequency and power of the interference signal, and send the radio frequency information to the DAC driving unit; The memory interface unit is used to implement storage and reading of data in the memory; The DAC driving unit reads data from the memory through the read control unit. The DAC driving unit is used to provide an interface for the DAC chip to transmit baseband interference signals and radio frequency information. The DAC chip is used to perform digital-to-analog conversion and up-conversion processing on the received baseband interference signal according to the radio frequency information. The signal after up-conversion processing then passes through the analog conditioning circuit, and the output of the analog conditioning circuit is output to the outside.

2. The interference signal generation system based on the PXIe bus according to claim 1, characterized in that: The main control module is connected to the PXIe interference generation module via a PXIe chassis backplane signal line.

3. The interference signal generation system based on the PXIe bus according to claim 2, characterized in that: The analog conditioning circuit is used to sequentially filter and amplify the up-conversion processing result.

4. The interference signal generation system based on the PXIe bus according to claim 3, characterized in that: When the non-periodic interference is generated, the host computer sends a configuration frame containing the interference signal frequency and power information to the XDMA core through the XDMA_user channel.

5. The interference signal generation system based on the PXIe bus according to claim 4, characterized in that: When the non-periodic interference is generated, the host computer sends the baseband signal waveform data of the interference signal to the memory through the XDMA_dma channel.

6. The interference signal generation system based on the PXIe bus according to claim 5, characterized in that: The PXIe interference generation module also includes an XDMA interrupt control unit. After the XDMA interrupt control unit sends an XDMA interrupt request to the XDMA core, the memory receives the baseband signal waveform data of the interference signal through the XDMA_dma channel.

7. A method for generating an interference signal based on a PXIe bus, wherein the specific process of the method is as follows: Step 1: The user selects the non-periodic interference type in the configuration interface of the host computer and triggers it to start; Step 2: The host computer calls the intelligent interference generation algorithm to generate the baseband signal waveform data of the interference signal and the configuration frame containing the interference parameters of the interference signal in real time according to the communication signal spectrum information collected by the data acquisition module; Step 3: The host computer sends the configuration frame to the XDMA core through the XDMA_user channel. After the configuration frame is converted by the XDMA core, the instruction parsing unit is used to parse the converted configuration frame to obtain the RF information of the interference signal. The host computer caches the baseband signal waveform data of the interference signal into the memory through the XDMA_dma channel; Step 4. When the system is running, the DAC driver unit reads the baseband signal waveform data from the asynchronous FIFO read port of the read control unit at the DAC interface rate, and sends the baseband signal waveform data to the DAC chip. The DAC chip then performs digital-to-analog conversion and up-conversion processing on the baseband signal waveform data in sequence. The up-converted signal then passes through the analog conditioning circuit, and the analog conditioning circuit uses the analog conditioning circuit to filter and amplify the up-converted signal before outputting it to the outside.

8. The method for generating interference signals based on the PXIe bus according to claim 7, wherein: The memory is divided into two storage areas of equal size, and the two storage areas are respectively recorded as BANK1 and BANK2; The working process of the memory is: Step 1: When the data in the storage area BANK1 of the memory is read out, the read control unit shifts the read address to the first address of the storage area BANK2 of the memory, and the read control unit simultaneously generates a flag signal to the XDMA interrupt control unit; Step 2: After receiving the flag signal, the XDMA interrupt control unit sends an XDMA interrupt request to the XDMA core; Step 3: The XDMA core sends a PCIe MSI interrupt message to the host computer. After receiving the PCIe MSI interrupt message, the host computer rewrites the baseband signal waveform data of the interference signal into the storage area BANK1 that has been read out. Step 4: When the data in the storage area BANK2 of the memory is read out, the read control unit shifts the read address to the first address of the storage area BANK1 of the memory, and the read control unit simultaneously generates a flag signal to the XDMA interrupt control unit; Step 5: After receiving the flag signal, the XDMA interrupt control unit sends an XDMA interrupt request to the XDMA core; Step 6: The XDMA core sends a PCIe MSI interrupt message to the host computer. After receiving the PCIe MSI interrupt message, the host computer rewrites the baseband signal waveform data of the interference signal into the storage area BANK2 that has been read out. Return to step 1.

9. The method for generating interference signals based on the PXIe bus according to claim 8, wherein: The intelligent interference generation algorithm is a Q-Learning algorithm.

10. A method for generating an interference signal based on a PXIe bus, wherein the specific process of the method is as follows: Step 1: Parameter setting: After the user enters the host computer main interface, he or she can set the interference signal type, frequency, power and trigger control parameters in the host computer configuration interface; Step 2: Generate configuration frame: The host computer generates a configuration frame based on the user's configuration parameters. Each field in the configuration frame corresponds to a configuration parameter. Step 3: Configure frame sending: The host computer sends the configuration frame to the XDMA core in the PXIe interference generation module through the XDMA_user channel. The instruction parsing unit then parses the configuration frame after the XDMA core mapping conversion to obtain the configuration parameters corresponding to each field in the configuration frame. The parsed configuration parameters are then sent to the interference signal generation unit in the PXIe interference generation module, and the baseband digital interference signal is synthesized in the interference signal generation unit according to the configuration parameters; Step 4: Digital-to-analog conversion and amplification: The interference signal generation unit sends the synthesized baseband digital interference signal and RF parameters to the DAC driving unit. After the DAC driving unit sends the baseband digital interference signal and RF parameters to the DAC chip, the DAC chip is used to perform digital-to-analog conversion and up-conversion processing on the received baseband interference signal in sequence. The up-converted signal then passes through the analog conditioning circuit, and the analog conditioning circuit is used to filter and amplify the signal before outputting it to the outside.

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