Fully depleted silicon-on-insulator device and preparation method thereof

Abstract

The invention provides a fully-depleted silicon-on-insulator device and a preparation method thereof, the fully-depleted silicon-on-insulator device comprises a substrate layer, a buried oxide layer and an active layer which are sequentially stacked along the stacking direction, the active layer in the middle region is used as a channel, the active layer in the edge region is used as a source-drain region, and the active layer in the edge region is used as a drain-source region. The device further comprises a first stress providing layer, a second stress providing layer and a gate structure, and the gate structure is located in the middle region of the device and located on the side, away from the buried oxide layer, of the channel. The first stress providing layer and the second stress providing layer are both located in the edge area of the device, the first stress providing layer is located between the source-drain region and the buried oxide layer, the second stress providing layer is located on the side, away from the first stress providing layer, of the source-drain region, the first stress providing layer and the second stress providing layer are both used for providing tensile stress or compressive stress, and the buried oxide layer is located between the source-drain region and the buried oxide layer. Stress can be introduced into a channel more easily, the mobility of carriers is improved to a greater extent, the driving current and speed of the device are improved, and the performance of the device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices, and in particular to a fully depleted silicon-on-insulator device and a method for preparing the same. Background Art

[0002] A fully depleted silicon-on-insulator (FD-SOI) device is a transistor structure based on silicon-on-insulator (SOI) technology. It achieves dielectric isolation by introducing a buried oxide layer (BOX) between the silicon substrate and the active layer. A fully depleted operating mode is achieved through an ultra-thin silicon channel layer atop the BOX. This device offers the advantages of low power consumption, high integration, and radiation resistance. However, the carrier mobility of existing FD-SOI devices is limited by the ultra-thin top silicon channel, making it difficult to improve. This severely restricts the device's drive current and speed, reducing its performance. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a fully depleted silicon-on-insulator device and its preparation method, which can more easily introduce stress into the channel, greatly improve carrier mobility, increase the device's drive current and speed, and enhance device performance. The specific solution is as follows:

[0004] In one aspect, the present application provides a fully depleted silicon-on-insulator device, comprising:

[0005] A base layer, a buried oxide layer, and an active layer are stacked in sequence along the stacking direction; the active layer in the middle region serves as a channel, and the active layer in the edge region serves as a source and drain region;

[0006] In the edge region, a first stress-providing layer is provided between the source / drain region and the buried oxide layer;

[0007] In the edge region, a second stress-providing layer is provided on a side of the source / drain region away from the first stress-providing layer; both the first stress-providing layer and the second stress-providing layer are used to provide tensile stress or compressive stress;

[0008] In the middle region, a side of the channel away from the buried oxide layer has a gate structure.

[0009] Optionally, in the stacking direction, a difference between a thickness of the first stress-providing layer and a thickness of the second stress-providing layer is smaller than a preset thickness.

[0010] Optionally, the thickness of the first stress-providing layer is equal to the thickness of the second stress-providing layer.

[0011] Optionally, when the fully depleted silicon-on-insulator device is an NMOS, a material of the first stress-providing layer or the second stress-providing layer is silicon or silicon carbide;

[0012] When the fully depleted silicon-on-insulator device is a PMOS, the material of the first stress-providing layer or the second stress-providing layer is silicon germanium.

[0013] Optionally, the target stress-providing layer is the first stress-providing layer or the second stress-providing layer;

[0014] In a direction from the active layer to the target stress-providing layer, the doping concentration of the doping element in the target stress-providing layer increases gradually.

[0015] Optionally, the fully depleted silicon-on-insulator device further includes:

[0016] An insulating layer is located on a side of the second stress-providing layer away from the source and drain regions, and a source-drain contact hole is located in the insulating layer; the source-drain contact hole is filled with metal and is used to realize source and drain extraction.

[0017] In another aspect, an embodiment of the present application further provides a method for preparing a fully depleted silicon-on-insulator device, the method comprising:

[0018] Providing a substrate; the substrate comprises a base layer, a buried oxide layer and an active layer stacked in sequence along a stacking direction, wherein a dummy gate structure is provided on a side of the active layer away from the buried oxide layer in a middle region;

[0019] Etching the buried oxide layer located in the edge region to form a lateral gap between the buried oxide layer and the active layer;

[0020] A first stress-providing layer and a second stress-providing layer are respectively formed in the edge region, in the lateral gap, and on a side of the active layer away from the buried oxide layer, and the active layer is in-situ doped to obtain a source-drain region; the active layer located in the middle region serves as a channel, and the first stress-providing layer and the second stress-providing layer are both used to provide tensile stress or compressive stress;

[0021] The dummy gate structure is etched and filled to obtain a gate structure.

[0022] Optionally, an isolation region is provided around the substrate, and the active layer and the buried oxide layer are surrounded by the isolation region;

[0023] The step of etching the buried oxide layer located in the edge region to form a lateral gap between the buried oxide layer and the active layer comprises:

[0024] Etching the buried oxide layer and the isolation region located in the edge region to form the lateral gap between the buried oxide layer and the active layer, and to form a longitudinal gap between the isolation region and the substrate, wherein the lateral gap and the longitudinal gap are connected;

[0025] The step of forming a first stress providing layer and a second stress providing layer in the edge region, in the lateral gap, and on a side of the active layer away from the buried oxide layer, respectively, comprises:

[0026] In the edge area, the first stress-providing layer is formed in the first part of the longitudinal gap and the transverse gap, and the second stress-providing layer is formed in the second part of the longitudinal gap and on the side of the active layer away from the buried oxide layer; the first part is closer to the buried oxide layer than the second part.

[0027] Optionally, etching the buried oxide layer and the isolation region located in the edge region to form the lateral gap between the buried oxide layer and the active layer, and forming the longitudinal gap between the isolation region and the substrate, comprises:

[0028] forming a photoresist layer on a side of the isolation region away from the base layer;

[0029] Using the photoresist layer as a mask, the buried oxide layer and the isolation region located in the edge area are etched to form the lateral gap between the buried oxide layer and the active layer, and the longitudinal gap between the isolation region and the substrate.

[0030] Optionally, in the extension direction of the substrate, the dummy gate structure is surrounded by sidewalls;

[0031] The etching and filling of the dummy gate structure to obtain a gate structure comprises:

[0032] removing the dummy gate structure;

[0033] The gate material is filled in the space surrounded by the sidewalls to obtain the gate structure.

[0034] An embodiment of the present application provides a fully depleted silicon-on-insulator device and a method for preparing the same. The fully depleted silicon-on-insulator device includes a base layer, a buried oxide layer, and an active layer stacked in sequence along a stacking direction. The active layer located in the middle region serves as a channel, and the active layer located in the edge region serves as a source and drain region. The device also includes a first stress-providing layer, a second stress-providing layer, and a gate structure. The gate structure is located in the middle region of the device and on the side of the channel away from the buried oxide layer. Both the first stress-providing layer and the second stress-providing layer are located in the edge region of the device, and the first stress-providing layer is located between the source and drain regions and the buried oxide layer, and the second stress-providing layer is located on a side of the source and drain regions away from the first stress-providing layer. The first stress-providing layer and the second stress-providing layer are both used to provide tensile stress or compressive stress, so that the first stress-providing layer can conduct the tensile stress (or compressive stress) into the channel through the lower surface of the active layer, and the second stress-providing layer can conduct the tensile stress (or compressive stress) into the channel through the upper surface of the active layer, thereby more easily introducing stress into the ultra-thin channel, thereby greatly improving carrier mobility, thereby increasing the drive current and speed of the device, and improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0036] Figure 1-4 A cross-sectional view of a fully depleted silicon-on-insulator device provided in an embodiment of the present application is shown;

[0037] Figure 5 FIG2 shows a top view of a fully depleted silicon-on-insulator device provided in an embodiment of the present application;

[0038] Figure 6-7 A cross-sectional view of another fully depleted silicon-on-insulator device provided in an embodiment of the present application is shown;

[0039] Figure 8 A schematic flow chart of a method for preparing a fully depleted silicon-on-insulator device provided in an embodiment of the present application is shown.

[0040] Reference numerals

[0041] Substrate 10, base layer 101, buried oxide layer 102, active layer 103, channel 1031, source and drain region 1032, first stress providing layer 11, second stress providing layer 12, gate structure 13, insulating layer 14, gate oxide layer 201, dummy gate structure 202, hard mask layer 203, dummy gate stack 20, sidewall 204, lateral gap 41, vertical gap 42, isolation region 30, contact metal layer 31, and metal silicide layer 32. DETAILED DESCRIPTION

[0042] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0043] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0044] Secondly, this application is described in detail with reference to schematic diagrams. When describing the embodiments of this application, for ease of explanation, cross-sectional views of device structures may be partially enlarged and not to scale. Furthermore, these schematic diagrams are merely illustrative and should not limit the scope of protection of this application. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0045] As described in the background art, the carrier mobility of existing FD-SOI devices is difficult to improve due to the ultra-thin top silicon layer, which severely limits the driving current and speed of the device and reduces the performance of the FD-SOI device.

[0046] Based on the above technical problems, an embodiment of the present application provides a fully depleted silicon-on-insulator device and a preparation method thereof. The fully depleted silicon-on-insulator device includes a base layer, a buried oxide layer, and an active layer stacked in sequence along a stacking direction. The active layer located in the middle area serves as a channel, and the active layer located in the edge area serves as a source and drain region. The device also includes a first stress-providing layer, a second stress-providing layer, and a gate structure. The gate structure is located in the middle area of ​​the device and on the side of the channel away from the buried oxide layer. Both the first stress-providing layer and the second stress-providing layer are located in the edge region of the device, and the first stress-providing layer is located between the source and drain regions and the buried oxide layer, and the second stress-providing layer is located on a side of the source and drain regions away from the first stress-providing layer. The first stress-providing layer and the second stress-providing layer are both used to provide tensile stress or compressive stress, so that the first stress-providing layer can conduct the tensile stress (or compressive stress) into the channel through the lower surface of the active layer, and the second stress-providing layer can conduct the tensile stress (or compressive stress) into the channel through the upper surface of the active layer, thereby more easily introducing stress into the ultra-thin channel, thereby greatly improving carrier mobility, thereby increasing the drive current and speed of the device, and improving device performance.

[0047] For ease of understanding, a fully depleted silicon-on-insulator device and a method for manufacturing the same provided in an embodiment of the present application are described in detail below with reference to the accompanying drawings.

[0048] refer to Figure 1 , which is a cross-sectional view of a fully depleted silicon-on-insulator device provided in an embodiment of the present application, the fully depleted silicon-on-insulator device includes a base layer 101 , a buried oxide layer 102 and an active layer 103 stacked in sequence along a stacking direction.

[0049] The stacking direction is the stacking direction of the film layers in the device, for example, it can be a vertical upward direction or a vertical downward direction. For the convenience of description, the vertical upward direction is used as an example of the stacking direction.

[0050] The base layer 101 is used to provide a base support. The material of the base layer 101 is, for example, silicon. The base layer 101 is usually thicker, while the buried oxide layer 102 and the active layer 103 are usually thinner. The base layer 101, the buried oxide layer 102 and the active layer 103 can form a silicon-on-insulator (SOI) to serve as the substrate 10 of the device. The buried oxide layer 102 is, for example, a silicon dioxide layer, and the active layer 103 is, for example, a single crystal silicon layer. Figure 1 As shown, the substrate 10 includes a base layer 101 , a buried oxide layer 102 and an active layer 103 stacked from bottom to top.

[0051] The active layer 103 includes a channel 1031 and a source / drain region 1032 . The active layer 103 located in the middle area can serve as the channel 1031 . The channel 1031 does not need to be doped, for example, it is a single crystal silicon layer. The active layer 103 located in the edge area can serve as the source / drain region 1032 . The source / drain region 1032 can be obtained by doping the active layer 103 .

[0052] The middle region can be understood as the region of the middle part of the device, and the edge region can be understood as the region of the edge part of the device. Figure 1 , a cross-sectional view of a single fully depleted silicon-on-insulator device is shown, wherein the middle region is surrounded by edge regions on both sides. The middle region of the active layer 103 can serve as a channel 1031 , and the edge regions of the active layer 103 can serve as source and drain regions 1032 .

[0053] In the edge region, a first stress providing layer 11 is provided between the source / drain region 1032 and the buried oxide layer 102 . The first stress providing layer 11 is used to provide stress to the channel 1031 . The material of the first stress providing layer 11 is not limited.

[0054] In the edge region, the side of the source / drain region 1032 away from the first stress providing layer 11 has a second stress providing layer 12. Both the first stress providing layer 11 and the second stress providing layer 12 are used to provide tensile stress or compressive stress. In other words, both stress providing layers can be used to provide tensile stress or compressive stress. Figure 7 As shown, a first stress providing layer 11 is provided below the active layer 103 , and a second stress providing layer 12 is provided above the active layer 103 .

[0055] In the middle region, a side of the channel 1031 away from the buried oxide layer 102 has a gate structure 13, such as Figure 7 shown.

[0056] In this way, the first stress-providing layer 11 can conduct the tensile stress (or compressive stress) to the channel 1031 through the lower surface of the active layer 103. Specifically, the first stress-providing layer 11 can conduct the stress to the channel 1031 through the source-drain region 1032. The second stress-providing layer 12 can conduct the tensile stress (or compressive stress) to the channel 1031 through the upper surface of the active layer 103. Specifically, the second stress-providing layer 12 can also conduct the stress to the channel 1031 through the source-drain region 1032. Thus, stress can be more easily introduced into the ultra-thin channel 1031 through the upper and lower surfaces of the active layer 103, thereby greatly improving the carrier mobility, thereby improving the driving current and speed of the device, and improving the device performance.

[0057] Next, the principle of how the two stress layers can improve the carrier mobility is explained.

[0058] On the one hand, stress can affect the carrier relaxation time by causing lattice distortion of the material, changing the lattice constant and bond length; on the other hand, it can change the effective mass of the carrier by changing the band structure of the material. According to the carrier mobility calculation formula:

[0059]

[0060] Where m* is the effective mass of the carrier, τ is the carrier relaxation time, and q is the elementary charge.

[0061] By applying stress, the present application can increase the carrier relaxation time and reduce the effective mass of the carriers, thereby increasing the carrier mobility of the device. Generally, for a dual stress structure, a simultaneous improvement in the mobility of NMOS and PMOS is achieved, wherein compressive stress can be applied to the channel 1031 of the PMOS device to increase the hole mobility, and tensile stress can be optionally applied to the channel 1031 of the NMOS device to increase the electron mobility, or no stress is introduced.

[0062] In the related art, in nanoscale devices, stress is easily relaxed, affecting the effect of stress engineering. The present application introduces stress from both the upper and lower surfaces of the active layer 103. Compared with introducing stress only from the upper surface of the active layer 103, more stress can be more effectively introduced into the channel 1031, thereby greatly improving the carrier mobility.

[0063] In a possible implementation, in the stacking direction, a difference between the thickness of the first stress-providing layer 11 and the thickness of the second stress-providing layer 12 is smaller than a preset thickness.

[0064] The preset thickness may be a thickness value pre-set based on an actual design. By setting the difference between the thickness of the first stress-providing layer 11 and the thickness of the second stress-providing layer 12 to be smaller than the preset thickness, the thickness of the second stress-providing layer 12 located above the active layer 103 is not much different from the thickness of the first stress-providing layer 11 located below the active layer 103. Consequently, the stress transferred from the upper surface of the active layer 103 to the channel 1031 is not much different from the stress transferred from the lower surface of the active layer 103 to the channel 1031. This results in a small difference in the forces applied to the upper and lower surfaces of the active layer 103, thereby avoiding warping of the active layer 103 due to large unilateral stress, ensuring mutual adhesion between the film layers, and improving device performance.

[0065] In a possible implementation, the thickness of the first stress providing layer 11 is equal to the thickness of the second stress providing layer 12. The thickness being equal can be understood as being substantially equal. By setting the thickness to be substantially equal, the center line of the entire two stress providing layers (e.g. Figure 7The center line shown) can coincide with the center line of the channel 1031, that is, their centers are on the same horizontal line. Furthermore, the stress introduced from the upper and lower surfaces of the active layer 103 to the channel 1031 will be basically equal, thereby further avoiding the warping of the active layer 103 due to large unilateral stress, ensuring that the film layers fit together, making it easier to introduce stress from the upper and lower surfaces into the channel 1031, and further improving the device performance.

[0066] In a possible implementation, when the fully depleted silicon-on-insulator device is an NMOS, the material of the first stress-providing layer 11 or the second stress-providing layer 12 is silicon or silicon carbide. When the fully depleted silicon-on-insulator device is a PMOS, the material of the first stress-providing layer 11 or the second stress-providing layer 12 is silicon germanium.

[0067] Specifically, when the fully depleted silicon-on-insulator device is a PMOS, the material of the first stress-providing layer 11 or the second stress-providing layer 12 can be Si Figure 7 , ,

[0072] Ge x , where 0 < x ≤ 0.5, thereby further enhancing the compressive stress exerted by the stress-providing layer on the channel 1031 and improving the mobility of hole carriers.

[0068] When the fully depleted silicon-on-insulator device is an NMOS, the material of the first stress-providing layer 11 or the second stress-providing layer 12 can be Si or SiC, thereby increasing the tensile stress exerted by the stress-providing layer on the channel 1031 and improving the mobility of electron carriers.

[0069] In a possible implementation, the target stress-providing layer can be the first stress-providing layer 11 or the second stress-providing layer 12; in the direction from the active layer 103 to the target stress-providing layer, the doping concentration of the doping element in the target stress-providing layer increases.

[0070] That is to say, in the target stress-providing layer, the part farther away from the active layer 103 has a higher doping concentration of the doping element, and the part closer to the active layer 103 has a lower doping concentration of the doping element, thereby minimizing the defects between the target stress-providing layer and the active layer 103, making these two film layers more matched and the film layers more adherent. It can be understood that the specific change degree of the doping concentration can be set based on device requirements and is not specifically limited. [[ID=​​​​​​As shown, an insulating layer 14, such as a silicon dioxide layer, can be formed above the device, and source-drain contact holes can be formed in the insulating layer 14. The source-drain contact holes have a contact metal layer 31. The material of the contact metal layer 31 is, for example, a silicide of nickel-platinum alloy, titanium, cobalt, etc., so that the metal in the contact hole forms a good ohmic contact with the source region and the drain region, thereby improving the device performance and ensuring the normal operation of the device.

[0073] refer to Figure 8 , which is a flow chart of a method for preparing a fully depleted silicon-on-insulator device provided in an embodiment of the present application, the method includes S101 - S103 .

[0074] S101 , providing a substrate 10 .

[0075] The substrate 10 includes a base layer 101, a buried oxide layer 102, and an active layer 103 stacked sequentially along the stacking direction. For a description of the substrate 10, refer to the aforementioned description of fully depleted silicon-on-insulator devices. A dummy gate structure 202 is provided on the side of the active layer 103 in the middle region, away from the buried oxide layer 102. The dummy gate structure 202 is subsequently removed to form a high-k / metal gate gate structure 13. Furthermore, a gate oxide layer 201 may be provided between the dummy gate structure 202 and the channel 1031 to isolate the gate from the channel 1031. A hard mask layer 203 may also be provided on the side of the dummy gate structure 202 away from the channel 1031 to protect the underlying film layer from being removed.

[0076] refer to Figure 2 As shown, the substrate 10 includes a base layer 101, a buried oxide layer 102 and an active layer 103 stacked from bottom to top, and the dummy gate stack 20 is located in the middle area of ​​the device. The dummy gate stack 20 includes a gate oxide layer 201, a dummy gate structure 202 and a hard mask layer 203 stacked from bottom to top.

[0077] In addition, a spacer 204 may be deposited around the dummy gate structure 202. The spacer 204 is used to subsequently protect the gate structure 13. The deposition process of the spacer 204 may be physical vapor deposition, chemical vapor deposition, or atomic layer deposition. Figure 3 As shown, there are spacers 204 on the left and right sides of the dummy gate structure 202 . The following description will be made by taking the spacers 204 around the dummy gate structure 202 as an example.

[0078] In addition, in the actual process, when forming the sidewall 204, a layer of material can be first deposited on the device, and the material layer above the dummy gate stack 20 and the material layer in the edge area can be etched, leaving only the material layer located on the side of the dummy gate stack 20, thereby forming the sidewall 204.

[0079] As an example, the material of the gate oxide layer 201 can be silicon dioxide, the material of the dummy gate structure 202 can be polysilicon, the material of the hard mask layer 203 can be silicon dioxide, silicon nitride or a stacked combination thereof, and the material of the sidewall 204 can be silicon nitride, silicon dioxide or a stacked combination thereof.

[0080] S102 , etching the buried oxide layer 102 located in the edge region to form a lateral gap 41 between the buried oxide layer 102 and the active layer 103 .

[0081] Specifically, the buried oxide layer 102 in the edge region of the device can be etched, leaving the buried oxide layer 102 in the middle region, thereby forming a lateral gap 41 between the buried oxide layer 102 and the active layer 103, thereby reserving space for forming the first stress-providing layer 11 and exposing the active layer 103 for forming the source and drain regions 1032. The etching method can be dry etching or wet etching after photolithographic patterning, and can be selected based on actual needs.

[0082] refer to Figure 1 As shown, the buried oxide layer 102 after etching has a morphology of being high in the middle and low on both sides. In the edge region, a lateral gap 41 is formed between the active layer 103 and the buried oxide layer 102 .

[0083] S103 , forming a first stress providing layer 11 and a second stress providing layer 12 in the edge region, in the lateral gap 41 and on a side of the active layer 103 away from the buried oxide layer 102 , and in-situ doping the active layer 103 to obtain source and drain regions 1032 .

[0084] Specifically, for the edge region, a first stress-providing layer 11 can be formed within the lateral gap 41, and a second stress-providing layer 12 can be formed on the upper surface of the active layer 103. Simultaneously, the active layer 103 in the edge region can be in-situ doped to form the source / drain region 1032. The deposition process for forming the first stress-providing layer 11 and the second stress-providing layer 12 can be physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

[0085] In practical applications, selective epitaxy can be used to surround the source and drain regions 1032 and perform source and drain epitaxy until they are in contact with the buried oxide layer 102, thereby forming the first stress providing layer 11 and the second stress providing layer 12, and in this process, the source and drain regions 1032 are heavily doped.

[0086] It can be understood that the materials of the first stress providing layer 11 and the second stress providing layer 12 are usually the same, and the two stress providing layers are generally formed at the same time.

[0087] In this way, the active layer 103 located in the middle area serves as the channel 1031, and the first stress-providing layer 11 and the second stress-providing layer 12 are both used to provide tensile stress or compressive stress. Specifically, when the device is a PMOS device, the two stress-providing layers are used to provide compressive stress, and when the device is an NMOS device, the two stress-providing layers are used to provide tensile stress.

[0088] In one possible implementation, an isolation region 30 is provided around the substrate 10, and the active layer 103 and the buried oxide layer 102 are surrounded by the isolation region 30; S102, the buried oxide layer 102 located in the edge region is etched to form a lateral gap 41 between the buried oxide layer 102 and the active layer 103, including S1021; then, S103, in the edge region, a first stress providing layer 11 and a second stress providing layer 12 are respectively formed within the lateral gap 41 and on a side of the active layer 103 away from the buried oxide layer 102, including S1031.

[0089] When forming a device array of fully depleted silicon-on-insulator devices, isolation regions 30 are usually set between adjacent devices for isolation. The isolation region 30 is also called shallow trench isolation (STI). The isolation region 30 is generally located in the substrate 10 of the adjacent devices to achieve isolation of the adjacent devices. Figure 2-7 As shown, the devices all have an isolation region 30. When forming a single fully depleted silicon-on-insulator device, there is no need to provide the isolation region 30. Next, an example is given to illustrate how to form two stress-providing layers when the isolation region 30 is provided.

[0090] S1021, the buried oxide layer 102 and the isolation region 30 located in the edge area are etched to form a transverse gap 41 between the buried oxide layer 102 and the active layer 103, and a longitudinal gap 42 between the isolation region 30 and the substrate 10, and the transverse gap 41 and the longitudinal gap 42 are connected.

[0091] Specifically, refer to Figure 2 or Figure 3 As shown, the isolation region 30 is adjacent to the active layer 103 and the buried oxide layer 102. Therefore, when forming the transverse gap 41, the isolation region 30 also needs to be etched so that the first stress-providing layer 11 can be subsequently formed between the active layer 103 and the buried oxide layer 102. The vertical gap between the isolation region 30 and the substrate 10 is denoted as the longitudinal gap 42. In short, both the buried oxide layer 102 and the isolation region 30 in the edge region can be etched to form a connected transverse gap 41 and longitudinal gap 42.

[0092] refer to Figure 4 As shown, a transverse gap 41 is formed between the active layer 103 and the buried oxide layer 102, and a longitudinal gap 42 is formed between the isolation region 30 and the substrate 10, and the two gaps are connected. Figure 5 , which is a top view of a fully depleted silicon-on-insulator device provided in an embodiment of the present application, Figure 4 for Figure 5 From the AA' cross-sectional view, it can be found that Figure 5 In the embodiment, a circle of longitudinal gaps 42 is formed around the active layer 103 .

[0093] S1031, in the edge area, a first stress providing layer 11 is formed in the first part of the longitudinal gap 42 and the transverse gap 41, and a second stress providing layer 12 is formed in the second part of the longitudinal gap 42 and on the side of the active layer 103 away from the buried oxide layer 102; the first part is closer to the buried oxide layer 102 than the second part.

[0094] refer to Figure 6 As shown, the first portion of the longitudinal gap 42 is the lower portion and communicates with the transverse gap 41, while the second portion of the longitudinal gap 42 is the upper portion and is exposed. In the edge region, a first stress-providing layer 11 can be formed within the first portion and the transverse gap 41, and a second stress-providing layer 12 can be formed on the second portion and the upper surface of the active layer 103.

[0095] In an actual process, the material of the stress-providing layer may be deposited in the transverse gap 41 and the longitudinal gap 42 at the same time, thereby forming the first stress-providing layer 11 and the second stress-providing layer 12 at the same time.

[0096] In summary, by etching the isolation region 30 to form the longitudinal gap 42, when forming the device array, it is possible to ensure that the first stress-providing layer 11 can be easily entered into the transverse gap 41, and the two stress-providing layers as a whole can better apply stress to the channel 1031 located inside the whole, thereby further improving the device performance.

[0097] Next, an example is given to illustrate how to form the transverse gap 41 and the longitudinal gap 42 .

[0098] In one possible implementation, S1021 etches the buried oxide layer 102 and the isolation region 30 located in the edge area to form a transverse gap 41 between the buried oxide layer 102 and the active layer 103, and a longitudinal gap 42 between the isolation region 30 and the substrate 10, including S10211-S10212.

[0099] S10211 , forming a photoresist layer on a side of the isolation region 30 away from the base layer 101 .

[0100] Specifically, a photoresist layer is formed above the isolation region 30 . The photoresist layer may cover the isolation region 30 . The photoresist layer may be a positive photoresist or a negative photoresist.

[0101] S10212 , using the photoresist layer as a mask, the buried oxide layer 102 and the isolation region 30 located in the edge area are etched to form a transverse gap 41 between the buried oxide layer 102 and the active layer 103 , and a longitudinal gap 42 between the isolation region 30 and the substrate 10 .

[0102] During the photolithography process, the pattern on the mask is transferred to the photoresist layer, and the photoresist layer is used as a mask to protect the film layer below the photoresist layer in the edge area, thereby forming a vertical gap between the isolation area 30 and the substrate 10, and a lateral gap 41 between the buried oxide layer 102 and the active layer 103.

[0103] In summary, by forming the longitudinal gap 42 and the transverse gap 41 by photolithography, the morphology and size of the gaps can be better controlled, and etching can be more accurate.

[0104] S104 , etching and filling the dummy gate structure 202 to obtain the gate structure 13 .

[0105] Specifically, the dummy gate structure 202 can be etched away, and the material of the gate structure 13 can be filled in the corresponding position to form the gate structure 13. The gate structure 13 is, for example, a high-k / metal gate stack. Figure 7 As shown, a gate structure 13 is formed inside the spacer 204 .

[0106] In this way, the first stress-providing layer 11 can conduct the tensile stress (or compressive stress) to the channel 1031 through the lower surface of the active layer 103, and the second stress-providing layer 12 can conduct the tensile stress (or compressive stress) to the channel 1031 through the upper surface of the active layer 103, so that stress can be more easily introduced into the ultra-thin channel 1031, thereby greatly improving the carrier mobility, thereby improving the driving current and speed of the device, and improving the device performance.

[0107] In a possible implementation, in the extension direction of the substrate 10 , the dummy gate structure 202 is surrounded by the sidewall spacer 204 ; S104 etches and fills the dummy gate structure 202 to obtain the gate structure 13 , which may include S1041 - S1042 .

[0108] S1041, removing the dummy gate structure 202;

[0109] S1042 , filling the space surrounded by the sidewalls 204 with a gate material to obtain a gate structure 13 .

[0110] Specifically, when the dummy gate structure 202 is surrounded by the sidewall 204, the dummy gate structure 202 can be removed first, and the gate material can be filled in the space surrounded by the sidewall 204 to form the gate structure 13, thereby improving the stability of the device structure and making the formation of the gate structure 13 more convenient. Figure 7 As shown, a metal silicide layer 32 is formed on the second stress-providing layer 12. The material of the metal silicide layer 32 is, for example, a nickel-platinum alloy, titanium, cobalt, or other silicide, so that the contact metal layer 31 forms a good ohmic contact with the source and drain regions. The gate material can be a high-k / metal gate material.

[0111] Those skilled in the art will understand that all or part of the steps of implementing the above-mentioned method embodiment can be completed by program instruction hardware, and the above-mentioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above-mentioned method embodiment; and the above-mentioned storage medium can be at least one of the following media: read-only memory (English: Read-only Memory, abbreviated: ROM), RAM, magnetic disk or optical disk, etc., various media that can store program codes.

[0112] The various embodiments in this specification are described in a progressive manner. Similar portions between the various embodiments can be referenced to each other. Each embodiment focuses on the differences from the other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the apparatus embodiments. For relevant portions, refer to the description of the apparatus embodiments.

[0113] The above is only a preferred embodiment of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above-disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of protection of the technical solution of the present application.

Claims

1. A fully depleted silicon-on-insulator device, characterized in that: include: A base layer, a buried oxide layer and an active layer stacked in sequence along a stacking direction; The active layer located in the middle area serves as the channel, and the active layer located in the edge area serves as the source and drain regions; In the edge region, a first stress-providing layer is provided between the source / drain region and the buried oxide layer; In the edge region, a second stress-providing layer is provided on a side of the source / drain region away from the first stress-providing layer; both the first stress-providing layer and the second stress-providing layer are used to provide tensile stress or compressive stress; In the middle region, a side of the channel away from the buried oxide layer has a gate structure.

2. The fully depleted silicon-on-insulator device according to claim 1, wherein: In the stacking direction, a difference between a thickness of the first stress-providing layer and a thickness of the second stress-providing layer is smaller than a preset thickness.

3. The fully depleted silicon-on-insulator device according to claim 2, wherein: The thickness of the first stress-providing layer is equal to the thickness of the second stress-providing layer.

4. The fully depleted silicon-on-insulator device according to claim 1, wherein: When the fully depleted silicon-on-insulator device is an NMOS, the material of the first stress-providing layer or the second stress-providing layer is silicon or silicon carbide; When the fully depleted silicon-on-insulator device is a PMOS, the material of the first stress-providing layer or the second stress-providing layer is silicon germanium.

5. The fully depleted silicon-on-insulator device according to claim 1, wherein: The target stress-providing layer is the first stress-providing layer or the second stress-providing layer; In a direction from the active layer to the target stress-providing layer, the doping concentration of the doping element in the target stress-providing layer increases gradually.

6. The fully depleted silicon-on-insulator device according to claim 1, wherein: The fully depleted silicon-on-insulator device further comprises: An insulating layer is located on a side of the second stress-providing layer away from the source and drain regions, and a source-drain contact hole is located in the insulating layer; the source-drain contact hole is filled with metal and is used to realize source and drain extraction.

7. A method for preparing a fully depleted silicon-on-insulator device, characterized in that: The method comprises: Providing a substrate; the substrate comprises a base layer, a buried oxide layer and an active layer stacked in sequence along a stacking direction, wherein a dummy gate structure is provided on a side of the active layer away from the buried oxide layer in a middle region; Etching the buried oxide layer located in the edge region to form a lateral gap between the buried oxide layer and the active layer; A first stress-providing layer and a second stress-providing layer are respectively formed in the edge region, in the lateral gap, and on a side of the active layer away from the buried oxide layer, and the active layer is in-situ doped to obtain a source-drain region; the active layer located in the middle region serves as a channel, and the first stress-providing layer and the second stress-providing layer are both used to provide tensile stress or compressive stress; The dummy gate structure is etched and filled to obtain a gate structure.

8. The method for preparing a fully depleted silicon-on-insulator device according to claim 7, wherein: An isolation region is provided around the substrate, and the active layer and the buried oxide layer are surrounded by the isolation region; The step of etching the buried oxide layer located in the edge region to form a lateral gap between the buried oxide layer and the active layer comprises: Etching the buried oxide layer and the isolation region located in the edge region to form the lateral gap between the buried oxide layer and the active layer, and to form a longitudinal gap between the isolation region and the substrate, wherein the lateral gap and the longitudinal gap are connected; The step of forming a first stress providing layer and a second stress providing layer in the edge region, in the lateral gap, and on a side of the active layer away from the buried oxide layer, respectively, comprises: In the edge area, the first stress-providing layer is formed in the first part of the longitudinal gap and the transverse gap, and the second stress-providing layer is formed in the second part of the longitudinal gap and on the side of the active layer away from the buried oxide layer; the first part is closer to the buried oxide layer than the second part.

9. The method for preparing a fully depleted silicon-on-insulator device according to claim 8, wherein: The etching of the buried oxide layer and the isolation region located in the edge region to form the lateral gap between the buried oxide layer and the active layer and the longitudinal gap between the isolation region and the substrate comprises: forming a photoresist layer on a side of the isolation region away from the base layer; Using the photoresist layer as a mask, the buried oxide layer and the isolation region located in the edge area are etched to form the lateral gap between the buried oxide layer and the active layer, and the longitudinal gap between the isolation region and the substrate.

10. The method for preparing a fully depleted silicon-on-insulator device according to claim 7, wherein: In the extension direction of the substrate, the dummy gate structure is surrounded by sidewalls; The etching and filling of the dummy gate structure to obtain a gate structure comprises: removing the dummy gate structure; The gate material is filled in the space surrounded by the sidewalls to obtain the gate structure.

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