Manufacturing method of semiconductor integrated structure with high and low voltage components and capacitor
By using high-voltage polysilicon hard shields and electrode plates as etching barriers in the preparation of high-voltage components, an oxide layer with an inclined angle is formed, which solves the problems of shallow trench insulation damage and thermal budget excess in the existing technology, and realizes the stable integration of high and low voltage components and capacitors.
Patent Information
- Application Number
- CN202410296746.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-15
- Publication Date
- 2025-09-19
AI Technical Summary
In the existing technology for preparing high-voltage components, there are problems such as damage to shallow trench insulation or LOCOS field oxide regions, wet etching photoresist stripping problems, and thermal oxidation processes exceeding the thermal budget, resulting in unstable integrated processes.
A high-voltage polysilicon hard shield and the first electrode plate are used as etching stoppers. A high-voltage CVD oxidation zone and a bottom thermal oxidation zone are formed by chemical vapor deposition. Ion implantation technology is used to form an oxide layer with an inclined angle, avoiding the use of additional masks, achieving PIP capacitance while reducing the thermal oxidation process.
It effectively avoids the damage of shallow trench insulation, reduces the thermal oxidation process, solves the pit problem, avoids the integration process from exceeding the thermal budget, and realizes stable integration of high and low voltage components and capacitors.
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Figure CN120676699A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a semiconductor integrated structure having high and low voltage components and capacitors, and more particularly to a semiconductor integrated structure having high and low voltage components and capacitors that integrates high voltage components, low voltage components and polysilicon-insulator-polysilicon (PIP) capacitors and a method for manufacturing the same. Background Art
[0002] Please refer to Figure 1 , which is a cross-sectional view of a semiconductor integrated structure 10 with high and low voltage components and capacitors according to the prior art. Figure 1 As shown, the semiconductor integrated structure 10 is formed in a substrate 11 and includes multiple insulating regions 12, a low-voltage gate 13a, a high-voltage gate 13b, a low-voltage source 14a, a high-voltage source 14b, a low-voltage drain 15a, a high-voltage drain 15b, a resurf oxide region 16 and a body region 17.
[0003] Multiple insulating regions 12 are formed in the substrate 11 to electrically isolate the low-voltage component LV1 from the high-voltage component HV1. A low-voltage gate 13a is formed on the substrate 11 of the low-voltage component LV1, while a low-voltage source 14a and a low-voltage drain 15a are formed in the substrate 11 shared by the low-voltage component LV1. Meanwhile, a high-voltage gate 13b and a resurf oxide region 16 are formed on the substrate 11 of the high-voltage component HV1, while a high-voltage source 14b and a high-voltage drain 15b are formed in the substrate 11 shared by the high-voltage component HV1.
[0004] In typical LDMOS components (such as Figure 1 In the manufacturing process of the high voltage device HV1 shown in FIG, the most effective way to improve the device breakdown voltage and the hot carrier injection problem near the gate edge is to use a field plate structure, which can alleviate the local electric field crowding that causes the device to break down early. Figure 1 The reduced surface electric field oxide region 16 shown is the simplest way to realize the field plate structure without the need for additional shielding definition, but the LOCOS field oxide region may cause some serious problems, such as high on-resistance during high-temperature heat treatment or outdiffusion of boron atoms in the LDMOS element into the field oxide region.
[0005] To address this issue, a field plate formed of a dielectric layer (typically silicon oxide, but silicon nitride, silicon oxynitride, or a high-k dielectric constant material) with an angled dielectric to the surface of the substrate 11 is used between the high-voltage gate 13b and the substrate 11 in the LDMOS device to implement this surface electric field reduction (RESURF) technology. However, more specifically, the dielectric layer structure with an angled dielectric may be accompanied by an additional oxide growth thermal process, causing the integrated process to exceed the thermal budget; and when defining the dielectric layer with an angled dielectric, an additional wet etching process may cause shallow trench insulation (STI) angle loss, or pitting. Therefore, the prior art proposes a novel two-step dielectric layer oxide process with an angled dielectric and an unshielded polysilicon-insulator-polysilicon (PIP) capacitor structure to address these issues.
[0006] However, this conventional technology has the problem of photoresist stripping during the wet etching process, which further causes damage to the shallow trench isolation or LOCOS field oxide region. In addition, multiple thermal oxidation processes will also cause the problem of exceeding the thermal budget limit.
[0007] In view of this, the present invention proposes a method for manufacturing a semiconductor integrated structure with high and low voltage components and capacitors, which can avoid damage to shallow trench insulation or LOCOS field oxide regions, reduce thermal oxidation processes, and solve the problems of pits and exceeding thermal budget limits. Summary of the Invention
[0008] In one aspect, the present invention provides a method for manufacturing a semiconductor integrated structure having high and low voltage components and capacitors, comprising: forming a bottom thermal oxide layer on a substrate, wherein the bottom thermal oxide layer completely covers a high voltage component region, a low voltage component region, and a capacitor region of the substrate; forming a high voltage well region in the high voltage component region; forming a chemical vapor deposition (CVD) oxide layer completely covering the bottom thermal oxide layer; forming a polysilicon hard mask layer completely covering the CVD oxide layer; etching the polysilicon hard mask layer to simultaneously form a high voltage polysilicon hard mask in the high voltage component region and a first electrode plate in the capacitor region; etching the CVD oxide layer and using the high voltage polysilicon hard mask and the first electrode plate as etch stop layers to simultaneously form a high voltage CVD oxide region in the high voltage component region and a capacitor CVD oxide region in the capacitor region; forming a low voltage well region in the low voltage component region; etching the bottom thermal oxide layer and using the high voltage polysilicon hard mask and the first electrode plate as etch stop layers to simultaneously form A high-voltage bottom thermal oxidation region is formed in the high-voltage component region and a capacitor bottom thermal oxidation region is formed in the capacitor region; a high-voltage gate oxide layer is formed in the high-voltage component region on the substrate; a low-voltage gate oxide layer is formed in the low-voltage component region on the substrate; wherein, when the high-voltage gate oxide layer or the low-voltage gate oxide layer is formed, a capacitor dielectric layer is simultaneously formed, connected to and completely covered on the first electrode plate; a gate polysilicon layer is formed, connected to and completely covered on the high-voltage gate oxide layer, the low-voltage gate oxide layer and the capacitor dielectric layer; and the gate polysilicon layer is etched to simultaneously form a high-voltage gate in the high-voltage component region, a low-voltage gate in the low-voltage component region and a second electrode plate in the capacitor region.
[0009] In one embodiment, the step of forming the low-voltage well region in the low-voltage device region includes: using an ion implantation process step to use the bottom thermal oxide layer as a sacrificial layer, and injecting accelerated ions through the sacrificial layer into the low-voltage device region to form the low-voltage well region.
[0010] In one embodiment, the step of etching the CVD oxide layer and using the high-voltage polysilicon hard mask and the first electrode plate as an etching barrier layer to simultaneously form the high-voltage CVD oxide region in the high-voltage component region and the capacitor CVD oxide region in the capacitor region includes etching the CVD oxide layer using a wet etching process step.
[0011] In one embodiment, the step of etching the bottom thermal oxide layer and using the high-voltage polysilicon hard mask and the first electrode plate as an etching barrier layer to simultaneously form the high-voltage bottom thermal oxide region in the high-voltage device region and the capacitor bottom thermal oxide region in the capacitor region includes: etching the bottom thermal oxide layer using a wet etching process step so that a high-voltage sidewall of the high-voltage bottom thermal oxide region and a capacitor sidewall of the capacitor bottom thermal oxide region respectively have a non-perpendicular tilt angle with an upper surface of the substrate.
[0012] In one embodiment, the method for manufacturing the semiconductor integrated structure with high and low voltage components and capacitors further includes: after forming the polysilicon hard shielding layer, accelerating N-type or P-type ions in an ion implantation process to implant the polysilicon hard shielding layer.
[0013] In one embodiment, the method for manufacturing the semiconductor integrated structure with high and low voltage components and capacitors further includes: after forming the gate polysilicon layer, accelerating N-type or P-type ions in an ion implantation process to implant the gate polysilicon layer.
[0014] In one embodiment, the high voltage gate is in direct contact with the high voltage polysilicon hard shield.
[0015] In one embodiment, the manufacturing method of the semiconductor integrated structure having high and low voltage elements and capacitors further includes: after forming the high voltage gate, the low voltage gate and the second electrode plate, forming two high voltage spacer layers correspondingly connected to the two sides of the high voltage gate and two low voltage spacer layers correspondingly connected to the two sides of the low voltage gate.
[0016] In one embodiment, the manufacturing method of the semiconductor integrated structure having high and low voltage components and capacitors further includes: after forming the high voltage gate, the low voltage gate and the second electrode plate, forming two capacitor spacer layers correspondingly connected to both sides of the second electrode plate.
[0017] In one embodiment, the method for manufacturing the semiconductor integrated structure having high and low voltage components and capacitors further includes: simultaneously forming a high voltage source and a high voltage drain in the high voltage component area, and a low voltage source and a low voltage drain in the low voltage component area.
[0018] In one embodiment, the manufacturing method of the semiconductor integrated structure having high and low voltage components and capacitors also includes: using a silicide metal process step to simultaneously form multiple silicide metal layers corresponding to the upper surfaces of the high voltage gate, the high voltage source, the high voltage drain, the low voltage gate, the low voltage source, the low voltage drain, the first electrode plate and the second electrode plate.
[0019] In one embodiment, the method for manufacturing the semiconductor integrated structure with high and low voltage components and capacitors further includes forming an inter-layer dielectric (ILD) layer on the substrate to completely cover the high voltage gate, the low voltage gate and the second electrode plate.
[0020] In one embodiment, the method for manufacturing the semiconductor integrated structure with high and low voltage devices and capacitors further includes: forming a plurality of electrical contact plugs on the ILD layer to electrically connect the plurality of silicide metal layers.
[0021] In one embodiment, the method for manufacturing the semiconductor integrated structure having high and low voltage components and capacitors further includes: forming a high voltage body region in the high voltage well region of the high voltage component region, and the high voltage source is located in the high voltage body region.
[0022] The advantages of the present invention are that the high-voltage polysilicon hard shield and the first electrode plate can be used to realize a two-stage sloped high-voltage bottom thermal oxidation zone and a high-voltage CVD oxidation zone without the need for an additional mask, and a PIP capacitor can be formed simultaneously while avoiding the pitting phenomenon of the shallow trench insulation (STI).
[0023] The following detailed description is made through specific embodiments to make it easier to understand the purpose, technical content, characteristics and effects achieved by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 FIG. 1 is a schematic cross-sectional view of a semiconductor integrated structure 10 having high and low voltage components according to the prior art.
[0025] Figure 2A-2Q FIG. 1 is a cross-sectional diagram illustrating a method for manufacturing a semiconductor integrated structure 20 having high and low voltage components and capacitors according to an embodiment of the present invention.
[0026] Explanation of symbols in the figure
[0027] 10: Semiconductor integrated structure with high and low voltage components
[0028] 11, 21: substrate
[0029] 12, 22a, 22b: Insulation area
[0030] 13a, 30b: low voltage gate
[0031] 13b, 30a: High-voltage gate
[0032] 14a, 32b: low voltage source
[0033] 14b, 32a: High voltage source
[0034] 15a, 33b: Low voltage drain
[0035] 15b, 33a: High voltage drain
[0036] 16: Reduce the surface electric field oxidation zone
[0037] 17: Ontology area
[0038] 20: Semiconductor integrated structure with high and low voltage components and capacitors
[0039] 23a: High-pressure bottom thermal oxidation zone
[0040] 23b: Thermal oxidation area at the bottom of the capacitor
[0041] 24: High-voltage well region
[0042] 25a: High-pressure CVD oxidation zone
[0043] 25b: Capacitor CVD oxidation area
[0044] 26a: High voltage polysilicon hard shield
[0045] 26b: First electrode plate
[0046] 27: Low-pressure well region
[0047] 28a, 28c: High-voltage gate oxide layer
[0048] 28b: Capacitor dielectric layer
[0049] 29: Low voltage gate oxide
[0050] 30c: Second electrode plate
[0051] 31a: High-voltage spacer
[0052] 31b: Low-pressure spacer
[0053] 31c: Capacitor spacer layer
[0054] 34: Silicide metal layer
[0055] 35: Inter-layer dielectric (ILD) layer
[0056] 36: Electrical contact plug
[0057] 37: High-voltage body area
[0058] HV1: High voltage components
[0059] HV2: High voltage component area
[0060] LV1: Low voltage components
[0061] LV2: Low voltage component area
[0062] PIP1: Capacitor area DETAILED DESCRIPTION
[0063] The foregoing and other technical aspects, features, and effects of the present invention will be more clearly understood in the following detailed description of preferred embodiments with reference to the accompanying drawings. The drawings in this application are schematic, primarily intended to illustrate the process steps and the hierarchical relationship between layers. Shapes, thicknesses, and widths are not drawn to scale.
[0064] Please refer to Figure 2A-2Q , which is a cross-sectional schematic diagram showing a method for manufacturing a semiconductor integrated structure 20 having high and low voltage components and capacitors according to an embodiment of the present invention. Figure 2A As shown, a substrate 21 is first provided, and insulating regions 22a and 22b are formed on the substrate. The substrate 21 is, for example but not limited to, a P-type or N-type semiconductor substrate. This is well known to those skilled in the art and will not be described in detail here. Figure 2B As shown, a bottom thermal oxide layer 23 is then formed on the substrate 21, wherein the bottom thermal oxide layer 23 completely covers the high voltage device region HV2, the low voltage device region LV2 and the capacitor region PIP1 of the substrate 21. Figure 2C As shown, a high voltage well region 24 is formed in the high voltage device region HV2. The high voltage well region 24 is formed, for example, by an ion implantation process step, where N-type or P-type impurities are implanted in the form of accelerated ions into the region defined by the mask 24'. This is well known to those skilled in the art and will not be described in detail here. Figure 2D As shown, a chemical vapor deposition (CVD) oxide layer 25 is formed to completely cover the bottom thermal oxide layer 23. Figure 2D As shown, a polysilicon hard mask layer 26 is then formed to completely cover the CVD oxide layer 25. In one embodiment, after the polysilicon hard mask layer 26 is formed, N-type or P-type ions are accelerated to implant the polysilicon hard mask layer 26 by, for example, an ion implantation process.
[0065] Continue, such as Figure 2E and Figure 2F As shown, the polysilicon hard mask layer 26 is etched using a mask 26', and a high-voltage polysilicon hard mask 26a is formed in the high-voltage device region HV2 and a first electrode plate 26b is formed in the capacitor region. Figure 2GAs shown, the CVD oxide layer 25 is etched using, for example, a wet etching process, and a high-voltage polysilicon hard mask 26a and a first electrode plate 26b are used as etching stops to simultaneously form a high-voltage CVD oxide region 25a in the high-voltage device region HV2 and a capacitor CVD oxide region 25b in the capacitor region PIP1. The method for forming the high-voltage CVD oxide region 25a, such as, but not limited to, a deposition process, is well known to those skilled in the art and will not be described in detail here.
[0066] Continue, such as Figure 2H As shown, a low voltage well region 27 is formed in the low voltage device region LV2. The low voltage well region 27 is formed, for example, by an ion implantation process step, through the bottom thermal oxide layer 23 as a sacrificial layer, and N-type or P-type impurities are implanted in the form of accelerated ions through the sacrificial layer into the low voltage device region LV2 defined by the mask 27', to form the low voltage well region 27. Figure 2I As shown, the bottom thermal oxide layer 23 is etched, and the high-voltage polysilicon hard mask 26a and the first electrode plate 26b are used as etching stops to simultaneously form a high-voltage bottom thermal oxide region 23a in the high-voltage device region HV2 and a capacitor bottom thermal oxide region 23b in the capacitor region PIP1. In one embodiment, the bottom thermal oxide layer 23 is etched using a wet etching process, for example, so that the high-voltage sidewalls of the high-voltage bottom thermal oxide region 23a and the capacitor sidewalls of the capacitor bottom thermal oxide region 23b have non-perpendicular angles with the top surface of the substrate 21.
[0067] Afterwards, if Figure 2J As shown, high voltage gate oxide layers 28c and 28a are formed on the high voltage device region HV2 on the substrate 21 and low voltage gate oxide layer 29 is formed on the low voltage device region LV2 on the substrate 21. Figure 2J As shown, when forming the high voltage gate oxide layer 28c, 28a or the low voltage gate oxide layer 29, the capacitor dielectric layer 28b is formed at the same time, connected to and completely covering the first electrode plate 26b. Figure 2K As shown, a gate polysilicon layer 30 is formed to connect and completely cover the high voltage gate oxide layers 28c and 28a, the low voltage gate oxide layer 29 and the capacitor dielectric layer 28b. In one embodiment, after the gate polysilicon layer 30 is formed, N-type or P-type ions are accelerated by, for example, an ion implantation process step to implant the gate polysilicon layer 30. Then, as shown in FIG. Figure 2L and Figure 2M As shown, the gate polysilicon layer 30 is etched using a mask 30' to simultaneously form a high voltage gate 30a in the high voltage device region HV2, a low voltage gate 30b in the low voltage device region LV2 and a second electrode plate 30c in the capacitor region PIP1. Figure 2M As shown, the high voltage gate 30a is in direct contact with the high voltage polysilicon hard shield 26a. Figure 2MAs shown, a high voltage body region 37 is formed in the high voltage well region 24 of the high voltage device region HV2 , and a high voltage source (described in detail later) is located in the high voltage body region 37 .
[0068] like Figure 2N As shown, after forming the high voltage grid 30a, the low voltage grid 30b and the second electrode plate 30c, two high voltage spacer layers 31a are formed to connect to both sides of the high voltage grid 30a and two low voltage spacer layers 31b are formed to connect to both sides of the low voltage grid 30b. Figure 2N As shown, in one embodiment, after forming the high voltage gate 30a, the low voltage gate 30b and the second electrode plate 30c, two capacitor spacer layers 31c are formed and connected to both sides of the second electrode plate 30c. Figure 2O As shown, then, a high voltage source 32a and a high voltage drain 33a are formed in the high voltage device region HV2, and a low voltage source 32b and a low voltage drain 33b are formed in the low voltage device region LV2. Figure 2P As shown, a plurality of metal silicide layers 34 are formed simultaneously corresponding to the upper surfaces of the high voltage gate 30a, the high voltage source 32a, the high voltage drain 33a, the low voltage gate 30b, the low voltage source 32b, the low voltage drain 33b, the first electrode plate 26b and the second electrode plate 30c by, for example, a metal silicide process step. Figure 2Q As shown, an inter-layer dielectric (ILD) layer 35 is formed on the substrate 21 and completely covers the high voltage gate 30a, the low voltage gate 30b and the second electrode plate 30c. Figure 2Q As shown, a plurality of electrical contact plugs 36 are then formed on (eg, through) the ILD layer 35 to electrically connect to the plurality of silicide metal layers 34 .
[0069] In summary, the present invention utilizes a high-voltage polysilicon hard shield and a first electrode plate to achieve a two-stage sloped high-voltage bottom thermal oxidation region and a high-voltage CVD oxidation region without the use of an additional mask, can simultaneously form a PIP capacitor, and can avoid the occurrence of shallow trench insulation (STI) pitting, and reduce the thermal process to prevent the integrated process from exceeding the thermal budget.
[0070] The present invention has been described above with respect to the preferred embodiments, but the above is only to make it easier for those skilled in the art to understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. Under the same spirit of the present invention, those skilled in the art can think of various equivalent changes. For example, other process steps or structures, such as lightly doped drain regions, etc., can be added without affecting the main characteristics of the component; for example, lithography technology is not limited to mask technology, but may also include electron beam lithography technology. All of these can be derived by analogy based on the teachings of the present invention. In addition, the various embodiments described are not limited to individual applications, but may also be applied in combination, such as but not limited to the use of two embodiments together. Therefore, the scope of the present invention should cover the above and all other equivalent changes. In addition, any embodiment of the present invention does not necessarily achieve all purposes or advantages, and therefore, any claim should not be limited to this.
Claims
1. A method for manufacturing a semiconductor integrated structure having high and low voltage components and capacitors, comprising: forming a bottom thermal oxide layer on a substrate, wherein the bottom thermal oxide layer completely covers a high-voltage device region, a low-voltage device region, and a capacitor region of the substrate; forming a high-voltage well region in the high-voltage device region; forming a chemical vapor deposition (CVD) oxide layer to completely cover the bottom thermal oxide layer; forming a polysilicon hard mask layer to completely cover the CVD oxide layer; Etching the polysilicon hard shield layer to simultaneously form a high-voltage polysilicon hard shield in the high-voltage device region and a first electrode plate in the capacitor region; Etching the CVD oxide layer and using the high-voltage polysilicon hard mask and the first electrode plate as an etching stop layer to simultaneously form a high-voltage CVD oxide region in the high-voltage device region and a capacitor CVD oxide region in the capacitor region; forming a low voltage well region in the low voltage device region; Etching the bottom thermal oxide layer and using the high-voltage polysilicon hard mask and the first electrode plate as etching stop layers to simultaneously form a high-voltage bottom thermal oxide region in the high-voltage device region and a capacitor bottom thermal oxide region in the capacitor region; forming a high voltage gate oxide layer in the high voltage device region on the substrate; forming a low voltage gate oxide layer in the low voltage device region on the substrate; in, When forming the high-voltage gate oxide layer or the low-voltage gate oxide layer, a capacitor dielectric layer is simultaneously formed to connect to and completely cover the first electrode plate; forming a gate polysilicon layer to connect and completely cover the high-voltage gate oxide layer, the low-voltage gate oxide layer, and the capacitor dielectric layer; and The gate polysilicon layer is etched to simultaneously form a high-voltage gate in the high-voltage device region, a low-voltage gate in the low-voltage device region, and a second electrode plate in the capacitor region.
2. The method for manufacturing a semiconductor integrated structure having high and low voltage components and capacitors according to claim 1, wherein: The step of forming the low-voltage well region in the low-voltage device region includes: using an ion implantation process step to use the bottom thermal oxide layer as a sacrificial layer and implanting accelerated ions through the sacrificial layer into the low-voltage device region to form the low-voltage well region.
3. The method for manufacturing a semiconductor integrated structure having high and low voltage components and capacitors according to claim 1, wherein: The step of etching the CVD oxide layer and using the high-voltage polysilicon hard shield and the first electrode plate as an etching barrier layer to simultaneously form the high-voltage CVD oxide region in the high-voltage component region and the capacitor CVD oxide region in the capacitor region includes etching the CVD oxide layer using a wet etching process step.
4. The method for manufacturing a semiconductor integrated structure having high and low voltage components and capacitors according to claim 3, wherein: The step of etching the bottom thermal oxide layer and using the high-voltage polysilicon hard mask and the first electrode plate as etching stop layers to simultaneously form the high-voltage bottom thermal oxide region in the high-voltage device region and the capacitor bottom thermal oxide region in the capacitor region includes: etching the bottom thermal oxide layer using a wet etching process step so that a high-voltage sidewall of the high-voltage bottom thermal oxide region and a capacitor sidewall of the capacitor bottom thermal oxide region respectively have a non-perpendicular tilt angle with an upper surface of the substrate.
5. The method for manufacturing a semiconductor integrated structure having high and low voltage components and capacitors according to claim 1, wherein: The method further comprises: after forming the polysilicon hard shielding layer, accelerating N-type or P-type ions by an ion implantation process step to implant the polysilicon hard shielding layer.
6. The method for manufacturing a semiconductor integrated structure having high and low voltage components and capacitors according to claim 1, wherein: The method further comprises: after forming the gate polysilicon layer, accelerating N-type or P-type ions by an ion implantation process step to implant the gate polysilicon layer.
7. The method for manufacturing a semiconductor integrated structure having high and low voltage components and capacitors according to claim 1, wherein: The high voltage gate is in direct contact with the high voltage polysilicon hard shield.
8. The method for manufacturing a semiconductor integrated structure having high and low voltage components and capacitors according to claim 1, wherein: The method further comprises: after forming the high voltage grid, the low voltage grid and the second electrode plate, forming two high voltage spacer layers correspondingly connected to both sides of the high voltage grid and two low voltage spacer layers correspondingly connected to both sides of the low voltage grid.
9. The method for manufacturing a semiconductor integrated structure having high and low voltage components and capacitors according to claim 8, wherein: The method further comprises: after forming the high-voltage grid, the low-voltage grid and the second electrode plate, forming two capacitor spacing layers correspondingly connected to two sides of the second electrode plate.
10. The method for manufacturing a semiconductor integrated structure having high and low voltage components and capacitors according to claim 1, wherein: The method further comprises: simultaneously forming a high voltage source and a high voltage drain in the high voltage component region, and a low voltage source and a low voltage drain in the low voltage component region.
11. The method for manufacturing a semiconductor integrated structure having high and low voltage components and capacitors according to claim 10, wherein: It also includes: using a silicide metal process step to simultaneously form multiple silicide metal layers corresponding to the upper surfaces of the high-voltage gate, the high-voltage source, the high-voltage drain, the low-voltage gate, the low-voltage source, the low-voltage drain, the first electrode plate and the second electrode plate.
12. The method for manufacturing a semiconductor integrated structure having high and low voltage components and capacitors according to claim 1, wherein: The method further comprises forming an interlayer dielectric (ILD) layer on the substrate and completely covering the high voltage gate, the low voltage gate and the second electrode plate.
13. The method for manufacturing a semiconductor integrated structure having high and low voltage components and capacitors according to claim 12, wherein: The method further includes forming a plurality of electrical contact plugs on the ILD layer to electrically connect the plurality of silicide metal layers.
14. The method for manufacturing a semiconductor integrated structure having high and low voltage components and capacitors according to claim 1, wherein: The method further comprises: forming a high-voltage body region in the high-voltage well region of the high-voltage element region, and the high-voltage source is located in the high-voltage body region.