Display device

Abstract

A display device includes: first pixels disposed in a first row and a first column; a second pixel disposed in the first row and a second column next to the first column; third pixels disposed in a second row beside the first row and the first column; fourth pixels disposed in the second row and the second column; a first scan line extending in a first direction between the first row and the second row; and a first gate pattern connected to the first scan line. The first gate pattern includes a gate electrode of a transistor of each of the first to fourth pixels.

Description

Technical Field

[0001] An embodiment of the present invention relates to a display device. Background Art

[0002] With the development of information-oriented society, various demands for display devices are increasing. For example, display devices are being adopted by various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices and smart TVs. The display device can be a flat panel display device such as a liquid crystal display device, a field emission display device and a light-emitting display device (such as an organic light-emitting display device). Among such flat panel display devices, the light-emitting display device includes a light-emitting element that can emit light by itself, so that each of the multiple pixels of the display panel can emit light by itself. Therefore, the light-emitting display device can display an image without a backlight unit that supplies light to the display panel. Summary of the Invention

[0003] An embodiment of the present invention provides a display device in which the area of ​​a pixel circuit is reduced by reducing the number of scan lines to realize a high-resolution display device.

[0004] An embodiment of the present invention provides a display device, comprising: a first pixel arranged in a first row and a first column; a second pixel arranged in a second column adjacent to the first row and the first column; a third pixel arranged in a second row and a first column adjacent to the first row; a fourth pixel arranged in a second row and a second column; a first scan line extending in a first direction between the first row and the second row; and a first gate pattern connected to the first scan line. In such an embodiment, the first gate pattern includes a gate electrode of a transistor in each of the first to fourth pixels.

[0005] In an embodiment, the display device may further include: a second scan line disposed below the second row and extending in the first direction; and a second gate pattern connected to the second scan line. In such an embodiment, the second gate pattern may include a gate electrode of another transistor in each of the third pixel and the fourth pixel.

[0006] In an embodiment, the display device may further include: an initialization voltage line for supplying an initialization voltage; a drive voltage line for supplying a drive voltage; and a data line for supplying a data voltage. In such an embodiment, each of the first to fourth pixels may include: a light-emitting element disposed on a substrate; a first transistor for supplying a drive current to a second node connected to a first electrode of the light-emitting element based on a voltage at a first node connected to a gate electrode of the first transistor; a first capacitor connected between the first node and the initialization voltage line; a second transistor connected to the first node; a second capacitor connected between the data line and a third node, the third node being connected to a drain electrode of the second transistor; and a third transistor connected between the third node and the second node.

[0007] In an embodiment, the first scan line may supply a first scan signal to the third transistor of the first pixel, the third transistor of the second pixel, the second transistor of the third pixel, and the second transistor of the fourth pixel through the first gate pattern.

[0008] In an embodiment, the second scan line may supply the second scan signal to the third transistor of the third pixel and the third transistor of the fourth pixel through the second gate pattern.

[0009] In an embodiment, the display device may further include: an active layer, disposed on the substrate and including a semiconductor region of each of the first to third transistors; a first gate layer, disposed on the active layer and including a gate electrode of the first transistor, a gate electrode of the second transistor, and a gate electrode of the third transistor of each of the first to fourth pixels; a second gate layer, disposed on the first gate layer and including a first scan line and a second scan line; a first source metal layer, disposed on the second gate layer; and a second source metal layer, disposed on the first source metal layer.

[0010] In an embodiment, the first gate pattern may be defined by the first gate layer and include a gate electrode of the third transistor of the first pixel, a gate electrode of the third transistor of the second pixel, a gate electrode of the second transistor of the third pixel, and a gate electrode of the second transistor of the fourth pixel.

[0011] In an embodiment, the second gate pattern may be defined by the first gate layer and may include a gate electrode of the third transistor of the third pixel and a gate electrode of the third transistor of the fourth pixel.

[0012] In an embodiment, the initialization voltage line may include a first portion defined by the second gate layer and extending in a first direction; and a second portion defined by the second source metal layer, extending in a second direction intersecting the first direction, and connected to the first portion.

[0013] In an embodiment, the first electrode of the first capacitor may include a gate electrode of the first transistor, and the second electrode of the first capacitor may be a portion of the first portion of the initialization voltage line.

[0014] In an embodiment, the display device may further include: a capacitor electrode disposed in the second source metal layer. In such an embodiment, the data line may be defined by the first source metal layer. In such an embodiment, the first electrode of the second capacitor may be the capacitor electrode, and the second electrode of the second capacitor may be part of the data line.

[0015] An embodiment of the present invention provides a display device, comprising: a first pixel arranged in a first row and a first column; a second pixel arranged in a second column adjacent to the first row and the first column; a third pixel arranged in a third column adjacent to the first row and the second column; a fourth pixel arranged in a second row and a first column adjacent to the first row; a fifth pixel arranged in a second row and a second column; a sixth pixel arranged in a second row and a third column; a first scan line extending in a first direction between the first row and the second row; a first gate pattern connected to the first scan line and overlapping the second, third, fifth, and sixth pixels; and a drive voltage line extending in a second direction intersecting the first direction between the first and second columns. In such an embodiment, the drive voltage line supplies a drive voltage to the first, second, fourth, and fifth pixels.

[0016] In an embodiment, the display device may further include: an initialization voltage line for supplying an initialization voltage; and a data line for supplying a data voltage. In such an embodiment, each of the first to sixth pixels may include: a light-emitting element disposed on a substrate; a first transistor for supplying a driving current to a second node connected to the first electrode of the light-emitting element based on a voltage at a first node connected to the gate electrode of the first transistor; a first capacitor connected between the first node and the initialization voltage line; a second transistor connected to the first node; a second capacitor connected between the data line and a third node, the third node being connected to the drain electrode of the second transistor; and a third transistor connected between the third node and the second node.

[0017] In an embodiment, the source electrode of the first transistor of the first pixel and the source electrode of the first transistor of the second pixel may be integrally formed with each other as a single, integral, and indivisible part. In such an embodiment, a drive voltage line may supply a drive voltage to the source electrode of the first transistor of each of the first pixel and the second pixel.

[0018] In an embodiment, the first gate pattern may include a gate electrode of the third transistor of the second pixel, a gate electrode of the third transistor of the third pixel, a gate electrode of the second transistor of the fifth pixel, and a gate electrode of the second transistor of the sixth pixel.

[0019] In an embodiment, the display device may further include: a second scan line disposed below the second row and extending in the first direction; and a second gate pattern connected to the second scan line. In such an embodiment, the second gate pattern may overlap with the fifth pixel and the sixth pixel.

[0020] In an embodiment, the second gate pattern may include a gate electrode of the third transistor of the fifth pixel and a gate electrode of the third transistor of the sixth pixel.

[0021] In an embodiment, the display device may further include: an active layer, disposed on the substrate and including a semiconductor region of each of the first to third transistors; a first gate layer, disposed on the active layer and including a gate electrode of the first transistor, a gate electrode of the second transistor, and a gate electrode of the third transistor of each of the first to sixth pixels; a second gate layer, disposed on the first gate layer and including a first scan line and a second scan line; a first source metal layer, disposed on the second gate layer; and a second source metal layer, disposed on the first source metal layer.

[0022] In an embodiment, the initialization voltage line may include a first portion defined by the second gate layer and extending in a first direction; and a second portion defined by the second source metal layer, extending in a second direction intersecting the first direction, and connected to the first portion.

[0023] In an embodiment, the first electrode of the first capacitor may include a gate electrode of the first transistor.In such an embodiment, the second electrode of the first capacitor may be part of the first portion of the initialization voltage line.

[0024] In an embodiment of the present invention, a scan line supplies scan signals to transistors of pixels arranged in rows and columns through a single gate pattern, so that the number of scan lines can be reduced, thereby reducing the area of ​​the pixel circuit. As a result, a high-resolution display device can be realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] These and / or other features of the present invention will become apparent and more readily understood from the following description of embodiments taken in conjunction with the accompanying drawings.

[0026] Figure 1 is a view showing a virtual reality device including a display device according to an embodiment.

[0027] Figure 2 and Figure 3 : is a view showing a head-mounted display including a display device according to the embodiment.

[0028] Figure 4 is a circuit diagram illustrating a pixel of a display device according to an embodiment of the present disclosure.

[0029] Figure 5 is a view showing the arrangement of pixels in a display device according to an embodiment of the present disclosure.

[0030] Figure 6 It shows Figure 5 A view of some layer of views.

[0031] Figure 7 It shows Figure 5 The view of some other layer.

[0032] Figure 8 It shows Figure 5 A view of one of a plurality of pixels.

[0033] Figure 9 It shows Figure 8 A view of some layer of views.

[0034] Figure 10 It shows Figure 8 The view of some other layer.

[0035] Figure 11 is a cross-sectional view illustrating a pixel in a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] The present invention will be described more fully hereinafter with reference to the accompanying drawings, which illustrate various embodiments of the invention. However, the present invention may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. Throughout the specification, like reference numerals indicate like components. In the drawings, the thickness of layers and regions is exaggerated for clarity.

[0037] It will be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Therefore, without departing from the teachings herein, the "first element," "first component," "first region," "first layer," or "first section" discussed below may be referred to as the "second element," "second component," "second region," "second layer," or "second section."

[0038] It will be understood that when a layer or substrate is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0039] The terms used herein are only for the purpose of describing specific embodiments and are not intended to be restrictive. As used herein, unless the context clearly indicates otherwise, the singular form "one", "one (kind / person)" and "described (should)" are intended to include the plural form comprising "at least one (kind / person)". Therefore, in the claims, "one" element is quoted, followed by "described" element, including one element and multiple elements. For example, unless the context clearly indicates otherwise, "one element" has the same meaning as "at least one element". "At least one (kind / person)" is not interpreted as limiting "one" or "one (kind / person)". "Or" means "and / or". "At least one (kind / person) of A and B" or "at least one (kind / person) selected from A and B" means "A and / or B". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. It will also be understood that when used in this specification, the terms “comprises and / or comprising” or “includes and / or including” specify the presence of stated features, regions, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or groups thereof.

[0040] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the drawings. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the drawings. For example, if the device in a drawing is turned over, an element described as being on the "lower" side of the other elements would subsequently be positioned as being on the "upper" side of the other elements. Thus, depending on the particular orientation of the drawing, the term "lower" can encompass both "lower" and "upper" orientations. Similarly, if the device in a drawing is turned over, an element described as being "below" or "beneath" other elements would subsequently be positioned as being "above" the other elements. Thus, the terms "below" or "beneath" can encompass both "upper" and "lower" orientations.

[0041] As used herein, “about” or “approximately” is inclusive of the stated value and means within the range of acceptable deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and errors associated with measurement of the particular quantity (i.e., limitations of the measurement system).

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that, unless expressly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their context in the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense.

[0043] The embodiments are described herein with reference to cross-sectional views which are schematic diagrams of idealized embodiments. Therefore, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shapes due to, for example, manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. In addition, sharp corners shown may be rounded. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0044] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0045] Figure 1 is a view showing a virtual reality device including a display device according to an embodiment.

[0046] Reference Figure 1The virtual reality device 1 may include a display device 10, a left-eye lens 10a, a right-eye lens 10b, a support frame 20, temples 30a and 30b, a reflective member 40, and a display device housing 50.

[0047] In another embodiment, the virtual reality device 1 may be applied to a head mounted display (HMD) including a band that can be worn on the head instead of the temples 30a and 30b. Therefore, it will be understood that the virtual reality device 1 is not limited to Figure 1 Rather, the virtual reality device 1 shown in FIG. 1 can be applied to various electronic devices in various forms.

[0048] The display device housing 50 may include the display device 10 and the reflective member 40. Specifically, the display device 10 and the reflective member 40 may be disposed within the display device housing 50. The image displayed on the display device 10 may be reflected by the reflective member 40 and provided to the user's right eye through the right-eye lens 10 b. Thus, the user may view the virtual reality image displayed on the display device 10 through the right eye.

[0049] In an embodiment, Figure 1 As shown in FIG, the display device housing 50 may be disposed at the right end of the support frame 20, but the position of the display device housing 50 is not limited thereto. In another embodiment, for example, the display device housing 50 may be disposed at the left end of the support frame 20. In such an embodiment, the image displayed on the display device 10 is reflected by the reflective member 40 and provided to the user's left eye through the left-eye lens 10a. Thus, the user can view the virtual reality image displayed on the display device 10 through the left eye.

[0050] In another embodiment, for example, the display device housing 50 may be respectively provided at both the left and right ends of the support frame 20. In such an embodiment, the user can view the virtual reality image displayed in the display device 10 through both the left eye and the right eye.

[0051] Figure 2 and Figure 3 : is a view showing a head-mounted display including a display device according to the embodiment.

[0052] Reference Figure 2 and Figure 3, an embodiment of the display device 10 can be applied to a head-mounted display (HMD). The first display device 1100 can provide an image to the right eye of the user, and the second display device 1200 can provide an image to the left eye of the user. The display surfaces of the first display device 1100 and the second display device 1200 can be on a plane defined by the X-axis direction (or the first direction) and the Y-axis direction (or the second direction). Here, the Z-axis direction (or the third direction) can be a direction perpendicular to the X-axis direction and the Y-axis direction or a thickness direction of the first display device 1100 and the second display device 1200.

[0053] The first lens array 1310 may be disposed between the first display device 1100 and the housing cover 1700. The first lens array 1310 may include a plurality of lenses 1311. The plurality of lenses 1311 may include convex lenses convex toward the housing cover 1700.

[0054] The second lens array 1410 may be disposed between the second display device 1200 and the housing cover 1700. The second lens array 1410 may include a plurality of lenses 1411. The plurality of lenses 1411 may include convex lenses convex toward the housing cover 1700.

[0055] The display panel housing 1600 can accommodate the first display device 1100, the second display device 1200, the first lens array 1310 and the second lens array 1410. One surface of the display panel housing 1600 can be opened to accommodate the first display device 1100, the second display device 1200, the first lens array 1310 and the second lens array 1410.

[0056] The housing cover 1700 may cover the open surface of the display panel housing 1600. The housing cover 1700 may include a first opening 1710 for the user's left eye and a second opening 1720 for the user's right eye. In an embodiment, for example, the first opening 1710 and the second opening 1720 may be formed in a rectangular shape, but the shapes of the first opening 1710 and the second opening 1720 are not limited thereto. In another embodiment, for example, the first opening 1710 and the second opening 1720 may be formed in a circular shape or an elliptical shape. In another embodiment, for example, the first opening 1710 and the second opening 1720 may be integrated to form a single opening.

[0057] The first opening 1710 may be aligned with the second display device 1200 and the second lens array 1410, and the second opening 1720 may be aligned with the first display device 1100 and the first lens array 1310. Therefore, the user may see a virtual image of the image in the second display device 1200 magnified by the second lens array 1410 through the first opening 1710, and see a virtual image of the image in the first display device 1100 magnified by the first lens array 1310 through the second opening 1720.

[0058] A head strap band 1800 can secure the display panel housing 1600 to the user's head so that the first opening 1710 and the second opening 1720 of the housing cover 1700 are aligned with the user's left eye and the user's right eye, respectively. The head strap band 1800 can be connected to the top, left, and right sides of the display panel housing 1600.

[0059] Figure 4 is a circuit diagram illustrating a pixel of a display device according to an embodiment of the present disclosure.

[0060] Reference Figure 4 , Figure 1 The display device 10 or Figure 2 An embodiment of the display device 10 may include a plurality of pixels SP. In an embodiment, the pixels SP may be employed in portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs). In another embodiment, the pixels SP may be applied as display units of televisions, laptop computers, monitors, electronic billboards, smart watches, watch phones, or Internet of Things (IoT) devices.

[0061] In an embodiment, the pixel SP can be connected to the nth scan line GWL[n], the (n+1)th scan line GWL[n+1], the data line DL, the initialization voltage line VIL, the driving voltage line VDL and the low-level voltage line VSL, where n is an integer equal to or greater than 2.

[0062] The pixel SP may include a light emitting element ED and a pixel circuit driving the light emitting element ED. The pixel circuit may include a first transistor T1, a second transistor T2, and a third transistor T3, and a first capacitor C1 and a second capacitor C2.

[0063] The first transistor T1 can supply a driving current to the light emitting element ED. The first transistor T1 may include a gate electrode, a source electrode, and a drain electrode. The gate electrode of the first transistor T1 may be connected to a first node N1, the source electrode of the first transistor T1 may be connected to a driving voltage line VDL, and the drain electrode of the first transistor T1 may be connected to a second node N2 which is a first electrode of the light emitting element ED. The first transistor T1 may control a source-drain current (Isd) (hereinafter referred to as “driving current (Isd)”) according to a data voltage applied to the gate electrode. The driving current (Isd) flowing through the channel of the first transistor T1 may be proportional to the square of the difference between the threshold voltage (Vth) of the first transistor T1 and the voltage (Vsg) between the source electrode and the gate electrode of the first transistor T1, that is, the driving current (Isd) satisfies the following equation: Isd=k×(Vsg–Vth) 2 , wherein Isd represents the source-drain current, k represents a proportionality coefficient determined by the structure and physical properties of the first transistor T1, Vsg represents the source-gate voltage of the first transistor T1, and Vth represents the threshold voltage of the first transistor T1.

[0064] The light-emitting element ED can receive a driving current (Isd) to emit light. The amount or brightness of light emitted from the light-emitting element ED can be proportional to the magnitude of the driving current (Isd). The light-emitting element ED may include a first electrode, a second electrode, and an emission layer disposed between the first electrode and the second electrode. The first electrode of the light-emitting element ED may be connected to a second node N2. The first electrode of the light-emitting element ED may be electrically connected to the drain electrode of the first transistor T1 and the drain electrode of the third transistor T3 through the second node N2. The second electrode of the light-emitting element ED may be connected to a low-level voltage line VSL to receive a low-level voltage from the low-level voltage line VSL. In an embodiment, for example, the first electrode of the light-emitting element ED may be an anode electrode or a pixel electrode, and the second electrode of the light-emitting element ED may be a cathode electrode or a common electrode. However, it will be understood that the present disclosure is not limited thereto.

[0065] The second transistor T2 can be turned on by the nth scan signal of the nth scan line GWL[n] to electrically connect the first node N1 to the third node N3. The gate electrode of the second transistor T2 can be connected to the nth scan line GWL[n], the source electrode of the second transistor T2 can be connected to the first node N1, and the drain electrode of the second transistor T2 can be connected to the third node N3. The first node N1 can be electrically connected to the first electrode of the first capacitor C1, and the voltage of the first node N1 can be initialized by the initialization voltage line VIL connected to the second electrode of the first capacitor C1. The third node N3 can be electrically connected to the first electrode of the second capacitor C2, and the voltage of the third node N3 can be changed to a voltage equal to the data voltage by the data line DL connected to the second electrode of the second capacitor C2.

[0066] The third transistor T3 may be turned on by the (n+1)th scan signal of the (n+1)th scan line GWL[n+1] to electrically connect the third node N3 to the second node N2. A gate electrode of the third transistor T3 may be connected to the (n+1)th scan line GWL[n+1], a source electrode of the third transistor T3 may be connected to the third node N3, and a drain electrode of the third transistor T3 may be connected to the second node N2.

[0067] Each of the first transistor T1, the second transistor T2, and the third transistor T3 may include a silicon-based active layer. In an embodiment, for example, each of the first transistor T1, the second transistor T2, and the third transistor T3 may include an active layer made of low-temperature polysilicon (LTPS). The active layer made of low-temperature polysilicon may have high electron mobility and excellent conduction characteristics. Therefore, since the display device 10 (see Figure 1 or Figure 2 ) includes transistors having excellent conduction characteristics, and thus can stably and efficiently drive a plurality of pixels SP.

[0068] The first transistor T1, the second transistor T2, and the third transistor T3 may be p-type transistors. In an embodiment, for example, each of the first transistor T1, the second transistor T2, and the third transistor T3 may output a current flowing into a source electrode to a drain electrode in response to a gate low voltage applied to the gate electrode.

[0069] In another embodiment, for example, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 may include an oxide-based active layer. The transistor including the oxide-based active layer may have a coplanar structure in which a gate electrode is disposed on top. The transistor including the oxide-based active layer may be an n-type transistor and may output current flowing into the drain electrode to the source electrode based on a gate high voltage applied to the gate electrode.

[0070] The first capacitor C1 may be connected between the first node N1, which is the gate electrode of the first transistor T1, and the initialization voltage line VIL. In an embodiment, for example, the first electrode of the first capacitor C1 may be connected to the first node N1, and the second electrode of the first capacitor C1 may be connected to the initialization voltage line VIL, so that the potential difference between the gate electrode of the first transistor T1 and the initialization voltage line VIL can be maintained. Therefore, the voltage of the first node N1 can be initialized by the initialization voltage line VIL.

[0071] The second capacitor C2 may be connected between the third node N3 and the data line DL. In an embodiment, for example, a first electrode of the second capacitor C2 may be connected to the third node N3, and a second electrode of the second capacitor C2 may be connected to the data line DL, so that a potential difference between the third node N3 and the data line DL can be maintained. Therefore, the voltage of the third node N3 can be changed to a voltage equal to the data voltage through the data line DL.

[0072] Figure 5 is a view showing the arrangement of pixels in a display device according to an embodiment of the present disclosure. Figure 6 It shows Figure 5 , showing in particular the active layer ACTL (see Figure 11 ), the first gate layer GTL1 (see Figure 11 ) and the second gate layer GTL2 (see Figure 11 ) stacking structure. Figure 7 It shows Figure 5 1 and 2. The diagram of some other layers of FIG. 1 shows in particular the first source metal layer SDL1 (see FIG. Figure 11 ) and the second source metal layer SDL2 (see Figure 11 ) stacking structure. Figure 8 It shows Figure 5 , and is an enlarged view of the 22nd pixel SP22. Figure 9 It shows Figure 8 , showing in particular the active layer ACTL (see Figure 11 ), the first gate layer GTL1 (see Figure 11 ) and the second gate layer GTL2 (see Figure 11 ) stacking structure. Figure 10 It shows Figure 8 1 and 2. The diagram of some other layers of FIG. 1 shows in particular the first source metal layer SDL1 (see FIG. Figure 11 ) and the second source metal layer SDL2 (see Figure 11 ) stacking structure. Figure 11 is a cross-sectional view illustrating a pixel in a display device according to an embodiment of the present disclosure.

[0073] Reference Figures 5 to 11 In an embodiment, the pixels SP may be arranged in rows and columns, that is, in a matrix form. In an embodiment, for example, the pixels SP may be arranged along the first row CRW1 and the second row CRW2 and the first column COL1, the second column COL2, the third column COL3, and the fourth column COL4. The 11th pixel SP11, the 12th pixel SP12, the 13th pixel SP13, and the 14th pixel SP14 may be arranged in the first row CRW1 and may be electrically connected to the (n-1)th scan line GWL[n-1] and the nth scan line GWL[n]. The 21st pixel SP21, the 22nd pixel SP22, the 23rd pixel SP23, and the 24th pixel SP24 may be arranged in the second row CRW2 and may be electrically connected to the nth scan line GWL[n] and the (n+1)th scan line GWL[n+1]. Pixels SP adjacent to each other in the Y-axis direction (or the second direction) may share one scan line. The n-th scan line GWL[n] may be disposed between the first row CRW1 and the second row CRW2 .

[0074] In an embodiment, Figure 6 As shown in , the n-th scan line GWL[n] can supply the n-th scan signal to four transistors through one gate pattern GTP. One gate pattern GTP can overlap four pixels SP. One gate pattern GTP can overlap two rows and two columns. Figure 6 , one gate pattern GTP may overlap with the lower right side of the 12th pixel SP12, the lower left side of the 13th pixel SP13, the upper right side of the 22nd pixel SP22, and the upper left side of the 23rd pixel SP23. In other words, one gate pattern GTP may overlap with the gate electrode GE3 of the third transistor T3 of the 12th pixel SP12, the gate electrode GE3 of the third transistor T3 of the 13th pixel SP13, the gate electrode GE2 of the second transistor T2 of the 22nd pixel SP22, and the gate electrode GE2 of the second transistor T2 of the 23rd pixel SP23. In an embodiment, for example, the nth scan line GWL[n] may provide the nth scan signal to the third transistor T3 of the 12th pixel SP12, the third transistor T3 of the 13th pixel SP13, the second transistor T2 of the 22nd pixel SP22, and the second transistor T2 of the 23rd pixel SP23 via the one gate pattern GTP. Therefore, the n-th scan line GWL[n] can provide the n-th scan signal to both the first row CRW1 and the second row CRW2, thereby reducing the number of scan lines in the display device 10 and reducing the area of ​​the pixel circuit. In this way, a high-resolution display device can be effectively implemented.

[0075] In an embodiment, Figure 7As shown in , the data line DL may extend in the Y-axis direction. Each of the plurality of data lines DL may be associated with a column. The pixels SP arranged in each of the first column COL1, the second column COL2, the third column COL3, and the fourth column COL4 may receive a data voltage from one data line DL.

[0076] The driving voltage line VDL may extend in the Y-axis direction. Pixels SP adjacent to each other in the X-axis direction (or the first direction) may share one driving voltage line VDL. One driving voltage line VDL may be provided between the first column COL1 and the second column COL2 to provide a driving voltage to the 11th pixel SP11, the 12th pixel SP12, the 21st pixel SP21, and the 22nd pixel SP22. Another driving voltage line VDL may be provided between the third column COL3 and the fourth column COL4 to provide a driving voltage to the 13th pixel SP13, the 14th pixel SP14, the 23rd pixel SP23, and the 24th pixel SP24.

[0077] The active layer ACTL of the 11th pixel SP11 and the active layer ACTL of the 12th pixel SP12 may be symmetrical about the axis in the Y-axis direction. The source electrode SE1 of the first transistor T1 of the 11th pixel SP11 and the source electrode SE1 of the first transistor T1 of the 12th pixel SP12 may be integrally formed with each other as a single, integral, and indivisible part. Therefore, the pixels SP arranged in the first column COL1 and the second column COL2 may share one driving voltage line VDL, and the source electrode SE1 of the first transistor T1 of each of the 11th pixel SP11 and the 12th pixel SP12 may receive a driving voltage through the one driving voltage line VDL.

[0078] The active layer ACTL of the 13th pixel SP13 and the active layer ACTL of the 14th pixel SP14 may be symmetrical about the axis in the Y-axis direction. The source electrode SE1 of the first transistor T1 of the 13th pixel SP13 and the source electrode SE1 of the first transistor T1 of the 14th pixel SP14 may be integrally formed as a single, indivisible part. Therefore, the pixels SP arranged in the third column COL3 and the fourth column COL4 may share a single drive voltage line VDL, and the source electrode SE1 of the first transistor T1 of each of the 13th pixel SP13 and the 14th pixel SP14 may receive a drive voltage via the single drive voltage line VDL. Therefore, by reducing the number of drive voltage lines VDL, the area of ​​the pixel circuit in the display device 10 can be reduced, making it possible to effectively implement a high-resolution display device.

[0079] The initialization voltage line VIL may include a first portion VILa and a second portion VILb. The first portion VILa of the initialization voltage line VIL may be disposed in the second gate layer GTL2 and extend in the X-axis direction. Each of the plurality of first portions VILa of the plurality of initialization voltage lines VIL may be associated with a row. The pixels SP disposed in each of the first row CRW1 and the second row CRW2 may receive an initialization voltage from the first portion VILa of the initialization voltage line VIL.

[0080] The second portion VILb of the initialization voltage line VIL can be disposed in the second source metal layer SDL2 and extend in the Y-axis direction, and can be electrically connected to the first portion VILa of the initialization voltage line VIL. The second portion VILb of one initialization voltage line VIL can be disposed between adjacent pixels SP in the X-axis direction. In an embodiment, for example, the second portion VILb of one initialization voltage line VIL can be disposed between the second column COL2 and the third column COL3. The second portion VILb of one initialization voltage line VIL can be disposed between adjacent driving voltage lines VDL in the X-axis direction. By reducing the number of initialization voltage lines VIL, the area of ​​the pixel circuit in the display device 10 can be reduced, so that a high-resolution display device can be effectively implemented.

[0081] Reference Figures 8 to 10 The 22nd pixel SP22 can be connected to the nth scan line GWL[n], the (n+1)th scan line GWL[n+1], the data line DL, the initialization voltage line VIL, the driving voltage line VDL and the low-level voltage line VSL (see Figure 4 ).

[0082] In an embodiment, Figure 9 As shown in Figure 11 The first transistor T1 may include a semiconductor region ACT1, a source electrode SE1, a drain electrode DE1, and a gate electrode GE1. The semiconductor region ACT1, the source electrode SE1, and the drain electrode DE1 of the first transistor T1 may be disposed in the active layer ACTL (or defined by a portion of the active layer ACTL), and the gate electrode GE1 of the first transistor T1 may be disposed in the first gate layer GTL1 (or defined by a portion of the first gate layer GTL1). The gate electrode GE1 of the first transistor T1 may overlap with the semiconductor region ACT1 of the first transistor T1. In an embodiment, for example, the semiconductor region ACT1 of the first transistor T1 may include low-temperature polysilicon, and the source electrode SE1 and the drain electrode DE1 of the first transistor T1 may be formed by p-type doping.

[0083] The gate electrode GE1 of the first transistor T1 can be electrically connected to the source electrode SE2 of the second transistor T2 via the connection electrode CE of the second gate layer GTL2. The gate electrode GE1 of the first transistor T1 can be part of the first electrode C1a of the first capacitor C1, and the second electrode C1b of the first capacitor C1 can be part of the first portion VILa of the initialization voltage line VIL provided in the second gate layer GTL2. Thus, the first capacitor C1 can initialize the gate electrode GE1 of the first transistor T1 with a voltage equal to the initialization voltage. The source electrode SE1 of the first transistor T1 can be connected to the drive voltage line VDL of the second source metal layer SDL2. The drain electrode DE1 of the first transistor T1 can be integrally formed with the drain electrode DE3 of the third transistor T3 as a single, integral part. The drain electrode DE1 of the first transistor T1 can be electrically connected to the first electrode AE ​​of the light-emitting element ED via the anode connection electrode ANE of the second source metal layer SDL2.

[0084] The second transistor T2 may include a semiconductor region ACT2, a source electrode SE2, a drain electrode DE2, and a gate electrode GE2. The semiconductor region ACT2, the source electrode SE2, and the drain electrode DE2 of the second transistor T2 may be disposed in the active layer ACTL (or defined by a portion of the active layer ACTL), and the gate electrode GE2 of the second transistor T2 may be disposed in the first gate layer GTL1 (or defined by a portion of the first gate layer GTL1). The gate electrode GE2 of the second transistor T2 may overlap with the semiconductor region ACT2 of the second transistor T2. In an embodiment, for example, the semiconductor region ACT2 of the second transistor T2 may include low-temperature polysilicon, and the source electrode SE2 and the drain electrode DE2 of the second transistor T2 may be formed by p-type doping.

[0085] The gate electrode GE2 of the second transistor T2 may be part of a gate pattern GTP that overlaps the first and second rows CRW1 and CRW2. The second transistor T2 of the 22nd pixel SP22 may receive the nth scan signal of the nth scan line GWL[n] via the gate pattern GTP. The source electrode SE2 of the second transistor T2 may be electrically connected to the gate electrode GE1 of the first transistor T1 via the connecting electrode CE. The drain electrode DE2 of the second transistor T2 may be integrally formed with the source electrode SE3 of the third transistor T3 as a single, integral, and indivisible part. The drain electrode DE2 of the second transistor T2 may be connected to the capacitor electrode CPE of the second source metal layer SDL2. The capacitor electrode CPE may be the first electrode C2a of the second capacitor C2, and the data line DL may be disposed in the first source metal layer SDL1 and may include the second electrode C2b of the second capacitor C2. The capacitor electrode CPE may be connected to the drain electrode DE2 of the second transistor T2 via a hole defined or formed in the data line DL. Therefore, the second capacitor C2 may change the voltage of the drain electrode DE2 of the second transistor T2 and the voltage of the source electrode SE3 of the third transistor T3 to a voltage equal to the data voltage.

[0086] The third transistor T3 may include a semiconductor region ACT3, a source electrode SE3, a drain electrode DE3, and a gate electrode GE3. The semiconductor region ACT3, the source electrode SE3, and the drain electrode DE3 of the third transistor T3 may be disposed in the active layer ACTL (or defined by a portion of the active layer ACTL), and the gate electrode GE3 of the third transistor T3 may be disposed in the first gate layer GTL1 (or defined by a portion of the first gate layer GTL1). The gate electrode GE3 of the third transistor T3 may overlap with the semiconductor region ACT3 of the third transistor T3. In an embodiment, for example, the semiconductor region ACT3 of the third transistor T3 may include low-temperature polysilicon, and the source electrode SE3 and the drain electrode DE3 of the third transistor T3 may be formed by p-type doping.

[0087] The gate electrode GE3 of the third transistor T3 can be a portion of the gate pattern GTP that overlaps the second row CRW2 and the third row (not shown). The third transistor T3 of the 22nd pixel SP22 can receive the n+1th scan signal of the (n+1)th scan line GWL[n+1] through the gate pattern GTP. The source electrode SE3 of the third transistor T3 can be integrally formed with the drain electrode DE2 of the second transistor T2 as a single, integral, and indivisible part. The source electrode SE3 of the third transistor T3 can be connected to the capacitor electrode CPE. The capacitor electrode CPE can be connected to the source electrode SE3 of the third transistor T3 through a hole defined or formed in the data line DL. The drain electrode DE3 of the third transistor T3 can be integrally formed with the drain electrode DE1 of the first transistor T1 as a single, integral, and indivisible part. The drain electrode DE3 of the third transistor T3 can be electrically connected to the first electrode AE ​​of the light-emitting element ED through the anode connection electrode ANE.

[0088] The first capacitor C1 may include a first electrode C1a and a second electrode C1b. The first electrode C1a and the second electrode C1b of the first capacitor C1 may overlap each other. The first electrode C1a of the first capacitor C1 may be disposed in the first gate layer GTL1 (or defined by a portion of the first gate layer GTL1), and the second electrode C1b may be disposed in the second gate layer GTL2 (or defined by a portion of the second gate layer GTL2). The first electrode C1a of the first capacitor C1 may include the gate electrode GE1 of the first transistor T1, and the second electrode C1b may be part of the first portion VILa of the initialization voltage line VIL. Therefore, the first capacitor C1 may maintain the potential difference between the gate electrode GE1 of the first transistor T1 and the initialization voltage line VIL.

[0089] The second capacitor C2 may include a first electrode C2a and a second electrode C2b. The first electrode C2a and the second electrode C2b of the second capacitor C2 may overlap each other. The first electrode C2a of the second capacitor C2 may be disposed in the second source metal layer SDL2 (or defined by a portion of the second source metal layer SDL2), and the second electrode C2b may be disposed in the first source metal layer SDL1 (or defined by a portion of the first source metal layer SDL1). The first electrode C2a of the second capacitor C2 may be the capacitor electrode CPE, and the second electrode C2b of the second capacitor C2 may be part of the data line DL. Therefore, the second capacitor C2 may maintain the potential difference between the drain electrode DE2 of the second transistor T2 and the data line DL.

[0090] In an embodiment, Figure 11 As shown in FIG, the display device 10 (see Figure 1 or Figure 2) may include a substrate SUB, an active layer ACTL, a first gate insulator GI1, a first gate layer GTL1, a second gate insulator GI2, a second gate layer GTL2, an interlayer dielectric layer ILD, a first source metal layer SDL1, a first via layer VIA1, a second source metal layer SDL2, a second via layer VIA2, a pixel defining layer PDL, a light emitting element ED and an encapsulation layer TFEL.

[0091] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or rolled. In an embodiment, for example, the substrate SUB may include a glass material, but the constituent material of the substrate SUB is not limited thereto. In another embodiment, for example, the substrate SUB may include a polymer resin such as polyimide (PI).

[0092] The active layer ACTL may be disposed on the substrate SUB. The active layer ACTL may include a silicon-based material. The active layer ACTL may include semiconductor regions ACT1, ACT2, and ACT3 of the first transistor T1, the second transistor T2, and the third transistor T3, source electrodes SE1, SE2, and SE3, and drain electrodes DE1, DE2, and DE3.

[0093] A first gate insulator GI1 may be disposed on the active layer ACTL. The first gate insulator GI1 may insulate the active layer ACTL from the first gate layer GTL1.

[0094] The first gate layer GTL1 may be disposed on the first gate insulator GI1. The first gate layer GTL1 may include gate electrodes GE1, GE2, and GE3 of the first, second, and third transistors T1, T2, and T3.

[0095] The second gate insulator GI2 may be disposed on the first gate layer GTL1. The second gate insulator GI2 may insulate the first gate layer GTL1 from the second gate layer GTL2.

[0096] The second gate layer GTL2 may be disposed on the second gate insulator GI2. The second gate layer GTL2 may include or define an nth scan line GWL[n], an (n+1)th scan line GWL[n+1], a connection electrode CE, and an initialization voltage line VIL (see FIG. Figure 5 )The first part VILa.

[0097] An interlayer dielectric layer ILD may be disposed on the second gate layer GTL2 . The second interlayer dielectric layer ILD2 may insulate the second gate layer GTL2 from the first source metal layer SDL1 .

[0098] The first source metal layer SDL1 may be disposed on the interlayer dielectric layer ILD. The first source metal layer SDL1 may include or define the data line DL.

[0099] The first via layer VIA1 may be disposed on the first source metal layer SDL1 and may insulate the first source metal layer SDL1 from the second source metal layer SDL2.

[0100] The second source metal layer SDL2 may be disposed on the first via layer VIA1. The second source metal layer SDL2 may include or define a driving voltage line VDL, an anode connection electrode ANE, and a capacitor electrode CPE.

[0101] The second via layer VIA2 may be disposed on the second source metal layer SDL2 and may insulate the second source metal layer SDL2 from the first electrode AE ​​of the light emitting element ED.

[0102] The light emitting material layer EDL may include a pixel defining layer PDL and a light emitting element ED. The light emitting element ED may include a first electrode AE, an emission layer EL, and a second electrode CAT.

[0103] The pixel defining layer PDL may be disposed on the second via layer VIA2. The pixel defining layer PDL may define a plurality of emission areas EA. The pixel defining layer PDL may include an organic insulating material such as polyimide (PI).

[0104] The first electrode AE ​​may be disposed on the second via layer VIA2. The first electrode AE ​​may overlap one of the plurality of emission areas EA defined by the pixel defining layer PDL. The first electrode AE ​​may be connected to the anode connection electrode ANE and may be connected to the pixel SP (see FIG. Figure 4 ) receives the driving current.

[0105] The emission layer EL may be provided on the first electrode AE. In an embodiment, for example, the emission layer EL may be (but is not limited to) an organic light-emitting layer made of an organic material. In an embodiment where the emission layer EL is an organic light-emitting layer, when the pixel circuit of the pixel SP applies a predetermined voltage to the first electrode AE ​​and the second electrode CAT receives a common voltage or a cathode voltage, holes may move to the emission layer EL through the hole transport layer, and electrons may move to the emission layer EL through the electron transport layer, and the holes and electrons may recombine with each other in the emission layer EL to emit light.

[0106] The second electrode CAT may be provided on the emission layer EL. In an embodiment, for example, the second electrode CAT may be implemented as a common electrode extending across all pixels SP, rather than being provided individually in each of the plurality of pixels SP. The second electrode CAT may be provided on the emission layer EL in the emission area EA, and may be provided on the pixel defining layer PDL other than the emission area EA.

[0107] The encapsulation layer TFEL may be provided on the second electrode CAT to cover the light-emitting element ED. The encapsulation layer TFEL may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light-emitting element ED. The encapsulation layer TFEL may include at least one organic film to protect the light-emitting element ED from particles such as dust.

[0108] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0109] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention as defined by the appended claims.

Claims

1. A display device, wherein: The display device includes: a first pixel disposed in a first row and a first column; a second pixel disposed in a second column adjacent to the first row and the first column; a third pixel disposed in a second row and in the first column next to the first row; a fourth pixel disposed in the second row and the second column; a first scan line extending in a first direction between the first row and the second row; and a first gate pattern connected to the first scan line, The first gate pattern includes a gate electrode of a transistor of each of the first to fourth pixels.

2. The display device according to claim 1, wherein The display device further includes: a second scan line disposed on a lower side of the second row and extending in the first direction; and a second gate pattern connected to the second scan line, The second gate pattern includes a gate electrode of another transistor of each of the third pixel and the fourth pixel.

3. The display device according to claim 2, wherein: The display device further includes: Initialization voltage line, supplying initialization voltage; a driving voltage line for supplying a driving voltage; and Data line, supply data voltage, Each of the first to fourth pixels includes: A light-emitting element is disposed on the substrate; a first transistor that supplies a driving current to a second node connected to a first electrode of the light emitting element based on a voltage of a first node connected to a gate electrode of the first transistor; a first capacitor connected between the first node and the initialization voltage line; a second transistor connected to the first node; a second capacitor connected between the data line and a third node connected to the drain electrode of the second transistor; and A third transistor is connected between the third node and the second node.

4. The display device according to claim 3, wherein The first scan line supplies a first scan signal to the third transistor of the first pixel, the third transistor of the second pixel, the second transistor of the third pixel, and the second transistor of the fourth pixel through the first gate pattern.

5. The display device according to claim 3, wherein The second scan line supplies a second scan signal to the third transistor of the third pixel and the third transistor of the fourth pixel through the second gate pattern. The display device according to claim 3 , wherein: The display device further includes: an active layer disposed on the substrate and including a semiconductor region of each of the first to third transistors; a first gate layer disposed on the active layer and including the gate electrode of the first transistor, the gate electrode of the second transistor, and the gate electrode of the third transistor of each of the first to fourth pixels; a second gate layer, disposed on the first gate layer and comprising the first scan line and the second scan line; a first source metal layer, disposed on the second gate layer; and The second source metal layer is disposed on the first source metal layer.

7. The display device according to claim 6, wherein: The first gate pattern is defined by the first gate layer and includes the gate electrode of the third transistor of the first pixel, the gate electrode of the third transistor of the second pixel, the gate electrode of the second transistor of the third pixel, and the gate electrode of the second transistor of the fourth pixel.

8. The display device according to claim 6, wherein: The second gate pattern is defined by the first gate layer and includes the gate electrode of the third transistor of the third pixel and the gate electrode of the third transistor of the fourth pixel.

9. The display device according to claim 6, wherein: The initialization voltage line includes a first portion defined by the second gate layer and extending in the first direction; and a second portion defined by the second source metal layer, extending in a second direction intersecting the first direction, and connected to the first portion.

10. The display device according to claim 9, wherein A first electrode of the first capacitor includes the gate electrode of the first transistor, and A second electrode of the first capacitor is part of the first portion of the initialization voltage line.

11. The display device according to claim 6, wherein The display device further includes: a capacitor electrode, disposed in the second source metal layer, Wherein, the data line is defined by the first source metal layer, and The first electrode of the second capacitor is the capacitor electrode, and the second electrode of the second capacitor is a portion of the data line.

12. A display device, wherein: The display device includes: a first pixel disposed in a first row and a first column; a second pixel disposed in a second column adjacent to the first row and the first column; a third pixel disposed in a third column next to the first row and the second column; a fourth pixel disposed in a second row and in the first column next to the first row; a fifth pixel disposed in the second row and the second column; a sixth pixel, arranged in the second row and the third column; a first scan line extending in a first direction between the first row and the second row; a first gate pattern connected to the first scan line and overlapping the second pixel, the third pixel, the fifth pixel, and the sixth pixel; and a driving voltage line extending between the first column and the second column in a second direction intersecting the first direction, The driving voltage line supplies a driving voltage to the first pixel, the second pixel, the fourth pixel, and the fifth pixel.

13. The display device according to claim 12, wherein: The display device further includes: an initialization voltage line for supplying an initialization voltage; and Data line, supply data voltage, Each of the first to sixth pixels includes: A light-emitting element is disposed on the substrate; a first transistor that supplies a driving current to a second node connected to a first electrode of the light emitting element based on a voltage of a first node connected to a gate electrode of the first transistor; a first capacitor connected between the first node and the initialization voltage line; a second transistor connected to the first node; a second capacitor connected between the data line and a third node connected to the drain electrode of the second transistor; and A third transistor is connected between the third node and the second node.

14. The display device according to claim 13, wherein: The source electrode of the first transistor of the first pixel and the source electrode of the first transistor of the second pixel are integrally formed with each other as a single, integral, indivisible part, and The driving voltage line supplies the driving voltage to the source electrode of the first transistor of each of the first pixel and the second pixel.

15. The display device according to claim 13, wherein The first gate pattern includes a gate electrode of the third transistor of the second pixel, a gate electrode of the third transistor of the third pixel, a gate electrode of the second transistor of the fifth pixel, and a gate electrode of the second transistor of the sixth pixel.

16. The display device according to claim 13, wherein The display device further includes: a second scan line disposed on a lower side of the second row and extending in the first direction; and a second gate pattern connected to the second scan line, The second gate pattern overlaps with the fifth pixel and the sixth pixel.

17. The display device according to claim 16, wherein: The second gate pattern includes a gate electrode of the third transistor of the fifth pixel and a gate electrode of the third transistor of the sixth pixel.

18. The display device according to claim 16, wherein: The display device further includes: an active layer disposed on the substrate and including a semiconductor region of each of the first to third transistors; a first gate layer disposed on the active layer and including the gate electrode of the first transistor, the gate electrode of the second transistor, and the gate electrode of the third transistor of each of the first to sixth pixels; a second gate layer, disposed on the first gate layer and comprising the first scan line and the second scan line; a first source metal layer, disposed on the second gate layer; and The second source metal layer is disposed on the first source metal layer.

19. The display device according to claim 18, wherein The initialization voltage line includes a first portion defined by the second gate layer and extending in the first direction; and a second portion defined by the second source metal layer, extending in a second direction intersecting the first direction, and connected to the first portion.

20. The display device according to claim 19, wherein A first electrode of the first capacitor includes the gate electrode of the first transistor, and a second electrode of the first capacitor is a portion of the first portion of the initialization voltage line.

Images