Display device and electronic device having the same

Abstract

A display device and an electronic device are provided. The electronic device includes a processor configured to provide input image data to a display device configured to display an image based on the input image data, and a power supply configured to provide power to the display device, the display device includes a pixel including a light emitting element and a photosensor including a light receiving element at the same layer as the light emitting element, and the photosensor further includes: a first sensor transistor configured to control a current flowing to a readout line in response to a voltage of one electrode of the light receiving element; a second sensor transistor electrically connected between the first sensor transistor and the readout line, and including a first sub-transistor and a second sub-transistor connected in series; and a first capacitor between a first intermediate node to which the first sub-transistor and the second sub-transistor are connected and a power supply line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0037713, filed on March 19, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device including a photosensor and an electronic device having the display device. Background Art

[0004] With the development of information technology, the importance of display devices as a link between users and information is increasing. Consequently, the use of display devices such as liquid crystal displays and organic light-emitting displays has increased. Furthermore, display devices can use photosensors to sense a user's fingerprint and perform user authentication. Summary of the Invention

[0005] An aspect of the present disclosure provides a display device that can improve performance of a photosensor.

[0006] Another aspect of the present disclosure provides an electronic device having a display device.

[0007] An embodiment of the present disclosure provides a display device including a pixel and a photosensor, wherein the pixel includes a light-emitting element, and the photosensor includes: a light-receiving element at the same layer as the light-emitting element; a first sensor transistor configured to control a current flowing to a readout line in response to a voltage of an electrode of the light-receiving element; a second sensor transistor electrically connected between the first sensor transistor and the readout line and including a first sub-transistor and a second sub-transistor connected in series; and a first capacitor between a first intermediate node to which the first sub-transistor and the second sub-transistor are connected and a power supply line.

[0008] A constant voltage may be configured to be applied to the power line.

[0009] The pixel may further include a switching transistor electrically connected between the power supply line and the anode electrode of the light emitting element.

[0010] The pixel may further include: a first transistor electrically connected between the first power line and the light emitting element; and a second transistor electrically connected between the data line and the first transistor, wherein a gate electrode of the second transistor and a gate electrode of the second sensor transistor are electrically connected to the first scan line.

[0011] In a cross-sectional view, the photosensor may further include: a semiconductor layer of a first sub-transistor and a second sub-transistor; a gate electrode above the semiconductor layer; an insulating layer covering the gate electrode; a capacitor electrode above the insulating layer; and at least one insulating layer above the capacitor electrode, wherein a power line is above the at least one insulating layer and contacts the capacitor electrode through a contact hole, and wherein the first capacitor includes the capacitor electrode and the semiconductor layer.

[0012] In a plan view, the power supply line may extend in the first direction between the first sensor transistor and the second sensor transistor, and partially protrude in the second direction to overlap with the capacitor electrode.

[0013] The photosensor may further include a third sensor transistor electrically connected between one electrode of the light receiving element and the reference power supply line.

[0014] The first and second sensor transistors may include a silicon semiconductor, wherein the third sensor transistor includes an oxide semiconductor.

[0015] One electrode of the first sensor transistor may be electrically connected to a power line, wherein the power line and a reference power line are configured to receive different voltages.

[0016] The power supply line and the reference power supply line may be configured to receive the same voltage.

[0017] The light emitting element may be electrically connected between a first power line and a second power line, wherein the power line is configured to receive the same voltage as the first power line.

[0018] The photosensor may further include: a third sensor transistor electrically connected between the reference power line and one electrode of the light receiving element and including a third sub-transistor and a fourth sub-transistor connected in series; and a second capacitor between a second intermediate node to which the third sub-transistor and the fourth sub-transistor are connected and the first power line.

[0019] The power line and the first power line may be configured to receive the same constant voltage.

[0020] The pixel may further include: a first transistor connected between the first power line and the light emitting element; and a storage capacitor electrically connected between the gate electrode of the first transistor and the first power line, wherein one electrode of the second capacitor is integral with one electrode of the storage capacitor.

[0021] In a plan view, one electrode of the storage capacitor may overlap with the first semiconductor pattern of the first transistor, wherein one electrode of the second capacitor has a size smaller than that of the one electrode of the storage capacitor and protrudes from the one electrode of the storage capacitor to overlap with the third semiconductor pattern of the third sensor transistor.

[0022] The pixel may further include a third transistor electrically connected between one electrode and the gate electrode of the first transistor, wherein, in a plan view, one electrode of the first capacitor overlaps the second semiconductor pattern of the second sensor transistor and protrudes toward the third transistor to overlap an intermediate node of the third transistor.

[0023] An embodiment of the present disclosure provides a display device, which includes a pixel including a light-emitting element and a photosensor, the photosensor including: a light-receiving element, at the same layer as the light-emitting element; a first sensor transistor, configured to control a current flowing to a readout line in response to a voltage of an electrode of the light-receiving element; a second sensor transistor, electrically connected between the first sensor transistor and the readout line; a third sensor transistor, electrically connected between a reference power line and an electrode of the light-receiving element, and including a third sub-transistor and a fourth sub-transistor connected in series; and a second capacitor, between a second intermediate node to which the third sub-transistor and the fourth sub-transistor are connected and the first power line.

[0024] The reference power line and the first power line may be configured to receive the same constant voltage.

[0025] The pixel may further include: a first transistor connected between the first power line and the light emitting element; and a storage capacitor electrically connected between the gate electrode of the first transistor and the first power line, wherein one electrode of the second capacitor is integral with one electrode of the storage capacitor.

[0026] An embodiment of the present disclosure provides an electronic device, which includes a processor configured to provide input image data to a display device and a power supply configured to provide power to the display device, the display device being configured to display an image based on the input image data, wherein the display device includes a pixel including a light-emitting element and a photosensor including a light-receiving element at the same layer as the light-emitting element, and the photosensor also includes: a first sensor transistor configured to control a current flowing to a readout line in response to a voltage of an electrode of the light-receiving element; a second sensor transistor electrically connected between the first sensor transistor and the readout line and including a first sub-transistor and a second sub-transistor connected in series; and a first capacitor between a first intermediate node to which the first sub-transistor and the second sub-transistor are connected and a power line.

[0027] In display devices and electronic devices according to embodiments of the present disclosure, the sensor transistor in the photosensor can be implemented as a dual-gate transistor, and a capacitor can be connected between the intermediate node of the sensor transistor and the constant voltage wiring. This reduces or minimizes leakage current through the sensor transistor, and improves the photosensor's sensitivity.

[0028] Aspects of the embodiments of the present disclosure are not limited to those shown above, and more various aspects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A block diagram of a display device according to an embodiment of the present disclosure is shown.

[0030] Figure 2 Shown Figure 1 A block diagram of one or more embodiments of a display device.

[0031] Figure 3 Shown in the included Figure 2 An example of disposition of a backplane circuit in a display area of ​​a display panel in a display device.

[0032] Figure 4 Shown included in Figure 2 An example of a display area of ​​a display panel in a display device.

[0033] Figure 5 Shown included in Figure 4 Circuit diagram of an example of pixels and photosensors in a display area.

[0034] Figure 6 Shown Figure 5 Waveform diagrams of one or more embodiments of the operation of a pixel and a photosensor.

[0035] Figure 7A 、 Figure 7B and Figure 7C Shown Figure 4 A top view of one or more embodiments of a display area.

[0036] Figure 8 Shown Figure 4 A cross-sectional view of one or more embodiments of a display area.

[0037] Figure 9 Shown Figure 7A A top view of one or more embodiments of region BB.

[0038] Figure 10 Shown included in Figure 4 Circuit diagram of one or more embodiments of pixels and photosensors in a display area.

[0039] Figure 11 Shown Figure 4 A top view of one or more embodiments of a display area.

[0040] Figure 12 Shown included in Figure 4 Circuit diagrams of one or more other embodiments of pixels and photosensors in a display area.

[0041] Figure 13 Shown included in Figure 4 Circuit diagrams of one or more other embodiments of pixels and photosensors in a display area.

[0042] Figure 14A 、 Figure 14B and Figure 14C Shown Figure 4 A top view of one or more embodiments of a display area.

[0043] Figure 15 Shown Figure 4 A cross-sectional view of one or more embodiments of a display area.

[0044] Figure 16A and Figure 16B Shown Figure 14C A top view of one or more embodiments of region CC.

[0045] Figure 17 Shown included in Figure 4 Circuit diagrams of one or more other embodiments of pixels and photosensors in a display area.

[0046] Figure 18 A block diagram of an electronic device according to an embodiment is shown.

[0047] Figure 19 Shown Figure 18 An example in which the electronic device is implemented as a smart phone.

[0048] Figure 20 Shown Figure 18 The electronic device is implemented as an example of a tablet PC. DETAILED DESCRIPTION

[0049] By referring to the detailed description and drawings of the embodiments, it is easier to understand the aspects of some embodiments of the present disclosure and the methods for realizing the present disclosure. The described embodiments are provided as examples so that the present disclosure will be thorough and complete and will fully convey the aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments, or unnecessary processes, elements and techniques for a complete understanding of the aspects of the present disclosure by those of ordinary skill in the art may be omitted. Unless otherwise stated, in all drawings and written descriptions, the same reference numerals, characters or combinations thereof represent the same elements, and therefore, their repeated descriptions may be omitted.

[0050] The described embodiments may have various modifications and may be implemented in different forms and should not be construed as limited to the embodiments shown herein. The use of "may," "could," or "may not" when describing an embodiment corresponds to one or more embodiments of the present disclosure.

[0051] Those skilled in the art will understand that, in view of the entire content of the present disclosure, unless otherwise stated or implied, the present disclosure covers all modifications, equivalents and replacements within the scope of the ideas and techniques of the present disclosure, each of the features of the embodiments of the present disclosure may be combined with each other in part or in whole, and various interlocking and operations are technically possible, and each embodiment may be implemented independently of each other, or may be implemented together in association.

[0052] In the accompanying drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In other words, because the sizes and thicknesses of the elements in the drawings are arbitrarily shown for ease of description, the present disclosure is not limited thereto. In addition, the use of cross hatching and / or shading is generally provided in the drawings to clarify the boundaries between adjacent elements. Therefore, unless specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the illustrated elements, and / or any other characteristics, attributes, properties, etc. of the elements.

[0053] Various embodiments are described herein with reference to cross-sectional views that are schematic representations of embodiments and / or intermediate structures. Therefore, deviations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Furthermore, the specific structural or functional descriptions disclosed herein are illustrative only, for the purpose of describing embodiments according to the concepts of the present disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the illustrated shapes of elements, layers, or regions, but rather should include deviations in shapes due to, for example, manufacturing.

[0054] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0055] For ease of explanation, spatial relative terms such as "below", "beneath", "down", "underside", "beneath", "above", "upper", "side" (e.g., as in "sidewall"), etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It will be understood that, in addition to the orientation depicted in the accompanying drawings, spatial relative terms are intended to encompass different orientations of the device in use or in operation. For example, if the device in the accompanying drawings is flipped, the elements described as being "below", "below" or "below" other elements or features will then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "below" can encompass both above and below orientations. The device may also be oriented otherwise (e.g., rotated 90 degrees or in other orientations), and the spatial relative terms used herein should be interpreted accordingly. Similarly, when a first portion is described as being disposed "on" a second portion, this indicates that the first portion is disposed at the upper or lower side of the second portion, without being limited to its upper side based on the direction of gravity.

[0056] In addition, the phrase "in a plan view" means when viewing an object portion from above, and the phrase "in a schematic cross-sectional view" means when viewing a schematic cross-section obtained by vertically cutting an object portion from the side. The terms "overlapping" or "overlapping" mean that the first object can be above or below the second object, or to one side of the second object, and vice versa. In addition, the term "overlapping" can include stacking, facing, or facing, extending over, covering, or partially covering, or any other suitable term as will be understood and appreciated by a person of ordinary skill in the art. The expression "non-overlapping" can include meanings such as "spaced from," "set beside," or "offset from," as well as any other suitable equivalents as will be understood and appreciated by a person of ordinary skill in the art. The terms "facing" and "facing" can mean that the first object can be directly or indirectly opposite to the second object. In the case where a third object is inserted between the first and second objects, the first and second objects can be understood to be indirectly opposite to each other, although still facing each other.

[0057] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, it may be directly formed on, directly on, directly connected to, or directly coupled to another element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to another element, layer, region, or component, such that there may be one or more intervening elements, layers, regions, or components. Furthermore, this may generally mean direct or indirect couplings or connections, as well as integral or non-integrated couplings or connections. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or directly electrically coupled to another layer, region, and / or component, or there may be one or more intervening layers, regions, or components. One or more intervening components may include switches, resistors, capacitors, etc. In describing the embodiments, unless explicitly described as directly connected, the expression of connection indicates electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or directly coupled to another component or directly on another component without intervening components.

[0058] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upward direction, but includes forming the part on the side surface or in the downward direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "under" another part, this includes not only the case where the part is "directly under" the other part, but also the case where there is another part between the part and the other part. At the same time, other expressions describing the relationship between parts, such as "between...", "directly between...", or "adjacent to..." and "directly adjacent to..." can be interpreted similarly. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0059] For the purposes of this disclosure, expressions such as “at least one of” or “any one of” or “one or more of” when preceding a list element modify the elements of the entire list rather than modifying the individual elements of the list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as, for example, XYZ, XY, YZ, and XZ), or any variation thereof. Similarly, the expression “at least one of A and B” may include A, B, or A and B. As used herein, “or” generally means “and / or,” and the term “and / or” includes any and all combinations of one or more of the relevant listed items. For example, the expression “A and / or B” may include A, B, or A and B. Similarly, expressions such as “at least one of,” “a plurality of,” “one of,” and other prepositional phrases when preceding or following a list element modify the elements of the entire list rather than modifying the individual elements of the list. When "C to D" is stated, it means C or more and D or less unless otherwise specified.

[0060] It will be understood that although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, areas, layers and / or sections, these elements, components, areas, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or priority, but are only used to distinguish an element, component, component, area, area, layer, section or part from another element, component, component, area, area, layer, section or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first area, first layer or first section described below can be referred to as the second element, second component, second area, second layer or second section. Describing an element as a "first" element may not require or may not imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used in this article to distinguish elements of different categories or different groups. For simplicity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0061] In the examples, the x-axis, y-axis, and / or z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0062] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a" and "an" are intended to include the plural forms as well, and the plural forms are intended to include the singular forms as well. It will also be understood that when used in this specification, the terms "comprises," "comprising," "have," "having," "includes," and "including" specify the presence of set forth features, wholes, steps, operations, elements, and / or parts, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts, and / or combinations thereof.

[0063] As used herein, the terms "substantially," "about," "approximately," and similar terms are used as approximate terms rather than as terms of degree, and are intended to account for inherent deviations in measurements or calculations that one of ordinary skill in the art would recognize. For example, "substantially" may include a range of + / - 5% of the corresponding value. In view of the measurements in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, "about" or "approximately" includes the value and means within an acceptable deviation range of the particular value determined by one of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value. In addition, "may" used in describing embodiments of the present disclosure means "one or more embodiments of the present disclosure."

[0064] In some embodiments, known structures and devices can be described in the accompanying drawings for one or more functional blocks (e.g., block diagrams), units and / or modules to avoid unnecessary ambiguity of various embodiments. Those skilled in the art will appreciate that these blocks, units and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, line connections and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein. Alternatively, blocks, units and / or modules implemented by microprocessors or other similar hardware can be driven by firmware and / or software. In addition, each block, unit and / or module can be implemented by a combination of dedicated hardware or dedicated hardware that performs certain functions and a processor (e.g., one or more programmed microprocessors and related circuits) that performs a function different from the function of the dedicated hardware. In addition, in some embodiments, without departing from the scope of this disclosure, blocks, units and / or modules can be physically separated into two or more interactive discrete blocks, units and / or modules. Furthermore, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0065] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0066] Figure 1 A block diagram of a display device according to an embodiment of the present disclosure is shown.

[0067] refer to Figure 1 , the display device 10 may include a display panel 100 and a driving circuit 200 . The driving circuit 200 may include a panel driver 210 and a sensor driver 220 .

[0068] The display device 10 may be implemented as a self-luminous display device including a plurality of self-luminous elements. For example, the display device 10 may be an organic light-emitting display device including organic light-emitting elements. However, this is an example, and the display device 10 may be implemented as a display device including inorganic light-emitting elements, a display device including light-emitting elements composed of a combination of inorganic and organic materials, or a display device that displays images using quantum dots.

[0069] The display device 10 may be a flat panel display, a flexible display device, a curved display device, a foldable display device, a bendable display device, or a rollable display device. Furthermore, the display device 10 may be applied to a transparent display device, a head-mounted display device, a wearable display device, or the like.

[0070] The display panel 100 includes a display area AA and a non-display area NA. The display area AA may be an area in which pixels PX are provided. The pixels PX may be referred to as sub-pixels or luminescent pixels. The pixels PX may include at least one light-emitting element. For example, the light-emitting element may include a light-emitting layer (e.g., an organic light-emitting layer). The portion of light emitted by the light-emitting element may be defined as a light-emitting area. The display device 10 may display an image in the display area AA by driving the pixels PX in response to image data.

[0071] The non-display area NA may be an area disposed around the display area AA. The non-display area NA may comprehensively refer to the remaining areas of the display panel 100 except the display area AA. For example, the non-display area NA may include a wiring area, a pad area, and various dummy areas.

[0072] The display area AA may include a photosensor PHS. The photosensor PHS may be referred to as a sensor pixel. The photosensor PHS may include a light receiving element including a light receiving layer. The light receiving element may be located on the same layer as the light emitting element. In the display area AA, the light receiving layer of the light receiving element is located on the same layer as the light emitting layer of the light emitting element and may be spaced apart from the light emitting layer in a plan view.

[0073] A plurality of photosensors PHS may be distributed throughout the entire display area AA while being spaced apart from one another. However, this is an example, and only a portion of the display area AA is set as a sensing area (e.g., a predetermined sensing area), and the photosensors PHS may be provided in the corresponding sensing area. Furthermore, at least a portion of the non-display area NA may also include photosensors PHS.

[0074] The photoelectric sensor PHS can detect light emitted from a light source (e.g., a light-emitting element of a pixel PX) reflected by an external object (e.g., a user's finger). For example, the photoelectric sensor PHS can detect a user's fingerprint. Hereinafter, the present disclosure will be described using the photoelectric sensor PHS as an example for fingerprint detection. However, in various embodiments, the photoelectric sensor PHS can detect various biometric information such as irises, veins, etc.

[0075] The driving circuit 200 may include a panel driver 210 and a sensor driver 220. The display device 10 may include the panel driver 210 and the sensor driver 220. For example, the panel driver 210 and the sensor driver 220 may be implemented as separate integrated circuits, or the driving circuit 200 may be implemented as a single integrated circuit. For example, at least a portion of the sensor driver 220 may be included in the panel driver 210, or may operate in conjunction with the panel driver 210.

[0076] The panel driver 210 may scan the pixels PX of the display area AA and may provide data signals corresponding to image data (or images) to the pixels PX. The display panel 100 may display an image corresponding to the data signals.

[0077] The panel driver 210 may provide a driving signal for light sensing (e.g., fingerprint sensing) to the pixel PX. The driving signal may be provided so that the pixel PX emits light and operates as a light source for the photosensor PHS. The panel driver 210 may provide a driving signal for light sensing and / or other driving signals to the photosensor PHS. However, this is an example, and the driving signal for light sensing may be provided by the sensor driver 220.

[0078] The sensor driver 220 may detect biometric information such as a user's fingerprint based on a sensing signal received from the photosensor PHS. The sensor driver 220 may provide a driving signal to the photosensor PHS and / or the pixels PX.

[0079] The panel driver 210 may provide a readout control signal RCS to the sensor driver 220, and the sensor driver 220 may read out (or sample) the detection signal in cooperation with the panel driver 210 based on the readout control signal RCS. For example, the sensor driver 220 may read out or sample the detection signal in units of at least one pixel row (or horizontal line) in response to the readout control signal RCS.

[0080] Figure 2 Shown Figure 1 A block diagram of one or more embodiments of a display device.

[0081] refer to Figure 1 and Figure 2 The display panel 100 may include signal lines, pixels PX, and photosensors PHS. The signal lines may include scan lines S1 to Sn, data lines D1 to Dm, readout lines RX1 to RXo, and a reset control line RSTL (or reset line). Here, n, m, and o may each be a natural number greater than 1.

[0082] The pixels PX may be located or positioned in an area (e.g., a pixel area) divided by the scan lines S1 to Sn and the data lines D1 to Dm. The photosensors PHS may be located or positioned in an area divided by the scan lines S1 to Sn and the readout lines RX1 to RXo. The pixels PX and the photosensors PHS may be positioned in a two-dimensional array in the display area AA of the display panel 100, but are not limited thereto.

[0083] The pixel PX may be electrically connected to at least one of the scan lines S1 to Sn and / or one of the data lines D1 to Dm. The photosensor PHS may be electrically connected to one of the scan lines S1 to Sn, one of the readout lines RX1 to RXo, and a reset control line RSTL. Figure 5 The connection configuration among the pixels PX, the photosensors PHS, and the signal lines is described.

[0084] Power supply voltages VDD, VSS, VRST, and VCOM suitable for driving the pixels PX and the photosensors PHS may be provided in the display panel 100. The power supply voltages VDD, VSS, VRST, and VCOM may be provided by a power supply, which may be implemented as a power management integrated circuit.

[0085] The driving circuit 200 may include a scan driver 211 (or gate driver), a data driver 212 (or source driver), a controller 213 (or a timing controller or a second processor), a reset circuit 221 (or reset portion), and a readout circuit 222 (or readout portion). For example, the scan driver 211, the data driver 212, and the controller 213 may be included in the panel driver 210, and the reset circuit 221 and the readout circuit 222 may be included in the sensor driver 220, but is not limited thereto. For example, the reset circuit 221 may be included in the panel driver 210.

[0086] The scan driver 211 can be electrically connected to the pixels PX and electrically connected to the photosensors PHS through the scan lines S1 to Sn. The scan driver 211 can generate scan signals based on the scan control signal SCS (or gate control signal) and can provide the scan signals to the scan lines S1 to Sn. Here, the scan control signal SCS may include a start signal, a clock signal, etc., and can be provided to the scan driver 211 from the controller 213. For example, the scan driver 211 can be implemented as a shift register that generates and outputs scan signals by sequentially shifting the start signal in the form of pulses using a clock signal. In other words, the scan driver 211 can selectively drive the pixels PX and the photosensors PHS while scanning the display panel 100.

[0087] The scan driver 211 may be formed together with the pixels PX in the display panel 100. However, the scan driver 211 is not limited thereto, and for example, the scan driver 211 may be implemented as an integrated circuit.

[0088] The pixels PX selectively driven by the scan driver 211 can emit light having a brightness corresponding to the data signal provided to the data line. The photosensor PHS selectively driven by the scan driver 211 can output an electrical signal (that is, a detection signal, such as a current / voltage) corresponding to the detected light to the readout line. For example, the pixel PX selectively driven by the i-th scan line Si can emit light having a brightness corresponding to the data signal provided to the j-th data line Dj (where i and j are natural numbers greater than 0). For example, the photosensor PHS selectively driven by the i-th scan line Si can output an electrical signal corresponding to the detected light to the k-th readout line RXk (where k is a natural number greater than 0).

[0089] The data driver 212 can generate data signals (or data voltages) based on the image data DATA2 and the data control signal DCS provided by the controller 213, and can transmit the data signals to the display panel 100 (or pixels PX) via the data lines D1 to Dm. Here, the data control signal DCS may be a signal that controls the operation of the data driver 212 and may include a data enable signal (or load signal) that guides the output of a valid data signal, a horizontal start signal, and a data clock signal. For example, the data driver 212 may include a shift register, a latch, a digital-to-analog converter (or decoder), and a buffer (or amplifier). The shift register generates a sampling signal by shifting the horizontal start signal in synchronization with the data clock signal, the latch latches the image data DATA2 in response to the sampling signal, the digital-to-analog converter (or decoder) converts the latched image data (e.g., data in digital form) into an analog data signal, and the buffer (or amplifier) ​​outputs the data signal to the data line (e.g., the j-th data line Dj).

[0090] The controller 213 may receive input image data DATA1 and a control signal CS from an external device (e.g., a graphics processor, an application processor, or a first processor), may generate a scan control signal SCS and a data control signal DCS based on the control signal CS, and may convert the input image data DATA1 to generate image data DATA2. The control signal CS may include a vertical synchronization signal, a horizontal synchronization signal, a reference clock signal, and the like. The vertical synchronization signal may indicate the start of a frame of data (i.e., data corresponding to a frame period for displaying one frame of image), and the horizontal synchronization signal may indicate the start of a data line (i.e., one of a plurality of data lines included in the frame of data). The controller 213 may convert the input image data DATA1 into image data DATA2 having a format that matches the pixel array in the display panel 100.

[0091] In addition, the controller 213 may generate a reset control signal and a readout control signal RCS based on the control signal CS.

[0092] The reset circuit 221 can be connected to the photosensors PHS provided in the display panel 100 through a reset control line RSTL. For example, the reset circuit 221 can be commonly connected to all photosensors PHS provided in the display panel 100 through one reset control line RSTL. The reset circuit 221 can provide a reset signal RST (or reset control signal) to all photosensors PHS synchronously or substantially simultaneously in response to the reset control signal. Here, the reset signal RST can be a control signal for providing a reset voltage VRST to the photosensors PHS. Because the reset signal RST is provided to all photosensors PHS synchronously or substantially simultaneously, the reset signal RST can be referred to as a global reset signal. However, the reset circuit 221 is not limited thereto. For example, the reset circuit 221 can be implemented similarly to the scan driver 211 to sequentially provide a reset signal to the photosensors PHS.

[0093] The readout circuit 222 may receive a detection signal from the photosensor PHS through the readout lines RX1 to RXo and may perform signal processing on the detection signal. For example, the readout circuit 222 may convert the analog detection signal into a digital signal (or digital value).

[0094] The read detection signal can be provided as a piece of sensing data (or biometric information) to an external device (e.g., an application processor), and biometric authentication (e.g., fingerprint authentication) can be performed based on the sensing data. Alternatively, the read detection signal can be provided to the controller 213, and the controller 213 can perform biometric authentication.

[0095] Figure 3 Shown in the included Figure 2 An example of disposition of a backplane circuit in a display area of ​​a display panel in a display device. Figure 4 Shown included in Figure 2 An example of a display area of ​​a display panel in a display device.

[0096] refer to Figures 1 to 4 , the pixels PX1 to PX4 and the plurality of photosensors PHS may be arranged in the display area AA of the display panel 100 .

[0097] The display area AA may be divided into pixel rows R1 to R4. Each of the pixel rows R1 to R4 may extend in a first direction DR1 and may be arranged in a second direction DR2. Each of the pixel rows R1 to R4 may include pixels PX1 to PX4. Each of the pixels PX1 to PX4 may include one of the pixel circuits PXC11 to PXC18, PXC21 to PXC28, PXC31 to PXC38, and PXC41 to PXC48, and one of the light-emitting elements LED1 to LED4.

[0098] The first pixel PX1, the second pixel PX2, and the third pixel PX3 can emit a first color light, a second color light, and a third color light, respectively. The first color light, the second color light, and the third color light are lights of different colors, and each of the first color light, the second color light, and the third color light can be one of red, green, and blue. The fourth pixel PX4 can emit light of the same color as the second pixel PX2. For example, the first light-emitting element LED1 can emit a first color light, the second light-emitting element LED2 and the fourth light-emitting element LED4 can emit a second color light, and the third light-emitting element LED3 can emit a third color light.

[0099] exist Figure 4 In the embodiment, each of the light-emitting elements LED1 to LED4 can be understood as a light-emitting area corresponding to the light-emitting layer. However, this is only for better understanding and ease of description, and the color of light emitted by each of the light-emitting elements LED1 to LED4 and the position, area, and shape of each of the light-emitting elements LED1 to LED4 are not limited thereto.

[0100] In each of the odd pixel rows including the first pixel row R1 (or the first horizontal line) and the third pixel row R3 (or the third horizontal line), pixels PX1 to PX4 may be arranged in the first direction DR1 in the order of a first pixel PX1 emitting red light, a second pixel PX2 emitting green light, a third pixel PX3 emitting blue light, and a fourth pixel PX4 emitting green light.

[0101] In each of the even pixel rows including the second pixel row R2 (or second horizontal line) and the fourth pixel row R4 (or fourth horizontal line), pixels PX1 to PX4 may be arranged in the first direction DR1 in the order of the third pixel PX3, the fourth pixel PX4, the first pixel PX1, and the second pixel PX2.

[0102] The first pixel PX1 and the second pixel PX2 may constitute a first sub-pixel unit SPU1, and the third pixel PX3 and the fourth pixel PX4 may constitute a second sub-pixel unit SPU2. Thus, the first sub-pixel unit SPU1 and the second sub-pixel unit SPU2 may be alternately located in odd-numbered pixel rows R1 and R3, and the second sub-pixel unit SPU2 and the first sub-pixel unit SPU1 may be alternately located in even-numbered pixel rows R2 and R4 in a pattern opposite to that of the odd-numbered pixel rows R1 and R3.

[0103] It can be understood that the first sub-pixel unit SPU1 and the second sub-pixel unit SPU2 adjacent to each other (for example, the predetermined first sub-pixel unit SPU1 and the predetermined second sub-pixel unit SPU2) constitute a pixel unit PU. Figure 4 The pixel unit PU of each of the first pixel row R1 and the second pixel row R2 is shown. However, this is an example, and the arrangement of the pixels PX1 to PX4 is not limited thereto.

[0104] In the first pixel row R1, pixel circuits PXC11 to PXC18 corresponding to the pixels PX1 to PX4 of the first pixel row R1, respectively, may be arranged in the first direction DR1. In the second pixel row R2, pixel circuits PXC21 to PXC28 corresponding to the pixels PX1 to PX4 of the second pixel row R2, respectively, may be arranged in the first direction DR1. Similarly, in the third pixel row R3 and the fourth pixel row R4, pixel circuits PXC31 to PXC38 and pixel circuits PXC41 to PXC48 corresponding to the pixels PX1 to PX4 of the third pixel row R3 and the fourth pixel row R4, respectively, may be arranged in the first direction DR1.

[0105] exist Figure 3 In the embodiment, the first pixel circuit PXC11, the second pixel circuit PXC12, the third pixel circuit PXC3 and the fourth pixel circuit PXC14 of the first pixel row R1 may be included in one pixel unit PU, and the fifth pixel circuit PXC15, the sixth pixel circuit PXC16, the seventh pixel circuit PXC17 and the eighth pixel circuit PXC18 of the first pixel row R1 may be included in another pixel unit PU.

[0106] Similarly, the first pixel circuit PXC21 to the fourth pixel circuit PXC24 of the second pixel row R2, the fifth pixel circuit PXC25 to the eighth pixel circuit PXC28 of the second pixel row R2, the first pixel circuit PXC31 to the fourth pixel circuit PXC34 of the third pixel row R3, the fifth pixel circuit PXC35 to the eighth pixel circuit PXC38 of the third pixel row R3, the first pixel circuit PXC41 to the fourth pixel circuit PXC44 of the fourth pixel row R4, and the fourth pixel circuit PXC45 to the eighth pixel circuit PXC48 of the fourth pixel row R4 can also be respectively included in different pixel units PU.

[0107] Pixel rows R1 to R4 may include light receiving elements LRD1 to LRD4, respectively. Light receiving elements LRD1 to LRD4 may be understood as light receiving areas corresponding to light receiving layers, respectively. However, this is merely for better understanding and ease of description, and the positions, areas, and shapes of light receiving elements LRD1 to LRD4 are not limited thereto.

[0108] The light receiving elements LRD1 and LRD2 of the first pixel row R1 may overlap with at least some of the pixel circuits PXC11 to PXC14 of the first pixel row R1 and the sensor circuits SC11 and SC12 of the first pixel row R1, respectively. The light receiving elements LRD3 and LRD4 of the second pixel row R2 may overlap with at least some of the pixel circuits PXC21 to PXC24 of the second pixel row R2 and the sensor circuits SC21 and SC22 of the second pixel row R2, respectively.

[0109] The first light receiving element LRD1 may overlap at least a portion of the first sensor circuit SC11 of the first pixel row R1 , and the third light receiving element LRD3 may overlap at least a portion of the first sensor circuit SC21 of the second pixel row R2 .

[0110] Furthermore, the second light receiving element LRD2 may overlap at least a portion of the second sensor circuit SC12 of the first pixel row R1 , and the fourth light receiving element LRD4 may overlap at least a portion of the second sensor circuit SC22 of the second pixel row R2 .

[0111] The light receiving elements LRD1 to LRD4 may be arranged in the display area AA as follows. Figure 4 The arrangement shown in is formed.

[0112] The sensor circuits SC11 to SC44 can be connected to corresponding light receiving elements. For example, the first sensor circuit SC11 of the first pixel row R1 can be connected to the first light receiving element LRD1, and the first sensor circuit SC11 and the first light receiving element LRD1 can form a photosensor PHS. Similarly, the second sensor circuit SC12 of the first pixel row R1 can be connected to the second light receiving element LRD2, the first sensor circuit SC21 of the second pixel row R2 can be connected to the third light receiving element LRD3, and the second sensor circuit SC22 of the second pixel row R2 can be connected to the fourth light receiving element LRD4. However, the present disclosure is not limited to this. For example, only some of the sensor circuits SC11 to SC44 can be provided, and some of them can be connected to multiple light receiving elements.

[0113] The first sensor circuit SC11 of the first pixel row R1 may be located between the first sub-pixel unit SPU1 and the second sub-pixel unit SPU2 included in the pixel unit PU. For example, the first pixel circuit PXC11 and the second pixel circuit PXC12 of the first pixel row R1 may be included in the first sub-pixel unit SPU1, and the third pixel circuit PXC13 and the fourth pixel circuit PXC14 of the first pixel row R1 may be included in the second sub-pixel unit SPU2. Therefore, at least two pixel circuits (e.g., PXC13 and PXC14) may be located between the first sensor circuit SC11 and the second sensor circuit SC12 that are adjacent to each other in the first pixel row R1.

[0114] Similar to the first sensor circuit SC11 of the first pixel row R1, the second sensor circuit SC12 of the first pixel row R1, the first sensor circuit SC21 of the second pixel row R2 and the second sensor circuit SC22 of the second pixel row R2 can be located between corresponding sub-pixel units in the first sub-pixel unit SPU1 and the second sub-pixel unit SPU2.

[0115] Figure 5 Shown included in Figure 4 The circuit diagram of an example of a pixel and a photosensor in the display area. For better understanding and ease of description, Figure 5 The pixel PX located on the i-th horizontal line (or the i-th pixel row) and connected to the j-th data line Dj is shown. The 1i-th scanning line S1i to the 4i-th scanning line S4i may be included in Figure 2 The scan lines S1 to Sn or the i-th scan line Si.

[0116] Hereinafter, the term "connection" or "coupling" may refer to an electrical connection based on a circuit. In addition, the term "connection" or "coupling" may refer to a physical connection (that is, physical contact) and an electrical connection in plan views and cross-sectional views.

[0117] refer to Figures 1 to 5 , the pixels PX and the photosensors PHS may be located in an i-th horizontal line.

[0118] The pixel PX may include a light emitting element LED and a pixel circuit PXC. The pixel circuit PXC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, and a storage capacitor Cst.

[0119] The first transistor T1 (or driving transistor) can be electrically connected between the first power line PL1 and the first electrode of the light-emitting element LED. The first transistor T1 may include a gate electrode connected to a first node N1. The first transistor T1 can control the amount of current (or driving current) flowing from the first power line PL1 to the electrode EP (or power line) via the light-emitting element LED based on the voltage of the first node N1. A first power supply voltage VDD can be provided to the first power line PL1, and a second power supply voltage VSS can be provided to the electrode EP. The first power supply voltage VDD can be a voltage higher than the second power supply voltage VSS. For example, the first power supply voltage VDD can be approximately 4.6V, and the second power supply voltage VSS can be approximately -2.5V.

[0120] The second transistor T2 may be connected between the j-th data line Dj and the second node N2. The gate electrode of the second transistor T2 may be connected to the 1i-th scan line S1i (or the first scan line). The second transistor T2 may be turned on when a first scan signal GW[i] (e.g., a low-level first scan signal GW[i]) is supplied to the 1i-th scan line S1i to connect the j-th data line Dj and the second node N2. When each of the first transistor T1 and the third transistor T3 is turned on, the second transistor T2 may transmit the data signal of the j-th data line Dj to the first node N1 in response to the first scan signal GW[i].

[0121] The third transistor T3 may be connected between the first node N1 and the third node N3. A gate electrode of the third transistor T3 may be connected to the 4i-th scan line S4i (or the third scan line). When the fourth scan signal GC[i] is supplied to the 4i-th scan line S4i, the third transistor T3 may be turned on. When the third transistor T3 is turned on, the first transistor T1 may have a diode connection structure.

[0122] The fourth transistor T4 may be connected between the first node N1 and the second power line PL2. The gate electrode of the fourth transistor T4 may be connected to the 2i-th scan line S2i (or the second scan line). A first initialization power supply voltage Vint1 may be provided to the second power line PL2. For example, the first initialization power supply voltage Vint1 may be approximately -3.5V. The fourth transistor T4 may be turned on by the second scan signal GI[i] provided to the 2i-th scan line S2i. When the fourth transistor T4 is turned on, the first initialization power supply voltage Vint1 may be provided to the first node N1 (that is, provided to the gate electrode of the first transistor T1).

[0123] The fifth transistor T5 may be connected between the first power line PL1 and the second node N2. The gate electrode of the fifth transistor T5 may be connected to the i-th emission control line Ei. The sixth transistor T6 may be connected between the third node N3 and the light-emitting element LED (or the fourth node N4). The gate electrode of the sixth transistor T6 may be connected to the i-th emission control line Ei. When the emission control signal EM[i] (e.g., a high-level emission control signal EM[i]) is provided to the i-th emission control line Ei, the fifth transistor T5 and the sixth transistor T6 may be turned off, and in other cases, they may be turned on.

[0124] The seventh transistor T7 (or switching transistor) can be connected between the first electrode of the light-emitting element LED (that is, the fourth node N4) and the third power line PL3. The gate electrode of the seventh transistor T7 can be connected to the 3i-th scan line S3i. A second initialization power supply voltage Vint2 can be provided to the third power line PL3. For example, the second initialization power supply voltage Vint2 can be approximately -3.5V. In some embodiments, the second initialization power supply voltage Vint2 can be different from the first initialization power supply voltage Vint1. The seventh transistor T7 can be turned on by the third scan signal GB[i] provided to the 3i-th scan line S3i to provide the second initialization power supply voltage Vint2 to the first electrode of the light-emitting element LED.

[0125] The storage capacitor Cst may be connected or formed between the first power line PL1 and the first node N1.

[0126] The photosensor PHS may include a sensor circuit SC and a light receiving element LRD. The sensor circuit SC may include a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11, and a first capacitor C1.

[0127] The tenth transistor T10 and the eleventh transistor T11 may be connected in series between the third power line PL3 and a kth readout line RXk (where k is a natural number greater than 0).

[0128] The tenth transistor T10 (or the first sensor transistor) may be connected between the third power line PL3 and the eleventh transistor T11. The gate electrode of the tenth transistor T10 may be connected to the fifth node N5 (or the sensor node). The tenth transistor T10 may control a current flowing from the third power line PL3 to the kth readout line RXk through the eleventh transistor T11 in response to the voltage of the fifth node N5.

[0129] The eleventh transistor T11 (or the second sensor transistor) may be connected between the tenth transistor T10 and the kth readout line RXk. The gate electrode of the eleventh transistor T11 may be connected to the 1i-th scan line S1i. That is, the gate electrode of the eleventh transistor T11 and the gate electrode of the second transistor T2 may share the 1i-th scan line S1i.

[0130] The eleventh transistor T11 may include a first sub-transistor T11-1 and a second sub-transistor T11-2 connected in series between the tenth transistor T10 and the kth readout line RXk. That is, the eleventh transistor T11 may be implemented as a dual-gate transistor. In this case, current leakage through the eleventh transistor T11 and the resulting sensing error of the sensor circuit SC may be reduced, and the stability of the photosensor PHS may be improved.

[0131] The first capacitor C1 may be formed or electrically connected between the constant voltage wiring and the sixth node N6 (or the first intermediate node) to which the first sub-transistor T11-1 and the second sub-transistor T11-2 are connected. The constant voltage wiring is a wiring to which a constant voltage (or DC voltage) is applied, and for example, the constant voltage wiring may be the third power line PL3, but is not limited thereto.

[0132] For reference, when the sensor circuit SC does not include the first capacitor C1, the sixth node N6 may be in a floating state, the voltage of the sixth node N6 may be undesirably changed by coupling between the sixth node N6 and an adjacent signal line, and current leakage through the eleventh transistor T11 may occur. The first capacitor C1 can reduce or prevent the undesirable change in the voltage of the sixth node N6.

[0133] The ninth transistor T9 (or third sensor transistor) may be connected between the fourth power line PL4 (or reference power line) and the fifth node N5. The gate electrode of the ninth transistor T9 may be connected to the reset control line RSTL. A reset voltage VRST is provided to the fourth power line PL4, and for example, the reset voltage VRST may be approximately -4.5V.

[0134] At least one light receiving element LRD may be connected between the fifth node N5 and the electrode EP to which the second power supply voltage VSS is supplied.

[0135] The light receiving element LRD may generate charge (or current) based on incident light. That is, the light receiving element LRD may perform a photoelectric conversion function. For example, the light receiving element LRD may be implemented as a photodiode.

[0136] When the ninth transistor T9 is turned on by the reset signal RST supplied to the reset control line RSTL, the reset voltage VRST may be supplied to the fifth node N5. For example, the voltage of the fifth node N5 may be reset by the reset voltage VRST. After the reset voltage VRST is applied to the fifth node N5, the light receiving element LRD may perform a photoelectric conversion function.

[0137] The voltage of the fifth node N5 can be changed by the operation of the light receiving element LRD. The voltage of the fifth node N5 (or the charge or current generated by the light receiving element LRD) can vary according to the intensity of light incident on the light receiving element LRD and according to the time of light incidence (or the time the light receiving element LRD is exposed to light).

[0138] When the eleventh transistor T11 is turned on by the first scan signal GW[i] supplied to the li-th scan line S1i, a detection value (current and / or voltage) generated based on the voltage of the fifth node N5 may flow to the k-th readout line RXk.

[0139] Each of the pixel circuit PXC and the sensor circuit SC may include a P-type transistor and an N-type transistor. The third transistor T3, the fourth transistor T4, and the ninth transistor T9 may be formed as an oxide semiconductor transistor including an oxide semiconductor (or a second-type semiconductor). For example, the third transistor T3, the fourth transistor T4, and the ninth transistor T9 may be an N-type oxide semiconductor transistor and may include an oxide semiconductor layer as an active layer.

[0140] Oxide semiconductor transistors can be processed at low temperatures and have a charge mobility lower than that of polysilicon semiconductor transistors. That is, oxide semiconductor transistors have excellent off-current characteristics. Therefore, leakage current in the third transistor T3, the fourth transistor T4, and the ninth transistor T9 can be reduced or minimized.

[0141] The remaining transistors (e.g., the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the tenth transistor T10, and the eleventh transistor T11) can be formed as polysilicon transistors including a silicon semiconductor (or a first type semiconductor), and can include a polysilicon semiconductor layer as an active layer. For example, the active layer can be formed by a low-temperature polysilicon process (LTPS process). For example, the polysilicon transistor can be a P-type polysilicon transistor. Because the polysilicon semiconductor transistor has the advantage of fast response speed, it can be applied to a switching element using a fast switch.

[0142] As described above, the pixel circuit PXC and the sensor circuit SC can share a scan line (eg, the 1i-th scan line S1i), and the pixel circuit PXC and the sensor circuit SC can be scanned simultaneously. In this case, the number of pixels located on the display panel 100 (see FIG. 10) can be relatively reduced. Figure 1 ) can reduce the number of wirings in the display, and the resolution degradation caused by the wiring (for example, a relatively large number of wirings) can be reduced. In addition, the driver (for example, the scan driver 211) for driving the pixels PX and the photosensors PHS can be integrated, and the space for the driver can be reduced.

[0143] In addition, the eleventh transistor T11 may be implemented as a dual-gate transistor, and the first capacitor C1 may be connected between the intermediate node (that is, the sixth node N6) of the eleventh transistor T11 and the constant voltage wiring (for example, the third power supply line PL3). Therefore, the current leaking to the k-th readout line RXk can be reduced or minimized, and the sensing sensitivity of the photosensor PHS including the sensor circuit SC can be improved.

[0144] Figure 6 Shown Figure 5 Waveform diagrams of one or more embodiments of the operation of a pixel and a photosensor.

[0145] refer to Figure 1 、 Figure 2 、 Figure 5 and Figure 6, the light-emitting control signal EM[i] may be provided to the i-th light-emitting control line Ei, the second scan signal GI[i] may be provided to the 2i-th scan line S2i, the fourth scan signal GC[i] may be provided to the 4i-th scan line S4i, the third scan signal GB[i] may be provided to the 3i-th scan line S3i, and the first scan signal GW[i] may be provided to the 1i-th scan line S1i. The reset signal RST may be provided to the reset control line RSTL. The sensing scan signal SCAN[i] (or the i-th sensing scan signal) may refer to a signal provided to the gate electrode of the eleventh transistor T11. Because the gate electrode of the eleventh transistor T11 is connected to the 1i-th scan line S1i, the sensing scan signal SCAN[i] may be the first scan signal GW[i].

[0146] The kth frame period FRAME_k may include a non-light-emitting period P_NE. The non-light-emitting period P_NE (or the kth frame period FRAME_k) may include an initialization period P_INT, a compensation period P_C, and a writing period P_W. The writing period P_W may be included in the compensation period P_C.

[0147] In the non-emission period P_NE, the emission control signal EM[i] may have a high level. In this case, the fifth transistor T5 and the sixth transistor T6 may be turned off in response to the high level emission control signal EM[i], and the pixel PX may not emit light.

[0148] During the initialization period P_INT, the second scan signal GI[i] may have a high level. In this case, the fourth transistor T4 may be turned on in response to the high level of the second scan signal GI[i], and the first initialization power supply voltage Vint1 of the second power line PL2 may be supplied to the first node N1 (or supplied to the gate electrode of the first transistor T1).

[0149] Thereafter, the fourth scan signal GC[i] may have a high level during the compensation period P_C. The third transistor T3 may be turned on in response to the high level fourth scan signal GC[i], and the first transistor T1 may be diode-connected.

[0150] During the write period P_W, the first scan signal GW[i] may have a low level. In this case, the second transistor T2 may be turned on in response to the low-level first scan signal GW[i], and the data signal may be supplied from the j-th data line Dj to the second node N2. Furthermore, because the third transistor T3 is turned on in response to the high-level fourth scan signal GC[i], the data signal may be transmitted from the second node N2 to the first node N1 through the first transistor T1 and the third transistor T3. Because the first transistor T1 maintains a diode connection due to the turned-on third transistor T3, the voltage of the first node N1 may have a voltage at which the threshold voltage of the first transistor T1 is compensated by the data signal.

[0151] Before the write period P_W, the third scan signal GB[i] may have a low level. In this case, the seventh transistor T7 may be turned on in response to the low-level third scan signal GB[i], and the second initialization power supply voltage Vint2 may be provided to the first electrode of the light-emitting element LED. The third scan signal GB[i] may be the first scan signal (e.g., GW[i-1]) provided in the previous row, but is not limited thereto.

[0152] Afterwards, the non-light-emitting period P_NE may end, and the light-emitting control signal EM[i] may have a low level. In this case, the fifth transistor T5 and the sixth transistor T6 may be turned on in response to the low-level light-emitting control signal EM[i]. In addition, a current movement path may be formed from the first power line PL1 through the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light-emitting element LED to the electrode EP. In addition, according to the operation of the first transistor T1, a driving current corresponding to the voltage of the first node N1 (e.g., a data signal) may flow through the light-emitting element LED. In addition, the light-emitting element LED may emit light having a brightness corresponding to the driving current.

[0153] Meanwhile, the reset signal RST may have a high level in the reset period P_RST before the k-th frame period FRAME_k. When a user's touch input or fingerprint detection request occurs, the reset circuit 221 (see Figure 2 ) may provide a high-level reset signal RST to the reset control line RSTL. In response to the high-level reset signal RST, the ninth transistor T9 may be turned on, and a reset voltage VRST may be applied to the fifth node N5. The voltage of the fifth node N5 may be reset by the reset voltage VRST.

[0154] Thereafter, the ninth transistor T9 may be turned off in response to the reset signal RST of a low level. When light is incident on the light receiving element LRD during the exposure time EIT, the voltage of the fifth node N5 may be changed by a photoelectric conversion function of the light receiving element LRD.

[0155] In the sensing scan period P_SC of the k-th frame period FRAME_k, the sensing scan signal SCAN[i] (that is, the first scan signal GW[i]) may have a low level. The sensing scan period P_SC may be the same as the write period P_W. The eleventh transistor T11 may be turned on in response to the first scan signal GW[i], and a current (or a detection value) may flow from the third power line PL3 to the k-th readout line RXk in response to the voltage of the fifth node N5.

[0156] For example, when a user's touch input occurs on the display panel 100, a current (that is, a detection value) corresponding to light reflected by the user (e.g., the user's finger) may be output in the k-th frame period FRAME_k. For example, the user's fingerprint may be detected based on the detection value.

[0157] Figure 7A 、 Figure 7B and Figure 7C Shown Figure 4 A top view of one or more embodiments of a display area. Figure 7A 、 Figure 7B and Figure 7C Shown Figure 5 Based on the pixel circuit PXC and sensor circuit SC. Figure 8 The first insulating layer INS1 of the pixel circuit PXC (and the sensor circuit SC) is formed on the bottom of the Figure 7B and some upper components of the pixel circuit PXC (and sensor circuit SC) are shown in Figure 7C Shown in. Figure 8 Shown Figure 4 A cross-sectional view of one or more embodiments of a display area.

[0158] exist Figures 7A to 8 , the sub-pixels are simplified by illustrating each electrode as an electrode of a single film and each insulating layer as an insulating layer of a single film, but the present disclosure is not limited thereto.

[0159] When describing the embodiments of the present disclosure, “formed and / or disposed in the same layer” may mean formed in the same process, and “formed and / or disposed in different layers” may mean formed in different processes.

[0160] exist Figure 7A 、 Figure 7B and Figure 7C , a horizontal direction in a plan view is represented as a first direction DR1, and a vertical direction in a plan view is represented as a second direction DR2.

[0161] refer to Figure 4 、 Figure 5、 Figure 7A 、 Figure 7B 、 Figure 7C and Figure 8 , the sensor circuit SC can be connected with Figure 4 11, and based on the sensor circuit SC, the pixel circuit PXC on the left and the pixel circuit PXC on the right may correspond to the twelfth pixel circuit PXC12 and the thirteenth pixel circuit PXC13, respectively. Based on the sensor circuit SC, the pixel circuit PXC on the left and the pixel circuit PXC on the right may be substantially symmetrical and may be substantially the same or similar. Therefore, the pixel circuit PXC on the left (that is, the twelfth pixel circuit PXC12) will be described on this basis, and the redundant description will not be repeated. For convenience, Figure 7B and Figure 7C Only the pixel circuit PXC on the left side (that is, the twelfth pixel circuit PXC12 ) and the sensor circuit SC are shown in FIG.

[0162] In the following, reference will be made to Figure 8 Components are described according to the order in which they are stacked on the base layer BL.

[0163] The base layer BL (or substrate) may be made of an insulating material such as glass or resin. In addition, the base layer BL may be made of a bendable or foldable flexible material and may have a single-layer structure or a multi-layer structure.

[0164] A back plate structure BP including the pixel circuit PXC and the sensor circuit SC may be disposed on the base layer BL. The back plate structure BP may include a semiconductor layer, a plurality of conductive layers, and a plurality of insulating layers.

[0165] The lower electrode BML may be located on the base layer BL. The lower electrode BML may overlap with the first transistor T1 (or the first capacitor electrode CE1 and the second capacitor electrode CE2) in a plan view. The lower electrode BML may shield the first transistor T1 (or the first capacitor electrode CE1 and the second capacitor electrode CE2) from the lower portion. A constant voltage may be applied to the lower electrode BML. For example, the first power supply voltage VDD may be applied to the lower electrode BML, but is not limited thereto. The lower electrode BML may extend in a first direction DR1 and a second direction DR2 relative to the first transistor T1. The lower electrode BML may have a mesh structure throughout the entire display area.

[0166] The lower electrode BML may include a conductive material, such as copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and / or alloys thereof.

[0167] The buffer layer BF may be provided on the base layer BL to cover the lower electrode BML. The buffer layer BF may be an insulating film including an inorganic material. For example, the inorganic material may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxides (AlO x ) of at least one of the metal oxides of . The buffer layer BF may be provided as a single film, but may be provided as a plurality of films of two or more. The buffer layer BF may reduce or prevent impurities from diffusing into the transistor.

[0168] The first semiconductor pattern ACT1 (or first active pattern or first semiconductor layer) of the pixel circuit PXC and the second semiconductor pattern ACT2 (or second active pattern or second semiconductor layer) of the sensor circuit SC may be located on the buffer layer BF. The first and second semiconductor patterns ACT1 and ACT2 may be formed of polysilicon semiconductor.

[0169] The first semiconductor pattern ACT1 overlapping the first capacitor electrode CE1 may form a channel region of the first transistor T1. The first semiconductor pattern ACT1 may extend from both ends of the channel region of the first transistor T1 in a direction opposite to the second direction DR2. The first semiconductor pattern ACT1 overlapping the i-th light emitting control line Ei may constitute a channel region of the fifth transistor T5 and a channel region of the sixth transistor T6. The first semiconductor pattern ACT1 may also extend from the channel region of the sixth transistor T6 in a direction opposite to the second direction DR2, and the first semiconductor pattern ACT1 overlapping the 1i-th scan line S1i (or the first semiconductor pattern ACT1 overlapping the 1i-th scan line S1i) may extend from the channel region of the sixth transistor T6 in a direction opposite to the second direction DR2. Figure 7B The first semiconductor pattern ACT1a) overlapping the 3i+1th scan line S3i+1 may constitute a channel region of the seventh transistor T7. The first semiconductor pattern ACT1 may extend from a right end portion of the channel region of the first transistor T1 in the second direction DR2, and the first semiconductor pattern ACT1 overlapping the 1ith scan line S1i may constitute a channel region of the second transistor T2.

[0170] For example, the channel region of the semiconductor pattern not doped with impurities may be an intrinsic semiconductor, and the remaining region of the semiconductor layer except the channel region (eg, the remaining region of the first semiconductor pattern ACT1 ) may be a semiconductor pattern doped with impurities.

[0171] The second semiconductor pattern ACT2 may be spaced apart from the first semiconductor pattern ACT1 in the first direction DR1. The second semiconductor pattern ACT2 overlapping the first gate electrode GE1 may constitute the channel region of the tenth transistor T10. The second semiconductor pattern ACT2 overlapping the 1i-th scan line S1i may constitute the channel region of the eleventh transistor T11 (or the first and second sub-transistors T11-1 and T11-2).

[0172] The first gate insulating layer GI1 may be positioned on the first and second semiconductor patterns ACT1 and ACT2 . The first gate insulating layer GI1 may be an insulating film made of an inorganic material.

[0173] The first capacitor electrode CE1, the first gate electrode GE1, the i-th light emitting control line Ei and the 1i-th scan line S1i (and Figure 7B The 3i+1th scan line S3i+1) may be located on the first gate insulating layer GI1. The first capacitor electrode CE1, the first gate electrode GE1, the i-th light emitting control line Ei, and the 1i-th scan line S1i may include a conductive material.

[0174] The first capacitor electrode CE1 overlapping the first semiconductor pattern ACT1 may constitute a gate electrode of the first transistor T1 .

[0175] The first gate electrode GE1 overlapping the second semiconductor pattern ACT2 may constitute a gate electrode of the tenth transistor T10 .

[0176] In a plan view, the i th light emitting control line Ei and the li th scan line S1i may be spaced apart from each other with the first capacitor electrode CE1 interposed therebetween, and each may extend in the first direction DR1.

[0177] The i-th light emitting control line Ei overlapping the first semiconductor pattern ACT1 may constitute a gate electrode of the fifth transistor T5 and a gate electrode of the sixth transistor T6 .

[0178] The 1i-th scan line S1i overlapping the first semiconductor pattern ACT1 may constitute the gate electrode of the second transistor T2. In addition, the 1i-th scan line S1i (or Figure 7B The 3i+1th scan line S3i+1) may constitute the gate electrode of the seventh transistor T7.

[0179] The interlayer insulating layer IL may be located between the first capacitor electrode CE1, the first gate electrode GE1, the i-th light emitting control line Ei, the 1i-th scan line S1i (and Figure 7B The interlayer insulating layer IL may be an insulating layer made of an inorganic material.

[0180] The second capacitor electrode CE2, the third capacitor electrode CE3, the first sub-reset control line RSTLa, the 2ia scan line S2ia (or the first sub-scan line), the 4ia scan line S4ia, and the second power line PL2 (or the second horizontal power line) may be located on the interlayer insulating layer IL. The second capacitor electrode CE2, the third capacitor electrode CE3, the first sub-reset control line RSTLa, the 2ia scan line S2ia, the 4ia scan line S4ia, and the second power line PL2 may include a conductive material. The first sub-reset control line RSTLa and the second sub-reset control line RSTLb may form a reset control line RSTL. Similarly, the 2ia scan line S2ia and the 2ib scan line S2ib (or the third sub-scan line) may form a 2i scan line S2i, and the 4ia scan line S4ia and the 4ib scan line S4ib (or the fourth sub-scan line) may form a 4i scan line S4i.

[0181] The second capacitor electrode CE2 may overlap the first capacitor electrode CE1 and may form a storage capacitor Cst. Most of the first capacitor electrode CE1 may overlap the second capacitor electrode CE2. The second capacitor electrode CE2 may include / define an opening exposing the first capacitor electrode CE1.

[0182] The third capacitor electrode CE3 may overlap with the second semiconductor pattern ACT2. For example, the third capacitor electrode CE3 may overlap with a portion (e.g., a region doped with impurities) of the second semiconductor pattern ACT2 between the channel region of the first sub-transistor T11-1 and the channel region of the second sub-transistor T11-2. The third capacitor electrode CE3 and this portion of the second semiconductor pattern ACT2 may form a first capacitor C1.

[0183] In a plan view, the first sub-reset control line RSTLa, the 2ia scan line S2ia, and the second power line PL2 may be spaced apart from each other in the second direction DR2, and each of the first sub-reset control line RSTLa, the 2ia scan line S2ia, the 4ia scan line S4ia, and the second power line PL2 may extend in the first direction DR1.

[0184] The first insulating layer INS1 may be on the second and third capacitor electrodes CE2 and CE3, the first sub reset control line RSTLa, the 2ia and 4ia scan lines S2ia and S4ia, and the second power line PL2. The first insulating layer INS1 may be an insulating film made of an inorganic material.

[0185] The third semiconductor pattern ACT3 (or the third active pattern and the third semiconductor layer) of the pixel circuit PXC and the fourth semiconductor pattern ACT4 (or the fourth active pattern and the fourth semiconductor layer) of the sensor circuit SC may be located on the first insulating layer INS1. The third semiconductor pattern ACT3 and the fourth semiconductor pattern ACT4 may be formed of an oxide semiconductor. Each of the third semiconductor pattern ACT3 and the fourth semiconductor pattern ACT4 may extend substantially in the second direction DR2.

[0186] The third semiconductor pattern ACT3 overlapping the 4ia scan line S4ia (and the 4ib scan line S4ib) may constitute the channel region of the third transistor T3. The third semiconductor pattern ACT3 overlapping the 2ia scan line S2ia (and the 2ib scan line S2ib) may constitute the channel region of the fourth transistor T4.

[0187] The fourth semiconductor pattern ACT4 overlapping the first sub reset control line RSTLa may constitute a channel region of the ninth transistor T9 .

[0188] The second gate insulating layer GI2 may be positioned on the third and fourth semiconductor patterns ACT3 and ACT4 . The second gate insulating layer GI2 may be an insulating layer made of an inorganic material.

[0189] The second sub reset control line RSTLb, the 2ib scan line S2ib (or the third sub scan line), and the 4ib scan line S4ib (or the fourth sub scan line) may be located on the second gate insulating layer GI2. The 2ib scan line S2ib and the 4ib scan line S4ib may include a conductive material.

[0190] In a plan view, the second sub reset control line RSTLb, the 2ib scan line S2ib, and the 4ib scan line S4ib may be spaced apart from each other in the second direction DR2, and each of the second sub reset control line RSTLb, the 2ib scan line S2ib, and the 4ib scan line S4ib may extend in the first direction DR1.

[0191] The second sub-reset control line RSTLb may overlap with the first sub-reset control line RSTLa. ​​Furthermore, the second sub-reset control line RSTLb overlapping with the fourth semiconductor pattern ACT4 may constitute the gate electrode (or first gate electrode) of the ninth transistor T9. Simultaneously, the first sub-reset control line RSTLa overlapping with the fourth semiconductor pattern ACT4 may constitute the lower gate electrode (or second gate electrode) of the ninth transistor T9.

[0192] The 2ib scan line S2ib may overlap with the 2ia scan line S2ia. Furthermore, the 2ib scan line S2ib overlapping with the third semiconductor pattern ACT3 may constitute the gate electrode (or first gate electrode) of the fourth transistor T4. Simultaneously, the 2ia scan line S2ia overlapping with the third semiconductor pattern ACT3 may constitute the lower gate electrode (or second gate electrode) of the fourth transistor T4.

[0193] The 4ib scan line S4ib may overlap with the 4ia scan line S4ia. Furthermore, the 4ib scan line S4ib overlapping with the third semiconductor pattern ACT3 may constitute the gate electrode (or first gate electrode) of the third transistor T3. Simultaneously, the 4ia scan line S4ia overlapping with the third semiconductor pattern ACT3 may constitute the lower gate electrode (or second gate electrode) of the third transistor T3.

[0194] The second insulating layer INS2 may be located on the second sub reset control line RSTLb, the 2ib-th scan line S2ib, and the 4ib-th scan line S4ib. The second insulating layer INS2 may be an insulating layer made of an inorganic material.

[0195] The third and fourth power lines PL3 and PL4 and the bridge patterns BRP1 to BRP8 may be located on the second insulating layer INS2. The third and fourth power lines PL3 and PL4 and the bridge patterns BRP1 to BRP8 may include a conductive material.

[0196] The third power line PL3 may extend substantially in the first direction DR1. The third power line PL3 may extend in the first direction DR1 between the tenth transistor T10 and the eleventh transistor T11. The third power line PL3 may protrude in a direction opposite to the second direction DR2 in a region adjacent to the tenth transistor T10 and may overlap with an upper portion of the second semiconductor pattern ACT2. The third power line PL3 may contact an upper portion of the second semiconductor pattern ACT2 through a contact hole. Furthermore, the third power line PL3 may protrude in the second direction DR2 in a region adjacent to the eleventh transistor T11, and a protruding portion CE4 of the third power line PL3 may overlap with the third capacitor electrode CE3. The third power line PL3 may contact the third capacitor electrode CE3 through a contact hole passing through at least one insulating layer (e.g., a contact hole passing through the first insulating layer INS1 to the second insulating layer INS2).

[0197] The first bridge pattern BRP1 may overlap the first semiconductor pattern ACT1 and may be connected to the first semiconductor pattern ACT1 through a contact hole. The first bridge pattern BRP1 may be electrically connected to the light emitting element LED (see Figure 8 ), and the first bridge pattern BRP1 may constitute Figure 5The fourth node N4.

[0198] The second bridge pattern BRP2 may overlap with the first semiconductor pattern ACT1 and may be connected to the first semiconductor pattern ACT1 (or one electrode of the first transistor T1) through a contact hole. In addition, the second bridge pattern BRP2 may overlap with the third semiconductor pattern ACT3 and may be connected to the third semiconductor pattern ACT3 (or one electrode of the third transistor T3) through a contact hole. The second bridge pattern BRP2 may electrically connect the first transistor T1 and the third transistor T3. The second bridge pattern BRP2 may constitute Figure 5 The third node N3 in .

[0199] The third bridge pattern BRP3 may overlap with the first capacitor electrode CE1 and may be connected to the first capacitor electrode CE1 through a contact hole (and an opening of the second capacitor electrode CE2). In addition, the third bridge pattern BRP3 may overlap with the third semiconductor pattern ACT3 and may be connected to the third semiconductor pattern ACT3 (or the other electrode of the third transistor T3) through a contact hole. The third bridge pattern BRP3 may electrically connect the first capacitor electrode CE1 (or the storage capacitor Cst) and the third transistor T3. The third bridge pattern BRP3 may constitute Figure 5 The first node N1 in.

[0200] The fourth bridge pattern BRP4 may overlap the first power line PL1 (or the first vertical power line).

[0201] The fifth bridge pattern BRP5 may overlap a lower end portion of the third semiconductor pattern ACT3 and the second power line PL2 and may be connected to the lower end portion of the third semiconductor pattern ACT3 and the second power line PL2 , respectively.

[0202] The sixth bridge pattern BRP6 may overlap a portion of the first semiconductor pattern ACT1 adjacent to the second transistor T2 and the j-th data line Dj, and may be connected to a portion of the first semiconductor pattern ACT1 adjacent to the second transistor T2 and the j-th data line Dj, respectively.

[0203] The seventh bridge pattern BRP7 may overlap with the first gate electrode GE1 and may be connected to the first gate electrode GE1 (or the gate electrode of the tenth transistor T10) through a contact hole. In addition, the seventh bridge pattern BRP7 may overlap with the fourth semiconductor pattern ACT4 and may be connected to the fourth semiconductor pattern ACT4 (or one electrode of the ninth transistor T9) through a contact hole. The seventh bridge pattern BRP7 may electrically connect the gate electrode of the tenth transistor T10 and the ninth transistor T9. The seventh bridge pattern BRP7 may constitute Figure 5 The fifth node N5 in .

[0204] The eighth bridge pattern BRP8 may overlap the second semiconductor pattern ACT2 (or one electrode of the eleventh transistor T11 ) and the k th readout line RXk, and may be connected to the second semiconductor pattern ACT2 and the k th readout line RXk, respectively.

[0205] The third insulating layer INS3 may be located on the third power line PL3, the fourth power line PL4, and the bridge patterns BRP1 to BRP8. The third insulating layer INS3 may be an insulating layer made of an inorganic material or an organic material. For example, the organic material may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0206] The first power line PL1 (or first vertical power line), the jth data line Dj, the fourth vertical power line PL4V, the kth readout line RXk, the ninth bridge pattern BRP9, and the tenth bridge pattern BRP10 may be located on the third insulating layer INS3. The first power line PL1, the jth data line Dj, the fourth vertical power line PL4V, the kth readout line RXk, the ninth bridge pattern BRP9, and the tenth bridge pattern BRP10 may include a conductive material.

[0207] The first power line PL1, the jth data line Dj, the fourth vertical power line PL4V, and the kth readout line RXk may be spaced apart from each other along the first direction DR1, and each of them may extend in the second direction DR2. The first power line PL1 may be connected to the fourth bridge pattern BRP4 through a contact hole. The jth data line Dj may be connected to the sixth bridge pattern BRP6 through a contact hole. The kth readout line RXk may be connected to the eighth bridge pattern BRP8 through a contact hole.

[0208] The ninth bridge pattern BRP9 may overlap the first bridge pattern BRP1 and may be connected to the first bridge pattern BRP1 through a contact hole.

[0209] The tenth bridge pattern BRP10 may overlap the seventh bridge pattern BRP7 and may be connected to the seventh bridge pattern BRP7 through a contact hole.

[0210] The fourth insulating layer INS4 may be located on the first power line PL1 (or first vertical power line), the jth data line Dj, the fourth vertical power line PL4V, the kth readout line RXk, the ninth bridge pattern BRP9, and the tenth bridge pattern BRP10. The fourth insulating layer INS4 may be an insulating layer made of an organic material and / or an inorganic material. The fourth insulating layer INS4 may function as a planarization layer.

[0211] A pixel layer including the first pixel electrode PEL1 , the first sensor electrode SEL1 , and the bank layer BK may be disposed on the fourth insulating layer INS4 .

[0212] The pixel layer may include a light emitting element LED connected to a pixel circuit PXC and a light receiving element LRD connected to a sensor circuit SC.

[0213] The light emitting element LED may include a first pixel electrode PEL1, a first hole transport layer HTL1, an emission layer EML, an electron transport layer ETL, and a second pixel electrode PEL2. The light receiving element LRD may include a first sensor electrode SEL1, a second hole transport layer HTL2, a light receiving layer LRL, an electron transport layer ETL, and a second sensor electrode SEL2.

[0214] The first pixel electrode PEL1 and the first sensor electrode SEL1 can be made of a metal layer such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and / or alloys thereof, and / or indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and / or indium tin zinc oxide (ITZO). The first pixel electrode PEL1 can be connected to the first connection pattern CNP1 through a contact hole. The first sensor electrode SEL1 can be connected to the second connection pattern CNP2 through a contact hole.

[0215] The first pixel electrode PEL1 and the first sensor electrode SEL1 may be formed simultaneously or substantially simultaneously by patterning using a mask.

[0216] A bank layer BK (or pixel defining film) for partitioning the light emitting area and the light receiving area may be disposed on the fourth insulating layer INS4 on which the first pixel electrode PEL1 and the first sensor electrode SEL1 are formed. The bank layer BK may be an insulating layer made of an organic material.

[0217] In some embodiments, the bank layer BK may include a light absorbing material, or may be used to absorb light introduced from the outside by applying a light absorber to the bank layer BK. For example, the bank layer BK may include a carbon-based black pigment. However, it is not limited thereto, and the bank layer BK may include an opaque metal material with high light absorptivity, such as chromium (Cr), molybdenum (Mo), an alloy of molybdenum and titanium (MoTi), tungsten (W), vanadium (V), niobium (Nb), tantalum (Ta), manganese (Mn), cobalt (Co), or nickel (Ni).

[0218] The bank layer BK may include / define openings corresponding to the light emitting area and the light receiving area.

[0219] The first hole transport layer HTL1 may be disposed on the upper surface of the first pixel electrode PEL1 exposed by the bank layer BK, and the second hole transport layer HTL2 may be disposed on the exposed upper surface of the first sensor electrode SEL1. Holes may move to the light emitting layer EML through the first hole transport layer HTL1, and holes may move to the light receiving layer LRL through the second hole transport layer HTL2.

[0220] The first hole transport layer HTL1 and the second hole transport layer HTL2 may be substantially the same, or may be different, according to materials of the light emitting layer EML and the light receiving layer LRL.

[0221] The light emitting layer EML may be disposed on the first hole transport layer HTL1. The light emitting layer EML may be configured as an organic light emitting layer. The light emitting layer EML may emit light such as red light, green light, or blue light according to an organic material included in the light emitting layer EML.

[0222] The electron blocking layer may be disposed on the second hole transport layer HTL2 in the light receiving region. The electron blocking layer may reduce or prevent the possibility of charges moving from the light receiving layer LRL to the second hole transport layer HTL2. In one or more embodiments, the electron blocking layer may be omitted.

[0223] The light receiving layer LRL may be positioned on the second hole transport layer HTL2 . The light receiving layer LRL may detect the intensity of light by emitting electrons in response to light of a corresponding wavelength band.

[0224] The light receiving layer LRL may include a low molecular weight organic material. For example, the light receiving layer LRL is made of a phthalocyanine compound containing at least one metal selected from the group consisting of copper (Cu), iron (Fe), nickel (Ni), cobalt (Co), manganese (Mn), aluminum (Al), palladium (Pd), tin (Sn), indium (In), lead (Pb), titanium (Ti), rubidium (Rb), vanadium (V), gallium (Ga), terbium (Tb), cerium (Ce), lanthanum (La), and zinc (Zn).

[0225] In addition, the low molecular weight organic material included in the light receiving layer LRL can be composed of two layers (double layer) including a layer containing a phthalocyanine compound and a layer containing C60, or can be composed of a mixed layer in which a phthalocyanine compound and C60 are mixed, and the phthalocyanine compound includes one or more of copper (Cu), iron (Fe), nickel (Ni), cobalt (Co), manganese (Mn), aluminum (Al), palladium (Pd), tin (Sn), indium (In), lead (Pb), titanium (Ti), rubidium (Rb), vanadium (V), gallium (Ga), terbium (Tb), cerium (Ce), lanthanum (La) and zinc (Zn).

[0226] However, this is an example, and the light receiving layer LRL may include a polymer organic layer.

[0227] The light receiving layer LRL can determine the photodetection band of the photosensor PHS by controlling the selection of the metal component included in the phthalocyanine compound. For example, when the phthalocyanine compound includes copper, it absorbs visible light wavelengths in the band ranging from about 600nm to about 800nm, and when the phthalocyanine compound includes tin (Sn), it absorbs near-infrared wavelengths in the band ranging from about 800nm ​​to about 1000nm. Therefore, by controlling the selection of the metal included in the phthalocyanine compound, it is possible to realize a photosensor that can detect wavelengths in the band desired by the user. For example, the light receiving layer LRL can be formed to selectively absorb wavelengths in the red light band, the green light band, or the blue light band.

[0228] An area of ​​the light receiving region may be smaller than an area of ​​the light emitting region.

[0229] The second pixel electrode PEL2 and the second sensor electrode SEL2 may be disposed on the electron transport layer ETL. The second pixel electrode PEL2 and the second sensor electrode SEL2 may be a common electrode CD integrally formed in the display area AA. The second power supply voltage VSS may be supplied to the second pixel electrode PEL2 and the second sensor electrode SEL2.

[0230] The common electrode CD may be formed of a metal layer and / or a transparent conductive layer, wherein the metal layer is made of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), or chromium (Cr), and the transparent conductive layer is made of ITO, IZO, ZnO, or ITZO. The common electrode CD may be formed of a multilayer including two or more thin metal layers (e.g., a triple layer of ITO / Ag / ITO).

[0231] The encapsulation layer TFE may be provided on the common electrode CD including the second pixel electrode PEL2 and the second sensor electrode SEL2. The encapsulation layer TFE may be provided as a single layer or as a multilayer. The encapsulation layer TFE may have a stacked structure in which an inorganic material, an organic material, and an inorganic material are sequentially deposited. The uppermost layer of the encapsulation layer TFE may be formed of an inorganic material.

[0232] As described above, the third capacitor electrode CE3 may be located on a portion (e.g., a region doped with impurities) of the second semiconductor pattern ACT2 between the channel region of the first sub-transistor T11-1 and the channel region of the second sub-transistor T11-2, and the third capacitor electrode CE3 may be connected to the third power line PL3. The third capacitor electrode CE3 and the portion of the second semiconductor pattern ACT2 may form the first capacitor C1. Therefore, current leakage through the eleventh transistor T11 may be reduced or minimized, and the accuracy of sensing using the photosensor PHS including the sensor circuit SC may be improved.

[0233] Figure 9 Shown Figure 7A A top view of one or more embodiments of region BB.

[0234] refer to Figure 4 、 Figure 5 、 7A to 7C 、 Figure 8 and Figure 9 , the shape of the second semiconductor pattern ACT2 may be variously modified.

[0235] For example, the second semiconductor pattern ACT2 may include a portion that protrudes or extends in opposite directions of the first direction DR1 and / or the second direction DR2 between the channel region of the first sub-transistor T11-1 and the channel region of the second sub-transistor T11-2. This portion of the second semiconductor pattern ACT2 may increase the overlap area with the third capacitor electrode CE3 and may increase the capacitance of the first capacitor C1. In other words, the capacitance of the first capacitor C1 may be adjusted by increasing or decreasing this portion of the second semiconductor pattern ACT2.

[0236] Figure 10 Shown included in Figure 4 Circuit diagram of one or more embodiments of pixels and photosensors in a display area. Figure 11 Shown Figure 4 A top view of one or more embodiments of a display area. Figure 11 In, with Figure 7C Similar, based on Figure 8 The first insulating layer INS1 shows some components of the upper part of the pixel circuit PXC (and the sensor circuit SC). Figure 12 Shown included in Figure 4 Circuit diagrams of one or more other embodiments of pixels and photosensors in a display area.

[0237] refer to Figure 4 、 Figure 5 、 7A to 7C 、 Figure 10 and Figure 11 , except for the third power line PL3 and the protruding portion CE4, Figure 10 and Figure 11 The sensor circuit SC (and pixel circuit PXC) can be basically the same as Figure 5 as well as 7A to 7C The sensor circuit SC (and pixel circuit PXC) are the same as or similar to those in FIG. Therefore, a redundant description will not be repeated.

[0238] The first capacitor C1 may be electrically connected between the sixth node N6 (or the first intermediate node) to which the first and second sub-transistors T11-1 and T11-2 are connected and the fourth power line PL4. The same voltage as the fourth power line PL4 to which the ninth transistor T9 is connected may be applied to the constant voltage wiring to which the first capacitor C1 is connected.

[0239] In this case, if Figure 11 As shown in FIG, the third power line PL3 may not include a portion protruding in the second direction DR2 (that is, toward Figure 7B The protruding portion CE4 of the fourth power line PL4 may protrude in a direction opposite to the second direction DR2. Figure 7B The third capacitor electrode CE3 overlaps with the first capacitor electrode CE3 and may be contacted through a contact hole passing through at least one insulating layer.

[0240] At the same time, the first capacitor C1 reference Figure 10 and Figure 11 It is described as being electrically connected to the fourth power line PL4, but is not limited thereto. Figure 12 As shown in FIG, the first capacitor C1 can be electrically connected to the fifth power line PL5. In some embodiments, the fifth power line PL5 can be electrically connected to the first power line PL1 or the second power line PL2, or the same voltage as the first power line PL1 or the second power line PL2 can be applied to the fifth power line PL5. That is, the first capacitor C1 is connected to the constant voltage wiring, and the constant voltage wiring is not limited to a specific wiring.

[0241] Figure 13 Shown included in Figure 4 Circuit diagrams of one or more other embodiments of pixels and photosensors in a display area.

[0242] refer to Figure 4 、 Figure 5 and Figure 13 , in addition to the second transistor T2, the third transistor T3, the fourth transistor T4, the eighth transistor T8 and the ninth transistor T9 and the second capacitor C2, Figure 13The sensor circuit SC (and pixel circuit PXC) can be basically the same as Figure 5 The sensor circuits SC (and pixel circuits PXC) are the same or similar. Therefore, redundant descriptions will not be repeated.

[0243] The transistors T1 to T11 may include a silicon semiconductor. For example, the transistors T1 to T11 may be formed of polysilicon transistors and may include a polysilicon semiconductor layer as an active layer. For example, the polysilicon transistors may be P-type transistors.

[0244] The gate electrode of the third transistor T3 can be connected to the 1i-th scan line S1i (or the first scan line). When the first scan signal GW[i] (that is, the low-level first scan signal GW[i]) is provided to the 1i-th scan line S1i, the third transistor T3, which is a polysilicon transistor, can be turned on. In some embodiments, the third transistor T3 can be implemented as a dual-gate transistor.

[0245] The fourth transistor T4 can be connected between the first node N1 and the second power line PL2. The gate electrode of the fourth transistor T4 can be connected to the 2i-th scan line S2i (or the second scan line). The fourth transistor T4, which is a polysilicon transistor, can be turned on by the second scan signal GI[i] (that is, the low-level second scan signal GI[i]) provided to the 2i-th scan line S2i. In some embodiments, the fourth transistor T4 can be implemented as a dual-gate transistor.

[0246] The eighth transistor T8 may be connected between the second node N2 and the fifth power line PL5. A gate electrode of the eighth transistor T8 may be connected to the 3i-th scan line S3i. A bias voltage VOBS may be provided to the fifth power line PL5. The eighth transistor T8 may be turned on by the third scan signal GB[i] provided to the 3i-th scan line S3i and may transmit the bias voltage VOBS to the first electrode of the first transistor T1. The bias voltage VOBS may be set to a voltage level suitable for compensating for the hysteresis characteristic of the first transistor T1. In some embodiments, the eighth transistor T8 may be omitted.

[0247] The ninth transistor T9 (or third sensor transistor) may be connected between the fourth power line PL4 (or reference power line) and the fifth node N5. The gate electrode of the ninth transistor T9 may be connected to the reset control line RSTL. A reset voltage VRST is provided to the fourth power line PL4, and for example, the reset voltage VRST may be approximately -4.5V.

[0248] The ninth transistor T9 (or third sensor transistor) may include a third sub-transistor T9-1 and a fourth sub-transistor T9-2 connected in series between the fourth power line PL4 (or reference power line) and the fifth node N5. That is, the ninth transistor T9 may be implemented as a dual-gate transistor. In this case, current leakage through the ninth transistor T9 may be reduced.

[0249] The first capacitor C1 may be formed or electrically connected between the constant voltage wiring and the sixth node N6 (or the first intermediate node) to which the first sub-transistor T11-1 and the second sub-transistor T11-2 are connected. For example, the constant voltage wiring to which the first capacitor C1 is connected may be the first power line PL1, but is not limited thereto.

[0250] The second capacitor C2 may be formed or electrically connected between the constant voltage wiring and the seventh node N7 (or the second intermediate node) to which the third sub-transistor T9-1 and the fourth sub-transistor T9-2 are connected. The constant voltage wiring to which the second capacitor C2 is connected may be, but is not limited to, the first power line PL1. The second capacitor C2 may reduce or prevent an undesirable change in the voltage of the seventh node N7 and may reduce or prevent current leakage through the ninth transistor T9.

[0251] As described above, the ninth transistor T9 can be implemented as a dual-gate transistor, and the second capacitor C2 can be connected between the middle node of the ninth transistor T9 (that is, the seventh node N7) and the constant voltage wiring (for example, the first power line PL1). Therefore, the leakage current between the fifth node N5 and the fourth power line PL4 can be reduced or minimized, and the sensing sensitivity of the photosensor PHS including the sensor circuit SC can be improved.

[0252] Figure 14A 、 Figure 14B and Figure 14C Shown Figure 4 A top view of one or more embodiments of a display area. Figure 14A 、 Figure 14B and Figure 14C Shown Figure 15 Based on the pixel circuit PXC and sensor circuit SC. Figure 15 The first insulating layer INS1 of the pixel circuit PXC (and the sensor circuit SC) is formed on the bottom of the Figure 14B and some of the upper components of the pixel circuit PXC (and sensor circuit SC) are shown in Figure 14C Further shown in . Figure 15 Shown Figure 4 For convenience, Figure 15 The backplane structure BP is shown in focus, and Figure 8The remaining components (e.g., pixel layer) can also be applied to Figure 15 .

[0253] refer to Figure 4 、 Figure 5 、 Figure 14A 、 Figure 14B 、 Figure 14C and Figure 15 , the sensor circuit SC can be connected with Figure 4 11, and based on the sensor circuit SC, the pixel circuit PXC on the left and the pixel circuit PXC on the right may correspond to the twelfth pixel circuit PXC12 and the thirteenth pixel circuit PXC13, respectively. Based on the sensor circuit SC, the pixel circuit PXC on the left and the pixel circuit PXC on the right may be substantially symmetrical and may be substantially the same or similar. Therefore, the pixel circuit PXC on the left (that is, the twelfth pixel circuit PXC12) will be described based on this, and redundant descriptions will not be repeated.

[0254] In the following, reference will be made to Figure 15 The components are described according to the order in which they are stacked on the base layer BL. Figure 7A 、 Figure 7B 、 Figure 7C and Figure 8 Describes the general characteristics of the components, so the main description will be Figure 7A 、 Figure 7B 、 Figure 7C and Figure 8 The difference in implementation methods.

[0255] A back plate structure BP including the pixel circuit PXC and the sensor circuit SC may be disposed on the base layer BL. The back plate structure BP may include a semiconductor layer, a plurality of conductive layers, and a plurality of insulating layers.

[0256] The first semiconductor pattern ACT1 (or first active pattern or first semiconductor layer) and the fourth semiconductor pattern ACT4 (or fourth active pattern or fourth semiconductor layer) of the pixel circuit PXC and the second semiconductor pattern ACT2 (or second active pattern or second semiconductor layer) and the third semiconductor pattern ACT3 (or third active pattern or third semiconductor layer) of the sensor circuit SC may be located on the buffer layer BF. The first semiconductor pattern ACT1, the second semiconductor pattern ACT2, the third semiconductor pattern ACT3, and the fourth semiconductor pattern ACT4 may be formed of a polycrystalline silicon semiconductor.

[0257] The first semiconductor pattern ACT1 overlapping with the first capacitor electrode CE1 may form the channel region of the first transistor T1. The first semiconductor pattern ACT1 may extend from both ends of the channel region of the first transistor T1 in the second direction DR2. The first semiconductor pattern ACT1 overlapping with the i-th light emission control line Ei may constitute the channel region of the fifth transistor T5 and the channel region of the sixth transistor T6. The first semiconductor pattern ACT1 may also extend from the channel region of the sixth transistor T6 in the second direction DR2. The first semiconductor pattern ACT1 overlapping with the 3i-th scan line S3i (or the portion of the first semiconductor pattern ACT1 connected to the second semiconductor pattern ACT2) may constitute the channel region of the seventh transistor T7. Furthermore, the first semiconductor pattern ACT1 may extend from the left end portion of the channel region of the first transistor T1 in a direction opposite to the second direction DR2. The first semiconductor pattern ACT1 overlapping with the 1i-th scan line S1i may constitute the channel region of the second transistor T2. The first semiconductor pattern ACT1 may extend from the right end portion of the channel region of the first transistor T1 in a direction opposite to the second direction DR2, and the first semiconductor pattern ACT1 overlapping with the 1i-th scan line S1i may constitute the channel region of the third transistor T3. Furthermore, the first semiconductor pattern ACT1 may extend from the third transistor T3 in a direction opposite to the second direction DR2, and the first semiconductor pattern ACT1 overlapping with the 2i-th scan line S2i may constitute the channel region of the fourth transistor T4. To implement the fourth transistor T4 as a dual-gate transistor, the first semiconductor pattern ACT1 may further extend in the second direction DR2 and may further include a curved portion (that is, the 1a-th semiconductor pattern ACT1a).

[0258] The second semiconductor pattern ACT2 may be spaced apart from the first semiconductor pattern ACT1 in the first direction DR1. The second semiconductor pattern ACT2 overlapping the first gate electrode GE1 may constitute the channel region of the tenth transistor T10. The second semiconductor pattern ACT2 overlapping the 1i-th scan line S1i may constitute the channel region of the eleventh transistor T11 (or the first and second sub-transistors T11-1 and T11-2).

[0259] The third semiconductor pattern ACT3 may be spaced apart from the second semiconductor pattern ACT2 in the second direction DR2. The third semiconductor pattern ACT3 overlapping the second gate electrode GE2 may constitute a channel region of the ninth transistor T9 (or the third and fourth sub-transistors T9-1 and T9-2).

[0260] The fourth semiconductor pattern ACT4 may be positioned to overlap the 3i-th scan line S3i and may constitute a channel region of the eighth transistor T8. To connect with other components, for example, to connect with the first transistor T1 through the fourteenth bridge pattern BRP14, the fourth semiconductor pattern ACT4 may include a portion ACT4a extending in a direction opposite to the second direction DR2.

[0261] The gate insulating layer GI may be positioned on the first to third semiconductor patterns ACT1, ACT2, and ACT3. The gate insulating layer GI may be an insulating layer made of an inorganic material.

[0262] The first capacitor electrode CE1 , the first gate electrode GE1 , the second gate electrode GE2 , the ith light emitting control line Ei, the ith scan line S1 i , and the ith scan line S3 i may be located on the gate insulating layer GI.

[0263] The first capacitor electrode CE1 overlapping the first semiconductor pattern ACT1 may constitute a gate electrode of the first transistor T1 .

[0264] The first gate electrode GE1 overlapping the second semiconductor pattern ACT2 may constitute a gate electrode of the tenth transistor T10 .

[0265] The second gate electrode GE2 overlapping the third semiconductor pattern ACT3 may constitute a gate electrode of the ninth transistor T9 .

[0266] In a plan view, the i-th light emitting control line Ei and the 1i-th scan line S1i may be spaced apart from each other with the first capacitor electrode CE1 interposed therebetween, and each of the i-th light emitting control line Ei and the 1i-th scan line S1i may extend in the first direction DR1. The 2i-th scan line S2i may be spaced apart from the i-th light emitting control line Ei and the 1i-th scan line S1i and may extend in the first direction DR1.

[0267] The i-th light emitting control line Ei overlapping the first semiconductor pattern ACT1 may constitute a gate electrode of the fifth transistor T5 and a gate electrode of the sixth transistor T6 .

[0268] The 1i-th scan line S1i overlapping the first semiconductor pattern ACT1 may constitute the gate electrode of the second transistor T2 and the gate electrode of the third transistor T3. Furthermore, the 1i-th scan line S1i overlapping the second semiconductor pattern ACT2 may constitute the gate electrode of the eleventh transistor T11. For the third transistor T3 and the fourth transistor T4, each of which is implemented as a dual-gate transistor, the 1i-th scan line S1i may include a portion protruding in a direction opposite to the second direction DR2.

[0269] The 3i scan line S3i overlapping the first semiconductor pattern ACT1 may form the gate electrode of the seventh transistor T7. The 3i scan line S3i overlapping the fourth semiconductor pattern ACT4 may form the gate electrode of the eighth transistor T8. The 2i scan line S2i overlapping the first semiconductor pattern ACT1 may form the gate electrode of the fourth transistor T4.

[0270] The interlayer insulating layer IL may be on the first capacitor electrode CE1, the first gate electrode GE1, the second gate electrode GE2, the i-th light emission control line Ei, the 1i-th scan line S1i, and the 3i-th scan line S3i. The interlayer insulating layer IL may be an insulating layer made of an inorganic material.

[0271] The zeroth bridge pattern BRP0 , the second capacitor electrode CE2 , and the reset control line RSTL may be located on the interlayer insulating layer IL.

[0272] The zeroth bridge pattern BRP0 may overlap the middle node of the third transistor T3. The zeroth bridge pattern BRP0 of the thirteenth pixel circuit PXC13 may include a portion (that is, the sixth capacitor electrode CE6) protruding toward the second semiconductor pattern ACT2 and may overlap the second semiconductor pattern ACT2 between the first sub-transistor T11-1 and the second sub-transistor T11-2. The portion of the zeroth bridge pattern BRP0 (that is, the sixth capacitor electrode CE6) and the second semiconductor pattern ACT2 overlapping with the portion may constitute the first capacitor C1. In other words, the sixth capacitor electrode CE6 constituting the first capacitor C1 may protrude toward the third transistor T3 to overlap the middle node of the third transistor T3.

[0273] The second capacitor electrode CE2 may overlap with the first capacitor electrode CE1 and may form a storage capacitor Cst. The second capacitor electrode CE2 may further include a portion protruding toward the third semiconductor pattern ACT3 (that is, a fifth capacitor electrode CE5 having a size smaller than that of the second capacitor electrode CE2). The portion of the second capacitor electrode CE2 (that is, the fifth capacitor electrode CE5) may overlap with the third semiconductor pattern ACT3 between the third sub-transistor T9-1 and the fourth sub-transistor T9-2 and may constitute the second capacitor C2. That is, the second capacitor electrode CE2 of the storage capacitor Cst and the fifth capacitor electrode CE5 of the second capacitor C2 may be formed integrally.

[0274] The reset control line RSTL and the third power line PL3 may be spaced apart from each other in the second direction DR2 , and each of the reset control line RSTL and the third power line PL3 may extend in the first direction DR1 .

[0275] The first insulating layer INS1 may be positioned on the zeroth bridge pattern BRP0, the second capacitor electrode CE2, and the reset control line RSTL. The first insulating layer INS1 may be an insulating film made of an inorganic material.

[0276] The first power line PL1 , the third vertical power line PL3_V, and the bridge patterns BRP11 to BRP19 may be located on the first insulating layer INS1 .

[0277] The first power line PL1 may extend substantially in the second direction DR2 and may be connected to the second capacitor electrode CE2 and the zeroth bridge pattern BRPO through the contact hole.

[0278] The third vertical power line PL3_V may extend substantially in the second direction DR2 and may be connected to the first semiconductor pattern ACT1 constituting one electrode of the seventh transistor T7 and the third power line PL3 through a contact hole.

[0279] The eleventh bridge pattern BRP11 may overlap the fourth semiconductor pattern ACT4 and may be connected to the fourth semiconductor pattern ACT4 through a contact hole. The eleventh bridge pattern BRP11 may connect the fifth power line PL5 and the fourth semiconductor pattern ACT4 constituting the eighth transistor T8.

[0280] The twelfth bridge pattern BRP12 may overlap the first semiconductor pattern ACT1 constituting one electrode of the second transistor T2 and may be connected to the first semiconductor pattern ACT1 through a contact hole. The twelfth bridge pattern BRP12 may connect the j-th data line Dj and the first semiconductor pattern ACT1 constituting one electrode of the second transistor T2.

[0281] The thirteenth bridge pattern BRP13 may be connected to the first capacitor electrode CE1 through the opening and the contact hole of the second capacitor electrode CE2, and may be connected to the first semiconductor pattern ACT1 through the contact hole between the third transistor T3 and the fourth transistor T4. The thirteenth bridge pattern BRP13 may connect the node between the third transistor T3 and the fourth transistor T4 to the first capacitor electrode CE1.

[0282] The fourteenth bridge pattern BRP14 may be connected to the first semiconductor pattern ACT1 constituting one electrode of the first transistor T1 through a contact hole and may be connected to the fourth semiconductor pattern ACT4 (or portion ACT4a) through a contact hole. The fourteenth bridge pattern BRP14 may connect the eighth transistor T8 to one electrode of the first transistor T1.

[0283] The fifteenth bridge pattern BRP15 may be connected to the first semiconductor pattern ACT1 constituting one electrode of the sixth transistor T6 through the contact hole. The fifteenth bridge pattern BRP15 may connect the sixth transistor T6 to the pixel layer.

[0284] The sixteenth bridge pattern BRP16 may be connected to the second gate electrode GE2 through a contact hole and may be connected to the reset control line RSTL through a contact hole. The sixteenth bridge pattern BRP16 may connect the second gate electrode GE2 of the ninth transistor T9 and the reset control line RSTL.

[0285] The seventeenth bridge pattern BRP17 may be connected to the third semiconductor pattern ACT3 through the contact hole. The seventeenth bridge pattern BRP17 may connect the third semiconductor pattern ACT3 constituting the ninth transistor T9 to the third power line PL3.

[0286] The eighteenth bridge pattern BRP18 may be connected to the first gate electrode GE1 through a contact hole and may be connected to the third semiconductor pattern ACT3 through a contact hole. The eighteenth bridge pattern BRP18 may connect the third semiconductor pattern ACT3 constituting the ninth transistor T9 and the first gate electrode GE1 of the tenth transistor T10.

[0287] The nineteenth bridge pattern BRP19 may be connected to the second semiconductor pattern ACT2 constituting one electrode of the eleventh transistor T11 through a contact hole. The nineteenth bridge pattern BRP19 may connect the eleventh transistor T11 and the k-th readout line RXk.

[0288] The second insulating layer INS2 may be positioned on the first power line PL1, the third vertical power line PL3_V, and the bridge patterns BRP11 to BRP19. The second insulating layer INS2 may be an insulating layer made of an inorganic material.

[0289] The first horizontal power line PL1_H, the third power line PL3 , the fourth power line PL4 , the fifth power line PL5 , and the bridge patterns BRP21 to BRP24 may be located on the second insulating layer INS2 .

[0290] The first to fifth horizontal power lines PL1_H, PL3, PL4, and PL5 may be spaced apart from each other in the second direction DR2, and each of the first to fifth horizontal power lines PL1_H, PL3, PL4, and PL5 may extend substantially in the first direction DR1.

[0291] The first horizontal power line PL1_H may be connected to the first power line PL1 through a contact hole.

[0292] The third power line PL3 may be connected to the third vertical power line PL3_V through a contact hole.

[0293] The fourth power line PL4 may be connected to the third semiconductor pattern ACT3 constituting the first electrode of the ninth transistor T9 through a contact hole.

[0294] The fifth power line PL5 may have a partially meandering shape to bypass the twenty-third bridge pattern BRP23 and may be connected to the eleventh bridge pattern BRP11 through a contact hole.

[0295] The twenty-first bridge pattern BRP21 may be connected to the twelfth bridge pattern BRP12 through a contact hole. The twenty-first bridge pattern BRP21 may connect the twelfth bridge pattern BRP12 and the j-th data line Dj.

[0296] The twenty-second bridge pattern BRP22 may be connected to the fifteenth bridge pattern BRP15 through a contact hole. The twenty-second bridge pattern BRP22 may be connected to the fifteenth bridge pattern BRP15 and the thirty-first bridge pattern BRP31 (or the light emitting element LED of the pixel layer).

[0297] The twenty-third bridge pattern BRP23 may be connected to the eighteenth bridge pattern BRP18 through a contact hole. The twenty-third bridge pattern BRP23 may connect the eighteenth bridge pattern BRP18 and the thirty-second bridge pattern BRP32 (or the light receiving element LRD of the pixel layer).

[0298] The twenty-fourth bridge pattern BRP24 may be connected to the nineteenth bridge pattern BRP19 through a contact hole. The twenty-fourth bridge pattern BRP24 may be connected to the nineteenth bridge pattern BRP19 and the k-th readout line RXk.

[0299] The third insulating layer INS3 may be on the first horizontal power line PL1_H, the third power line PL3, the fourth power line PL4, the fifth power line PL5, and the bridge patterns BRP21 to BRP24. The third insulating layer INS3 may be an insulating layer made of an inorganic material or an organic material.

[0300] The j-th data line Dj, the k-th readout line RXk, the thirty-first bridge pattern BRP31 , and the thirty-second bridge pattern BRP32 may be located on the third insulating layer INS3 .

[0301] The j-th data line Dj and the k-th readout line RXk may be spaced apart from each other in the first direction DR1 , and each of the j-th data line Dj and the k-th readout line RXk may substantially extend in the second direction DR2 .

[0302] The fourth insulating layer INS4 may be located on the jth data line Dj, the kth readout line RXk, the 31st bridge pattern BRP31, and the 32nd bridge pattern BRP32. The fourth insulating layer INS4 may be an insulating layer made of an organic material and / or an inorganic material. The fourth insulating layer INS4 may serve as a planarization layer.

[0303] refer to Figure 8 The described pixel layer may be disposed on the fourth insulating layer INS4 .

[0304] As described above, the sixth capacitor electrode CE6 may be located on a portion (e.g., a region doped with impurities) of the second semiconductor pattern ACT2 between the channel region of the first sub-transistor T11-1 and the channel region of the second sub-transistor T11-2, and the sixth capacitor electrode CE6 may be connected to the first power line PL1. The sixth capacitor electrode CE6 and this portion of the second semiconductor pattern ACT2 may form the first capacitor C1. Therefore, current leakage through the eleventh transistor T11 may be reduced or minimized.

[0305] Furthermore, a fifth capacitor electrode CE5 may be located on a portion (e.g., a region doped with impurities) of the third semiconductor pattern ACT3 between the channel region of the third sub-transistor T9-1 and the channel region of the fourth sub-transistor T9-2, and the fifth capacitor electrode CE5 may be connected to the first power line PL1 via the second capacitor electrode CE2. The fifth capacitor electrode CE5 and the portion of the third semiconductor pattern ACT3 may form a second capacitor C2. Therefore, current leakage through the ninth transistor T9 may be reduced or minimized, and the accuracy of sensing using the photosensor PHS including the sensor circuit SC may be improved.

[0306] At the same time, Figures 13 to 15 , the sensor circuit SC is shown as including a ninth transistor T9 and an eleventh transistor T11, each of which is a dual-gate transistor, and a first capacitor C1 and a second capacitor C2, but is not limited thereto. For example, the sensor circuit SC may include only one of the ninth transistor T9 and the eleventh transistor T11 as a dual-gate transistor, and may include only the first capacitor C1 or the second capacitor C2 connected to the dual-gate transistor.

[0307] Figure 16A and Figure 16B Shown Figure 14C A top view of one or more embodiments of region CC.

[0308] refer to Figure 4 、 Figure 5 、 Figure 15 、 Figure 16A and Figure 16B, the shape of the second semiconductor pattern ACT2 and the shape of the third semiconductor pattern ACT3 may be variously modified.

[0309] For example, with the corresponding Figure 14B Compared to one or more embodiments of Figure 16A As shown in FIG, the second semiconductor pattern ACT2 may not include a portion protruding or extending in the opposite direction of the second direction DR2 between the channel region of the first sub-transistor T11-1 and the channel region of the second sub-transistor T11-2. Figure 14B Compared to one or more embodiments of Figure 16B As shown in FIG, the second semiconductor pattern ACT2 may include a portion that protrudes or extends more in the opposite direction of the second direction DR2 between the channel region of the first sub-transistor T11-1 and the channel region of the second sub-transistor T11-2. That is, the capacitance of the first capacitor C1 can be adjusted by increasing or decreasing the portion of the second semiconductor pattern ACT2.

[0310] For example, with the corresponding Figure 14B Compared to one or more embodiments of Figure 16A As shown in FIG, the third semiconductor pattern ACT3 may not include a portion protruding or extending in the opposite direction of the first direction DR1 between the channel region of the third sub-transistor T9-1 and the channel region of the fourth sub-transistor T9-2. As another example, Figure 14B Compared to one or more embodiments of Figure 16B As shown in FIG, the third semiconductor pattern ACT3 may include a portion that protrudes or extends more in the opposite direction of the first direction DR1 between the channel region of the third sub-transistor T9-1 and the channel region of the fourth sub-transistor T9-2. That is, the capacitance of the second capacitor C2 can be adjusted by increasing or decreasing the portion of the third semiconductor pattern ACT3.

[0311] At the same time, reference has been made Figure 16A and Figure 16B While the protrusions of the second semiconductor pattern ACT2 and / or the third semiconductor pattern ACT3 have been described as being adjusted, the present disclosure is not limited thereto. For example, the capacitance of the first capacitor C1 can be adjusted by adjusting the area or shape of the sixth capacitor electrode CE6 that overlaps with the second semiconductor pattern ACT2. Similarly, the capacitance of the second capacitor C2 can be adjusted by adjusting the area or shape of the fifth capacitor electrode CE5 that overlaps with the third semiconductor pattern ACT3.

[0312] Figure 17 Shown included in Figure 4 Circuit diagrams of one or more other embodiments of pixels and photosensors in a display area.

[0313] refer to Figure 13 and Figure 17 , except for the sixth power line PL6 and the seventh power line PL7, Figure 17 The sensor circuit SC (and pixel circuit PXC) can be basically the same as Figure 13 The sensor circuit SC (and pixel circuit PXC) are the same or similar. Therefore, redundant descriptions will not be repeated.

[0314] The first capacitor C1 may be connected to the sixth power line PL6 , and the second capacitor C2 may be connected to the seventh power line PL7 .

[0315] In some embodiments, the second capacitor C2 and the first capacitor C1 may be connected to the same constant voltage wiring or other constant voltage wirings.

[0316] For example, the sixth power line PL6 and the seventh power line PL7 may be electrically connected or integrally formed. Figure 5 、 Figure 10 and Figure 12 As described above, the first capacitor C1 can be connected to the third power line PL3, the fourth power line PL4, or the fifth power line PL5, and similarly to the first capacitor C1, the second capacitor C2 can be connected to the third power line PL3, the fourth power line PL4, or the fifth power line PL5. That is, the sixth power line PL6 and the seventh power line PL7 can be connected to the third power line PL3, the fourth power line PL4, or the fifth power line PL5, or can be formed integrally with the third power line PL3, the fourth power line PL4, or the fifth power line PL5.

[0317] As another example, the sixth power line PL6 and the seventh power line PL7 may be electrically separated. Figure 5 、 Figure 10 、 Figure 12 and Figure 13 As described, the first capacitor C1 can be connected to one of the first power line PL1, the third power line PL3, the fourth power line PL4 and the fifth power line PL5, and the second capacitor C2 can be connected to another one of the first power line PL1, the third power line PL3, the fourth power line PL4 and the fifth power line PL5.

[0318] That is, the constant voltage wiring to which the first capacitor C1 and the second capacitor C2 are connected is not limited to a specific wiring.

[0319] Figure 18 A block diagram of an electronic device according to an embodiment is shown. Figure 19 Shown Figure 18 An example where the electronic device is implemented as a smart phone. Figure 20 Shown Figure 18 The electronic device is implemented as an example of a tablet PC.

[0320] refer to Figures 18 to 20 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output device 1040, a power supply 1050, and a display device 1060. In this case, the display device 1060 may be Figure 1 In addition, the electronic device 1000 may also include some ports that can communicate with video cards, sound cards, memory cards, USB devices, etc. or communicate with other systems. Figure 19 As shown in FIG, the electronic device 1000 may be implemented as a smart phone. In one or more other embodiments, as Figure 20 As shown in FIG, the electronic device 1000 may be implemented as a tablet PC. However, this is an example, and the electronic device 1000 is not limited thereto. For example, the electronic device 1000 may be implemented as a mobile phone, a video phone, a smart pad, a smart watch, a car navigation, a computer monitor, a laptop computer, a head-mounted display device, etc.

[0321] The processor 1010 can perform corresponding calculations or tasks. In some embodiments, the processor 1010 can be a microprocessor, a central processing unit, an application processor, etc. The processor 1010 can be connected to other components via an address bus, a control bus, and a data bus. In some embodiments, the processor 1010 can also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0322] The memory device 1020 may store data required for the operation of the electronic device 1000. For example, the memory device 1020 may include a non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device, and / or a volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device.

[0323] The storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, or the like.

[0324] The input / output device 1040 may include input devices such as a keyboard, keypad, touchpad, touch screen, mouse, etc. and output devices such as speakers, printers, etc. In some embodiments, the display device 1060 may be included in the input / output device 1040 .

[0325] The power supply 1050 (or power supply device) may provide power required for the operation of the electronic device 1000. For example, the power supply 1050 may be a power management integrated circuit (PMIC).

[0326] The display device 1060 can display an image corresponding to the visual information of the electronic device 1000. In this case, the display device 1060 can be an organic light-emitting display device or a quantum dot light-emitting display device, but is not limited thereto. The display device 1060 can be connected to other components via a bus or other communication links.

[0327] The technical ideas of the present disclosure have been specifically described according to the preferred embodiments, but it should be noted that the above embodiments are provided only for illustration and not for limitation. In addition, it will be understood by those skilled in the art that various changes in form and details may be made herein without departing from the scope of the present disclosure.

Claims

1. A display device comprising: Pixels, including light-emitting elements; as well as Photoelectric sensors, including: a light receiving element at the same layer as the light emitting element; a first sensor transistor configured to control a current flowing to a readout line in response to a voltage of one electrode of the light receiving element; a second sensor transistor electrically connected between the first sensor transistor and the readout line and including a first sub-transistor and a second sub-transistor connected in series; and A first capacitor is provided between a first intermediate node to which the first sub-transistor and the second sub-transistor are connected and a power supply line.

2. The display device according to claim 1, wherein A constant voltage is configured to be applied to the power line.

3. The display device according to claim 1, wherein The pixel further includes a switching transistor electrically connected between the power line and the anode electrode of the light emitting element.

4. The display device according to claim 1, wherein The pixel further comprises: a first transistor electrically connected between a first power supply line and the light emitting element; and a second transistor electrically connected between the data line and the first transistor, and The gate electrode of the second transistor and the gate electrode of the second sensor transistor are electrically connected to the first scan line.

5. The display device according to claim 1, wherein In the cross-sectional view, the photoelectric sensor further includes: semiconductor layers of the first sub-transistor and the second sub-transistor; a gate electrode, above the semiconductor layer; an insulating layer covering the gate electrode; a capacitor electrode over the insulating layer; and at least one insulating layer, above said capacitor electrode, wherein the power line is above the at least one insulating layer and contacts the capacitor electrode through a contact hole, and The first capacitor includes the capacitor electrode and the semiconductor layer. The display device according to claim 5 , wherein: In a plan view, the power supply line extends in a first direction between the first sensor transistor and the second sensor transistor, and partially protrudes in a second direction to overlap with the capacitor electrode.

7. The display device according to claim 1, wherein The photosensor further includes a third sensor transistor electrically connected between a reference power supply line and the one electrode of the light receiving element.

8. The display device according to claim 7, wherein: The first sensor transistor and the second sensor transistor include a silicon semiconductor, and Wherein, the third sensor transistor includes an oxide semiconductor.

9. The display device according to claim 7, wherein: One electrode of the first sensor transistor is electrically connected to the power supply line, and The power line and the reference power line are configured to receive different voltages.

10. The display device according to claim 7, wherein: The power line and the reference power line are configured to receive the same voltage.

11. The display device according to claim 1, wherein The light emitting element is electrically connected between the first power line and the second power line, and Wherein, the power line is configured to receive the same voltage as the first power line.

12. The display device according to claim 1, wherein The photoelectric sensor further comprises: a third sensor transistor electrically connected between a reference power supply line and the one electrode of the light receiving element and including a third sub-transistor and a fourth sub-transistor connected in series; and A second capacitor is provided between a second intermediate node to which the third sub-transistor and the fourth sub-transistor are connected and a first power supply line.

13. The display device according to claim 12, wherein: The power line and the first power line are configured to receive the same constant voltage.

14. The display device according to claim 13, wherein: The pixel further comprises: a first transistor connected between the first power line and the light emitting element; and a storage capacitor electrically connected between the gate electrode of the first transistor and the first power supply line, and One electrode of the second capacitor is integrated with one electrode of the storage capacitor.

15. The display device according to claim 14, wherein The one electrode of the storage capacitor overlaps the first semiconductor pattern of the first transistor in a plan view, and The one electrode of the second capacitor has a size smaller than that of the one electrode of the storage capacitor and protrudes from the one electrode of the storage capacitor to overlap with the third semiconductor pattern of the third sensor transistor.

16. The display device according to claim 14, wherein: The pixel further includes a third transistor electrically connected between one electrode of the first transistor and the gate electrode, and In a plan view, one electrode of the first capacitor overlaps with the second semiconductor pattern of the second sensor transistor and protrudes toward the third transistor to overlap with a middle node of the third transistor.

17. A display device comprising: Pixels, including light-emitting elements; as well as Photoelectric sensors, including: a light receiving element at the same layer as the light emitting element; a first sensor transistor configured to control a current flowing to a readout line in response to a voltage of one electrode of the light receiving element; a second sensor transistor electrically connected between the first sensor transistor and the readout line; a third sensor transistor electrically connected between a reference power supply line and the one electrode of the light receiving element and including a third sub-transistor and a fourth sub-transistor connected in series; and A second capacitor is provided between a second intermediate node to which the third sub-transistor and the fourth sub-transistor are connected and a first power supply line.

18. The display device according to claim 17, wherein: The reference power line and the first power line are configured to receive the same constant voltage.

19. The display device according to claim 17, wherein: The pixel further comprises: a first transistor connected between the first power line and the light emitting element; and a storage capacitor electrically connected between the gate electrode of the first transistor and the first power supply line, and One electrode of the second capacitor is integrated with one electrode of the storage capacitor.

20. Electronic devices, including: a processor configured to provide input image data to a display device, the display device configured to display an image based on the input image data; as well as a power supply configured to provide power to the display device, Wherein, the display device includes: Pixels, including light-emitting elements; and A photosensor including a light receiving element at the same layer as the light emitting element, and further comprising: a first sensor transistor configured to control a current flowing to a readout line in response to a voltage of one electrode of the light receiving element; a second sensor transistor electrically connected between the first sensor transistor and the readout line and including a first sub-transistor and a second sub-transistor connected in series; and A first capacitor is provided between a first intermediate node to which the first sub-transistor and the second sub-transistor are connected and a power supply line.

Images