Light detection device and electronic apparatus

Abstract

[Problem] To obtain high resolution and improve image quality of a captured image. [Solution] This light detection device is equipped with a shared second pixel circuit shared by two or more first pixel circuits. A second pixel circuit is provided with: a first capacitance element that holds a voltage signal output from a corresponding pixel in a state in which a charge of a first floating diffusion region of the pixel has been initialized; a second capacitance element that holds a voltage signal output from the pixel in a state in which the accumulated charge of the photoelectric conversion element has been transferred to the first floating diffusion region of the corresponding pixel; a first transistor switching whether to transfer the charge held in the first capacitive element to a second floating diffusion region shared by the two or more first pixel circuits; and a second transistor switching whether to transfer the charge held in the second capacitive element to the second floating diffusion region, two or more first transistors and two or more second transistors included in the two or more first pixel circuits are arranged around one third transistor in a point-symmetric or line-symmetric manner.

Description

Technical Field

[0001] The present disclosure relates to a light detection device and an electronic device. Background Art

[0002] Imaging devices that use a rolling shutter method, in which exposure times are staggered by pixel row, suffer from the problem of distorted images of moving objects in captured images. To address this issue, imaging devices that use a global shutter method, in which all pixels begin exposure simultaneously, have been proposed (see Patent Document 1).

[0003] [Citation List]

[0004] [Patent Document]

[0005] [Patent Document 1] WO 2021 / 215105 Summary of the Invention

[0006] [Technical Issues]

[0007] Because the global shutter method requires each pixel to be equipped with a charge retention unit to hold the accumulated charge of its photoelectric conversion element, the increased pixel size has become an obstacle to improving resolution. Furthermore, innovation is needed to ensure that the charge retention unit is not affected by noise when holding the accumulated charge of the photoelectric conversion element.

[0008] In view of this, the present disclosure provides a light detection device and an electronic device, which can achieve higher resolution and improve the image quality of captured images.

[0009] [Solution to the problem]

[0010] In order to solve the above-mentioned problem, the present disclosure provides a light detection device including: a plurality of pixels, each pixel having a photoelectric conversion element configured to accumulate charges according to an amount of incident light;

[0011] a plurality of first pixel circuits configured to hold voltage signals according to charges accumulated in the plurality of pixels at the same timing;

[0012] a plurality of second pixel circuits shared by every two or more first pixel circuits among the plurality of first pixel circuits and configured to sequentially read out voltage signals held by the two or more first pixel circuits and generate pixel signals; and

[0013] a logic circuit configured to perform signal processing on a plurality of pixel signals generated by the plurality of second pixel circuits, wherein

[0014] Each of the plurality of first pixel circuits comprises:

[0015] a first capacitive element configured to hold a voltage signal output from a pixel in a state in which the charge of the first floating diffusion region of the corresponding pixel has been initialized;

[0016] a second capacitance element configured to hold a voltage signal output from a pixel in a state in which the accumulated charge of the photoelectric conversion element has been transferred to the first floating diffusion region of the corresponding pixel;

[0017] a first transistor configured to switch whether to transfer the charge held in the first capacitance element to a second floating diffusion region shared by the two or more first pixel circuits; and

[0018] a second transistor configured to switch whether to transfer the charge held in the second capacitance element to the second floating diffusion region,

[0019] Each of the plurality of second pixel circuits includes a source follower circuit having a third transistor configured to generate a pixel signal according to the charge of the second floating diffusion region, and

[0020] The two or more first transistors and the two or more second transistors included in the two or more first pixel circuits are arranged around one third transistor in a point-symmetrical or line-symmetrical manner.

[0021] A unit pixel group area may be provided having two or more first pixel circuits and one second pixel circuit for every two or more pixels, wherein the unit pixel group area may have a third transistor and the two or more first transistors and the two or more second transistors configured in a point-symmetrical or line-symmetrical manner relative to the third transistor.

[0022] The third transistor may be arranged in a central portion of the unit pixel group region, and each gate of the two or more first transistors and the two or more second transistors may be arranged at an equal distance from the gate of the third transistor.

[0023] A gate length direction of the third transistor disposed in the unit pixel group region and gate length directions of the two or more first transistors and the two or more second transistors may be parallel to each other.

[0024] A gate length direction of the third transistor disposed in the unit pixel group region may intersect with gate length directions of the two or more first transistors and the two or more second transistors.

[0025] The unit pixel group area may be a rectangular area arranged in a first direction and a second direction intersecting the first direction.

[0026] The unit pixel group area may include:

[0027] a first region, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along a first direction; and

[0028] a second region arranged apart from the first region in the second direction, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along the first direction;

[0029] The third transistor is arranged between the first region and the second region which are arranged to be separated from each other in the second direction, and

[0030] A gate length direction of the first transistor, the second transistor, and the third transistor is a first direction.

[0031] Each of the plurality of second pixel circuits may include:

[0032] a fourth transistor configured to output a pixel signal to a signal line; and

[0033] a fifth transistor configured to switch whether to initialize the charge in the second floating diffusion region, and

[0034] The unit pixel group area may include:

[0035] a third region in which the fourth transistor, the third transistor, and the fifth transistor are arranged on one axis along the first direction, and

[0036] The third region is arranged between the first region and the second region which are arranged to be separated from each other in the second direction.

[0037] Each of the plurality of first pixel circuits may include a sixth transistor and a seventh transistor configured to precharge the first capacitance element and the second capacitance element,

[0038] The unit pixel group area may include:

[0039] a fourth region in which two or more sixth transistors and two or more seventh transistors are arranged on one axis along the first direction; and

[0040] a fifth region arranged apart from the fourth region in the second direction, wherein two or more sixth transistors and two or more seventh transistors are arranged on one axis along the first direction, and

[0041] The fourth region is arranged between the fourth region and the fifth region which are arranged to be separated from each other in the second direction.

[0042] The unit pixel group area may be a rectangular area arranged in a first direction and a second direction intersecting the first direction.

[0043] The unit pixel group area may include:

[0044] a first region, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along a second direction; and

[0045] a second region arranged apart from the first region in the first direction, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along the second direction;

[0046] The third transistor is arranged between the first region and the second region which are arranged to be separated from each other in the first direction.

[0047] The channels of the first transistor and the second transistor extend in the second direction, and

[0048] A channel of the third transistor extends in the first direction.

[0049] The diffusion layers of the third transistor may be arranged on both sides of the channel of the third transistor in the second direction.

[0050] Each of the plurality of second pixel circuits may include:

[0051] a fourth transistor configured to output a pixel signal to a signal line; and

[0052] a fifth transistor configured to switch whether to initialize the charge in the second floating diffusion region,

[0053] The unit pixel group area is a rectangular area arranged in a first direction and a second direction intersecting the first direction.

[0054] The unit pixel group area may include:

[0055] a first region, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along a second direction;

[0056] a second region arranged apart from the first region in the first direction, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along the first direction; and

[0057] a third region in which the fourth transistor, the third transistor, and the fifth transistor are arranged along the first direction, and

[0058] The third region is configured to separate the first region and the second region, which are spaced apart from each other in the first direction, at a central portion of the unit pixel group region in the second direction.

[0059] Each of the plurality of first pixel circuits may include a sixth transistor and a seventh transistor configured to precharge the first capacitance element and the second capacitance element,

[0060] Each of the plurality of second pixel circuits may include:

[0061] a fourth transistor configured to output a pixel signal to a signal line; and

[0062] a fifth transistor configured to switch whether to initialize the charge in the second floating diffusion region,

[0063] The unit pixel group area is a rectangular area arranged in a first direction and a second direction intersecting the first direction.

[0064] The unit pixel group area may include:

[0065] a first region, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along a second direction;

[0066] a second region arranged apart from the first region in the first direction, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along the first direction;

[0067] a third region, wherein the fourth transistor, the third transistor, and the fifth transistor are arranged along the first direction;

[0068] a fourth region in which two or more sixth transistors and two or more seventh transistors are arranged along the first direction; and

[0069] a fifth region arranged apart from the fourth region in the second direction, wherein two or more sixth transistors and two or more seventh transistors are arranged along the first direction, and

[0070] The third region is arranged between the fourth region and the fifth region, which are arranged to be separated from each other in the second direction.

[0071] The size of the third transistor may be larger than that of the first transistor and the second transistor.

[0072] The unit pixel group region may include a plurality of third transistors arranged in a central portion, and the two or more first transistors and the two or more second transistors arranged in a point-symmetric or line-symmetric manner with respect to the plurality of third transistors.

[0073] The unit pixel group area may include two first pixel circuits in each of the first direction and the second direction, and include one second pixel circuit, and the unit pixel group area may have two first transistors and two second transistors configured in a point-symmetrical or line-symmetrical manner with respect to the third transistor in the central portion.

[0074] The unit pixel group region may include one first pixel circuit in the first direction, two first pixel circuits in the second direction, and one second pixel circuit, and

[0075] The two unit pixel group regions arranged in the first direction may include two first transistors and two second transistors arranged in a point-symmetrical or line-symmetrical manner with respect to the two third transistors in the center.

[0076] A first substrate may be provided on which the plurality of pixels are arranged; and

[0077] The second substrate is stacked on the first substrate and has the plurality of first pixel circuits, the plurality of second pixel circuits, and the logic circuit arranged thereon.

[0078] A first substrate may be provided on which the plurality of pixels are arranged.

[0079] a second substrate stacked on the first substrate and having the plurality of first pixel circuits and the plurality of second pixel circuits arranged thereon, and

[0080] A third substrate is stacked on the second substrate and has the logic circuit configured thereon, wherein

[0081] The first substrate has a plurality of first metal pads arranged opposite to the second substrate and connected to the output nodes of the plurality of pixels.

[0082] The second substrate has

[0083] a semiconductor layer disposed opposite to the third substrate,

[0084] a plurality of second metal pads bonded to the plurality of first metal pads,

[0085] a plurality of first via holes configured to pass through the semiconductor layer from the plurality of second pixel circuits, and

[0086] a plurality of third metal pads configured to be opposite to the third substrate and connected to the plurality of first vias,

[0087] The third substrate has a plurality of fourth metal pads bonded to the third metal pads, and

[0088] Each of the plurality of first via holes is arranged for every two or more pixels.

[0089] Each of the plurality of pixels may have

[0090] a third capacitance element configured to accumulate a portion of the accumulated charge of the photoelectric conversion element;

[0091] an eighth transistor configured to switch whether to accumulate a portion of the accumulated charge of the photoelectric conversion element in a third capacitance element; and

[0092] A ninth transistor is configured to switch whether to discard the accumulated charge of the photoelectric conversion element.

[0093] The present disclosure provides an electronic device, comprising:

[0094] a light detection device configured to generate an image according to an amount of incident light; and

[0095] a processing unit configured to process the image, wherein

[0096] The light detection device comprises:

[0097] a plurality of pixels each having a photoelectric conversion element configured to accumulate charge according to an amount of incident light;

[0098] a plurality of first pixel circuits configured to hold voltage signals according to charges accumulated in the plurality of pixels at the same timing;

[0099] a plurality of second pixel circuits shared by every two or more first pixel circuits among the plurality of first pixel circuits and configured to sequentially read out voltage signals held by the two or more first pixel circuits and generate pixel signals; and

[0100] a logic circuit configured to perform signal processing on a plurality of pixel signals generated by the plurality of second pixel circuits, wherein

[0101] Each of the plurality of first pixel circuits comprises:

[0102] a first capacitive element configured to hold a voltage signal output from a pixel in a state in which the charge of the first floating diffusion region of the corresponding pixel has been initialized;

[0103] a second capacitance element configured to hold a voltage signal output from a pixel in a state in which the accumulated charge of the photoelectric conversion element has been transferred to the first floating diffusion region of the corresponding pixel;

[0104] a first transistor configured to switch whether to transfer the charge held in the first capacitance element to a second floating diffusion region shared by the two or more first pixel circuits; and

[0105] a second transistor configured to switch whether to transfer the charge held in the second capacitance element to the second floating diffusion region,

[0106] Each of the plurality of second pixel circuits includes a source follower circuit having a third transistor configured to generate a pixel signal according to the charge of the second floating diffusion region, and

[0107] The two or more first transistors and the two or more second transistors included in the two or more first pixel circuits are arranged around one third transistor in a point-symmetrical or line-symmetrical manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0108] Figure 1 is a block diagram of an electronic device according to a first embodiment of the present disclosure.

[0109] Figure 2 is a block diagram showing a schematic configuration of a light detecting device according to the embodiment.

[0110] Figure 3 This is a circuit diagram of pixels and pixel circuits in a pixel array section.

[0111] Figure 4 is a circuit diagram showing an example in which four pixels and four first pixel circuits share one second pixel circuit.

[0112] Figure 5 is a cross-sectional view showing a cross-sectional structure of a light detecting device according to the embodiment.

[0113] Figure 6 is a cross-sectional view illustrating a first example of a cross-sectional structure of a peripheral circuit of a pixel.

[0114] Figure 7 is a cross-sectional view illustrating a second example of the cross-sectional structure of the peripheral circuit of the pixel.

[0115] Figure 8 FIG. 2 is a planar layout diagram of 2×2 pixels of the first substrate in the case where four pixels and four first pixel circuits share one second pixel circuit.

[0116] Figure 9 is layered on Figure 8 The plan layout of the 2×2 pixel unit pixel group area of ​​the second substrate on the first substrate is shown.

[0117] Figure 10 is based on Figure 9 A planar layout diagram of the second substrate of the first modified example.

[0118] Figure 11 is based on Figure 9 A planar layout diagram of the second substrate of the second variation example.

[0119] Figure 12 is based on Figure 9 A planar layout diagram of the second substrate of the third variation example.

[0120] Figure 13 is based on Figure 9 A planar layout diagram of the second substrate of the fourth variation example.

[0121] Figure 14 is based on Figure 9 A planar layout diagram of the second substrate of the fifth variation example.

[0122] Figure 15 is based on Figure 9 A planar layout diagram of the second substrate of the sixth variation example.

[0123] Figure 16 is based on Figure 9 A planar layout diagram of the second substrate of the seventh variation example.

[0124] Figure 17 is based on Figure 9 A planar layout diagram of the second substrate of the eighth variation example.

[0125] Figure 18 is based on Figure 9 A planar layout diagram of the second substrate of the ninth variation.

[0126] Figure 19 is based on Figure 9 A planar layout diagram of the second substrate of the tenth variation.

[0127] Figure 20 is based on Figure 9 A planar layout diagram of the second substrate of the eleventh variation.

[0128] Figure 21 is based on Figure 3 A circuit diagram of a pixel and a pixel circuit according to a modified example.

[0129] Figure 22 is based on Figure 21 The circuit configuration shown is a circuit diagram in which four pixels and four first pixels share one second pixel circuit.

[0130] Figure 23 is Figure 22 The pixel and pixel circuit shown are a planar layout diagram of a 4×4 pixel unit pixel group area of ​​the second substrate.

[0131] Figure 24 is based on Figure 23A planar layout diagram of the second substrate of the first modified example.

[0132] Figure 25 is based on Figure 23 A planar layout diagram of the second substrate of the second variation example.

[0133] Figure 26 is based on Figure 23 A planar layout diagram of the second substrate of the third variation example.

[0134] Figure 27 is based on Figure 23 A planar layout diagram of the second substrate of the fourth variation example.

[0135] Figure 28 is based on Figure 23 A planar layout diagram of the second substrate of the fifth variation example.

[0136] Figure 29 is based on Figure 23 A planar layout diagram of the second substrate of the sixth variation example.

[0137] Figure 30 is based on Figure 23 A planar layout diagram of the second substrate of the seventh variation example.

[0138] Figure 31 Is used based on Figure 3 The circuit configuration shown is a circuit diagram of a pixel, a first pixel circuit, and a second pixel circuit in the case where two pixels and two first pixel circuits share one second pixel circuit.

[0139] Figure 32 is Figure 31 The illustrated pixel and pixel circuit are configured to form a planar layout diagram of an area of ​​the second substrate where two unit pixel groups of 1×2 pixels are arranged in the first direction X.

[0140] Figure 33 is based on Figure 32 A planar layout diagram of the second substrate of the first modified example.

[0141] Figure 34 is based on Figure 32 A planar layout diagram of the second substrate of the second variation example.

[0142] Figure 35 is based on Figure 32 A planar layout diagram of the second substrate of the third variation example.

[0143] Figure 36 is based on Figure 32 A planar layout diagram of the second substrate of the fourth variation example.

[0144] Figure 37 is based on Figure 32 A planar layout diagram of the second substrate of the fifth variation example.

[0145] Figure 38 is based on Figure 32 A planar layout diagram of the second substrate of the sixth variation example.

[0146] Figure 39 is based on Figure 32 A planar layout diagram of the second substrate of the seventh variation example.

[0147] Figure 40 Is used based on Figure 21 The circuit configuration shown is a circuit diagram of a pixel, a first pixel circuit, and a second pixel circuit in the case where two pixels and two first pixel circuits share one second pixel circuit.

[0148] Figure 41 is Figure 40 The pixel and pixel circuit shown are arranged in a planar layout of an area of ​​the second substrate where two unit pixel groups of 1×2 pixels are arranged.

[0149] Figure 42 is based on Figure 41 A planar layout diagram of the second substrate of the first modified example.

[0150] Figure 43 is based on Figure 41 A planar layout diagram of the second substrate of the second variation example.

[0151] Figure 44 is based on Figure 41 A planar layout diagram of the second substrate of the third variation example.

[0152] Figure 45 is based on Figure 41 A planar layout diagram of the second substrate of the fourth variation example.

[0153] Figure 46 is based on Figure 41 A planar layout diagram of the second substrate of the fifth variation example.

[0154] Figure 47 is based on Figure 41 A planar layout diagram of the second substrate of the sixth variation example.

[0155] Figure 48 is based on Figure 41 A planar layout diagram of the second substrate of the sixth variation example.

[0156] Figure 49FIG. 1 is a planar layout diagram illustrating an example of bonding positions of a first metal pad and a second metal pad and arrangement positions of TSVs on a second substrate.

[0157] Figure 50 is a circuit diagram of a pixel, a first pixel circuit, and a second pixel circuit according to a first modification example.

[0158] Figure 51 is a circuit diagram of a pixel, a first pixel circuit, and a second pixel circuit according to a second modification example.

[0159] Figure 52 is a circuit diagram of a pixel, a first pixel circuit, and a second pixel circuit according to a third modification example.

[0160] Figure 53 is a circuit diagram of a pixel, a first pixel circuit, and a second pixel circuit according to a fourth modification example.

[0161] Figure 54 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0162] Figure 55 1 and 2 are diagrams for assisting in explaining examples of installation positions of the vehicle exterior information detection unit and the imaging portion.

[0163] Figure 56 is a diagram showing an example of a schematic configuration of an endoscopic surgery system.

[0164] Figure 57 : is a block diagram showing an example of the functional configuration of a camera head and a camera control unit (CCU). DETAILED DESCRIPTION

[0165] Hereinafter, embodiments of a light detection device and an electronic device will be described with reference to the accompanying drawings. Although the following description focuses on the primary components of the light detection device and the electronic device, the light detection device or the electronic device may include other components and functions not shown or described. The following description does not exclude any components or functions not shown or described.

[0166] Figure 1 1 is a block diagram of an electronic device 1 according to a first embodiment of the present disclosure. The electronic device 1 is provided with a function of generating an image according to the brightness of incident light. Figure 1 The electronic device 1 includes an imaging lens 2, a light detection device 3, an image processing unit 4, a recording unit 5, and a control unit 6. Although the electronic device 1 can be applied to, for example, a surveillance camera, a camera mounted on an industrial robot, or a general-purpose camera, the specific use and specific configuration of the electronic device 1 are arbitrary.

[0167] Imaging lens 2 collects incident light and directs it to light detection device 3. Light detection device 3 captures the incident light. Light detection device 3 is equipped with a function to photoelectrically convert light within a predetermined wavelength range (such as visible light or infrared light) and generate a captured image. The captured image generated by light detection device 3 is transmitted to image processing unit 4 and recording unit 5.

[0168] The image processing section 4 performs predetermined image processing on the captured image, such as color or brightness adjustment, image compression, image recognition, tracking, or analysis. The image processed by the image processing section 4 is output to the recording section 5, for example.

[0169] The recording unit 5 records the image output from the light detection device 3 or the image processing unit 4. The recording unit 5 may be configured on a server or the like connected via a network. In the electronic device 1 according to this embodiment, the image processing unit 5 may be omitted. Figure 1 At least one of the image processing unit 4 and the recording unit 5.

[0170] The control section 6 controls the operation of the light detecting device 3. Figure 1 Although not explicitly shown, the control unit 6 can control the image processing unit 4 and the recording unit 5.

[0171] Figure 2 : is a block diagram showing a schematic configuration of the light detecting device 3 according to the embodiment. Figure 2 As shown, the light detection device 3 according to the present embodiment includes a pixel array section 11 , a vertical drive section 12 , a column signal processing section 13 , and a timing control section 14 .

[0172] The pixel array section 11 includes a plurality of pixels 15 arranged along a first direction (eg, row direction) X and a second direction (eg, vertical direction) Y. Figure 2 Although not shown in the figure, a pixel circuit is connected to each pixel 15. The detailed configuration of the pixel 15 and the pixel circuit will be described later.

[0173] The vertical drive section 12 sequentially selects and drives each of a plurality of pixel groups (e.g., pixel rows) arranged along the first direction X of the pixel array section 11. More specifically, a plurality of row selection lines L1 are connected to the vertical drive section 12. Each of the plurality of row selection lines L1 is used to drive a corresponding pixel row.

[0174] The vertical signal lines VSL are connected to each of a plurality of pixel groups (e.g., pixel columns) arranged along the second direction Y of the pixel array section 11. Each vertical signal line VSL transmits a pixel signal generated by a pixel circuit connected to each pixel 15. The plurality of vertical signal lines VSL are connected to the column signal processing section 13.

[0175] The column signal processing section 13 performs analog-to-digital conversion on the pixel signal transmitted by each vertical signal line VSL and generates a digital pixel signal. The column signal processing section 13 is controlled by a horizontal driving section (not shown) and sequentially outputs the digital pixel signal.

[0176] The timing control section 14 controls the timing of the vertical drive section 12 and the column signal processing section 13 .

[0177] As described later, the light detection device 3 according to this embodiment is constructed by stacking three semiconductor substrates (referred to as a first substrate, a second substrate, and a third substrate). Each pixel 15 and pixel circuit of the pixel array unit 11 is arranged so as to be separated between the first substrate and the second substrate. In this specification, the pixels 15 and pixel circuits are referred to as pixels 15 and pixel circuits, respectively, while those arranged on the first substrate are referred to as pixels 15 and those arranged on the second substrate are referred to as pixel circuits. However, the boundary between the pixels 15 and pixel circuits is not clearly defined, and in this specification, the pixels 15 and pixel circuits are collectively referred to as pixels 15.

[0178] Figure 3 1 is a circuit diagram of the pixels 15 and pixel circuits within the pixel array section 11. In this embodiment, a pixel sharing method is adopted in which a portion of the pixel circuit connected to the pixel 15 is shared by a plurality of pixels 15. In this specification, in the pixel circuit, the circuit portion provided for each pixel 15 is referred to as a first pixel circuit 16, and the circuit portion shared by a plurality of pixels 15 is referred to as a second pixel circuit 17.

[0179] like Figure 3 As shown, the pixel 15 has a photoelectric conversion element 21, a transfer transistor 22, a first reset transistor 23, a first amplifying transistor 25 constituting a first source follower circuit (SF1) 24, and a first selection transistor 26. Figure 3 An example is shown in which all transistors of the pixel 15 and the pixel circuit are composed of NMOS (N-channel metal oxide semiconductor) transistors, but at least a part of the transistors can be composed of PMOS (P-channel MOS) transistors.

[0180] The photoelectric conversion element 21 is, for example, a photodiode and accumulates electric charge according to the amount of incident light.

[0181] The photoelectric conversion elements 21 of all pixels 15 begin exposure at the same timing. The transfer transistors 22 of all pixels 15 transfer the accumulated charge in the photoelectric conversion elements 21 to the first floating diffusion region FD1. The first floating diffusion region FD1 is set to a reset state, where the charge has been discharged, or a state where the accumulated charge (in other words, signal charge) in the photoelectric conversion elements 21 has been transferred. When the TRG signal is at a high level, the transfer transistors 22 are turned on. As described above, the TRG signal of all pixels 15 transitions to a high level at the same timing.

[0182] Before the photoelectric conversion element 21 starts a photoelectric conversion operation (hereinafter, sometimes also referred to as an exposure operation), the first reset transistor 23 discharges the accumulated charge in the photoelectric conversion device 21 and the charge in the first floating diffusion region FD1. When the RST signal is at a high level, the first reset transistor 23 is turned on.

[0183] Despite Figure 3 In the embodiment, the conversion efficiency switching transistor 27 and the charge retention unit 28 are arranged between the first reset transistor 23 and the first floating diffusion region FD1, but the conversion efficiency switching transistor 27 and the charge retention unit 28 can be omitted. The charge retention unit 28 is connected between the drain of the conversion efficiency switching transistor 27 and a reference voltage node (e.g., a ground voltage node). By having the charge retention unit 28 retain a portion of the accumulated charge in the photoelectric conversion element 21 via the conversion efficiency switching transistor 27, a larger accumulated charge can be retained and the dynamic range can be extended. When the FDG signal is at a high level, the conversion efficiency switching transistor 27 is turned on, and the charge retention unit 28 retains the accumulated charge in the photoelectric conversion element 21.

[0184] The first amplifier transistor 25 constituting the first source follower circuit 24 generates a voltage signal according to the accumulated charge in the first floating diffusion region FD1 , and the voltage signal is transmitted to the first pixel circuit 16 when the first selection transistor 26 is turned on.

[0185] like Figure 3 As shown, the drain of the first amplifier transistor 25 can be connected to a power supply voltage node or a voltage switch 29. The voltage switch 29 switches and connects the drain of the first amplifier transistor 25 to either a first reference voltage node or a second reference voltage node. When a voltage signal corresponding to accumulated charge or reset charge caused by photoelectric conversion is held in a first capacitor or a second capacitor, described later, the voltage switch 29 selects the first reference voltage node, and when a pixel signal is read out from the second pixel circuit 17 to the vertical signal line VSL, the voltage switch 29 selects the second reference voltage node. The first reference voltage node has a higher voltage level than the second reference voltage node.

[0186] When the SW signal is high, the first selection transistor 26 is turned on. When the first selection transistor 26 is turned on, the voltage signal of the first floating diffusion region FD1 is sent to the first pixel circuit 16. In this specification, the source of the first selection transistor is referred to as the output node n1 of the pixel 15.

[0187] The pixel 15 may be provided with a drain transistor 30. When the OFG signal is at a high level, the drain transistor 30 is turned on and drains the charge overflowing from the photoelectric conversion element 21.

[0188] like Figure 3 As shown, the first pixel circuit 16 includes a first capacitance element 31 , a second capacitance element 32 , a first sampling transistor 33 , and a second sampling transistor 34 .

[0189] The first capacitance element 31 and the first sampling transistor 33 are connected in series between the output node n1 and the second floating diffusion region FD2 of the pixel 15. The second capacitance element 32 and the second sampling transistor 34 are connected in series between the output node n1 and the second floating diffusion region FD2 of the pixel 15.

[0190] When the first sampling transistor 33 is on, the first capacitor 31 holds the voltage signal indicating that the first floating diffusion region FD1 is in the reset state. When the SR signal is high, the first sampling transistor 33 is also on. When the second sampling transistor 34 is on, the second capacitor 32 holds the voltage signal indicating that signal charge has accumulated in the first floating diffusion region FD1. When the SD signal is high, the second sampling transistor 34 is also on.

[0191] The first capacitor element 31 and the second capacitor element 32 are formed by, for example, a MIM (metal-insulator-metal) structure. For example, by forming a concave-convex portion of a semiconductor layer and laminating a metal layer, an insulating layer, and a metal layer along the concave-convex surface, the first capacitor element 31 and the second capacitor element 32 having the MIM structure can be formed in a semiconductor process. By increasing the number of concave-convex portions, the surface area of ​​the metal layer can be increased, and the capacitance can be increased.

[0192] The first pixel circuit 16 has a current source connected between the output node n1 of the pixel 15 and a reference voltage node (for example, a ground voltage node). The current source can be composed of, for example, two transistors 35 and 36 connected in cascade. A control signal PC is input to the gate of a transistor, and a control signal VB is input to the gate of another transistor. When the control signal PC is at a high level, transistor 35 is turned on, and when the control signal VB is at a high level, transistor 36 is turned on. Transistors 35 and 36 are used to precharge the first capacitor element 31 and the second capacitor element 32. Precharging the first capacitor element 31 and the second capacitor element 32 can reduce noise.

[0193] As described above, in this embodiment, the second pixel circuit 17 as a part of the pixel circuit is shared by the plurality of pixels 15 and the plurality of first pixel circuits 16. The second pixel circuit 17 includes a second reset transistor 41, a second amplifying transistor 43 constituting a second source follower circuit 42, a second selection transistor 44, and a current source 45.

[0194] The second reset transistor 41 is disposed between the reference voltage node VREG and the second floating diffusion region FD2. When the RB signal is at a high level, the second reset transistor 41 is turned on and initializes the charge of the second floating diffusion region FD2.

[0195] The second amplifying transistor 43 constituting the second source follower circuit 42 has a gate connected to the second floating diffusion region FD2, a drain connected to the reference voltage node VDD, and a source connected to the drain of the second selection transistor 44. The second source follower circuit 42 generates a pixel signal according to the voltage level of the second floating diffusion region FD2 and supplies the pixel signal to the second selection transistor 44.

[0196] When the SEL signal is at a high level, the second selection transistor 44 is turned on and outputs the pixel signal generated by the second source follower circuit 42 to the vertical signal line VSL. Figure 1 The row selection lines of the vertical drive section 12 are shown.

[0197] Figure 4 1 is a circuit diagram showing an example in which four pixels 15 and four first pixel circuits 16 share one second pixel circuit 17 . Figure 4 An example is shown in which the second pixel circuit 17 is shared by a total of four pixels 15, including two pixels 15 in the first direction X (row direction) and two pixels 15 in the second direction Y (vertical direction).

[0198] like Figure 4 As shown, the output nodes n2 of the four first pixel circuits 16 are connected to one second floating diffusion region FD2. Therefore, the second reset transistor 41, the second source follower circuit 42 and the second selection transistor 44 in the second pixel circuit 17 are shared by the four pixels 15 and the four first pixel circuits 16.

[0199] In this manual, Figure 4 The four pixels 15, four first pixel circuits 16, and one second pixel circuit 17 shown are referred to as a unit pixel group region 40. Figure 4In the illustrated example, the photoelectric conversion element 21, transfer transistor 22, first reset transistor 23, first source follower circuit 24, first selection transistor 26, conversion efficiency switching transistor 27, and drain transistor 30 that constitute the pixel 15 are arranged on the first substrate. Furthermore, the first capacitor 31, first sampling transistor 33, second capacitor 32, second sampling transistor 34, and transistor groups 35 and 36 that constitute the current source that constitute the first pixel circuit 16, as well as the second reset transistor 41, second source follower circuit 42, and second selection transistor 44 that constitute the second pixel circuit 17, are arranged on the second substrate.

[0200] Figure 5 is a cross-sectional view illustrating the cross-sectional structure of the light detection device 3 according to the embodiment. As described above, the light detection device 3 according to this embodiment has a stacked structure in which three semiconductor substrates (first to third substrates) 51 to 53 are stacked. The first substrate 51 is arranged on the light incident side, the second substrate 52 is stacked on the first substrate 51, and the third substrate 53 is stacked on the second substrate 52. The first and second substrates 51, 52 are bonded together via metal pads, and signals are transmitted and received. More specifically, a plurality of first metal pads 63 provided on the first substrate 51 and a plurality of second metal pads 68 provided on the second substrate 52 are bonded together, and signals are transmitted and received via the metal pads.

[0201] A semiconductor layer (second semiconductor layer) 64 is disposed on the side of the second substrate 52 opposite to the third substrate 53, and a via 70 is provided that penetrates the semiconductor layer 64. Since the via penetrates the semiconductor layer (specifically, the silicon layer), the via is called a TSV (through silicon via) 70. A plurality of third metal pads 71 ​​disposed at the end of the TSV 70 on the third substrate 53 side and a plurality of fourth metal pads 75 of the third substrate 53 are bonded to each other, and the second substrate 52 and the third substrate 53 transmit and receive signals via the metal pads 71, 75.

[0202] The plurality of pixels 15 are arranged on the first substrate 51. The plurality of first pixel circuits 16 and the plurality of second pixel circuits 17 are arranged on the second substrate 52. The logic circuit 54 is arranged on the third substrate 53. As will be described later, Figure 2 The peripheral circuit 55 including the vertical drive section 12, the column signal processing section 13 and the timing control section 14 other than the pixel array section 11 shown in FIG (see FIG) Figure 6 ) is configured in an empty area of ​​at least one of the first substrate 51 and the second substrate 52. At least a portion of the peripheral circuit 55 may be configured on the third substrate 53.

[0203] The first semiconductor layer 56 , the first wiring layer 57 , the color filter 58 , the on-chip lens 59 , and the like are arranged on the first substrate 51 .

[0204] On the first semiconductor layer 56, a photoelectric conversion element 21 is arranged for each pixel 15. For example, the photoelectric conversion element 21 is formed by arranging an n-type semiconductor region within a p-type well region. A light shielding wall 60 that absorbs light from adjacent pixels 15 is arranged in the boundary region between pixels 15. A fixed charge film 61 for preventing the generation of dark current is arranged on the surface of the light shielding wall 60.

[0205] The first principal surface S1 of the first semiconductor layer 56 is a light incident surface. The first principal surface S1 has a concavo-convex structure 62 for preventing reflection. A color filter 58 is disposed on the first principal surface S1, and an on-chip lens 59 is disposed on top of the color filter 58. Note that the color filter 58 and the on-chip lens 59 are not essential components and can be omitted.

[0206] A portion of the pixel transistors such as the transfer transistor 22 is arranged on the second main surface S2 of the first semiconductor layer 56, and the first wiring layer 57 is arranged thereon ( Figure 5 The first wiring layer 57 has a stacked structure including a plurality of wiring layers and vias separated from each other by the first insulating layer 50. A plurality of first metal pads 63 are arranged on the end surface of the first wiring layer 57 on the second substrate 52 side.

[0207] The second semiconductor layer 64, the second wiring layer 65, the third wiring layer 66, and the like are arranged on the second substrate 52. The second wiring layer 65 is arranged on the first principal surface S3 side of the second semiconductor layer 64, and the third wiring layer 66 is arranged on the second principal surface S4 side of the second semiconductor layer 64. The first principal surface S3 of the second semiconductor layer 64 is on the first substrate 51 side, and the second principal surface S4 is on the third substrate 53 side.

[0208] The second wiring layer 65 is a stacked structure having a plurality of wiring layers and vias separated from each other by a second insulating layer 67. A plurality of second metal pads 68 are arranged on the end surface of the second wiring layer 65 on the first substrate 51 side. Each of the plurality of second metal pads 68 is bonded to a corresponding first metal pad 63, and signals are transmitted and received by the first substrate 51 and the second substrate 52. A first metal pad 63 and a second metal pad 68 are provided for each pixel 15, and are arranged on the first substrate 51 and the second substrate 52. Figure 3 The pixel 15 is shown to send and receive a voltage signal at an output node n1.

[0209] Figure 3 Each transistor in the illustrated first pixel circuit 16 and second pixel circuit 17 is arranged on the second semiconductor layer 64. Vias extending from the second wiring layer 65 are connected to the transistors.

[0210] Furthermore, a TSV 70 is provided which penetrates the second semiconductor layer 64 and the third wiring layer 66 and extends to the third substrate 53 side. The TSV 70 is connected to Figure 3 The vertical signal line VSL is shown. For example, the vertical signal line VSL is formed on the second wiring layer 65 of the second substrate 52. A plurality of third metal pads 71 ​​are arranged at the end of the TSV 70 on the third substrate 53 side.

[0211] The third semiconductor layer 72 , the fourth wiring layer 73 , and the like are arranged on the third substrate 53 . The fourth wiring layer 73 is arranged on the first principal surface S5 side of the third substrate 53 , and the third semiconductor layer 72 is arranged on the second principal surface S6 of the second substrate 53 .

[0212] The fourth wiring layer 73 is a stacked structure having multiple wiring layers and vias separated from each other by a third insulating layer 74. A plurality of fourth metal pads 75 are arranged on the end surface of the fourth wiring layer 73 on the second substrate 52 side. Each of the plurality of fourth metal pads 75 is bonded to a corresponding third metal pad 71, and signals are transmitted and received by the second substrate 52 and the third substrate 53. The number of third metal pads 71 ​​and fourth metal pads 75 provided is the same as the number of vertical signal lines VSL.

[0213] In this manner, the first wiring layer 57 and the second wiring layer 65 are arranged face to face (F to F), and the first substrate 51 and the second substrate 52 are bonded via the first metal pad 63 and the second metal pad 68. Furthermore, the second wiring layer 65 and the fourth wiring layer 73 are arranged face to back (F to B), and the second substrate 52 and the third substrate 53 are bonded via the third metal pad 71 and the fourth metal pad 75.

[0214] like Figure 5 As shown, the cross-sectional structure directly below the pixel 15 is different from the cross-sectional structure of the region other than directly below the pixel 15. In the pixel region, in the region other than directly below the pixel 15, a TSV 76 having a larger diameter than the TSV 70 is provided from the second substrate 52 to the third substrate 53. The TSV 76 is used, for example, to make a substrate contact and to apply a predetermined reference voltage (for example, a power supply voltage or a ground voltage).

[0215] Despite Figure 5 Although omitted in the figure, a reference contact portion is provided for supplying a reference potential to at least one of the first substrate 51, the second substrate 52, and the third substrate 53. The reference contact portion is also called a well contact portion.

[0216] Despite Figure 5 The cross-sectional structure of the peripheral circuit of the pixel 15 on the first substrate 51 and the second substrate 52 is not shown in FIG. 1 , but as described later, the peripheral circuit is configured on the first substrate 51 or the second substrate 52 directly above the TSV 76 .

[0217] The peripheral circuits of pixel 15 include Figure 2The vertical drive unit 12 and the column signal processing unit 13 shown in the figure have a plurality of transistors. Each transistor in the peripheral circuit is arranged in a free area of ​​at least one of the first substrate 51 , the second substrate 52 and the third substrate 53 .

[0218] Figure 6 1 is a cross-sectional view showing a first example of a cross-sectional structure of the peripheral circuit 55 of the pixel 15. In the first example, the peripheral circuit 55 of the pixel 15 is configured on the second substrate 52. In this case, since the peripheral circuit 55 does not need to be configured on the first substrate 51, the number of pixels can be increased by that amount, and a higher resolution can be achieved. Alternatively, the capacitance of the first capacitor element 31 and the second capacitor element 32 formed on the first substrate 51 can be increased, and improved sensitivity can be achieved.

[0219] Figure 7 1 is a cross-sectional view showing a second example of the cross-sectional structure of the peripheral circuit 55 of the pixel 15. In the second example, the peripheral circuit 55 of the pixel 15 is divided into a first substrate 51 and a second substrate 52. By distributing the peripheral circuit 55 between the first to third substrates 51 to 53, the component density of each substrate can be made uniform, and noise such as crosstalk can be more easily suppressed. Although Figure 7 The bonding structure between the peripheral circuit 55 of the first substrate 51 and the peripheral circuit 55 of the second substrate 52 is not shown in the figure, but the peripheral circuit 55 can be bonded through the corresponding metal pads or through vias.

[0220] Figure 8 1 is a planar layout diagram of 2×2 pixels of the first substrate 51 when four pixels 15 and four first pixel circuits 16 share one second pixel circuit 17. Figure 8 In the embodiment, the 2×2 pixel region on the first substrate 51 and the second substrate 52 is referred to as a unit pixel group region 40. Multiple unit pixel group regions 40 are arranged two-dimensionally on the first substrate 51 and the second substrate 52. The four pixels 15 and the four first pixel circuits 16 that share one second pixel circuit 17 can be, for example, a unit pixel group of a Bayer array. In this case, the unit pixel group can be composed of four pixels 15 of red (R), green (G), blue (B), and green (G), or four pixels 15 of red (R), green (G), blue (B), and white (W).

[0221] Figure 8 The example of the first substrate 51 shown includes a unit pixel group region 40 including two pixels in each of the first direction X and the second direction Y. Figure 8As shown, a unit pixel group region 40 including four pixels 15 is arranged in a plurality of units in a two-dimensional direction on a first substrate 51. A transfer transistor 22, a first reset transistor 23, a first source follower circuit 24, a first selection transistor 26, a drain transistor 30, and a conversion efficiency switching transistor 27 are arranged in each unit pixel group region 40. The photoelectric conversion element 21 is arranged on almost the entire pixel region below the transistor. More specifically, as shown in FIG. Figure 8 As shown, the gate TRG of the transfer transistor 22, the gate RST of the first reset transistor 23, the gate SF1 of the first source follower circuit 24, the gate SW of the first selection transistor 26, the gate FDG of the conversion efficiency switching transistor 27, and the gate OFG of the drain transistor 30 are arranged in the unit pixel group region 40 with a diffusion layer 37 interposed therebetween. The white portion in each pixel region is an insulating layer 38.

[0222] Figure 9 is layered on Figure 8 The planar layout diagram of the unit pixel group region 40 of 2×2 pixels on the second substrate 52 on the first substrate 51 is shown. The plurality of unit pixel group regions 40 are arranged in a two-dimensional direction on the second substrate 52. Four first pixel circuits 16 and one second pixel circuit 17 are arranged in each unit pixel group region 40. In addition, although one TSV 70 is arranged in each unit pixel group region 40, the TSV is not Figure 9 Shown in.

[0223] exist Figure 9 In the example shown, arranged along the first direction X within the region of four pixels are: a first row, in which two transistor groups 35 and 36 forming a current source are arranged; a second row, in which two groups, each consisting of a first sampling transistor 33 and a second sampling transistor 34, are arranged; a third row, in which a second selection transistor 44, a second source follower circuit 42, and a second reset transistor 41 are arranged; a fourth row, in which two groups, each consisting of a first sampling transistor 33 and a second sampling transistor 34, are arranged; and a fifth row, in which two transistor groups 35 and 36 forming a current source are arranged. In each row, the gates and diffusion regions of the transistors are arranged along the first direction X.

[0224] For example, in the first and fifth rows, the gates VB, PC, PC, and VB of the two transistor groups 35 and 36 constituting the current source are arranged in this order along the first direction X with the diffusion layer 37 interposed between the gates. In the second and fourth rows, the well contact region WC, the gates SD, SR, SR, and SD of the second sampling transistor 34 and the first sampling transistor 33, and the well contact region WC are arranged in this order along the first direction X with the diffusion layer 37 interposed between the gates. In the third row, the gate SEL of the second selection transistor 44, the gate SF2 of the second source follower circuit 42, and the gate RB of the second reset transistor 41 are arranged in this order along the first direction X with the diffusion layer 37 interposed between the gates.

[0225] As described above, the transistors and the like constituting the four first pixel circuits 16 and the one second pixel circuit 17 are symmetrically arranged on the second substrate 52. More specifically, the gate SF2 of the second source follower circuit 42 is arranged substantially in the center of the unit pixel group region 40, the gates SR of the two or more first sampling transistors 33 are located at an equal distance from the gate SF2, and the gates SD of the two or more second sampling transistors 34 are located at an equal distance from the gate SF2.

[0226] In particular, Figure 9 In the example shown, all extension directions of the channel of each transistor (hereinafter referred to as the channel direction or gate length direction) are the first direction X, and the diffusion layer 37 is arranged on both sides of the channel of each transistor in the first direction X. Therefore, transistors adjacent to each other in the first direction X are arranged with the diffusion layer 37 interposed therebetween, and the risk of channel modulation due to the influence of adjacent transistors can be avoided.

[0227] In addition, despite Figure 9 Although the TSVs 70 are omitted from the illustration, for example, the TSVs 70 are arranged along the third row located in the center of the unit pixel group region 40 in the second direction Y. More specifically, for example, the TSVs 70 are arranged near the gate SEL of the second selection transistor 44. Therefore, the TSVs 70 are arranged across the diffusion layer 37 of the second selection transistor 44 adjacent in the first direction X, and the risk of the TSVs 70 modulating the signal variation of the channel of the second selection transistor 44 can be avoided. Note that the TSVs 70 can be arranged along the Figure 9 Arrange rows other than the third row as shown.

[0228] As described above, first substrate 51 and second substrate 52 transmit and receive signals due to the bonding of first metal pad 63 and second metal pad 68, and second substrate 52 and third substrate 53 transmit and receive signals due to the bonding of third metal pad 71 and fourth metal pad 75 arranged at the end of TSV 70 penetrating second semiconductor layer 64 on second substrate 52. The arrangement position and size of the metal pads are arbitrary.

[0229] exist Figure 9 In the example, the gate SF2 of the second source follower circuit 42 is arranged in the center of the unit pixel group region 40 for each of the 2×2 pixels 15 on the second substrate 52. Furthermore, in the unit pixel group region 40, the gates SD of the four first sampling transistors 33 and the gates SR of the four second sampling transistors 34 are arranged in point-symmetry or line-symmetry with respect to the gate SF2.

[0230] When reading out pixel signals, there is a risk that the gates of the first sampling transistor 33 and the second sampling transistor 34, which are controlled to hold voltage signals in the first capacitor 31 and the second capacitor 32, may cause crosstalk in the channel immediately below the gate SF2 of the second source follower circuit 42 in the subsequent stage. In particular, when multiple pixels 15 and multiple first pixel circuits 16 share a single second pixel circuit 17, if the distances from the gates SR of the first sampling transistor 33 and SD of the second sampling transistor 34 to the gate SF2 of the second source follower circuit 42 vary for each shared pixel, the magnitude of the crosstalk also varies for each pixel, potentially leading to degradation in image quality.

[0231] Taking the above into consideration, Figure 9 In the embodiment, the gates SR of the four first sampling transistors 33 are arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the second source follower circuit, and the gates SD of the four second sampling transistors 34 are also arranged in a point-symmetric or line-symmetric manner.

[0232] Therefore, the distances between the gate SF2 of the second source follower circuit 42 and the gates SR of the four first sampling transistors 33 become uniform, and the distances between the gate SF2 of the second source follower circuit 42 and the gates SD of the four second sampling transistors 33 also become uniform. Therefore, the influence of crosstalk becomes the same in all pixels 15, and output differences between colors can be eliminated.

[0233] The layout configuration of the second substrate 52 is not limited to Figure 9 As shown, various modifications are conceivable. Figure 10 is based on Figure 9 FIG. 4 is a planar layout diagram of the second substrate 52 of the first modified example. Figure 10The unit pixel group region 40 according to the first modification example shown has the following layout configuration, wherein Figure 9 The first and second rows in are swapped and Figure 9 The fourth and fifth rows in are swapped. Even in Figure 10 In the first modification shown, the gates SR of the first sampling transistors 33 of the four pixels and the gates SD of the second sampling transistors 34 of the four pixels are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the second source follower circuit 42 arranged in the central portion of the unit pixel group region 40.

[0234] Therefore, since the distances between the gate SF2 of the second source follower circuit 42 and the gates SR of the first sampling transistors 33 of the four pixels become uniform, and the distances between the gate SF2 of the second source follower circuit 42 and the gates SD of the four second sampling transistors 33 also become uniform, the influence of crosstalk can be made uniform in all pixels, and improvement in image quality can be achieved.

[0235] exist Figure 9 and Figure 10 In the illustrated layout of the second substrate 52, the gates of the transistors in the first pixel circuit 16 and the second pixel circuit 17 extend in a first direction X, and the diffusion layer 37 is disposed on both sides of each gate in the first direction X. The direction in which the gates of at least some of the transistors extend and the direction in which the diffusion layer 37 is disposed may be a second direction Y that intersects the first direction X.

[0236] Figure 11 is based on Figure 9 The plan layout diagram of the second substrate 52 of the second modified example. Figure 11 As shown, in the unit pixel group region 40 of the second substrate 52 according to the second modification, a row extending in the first direction X is arranged in the center portion in the second direction Y. In this row, the gate SEL of the second select transistor 44, the gate SF2 of the second source follower circuit 42, and the gate RB of the second reset transistor 41 are arranged in this order along the first direction X. The channels of the transistors extend in the first direction X, and the diffusion layers 37 are arranged at both ends of the channel in the first direction X.

[0237] In addition, if Figure 11As shown, in the unit pixel group region 40 of the second substrate 52 according to the second modified example, four columns (first to fifth columns) are arranged in the first direction X. All of the first to fifth columns extend in the second direction Y. The first to fifth columns are divided by the rows at their centers in the second direction Y. In the first and fifth columns, the gates VB, PC, PC, and VB of the two transistor groups 35 and 36 constituting the current source are arranged in this order along the second direction Y, with a diffusion layer 37 interposed between the gates. In the second and third columns, the gate SD of the second sampling transistor 34, the gate SR of the first sampling transistor 33, the gate SR of the first sampling transistor 33, and the gate SD of the second sampling transistor 34 are arranged in this order along the second direction Y, with a diffusion layer 37 interposed between the gates. Furthermore, in the third column, two well contact regions WC are arranged along the second direction Y.

[0238] In this manner, in the unit pixel group region 40 of the second substrate 52 according to the second modification, as shown in FIG. Figure 11 As shown, the gate SF2 of the second source follower circuit 42 is arranged in the center of the unit pixel group area 40, and the gates SR of the first sampling transistors 33 of the four pixels and the gates SD of the second sampling transistors 34 of the four pixels are arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2.

[0239] Therefore, since the distances between the gate SF2 of the second source follower circuit 42 and the gates SR of the first sampling transistors 33 of the four pixels become uniform, and the distances between the gate SF2 of the second source follower circuit 42 and the gates SD of the four second sampling transistors 33 also become uniform, the influence of crosstalk can be made uniform in all pixels, and improvement in image quality can be achieved.

[0240] Figure 12 is based on Figure 9 The plan layout diagram of the second substrate 52 of the third modified example. Figure 12 As shown, the unit pixel group region 40 of the second substrate 52 according to the third modification has the following layout configuration, wherein Figure 11 The first and second columns in are swapped and Figure 11 The fourth and fifth columns in are swapped. Even in Figure 12 In the third modification shown, the gates SR of the first sampling transistors 33 of the four pixels and the gates SD of the second sampling transistors 34 of the four pixels are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the second source follower circuit 42 arranged in the central portion of the unit pixel group area 40.

[0241] Figure 13 is based on Figure 9 The plan layout diagram of the second substrate 52 of the fourth modified example. Figure 13 As shown, the unit pixel group region 40 of the second substrate 52 according to the fourth modification includes a gate SF2 of the second source follower circuit 42, which is arranged in the center of the unit pixel group region 40 in the second direction Y. Gate SF2 has a larger area than the gates of other transistors to improve symmetry. The gate length of the gate is in the first direction X, and diffusion layers 37 are arranged on both sides of the gate in the second direction Y.

[0242] In addition, if Figure 13 As shown, the unit pixel group region 40 of the second substrate 52 according to the fourth modification includes five columns (first to fifth columns) arranged in the first direction X. All of the first to fifth columns extend in the second direction Y and are interrupted in the center of the second direction Y. In the first and fifth columns, the gates VB, PC, PC, and VB of the two transistor groups 35 and 36 constituting the current source are arranged in this order along the second direction Y, with a diffusion layer 37 interposed between the gates. In the second and fourth columns, the gate SD of the second sampling transistor 34, the gate SR of the first sampling transistor 33, the gate SR of the first sampling transistor 33, and the gate SD of the second sampling transistor 34 are arranged in this order along the second direction Y, with a diffusion layer 37 interposed between the gates. In the third column, the well contact region WC, the gate RB of the second reset transistor 41, and the gate SEL of the second select transistor 44 are arranged in this order along the second direction Y, with a diffusion layer 37 interposed between the gates.

[0243] The gate SF2 of the second source follower circuit 42 is configured to interrupt the second to fourth columns in the central portion in the second direction Y.

[0244] like Figure 13 As shown, the unit pixel group region 40 of the second substrate 52 according to the fourth modification includes a gate SF2 of the second source follower circuit 42 arranged in the central portion of the unit pixel group region 40, gates SR of the first sampling transistors 33 of four pixels arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2, and gates SD of the second sampling transistors 34 of four pixels arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2.

[0245] Therefore, the distances between the gate SF2 of the second source follower circuit 42 and the gates SR of the four first sampling transistors 33 become uniform, and the distances between the gate SF2 of the second source follower circuit 42 and the gates SD of the four second sampling transistors 33 also become uniform. Therefore, the influence of crosstalk becomes uniform in all pixels 15, and output differences between colors can be eliminated.

[0246] Figure 14 is based on Figure 9 The plan layout diagram of the second substrate 52 of the fifth modified example. Figure 14 As shown, the unit pixel group region 40 of the second substrate 52 according to the fourth modification has the following layout configuration, wherein Figure 13 The first and second columns in are swapped and Figure 13 The fourth and fifth columns in are swapped. Even in Figure 14 In the example, the gates SR of the first sampling transistors 33 of the four pixels and the gates SD of the second sampling transistors 34 of the four pixels are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the second source follower circuit 42 arranged in the central portion of the unit pixel group region 40. Figures 9 to 13 Similar effect.

[0247] The channel direction of some transistors in the unit pixel group area 40 can be in the same direction as Figure 13 and Figure 14 Configured in different directions.

[0248] Figure 15 is based on Figure 9 The plan layout diagram of the second substrate 52 of the sixth modified example. Figure 15 As shown, the unit pixel group region 40 of the second substrate 52 according to the sixth modification includes Figure 14 The extending directions of the first, second, fourth and fifth columns in the image are changed from the second direction Y to the first, second, third and fourth rows in the first direction X. The first to fourth rows are interrupted in the central part of the first direction X.

[0249] In the first and fourth rows, the gates VB, PC, PC, and VB of the two transistor groups 35 and 36 constituting the current source are arranged in this order along the first direction X with a diffusion layer 37 interposed between the gates. In the second and third rows, the gate SD of the second sampling transistor 34, the gate SR of the first sampling transistor 33, the gate SR of the first sampling transistor 33, and the gate SD of the second sampling transistor 34 are arranged in this order along the first direction X with a diffusion layer 37 interposed between the gates.

[0250] exist Figure 15 In the central portion of the unit pixel group area 40 in the first direction X shown, the well contact area WC, the gate RB of the second reset transistor 41, the gate SF2 of the second source follower circuit 42, and the gate SEL of the second selection transistor 44 are arranged in this order along the second direction Y with the diffusion layer 37 sandwiched between the gates.

[0251] Even in the unit pixel group region 40 of the second substrate 52 according to the sixth modification, the gates SR of the first sampling transistors 33 of the four pixels and the gates SD of the second sampling transistors 34 of the four pixels are arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the second source follower circuit 42, and a similar gate symmetry to that of the first sampling transistor 33 of the four pixels and the gates SD of the second sampling transistor 34 of the four pixels is generated. Figures 9 to 14 Similar effect.

[0252] Figure 16 is based on Figure 9 The plan layout diagram of the second substrate 52 of the seventh variation. Figure 16 As shown, the unit pixel group region 40 of the second substrate 52 according to the seventh modification has the following layout configuration, wherein Figure 15 The first and second rows in are swapped and Figure 15 The third and fourth rows in are swapped. Even in Figure 16 In the embodiment, the gates SR of the first sampling transistors 33 of the four pixels and the gates SD of the second sampling transistors 34 of the four pixels are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the second source follower circuit 42, and generate the same Figures 9 to 15 Similar effect.

[0253] As described above, there is a risk that the gates of the first sampling transistor 33 and the second sampling transistor 34 may cause crosstalk in the channel directly below the gate SF2 of the subsequent second source follower circuit 42. One possible countermeasure to suppress the influence of this crosstalk is to use a twin structure for the gate of the second source follower circuit 42. The example described below is provided with two second amplification transistors 43 constituting the second source follower circuit 42.

[0254] Figure 17 is based on Figure 9 The plan layout diagram of the second substrate 52 of the eighth modified example. Figure 17 As shown, the unit pixel group region 40 of the second substrate 52 according to the eighth modification includes five columns (first to fifth columns) arranged in the first direction X. The two gate electrodes SF2 of the second source follower region are provided in one second pixel circuit 17 shared by four pixels 15 and four first pixel circuits 16 .

[0255] In the first and fifth columns, the gates VB, PC, PC, and VB of the two transistor groups 35 and 36 constituting the current source are arranged in this order along the second direction Y, with a diffusion layer 37 interposed between the gates. A dummy gate 80 is disposed between two gates PC adjacent to each other in the second direction Y in the first and fifth columns. The dummy gate 80 is disposed to ensure symmetry and uniform crosstalk. In the second and fourth columns, the gate SD of the second sampling transistor 34, the gate SR of the first sampling transistor 33, the gate SF2 of the second source follower circuit 42, the gate SR of the first sampling transistor 33, and the gate SD of the second sampling transistor 34 are arranged in this order along the second direction Y, with a diffusion layer 37 interposed between the gates. In the third column, the well contact region WC, the gate RB of the second reset transistor 41, the dummy gate 80, and the gate SEL of the second select transistor 44 are arranged in this order along the second direction Y, with a diffusion layer 37 interposed between the gates.

[0256] like Figure 17 As shown, on the second substrate 52 according to the eighth modification, the two gates SF2 of the second source follower circuit 42 are arranged in the central portion of the unit pixel group region 40 in the second direction Y, and the gates SR of the first sampling transistors 33 of the four pixels and the gates SD of the second sampling transistors 34 of the four pixels are arranged in a point-symmetric or line-symmetric manner with respect to the gates SF2.

[0257] Giving the gate SF2 of the second source follower circuit 42 a dual structure can make the influence of crosstalk uniform on the gates SR of the first sampling transistors 33 and the gates SD of the second sampling transistors 34 of the four pixels.

[0258] Figure 18 is based on Figure 9 The plan layout diagram of the second substrate 52 of the ninth variation. Figure 18 As shown, the unit pixel group region 40 of the second substrate 52 according to the ninth modification has the following layout configuration, wherein Figure 17 The first and second columns in are swapped and Figure 17 The fourth and fifth columns in are swapped.

[0259] Even in Figure 18 In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetrical or line-symmetrical manner with respect to the two gates SF2 of the second source follower circuit 42 in the center portion in the second direction Y of the unit pixel group area 40, thereby making the influence of crosstalk uniform.

[0260] although Figure 17 and Figure 18The channels of all transistors in the unit pixel group region 40 are arranged in the second direction Y, but the channels of at least a portion of the transistors may be arranged in the first direction X.

[0261] Figure 19 is based on Figure 9 The plan layout diagram of the second substrate 52 of the tenth variation. Figure 19 As shown, the unit pixel group area 40 of the second substrate 52 according to the tenth variant has four rows (first to fourth rows) arranged in the second direction Y and extending in the first direction X, and the gate RB of the second reset transistor 41, the two gates SF2 of the second source follower circuit 42 and the gate SEL of the second selection transistor 44 arranged along the first direction X in the central part of the first direction Y.

[0262] In the first and fourth rows, gates VB and PC of transistor groups 35 and 36 constituting current sources, well contact regions WC, and gates PC and VB of transistor groups 35 and 36 are arranged in this order along the first direction X with diffusion layers 37 interposed therebetween.

[0263] In the second and third rows, the gate SD of the second sampling transistor 34 , the gate SR of the first sampling transistor 33 , the gate SR of the first sampling transistor 33 , and the gate SD of the second sampling transistor 34 are arranged in this order along the first direction X with the diffusion layer 37 interposed therebetween.

[0264] Even in Figure 19 In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetrical or line-symmetrical manner with respect to the two gates SF2 of the second source follower circuit 42 in the center portion in the second direction Y of the unit pixel group area 40, thereby making the influence of crosstalk uniform.

[0265] Figure 20 is based on Figure 9 The plan layout diagram of the second substrate 52 of the eleventh modified example. Figure 20 As shown, the unit pixel group region 40 of the second substrate 52 according to the eleventh modification has the following layout configuration, wherein Figure 19 The first and second rows in are swapped and Figure 19 The third and fourth rows in are swapped.

[0266] Even in Figure 20 In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetrical or line-symmetrical manner with respect to the two gates SF2 of the second source follower circuit 42 in the center portion in the second direction Y of the unit pixel group area 40, thereby making the influence of crosstalk uniform.

[0267] The circuit configuration of the pixel 15 and the pixel circuit is not limited to Figure 3 The light detection device 3 according to the present disclosure can also be applied to Figure 3 The pixel 15 and the pixel circuit are constituted by circuits other than those shown.

[0268] Figure 21 is based on Figure 3 A circuit diagram of a pixel 15 and a pixel circuit according to a modified example. Figure 21 The first pixel circuit 16 shown has a first output node SF21 and a second output node SF22, and a separate second pixel circuit 17 is connected to the first output node SF21 and the second output node SF22, respectively. One of the second pixel circuits 17 has a second source follower circuit 42R and a second select transistor 44R, and the other of the second pixel circuits 17 has a second source follower circuit 42D and a second select transistor 44D.

[0269] Figure 21 The first pixel circuit 16 shown is connected to the output node n1 of the pixel 15 and includes a transistor group 35 and 36 forming a current source, a first sampling transistor 33 and a first capacitor 31, a second sampling transistor 34, and a second capacitor 32. The first capacitor 31 is connected between the reference voltage node and the first output node SF21. The first sampling transistor 33 is connected between the first output node SF21 and the output node n1 of the pixel 15. The second capacitor 32 is connected between the reference voltage node and the second output node SF22. The second sampling transistor 34 is connected between the second output node SF22 and the output node n1 of the pixel 15.

[0270] Figure 22 is based on Figure 21 The circuit structure shown is a circuit diagram in which four pixels 15 and four first pixels 15 share one second pixel circuit 17. Figure 21 There are two second pixel circuits 17, but Figure 22 There is a second pixel circuit 17, and a third selection transistor 38 is arranged between the output node n1 of the pixel 15 and the input node of the second pixel circuit 17. When the PSEL signal is at a high level, the third selection transistor 38 is turned on.

[0271] Figure 23 is Figure 22 The pixel 15 and the pixel circuit shown are a planar layout diagram of a 4×4 pixel unit pixel group area 40 of a second substrate 52. Figure 23The illustrated unit pixel group region 40 includes five rows (first to fifth rows). In the first and fifth rows, the gates VB, PC, PC, and VB of the two transistor groups 35 and 36 constituting current sources are arranged in this order along the first direction X, with a diffusion layer 37 interposed between the gates. In the second and fourth rows, the gate PSEL of the third selection transistor 38, the gate SD of the second sampling transistor 34, the gate SR of the first sampling transistor 33, the gate SR of the first sampling transistor 33, the gate SD of the second sampling transistor 34, and the gate PSEL of the third selection transistor 38 are arranged in this order along the first direction X, with a diffusion layer 37 interposed between the gates. In the third row, the gate SEL of the second selection transistor 44, the gate SF2 of the second source follower circuit 42, and the well contact region WC are arranged in this order along the first direction X, with a diffusion layer 37 interposed between the gates.

[0272] exist Figure 23 In FIG. 4 , the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are arranged in point symmetry or line symmetry with respect to the gate SF2 of the second source follower circuit 42 arranged in the center of the unit pixel group region 40 .

[0273] Therefore, the distances between the gate SF2 of the second source follower circuit 42 and the gates SR of the four first sampling transistors 33 become uniform, and the distances between the gate SF2 of the second source follower circuit 42 and the gates SD of the four second sampling transistors 33 also become uniform. Therefore, the influence of crosstalk becomes the same in all pixels 15, and output differences between colors can be eliminated.

[0274] Figure 24 is based on Figure 23 The plan layout diagram of the second substrate 52 of the first modified example. Figure 24 As shown, the unit pixel group region 40 of the second substrate 52 according to the first modification has the following layout configuration, wherein Figure 23 The first and second rows in are swapped and Figure 23 The fourth and fifth rows in are swapped.

[0275] Even in Figure 24 In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the second source follower circuit 42 arranged in the center of the unit pixel group area 40. Figure 23 The layout configuration has a similar effect.

[0276] Figure 25 is based on Figure 23 The plan layout diagram of the second substrate 52 of the second modified example. Figure 25As shown, the unit pixel group region 40 of the second substrate 52 according to the second modification example includes four columns (first to fourth columns) and one row.

[0277] In the first and fourth columns, the gates VB, PC, PC, and VB of the two transistor groups 35 and 36 constituting the current source are arranged in this order along the second direction Y. In the second and third columns, the gate PSEL of the third selection transistor 38, the gate SD of the second sampling transistor 34, the gate SR of the first sampling transistor 33, the gate SR of the first sampling transistor 33, the gate SD of the second sampling transistor 34, and the gate PSEL of the third selection transistor 38 are arranged in this order along the second direction Y with the diffusion layer 37 interposed between the gates.

[0278] In a row arranged in the center of the unit pixel group region 40 in the second direction Y, the gate SEL of the second selection transistor 44, the gate SF2 of the second source follower circuit 42, and the well contact region WC are arranged in this order along the first direction X with the diffusion layer 37 interposed between the gates.

[0279] Even in Figure 25 In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the second source follower circuit 42 arranged in the center of the unit pixel group area 40. Figure 23 The layout configuration has a similar effect.

[0280] Figure 26 is based on Figure 23 The plan layout diagram of the second substrate 52 of the third modified example. Figure 26 As shown, the unit pixel group region 40 of the second substrate 52 according to the third modification has the following layout configuration, wherein Figure 25 The first and second columns in are swapped and Figure 25 The third and fourth columns in are swapped.

[0281] Even in Figure 26 In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the second source follower circuit 42 arranged in the center of the unit pixel group area 40. Figure 23 The layout configuration has a similar effect.

[0282] Figure 27 is based on Figure 23 The plan layout diagram of the second substrate 52 of the fourth modified example. Figure 27 As shown, the unit pixel group region 40 of the second substrate 52 according to the fourth modification example is Figure 25The difference is that the direction in which the gate SF2 of the second source follower circuit 42 extends is the second direction Y. Otherwise, the layout configuration is the same as Figure 25 The diffusion layers of the second source follower circuit 42 are arranged on both end sides in the second direction Y of the gate electrode SF2.

[0283] Even in Figure 27 In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the second source follower circuit 42 arranged in the center of the unit pixel group area 40. Figure 23 The layout configuration has a similar effect.

[0284] Figure 28 is based on Figure 23 The plan layout diagram of the second substrate 52 of the fifth modified example. Figure 28 As shown, the unit pixel group region 40 of the second substrate 52 according to the fifth modification example is Figure 26 The difference is that the direction in which the gate SF2 of the second source follower circuit 42 extends is the second direction Y. Otherwise, the layout configuration is the same as Figure 26 Same as shown.

[0285] Even in Figure 28 In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the second source follower circuit 42 arranged in the center of the unit pixel group area 40. Figure 23 The layout configuration has a similar effect.

[0286] Figure 29 is based on Figure 23 The plan layout diagram of the second substrate 52 of the sixth modified example. Figure 29 As shown, the unit pixel group region 40 of the second substrate 52 according to the sixth modification example is Figure 23 The difference is that the direction in which the gate SF2 of the second source follower circuit 42 extends is the second direction Y. Otherwise, the layout configuration is the same as Figure 23 Same as shown.

[0287] Even in Figure 29 In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the second source follower circuit 42 arranged in the center of the unit pixel group area 40. Figure 23 The layout configuration has a similar effect.

[0288] Figure 30 is based on Figure 23 The plan layout diagram of the second substrate 52 of the seventh variation. Figure 30 As shown, the unit pixel group region 40 of the second substrate 52 according to the seventh modification example is Figure 24 The difference is that the direction in which the gate SF2 of the second source follower circuit 42 extends is the second direction Y. Otherwise, the layout configuration is the same as Figure 24 Same as shown.

[0289] Even in Figure 30 In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the second source follower circuit 42 arranged in the center of the unit pixel group area 40. Figure 23 The layout configuration has a similar effect.

[0290] although Figure 4 Although an example is shown in which four pixels 15 and four first pixels 15 share one second pixel 15, the unit of sharing of pixels 15 is not limited to four. For example, one pixel 15 in the first direction X (e.g., horizontal direction) and two pixels 15 in the second direction Y (e.g., vertical direction) as the unit pixel group area 40 may share one second pixel 15.

[0291] Figure 31 Is used based on Figure 3 The circuit diagram of the pixel 15, the first pixel circuit 16 and the second pixel circuit 17 of the circuit structure shown in FIG. 1 is a circuit diagram in which two pixels 15 and two first pixel circuits 16 share one second pixel circuit 17. Figure 31 As shown, two pixels 15 and two first pixel circuits 16 arranged in the second direction Y are objects to be shared, and the two first pixel circuits 16 and one second pixel circuit 17 share the second floating diffusion region FD2 . Figure 31 The circuit configuration of four pixels is shown, in which two (upper and lower) first pixel circuits 16 on the left are connected to one second pixel circuit 17 , and two (upper and lower) first pixel circuits 16 on the right are connected to another second pixel circuit 17 .

[0292] Figure 32 is Figure 31 The illustrated pixel 15 and the pixel circuit are configured to form a planar layout of an area of ​​the second substrate 52 where two unit pixel group areas 40 of 1×2 pixels are arranged in the first direction X. Figure 32The illustrated region where the two unit pixel group regions 40 are arranged includes five rows (first to fifth rows). In the first and fifth rows, the gates VB and PC of the transistor groups 35 and 36 forming the current source, the gate RB of the second reset transistor 41, and the gates PC and VB of the transistor groups 35 and 36 forming the current source are arranged in this order along the first direction X, with a diffusion layer 37 interposed between the gates. In the second and fourth rows, the gate SD of the second sampling transistor 34, the gate SR of the first sampling transistor 33, the well contact region WC, the gate SR of the first sampling transistor 33, and the gate SD of the second sampling transistor 34 are arranged in this order along the first direction X. In the third row, the gate SEL of the second selection transistor 44, the gate SF2 of the second source follower circuit 42, the gate SF2 of the second source follower circuit 42, and the gate SEL of the second selection transistor 44 are arranged in this order along the first direction X, with a diffusion layer 37 interposed between the gates.

[0293] exist Figure 32 In the embodiment, in the central portion in the second direction Y of the region where the two unit pixel group regions 40 are arranged, the gates SF2 of the two second source follower circuits 42 are arranged along the first direction X, and the gates SR of the first sampling transistors 33 and the gates SD of the second sampling transistors 34 of the two pixels are arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2.

[0294] Therefore, the distance between the gate SF2 of the second source follower circuit 42 and the gates SR of the two first sampling transistors 33 becomes uniform, and the distance between the gate SF2 of the second source follower circuit 42 and the gates SD of the two second sampling transistors 33 also becomes uniform. Therefore, the influence of crosstalk becomes the same in all pixels 15, and the output difference between colors can be eliminated.

[0295] Figure 33 is based on Figure 32 The plan layout diagram of the second substrate 52 of the first modified example. Figure 33 As shown, the area where the two unit pixel group areas 40 of the second substrate 52 according to the first modification are arranged has such a layout configuration, wherein Figure 32 The first and second rows in are swapped and Figure 32 The fourth and fifth rows in are swapped.

[0296] Even in Figure 33 In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the two second source follower circuits 42 arranged in the center of the area where the two unit pixel group areas 40 are arranged. Figure 32 The layout configuration has a similar effect.

[0297] Figure 34 is based on Figure 32 The plan layout diagram of the second substrate 52 of the second modified example. Figure 34 As shown, the area where the two unit pixel group regions 40 are arranged in the second substrate 52 according to the second modification example includes five columns (first to fifth columns) and one row.

[0298] In the first and fifth columns, the gates VB, PC, PC, and VB of the two transistor groups 35 and 36 constituting the current source are arranged in this order along the second direction Y with a diffusion layer 37 interposed between the gates. In the second and fourth columns, the gate SD of the second sampling transistor 34, the gate SR of the first sampling transistor 33, the gate SR of the first sampling transistor 33, and the gate SD of the second sampling transistor 34 are arranged in this order along the second direction Y with a diffusion layer 37 interposed between the gates.

[0299] In the third column, the well contact region WC, the gate RB of the second reset transistor 41 , the gate RB of the second reset transistor 41 , and the well contact region WC are arranged along the second direction Y in this order.

[0300] Even in Figure 34 In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the two second source follower circuits 42 arranged in the center of the area where the two unit pixel group areas 40 are arranged. Figure 32 The layout configuration has a similar effect.

[0301] Figure 35 is based on Figure 32 The plan layout diagram of the second substrate 52 of the third modified example. Figure 35 As shown, the area where the two unit pixel group areas 40 of the second substrate 52 according to the third modification example are arranged has the following layout configuration, wherein Figure 34 The first and second columns in are swapped and Figure 34 The fourth and fifth columns in are swapped.

[0302] Even in Figure 35 In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the two second source follower circuits 42 arranged in the center of the area where the two unit pixel group areas 40 are arranged. Figure 32 The layout configuration has a similar effect.

[0303] Figure 36 is based on Figure 32 The plan layout diagram of the second substrate 52 of the fourth modified example. Figure 36 As shown, the area where the two unit pixel group regions 40 are arranged in the second substrate 52 according to the fourth modification includes five columns (first to fifth columns).

[0304] In the first and fifth columns, the gates VB and PC of the transistor groups 35 and 36 constituting the current source, the well contact region WC, and the gates PC and VB of the transistor groups 35 and 36 constituting the current source are arranged in this order with a diffusion layer 37 interposed between the gates, along the second direction Y. In the second and fourth columns, the gate SD of the second sampling transistor 34, the gate SR of the first sampling transistor 33, the gate SF2 of the second source follower circuit 42, the gate SR of the first sampling transistor 33, and the gate SD of the second sampling transistor 34 are arranged in this order with a diffusion layer 37 interposed between the gates, along the second direction Y. In the third column, the gate SEL of the second selection transistor 44, the gate RB of the second reset transistor 41, the gate RB of the second reset transistor 41, and the gate SEL of the second selection transistor 44 are arranged in this order with a diffusion layer 37 interposed between the gates, along the second direction Y.

[0305] Even in Figure 36 In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the two second source follower circuits 42 arranged in the center of the area where the two unit pixel group areas 40 are arranged. Figure 32 The layout configuration has a similar effect.

[0306] Figure 37 is based on Figure 32 The plan layout diagram of the second substrate 52 of the fifth modified example. Figure 37 As shown, the area where the two unit pixel group areas 40 are arranged on the second substrate 52 according to the fifth modification has the following layout configuration, wherein Figure 36 The first and second columns in are swapped and Figure 36 The fourth and fifth columns in are swapped.

[0307] Even in Figure 37 In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the two second source follower circuits 42 arranged in the center of the area where the two unit pixel group areas 40 are arranged. Figure 32 The layout configuration has a similar effect.

[0308] Figure 38 is based on Figure 32 The plan layout diagram of the second substrate 52 of the sixth modified example. Figure 38As shown, the area where the two unit pixel group regions 40 are arranged in the second substrate 52 according to the sixth modification includes five rows (first to fifth rows) and one column.

[0309] In the first and fifth rows, the gates VB, PC, PC, and VB of the two transistor groups 35 and 36 constituting the current source are arranged in this order along the first direction X, with a diffusion layer 37 interposed between the gates. In the second and fourth rows, the gate SD of the second sampling transistor 34, the gate SR of the first sampling transistor 33, the gate SR of the first sampling transistor 33, and the gate SD of the second sampling transistor 34 are arranged in this order along the first direction X. In the third row, the well contact region WC, the gate SF2 of the second source follower circuit 42, the gate SF2 of the second source follower circuit 42, and the well contact region WC are arranged in this order along the first direction X, with a diffusion layer 37 interposed between the gates. The channels of the transistors in the third row are arranged in the second direction Y, while the channels of the transistors in the other rows are arranged in the first direction X.

[0310] Even in Figure 38 In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the two second source follower circuits 42 arranged in the center of the area where the two unit pixel group areas 40 are arranged. Figure 32 The layout configuration has a similar effect.

[0311] Figure 39 is based on Figure 32 The plan layout diagram of the second substrate 52 of the seventh variation. Figure 39 As shown, the area where the two unit pixel group areas 40 of the second substrate 52 according to the seventh modification example are arranged has the following layout configuration, wherein Figure 38 The first and second rows in are swapped and Figure 38 The fourth and fifth rows in are swapped.

[0312] Even in Figure 39 In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the two second source follower circuits 42 arranged in the center of the area where the two unit pixel group areas 40 are arranged. Figure 32 The layout configuration has a similar effect.

[0313] Figure 40 Is used based on Figure 21The circuit diagram of the pixel 15, the first pixel circuit 16 and the second pixel circuit 17 of the circuit structure shown in FIG. 1 is a circuit diagram in which two pixels 15 and two first pixel circuits 16 share one second pixel circuit 17. Figure 40 As shown, two pixels 15 and two first pixel circuits 16 arranged in the second direction Y are objects to be shared, and the two first pixel circuits 16 and one second pixel circuit 17 share the second floating diffusion region FD2 . Figure 31 The circuit configuration of four pixels is shown, in which two (upper and lower) first pixel circuits 16 on the left are connected to one second pixel circuit 17 , and two (upper and lower) first pixel circuits 16 on the right are connected to another second pixel circuit 17 .

[0314] Figure 41 is Figure 40 The pixel 15 and the pixel circuit shown are arranged in a planar layout of an area of ​​the second substrate 52 where two unit pixel group areas 40 of 1×2 pixels are arranged. Figure 41 The illustrated region where the two unit pixel group regions 40 are arranged includes five rows (first to fifth rows). In the first and fifth rows, the gates VB and PC of the transistor groups 35 and 36 constituting the current source, the well contact region WC, and the gates PC and VB of the transistor groups 35 and 36 constituting the current source are arranged in this order along the first direction X, with a diffusion layer 37 interposed between the gates. In the second and fourth rows, the gate PSEL of the third selection transistor 38, the gate SD of the second sampling transistor 34, the gate SR of the first sampling transistor 33, the gate SR of the first sampling transistor 33, the gate SD of the second sampling transistor 34, and the gate PSEL of the third selection transistor 38 are arranged in this order along the first direction X, with a diffusion layer 37 interposed between the gates. In the third row, the gate SEL of the second selection transistor 44, the gate SF2 of the second source follower circuit 42, the gate SF2 of the second source follower circuit 42, and the gate SEL of the second selection transistor 44 are arranged in this order along the first direction X.

[0315] exist Figure 41 In the embodiment, in the central portion in the second direction Y of the region where the two unit pixel group regions 40 are arranged, the gates SF2 of the two second source follower circuits 42 are arranged along the first direction X, and the gates SR of the first sampling transistors 33 and the gates SD of the second sampling transistors 34 of the two pixels are arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2.

[0316] Therefore, the distance between the gate SF2 of the second source follower circuit 42 and the gates SR of the two first sampling transistors 33 becomes uniform, and the distance between the gate SF2 of the second source follower circuit 42 and the gates SD of the two second sampling transistors 33 also becomes uniform. Therefore, the influence of crosstalk becomes the same in all pixels 15, and the output difference between colors can be eliminated.

[0317] Figure 42 is based on Figure 41 The plan layout diagram of the second substrate 52 of the first modified example. Figure 42 As shown, the area where the two unit pixel group areas 40 of the second substrate 52 according to the first modification example are arranged has the following layout configuration, wherein Figure 41 The first and second rows in are swapped and Figure 41 The fourth and fifth rows in are swapped.

[0318] Even in Figure 42 In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the two second source follower circuits 42 arranged in the center of the area where the two unit pixel group areas 40 are arranged. Figure 32 The layout configuration has a similar effect.

[0319] Figure 43 is based on Figure 41 The plan layout diagram of the second substrate 52 of the second modified example. Figure 43 As shown, the area where the two unit pixel group regions 40 are arranged in the second substrate 52 according to the second modification example includes five columns (first to fifth columns) and one row.

[0320] In the first and fifth columns, the gates VB, PC, PC, and VB of the two transistor groups 35 and 36 constituting the current source are arranged in this order along the second direction Y, with a diffusion layer 37 interposed between the gates. In the second and fourth columns, the gate PSEL of the third select transistor 38, the gate SD of the second sampling transistor 34, the gate SR of the first sampling transistor 33, the gate SR of the first sampling transistor 33, the gate SD of the second sampling transistor 34, and the gate PSEL of the third select transistor 38 are arranged in this order along the second direction Y, with a diffusion layer 37 interposed between the gates. In the third column, two well contact regions WC are arranged along the second direction Y. In a row located in the center of the unit pixel group region 40 in the second direction Y, the gate SEL of the second select transistor 44, the gate SF2 of the second source follower circuit 42, the gate SF2 of the second source follower circuit 42, and the gate SEL of the second select transistor 44 are arranged in this order along the first direction X.

[0321] Even in Figure 43 In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the two second source follower circuits 42 arranged in the center of the area where the two unit pixel group areas 40 are arranged. Figure 32 The layout configuration has a similar effect.

[0322] Figure 44 is based on Figure 41 The plan layout diagram of the second substrate 52 of the third modified example. Figure 44 As shown, the region where two unit pixel group regions 40 are arranged in the second substrate 52 according to the third modification has a layout configuration in which the first column and the second column are swapped and the fourth column and the fifth column are swapped.

[0323] Even in Figure 44 In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the two second source follower circuits 42 arranged in the center of the area where the two unit pixel group areas 40 are arranged. Figure 32 The layout configuration has a similar effect.

[0324] Figure 45 is based on Figure 41 The plan layout diagram of the second substrate 52 of the fourth modified example. Figure 45 As shown, the area where the two unit pixel group regions 40 are arranged in the second substrate 52 according to the fourth modification includes five columns (first to fifth columns) and one row.

[0325] In the first and fifth columns, the gates VB, PC, PC, and VB of the transistor groups 35 and 36 constituting the current source are arranged in this order along the second direction Y, with a diffusion layer 37 interposed between the gates. In the second and fourth columns, the gate PSEL of the third selection transistor 38, the gate SD of the second sampling transistor 34, the gate SR of the first sampling transistor 33, the gate SR of the first sampling transistor 33, and the gate SD of the second sampling transistor 34 are arranged in this order along the second direction Y, with a diffusion layer 37 interposed between the gates. In the third column, two well contact regions WC are arranged along the second direction Y. In a row arranged in the center of the unit pixel group region 40 in the second direction, the gate SEL of the second selection transistor 44, the gate SF2 of the second source follower circuit 42, the gate SF2 of the second source follower circuit 42, and the gate SEL of the second selection transistor 44 are arranged along the first direction X.

[0326] Even in Figure 45In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the two second source follower circuits 42 arranged in the center of the area where the two unit pixel group areas 40 are arranged. Figure 32 The layout configuration has a similar effect.

[0327] Figure 46 is based on Figure 41 The plan layout diagram of the second substrate 52 of the fifth modified example. Figure 46 As shown, the area where the two unit pixel group areas 40 are arranged on the second substrate 52 according to the fifth modification has the following layout configuration, wherein Figure 45 The first and second columns in are swapped and Figure 45 The fourth and fifth columns in are swapped.

[0328] Even in Figure 46 In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the two second source follower circuits 42 arranged in the center of the area where the two unit pixel group areas 40 are arranged. Figure 32 The layout configuration has a similar effect.

[0329] Figure 47 is based on Figure 41 The plan layout diagram of the second substrate 52 of the sixth modified example. Figure 47 As shown, the area where the two unit pixel group regions 40 are arranged in the second substrate 52 according to the sixth modification includes five rows (first to fifth rows).

[0330] In the first and fifth rows, the gates VB and PC of the transistor groups 35 and 36 constituting the current source, the well contact region WC, and the gates PC and VB of the transistor groups 35 and 36 constituting the current source are arranged in this order along the first direction X with the diffusion layer 37 interposed between the gates. In the second and fourth rows, the gate PSEL of the third selection transistor 38, the gate SD of the second sampling transistor 34, the gate SR of the first sampling transistor 33, the gate SR of the first sampling transistor 33, the gate SD of the second sampling transistor 34, and the gate PSEL of the third selection transistor 38 are arranged in this order along the first direction X with the diffusion layer 37 interposed between the gates. In the third row, the gate SEL of the second selection transistor 44, the gate SF2 of the second source follower circuit 42, the gate SF2 of the second source follower circuit 42, and the gate SEL of the second selection transistor 44 are arranged in this order along the first direction X.

[0331] Even in Figure 47In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the two second source follower circuits 42 arranged in the center of the area where the two unit pixel group areas 40 are arranged. Figure 32 The layout configuration has a similar effect.

[0332] Figure 48 is based on Figure 41 The plan layout diagram of the second substrate 52 of the sixth modified example. Figure 47 As shown, the area where the two unit pixel group areas 40 are arranged on the second substrate 52 according to the sixth modification has the following layout configuration, wherein Figure 47 The first and second rows in are swapped and Figure 47 The fourth and fifth rows in are swapped.

[0333] Even in Figure 48 In the embodiment, the gate SR of the first sampling transistor 33 and the gate SD of the second sampling transistor 34 are also arranged in a point-symmetric or line-symmetric manner with respect to the gate SF2 of the two second source follower circuits 42 arranged in the center of the area where the two unit pixel group areas 40 are arranged. Figure 32 The layout configuration has a similar effect.

[0334] As described above, due to the bonding of first metal pad 63 and second metal pad 68, first substrate 51 and second substrate 52 transmit and receive signals, and due to the bonding of third metal pad 71 arranged at the end of TSV 70 extending from second substrate 52 toward third substrate 53 and fourth metal pad 75 of third substrate 53, second substrate 52 and third substrate 53 transmit and receive signals. The arrangement position and size of the metal pads are arbitrary.

[0335] Figure 49 is a planar layout diagram showing an example of the bonding position of the first metal pad 63 and the second metal pad 68 and the configuration position of the TSV 70 on the second substrate 52. Although the bonding position of the first metal pad 63 and the second pad is set for each pixel 15, one TSV 70 is set for each unit pixel group area 40 composed of a plurality of (for example, four) pixels 15. Therefore, for example, Figure 49 As shown, it is conceivable that the bonding position of the first metal pad 63 and the second metal pad 68 can be arranged in the center of the region of each pixel 15 , and the TSV 70 can be arranged in the center of the boundary edge in the first direction X of the unit pixel group region 40 . Figure 49 The configuration positions and sizes of the first metal pad 63 , the second metal pad 68 , and the TSV 70 are shown as examples, and various modifications may be employed.

[0336] The specific circuit structure of the pixel 15 and the pixel circuit is not limited to Figure 3 or Figure 15 The circuit configuration shown is applicable to various circuit configurations.

[0337] Figure 50 1 is a circuit diagram of a pixel 15 , a first pixel circuit 16 , and a second pixel circuit 17 according to a first modification example. Figure 50 and Figure 3 and Figure 21 The difference lies in the circuit configuration of the first pixel circuit 16. Note that although Figure 50 The drain transistor 30 and the conversion efficiency switching transistor 27 in the pixel 15 are omitted, but transistors can be provided, and the configuration of the pixel 15 is the same as that of the pixel 15. Figure 3 The same as in.

[0338] In addition to the first and second capacitance elements 31 and 32, the first and second sampling transistors 33 and 34, and the transistor groups 35 and 36 constituting the current source, Figure 50 The first pixel circuit 16 further includes a sampling and holding transistor 83 .

[0339] The sample-and-hold transistor 83 is connected between the output node n1 of the pixel 15 and the output node n2 of the first pixel circuit 16. The first capacitor 31 and the first sampling transistor 33 are connected in series between a reference voltage node (e.g., a power supply voltage node) and the output node n2 of the first pixel circuit 16. The second capacitor 32 and the second sampling transistor 34 are connected in series between the reference voltage node and the output node n2 of the first pixel circuit 16.

[0340] Figure 51 1 is a circuit diagram of a pixel 15 , a first pixel circuit 16 , and a second pixel circuit 17 according to a second modification example. Figure 51 Including circuit structure and Figure 3 The pixel 15 and circuit configuration are substantially the same as Figure 3 Different first pixel circuits 16 .

[0341] Figure 51 The illustrated first pixel circuit 16 includes a first sampling transistor 33 , a second sampling transistor 34 , a first capacitance element 31 , and a second capacitance element 32 .

[0342] The first sampling transistor 33 and the second capacitive element 32 are connected in series between the output node n1 of the pixel 15 and the output node n2 of the first pixel circuit 16. The first capacitive element 31 is connected between a reference voltage node (e.g., a power supply voltage node) and the output node n2 of the first pixel circuit 16. The second sampling transistor 34 is connected between the reference voltage node and the output node n2 of the first pixel circuit 16.

[0343] Figure 52 1 is a circuit diagram of a pixel 15 , a first pixel circuit 16 , and a second pixel circuit 17 according to a third modification example. Figure 52 Including circuit structure and Figure 3 The pixel 15 and circuit structure are basically the same as Figure 3 Different first pixel circuits 16 and second pixel circuits 17 .

[0344] Figure 52 The first pixel circuit 16 in the embodiment includes a transistor 35 constituting a current source connected between the output node n1 of the pixel 15 and a reference voltage node (e.g., a ground node), a first sampling transistor 33 and a second sampling transistor 34 connected in cascade between the output node n1 of the pixel 15 and the output node n2 of the first pixel circuit 16, a first capacitor 31 connected between a connection node of the first sampling transistor 33 and the second sampling transistor 34 and a reference voltage node (e.g., a ground node), and a second capacitor 32 connected between the output node n2 of the first pixel circuit 16 and the reference voltage node (e.g., a ground node).

[0345] Figure 52 The second pixel circuit 17 in FIG. 1 has a second source follower circuit 42 (a second amplifying transistor 43) and a second selecting transistor 44 connected in cascade between a reference voltage node (eg, a power supply voltage node) and a vertical signal line VSL. Figure 53 The second pixel circuit 17 does not have Figure 3 The second reset transistor 41 in FIG. 4 is omitted, but a second reset transistor 41 may be added.

[0346] Figure 53 1 is a circuit diagram of a pixel 15 , a first pixel circuit 16 , and a second pixel circuit 17 according to a fourth modification example. Figure 52 Including circuit structure and Figure 3 The pixel 15 and circuit configuration are substantially the same as Figure 3 Different first pixel circuits 16 .

[0347] Figure 53 The first pixel circuit 16 has a transistor 35 forming a current source connected between the output node n1 of the pixel 15 and a reference voltage node (for example, a ground node), a first capacitor element 31 connected between the output node n1 of the pixel 15 and the output node n2 of the first pixel circuit 16, and a second capacitor element 32 connected between the output node n2 of the first pixel circuit 16 and a reference voltage node (for example, a ground node).

[0348] Although according to Figure 3 、 Figure 21The first pixel circuit 16 of the first to fourth modified examples includes a current source connected between the output node n1 of the pixel 15 and a reference voltage node (e.g., a ground node), but the current source may be formed by the transistor group 35 and 36 or by a single transistor 35. Furthermore, whether or not to provide the conversion efficiency switching transistor 27 and the drain transistor 30 in the pixel 15 is also optional.

[0349] although Figure 5 , the light detection device 3 is shown as having a three-layer structure consisting of a first substrate 51 to a third substrate 53. However, the light detection device 2 may also have a two-layer structure having a first substrate 51 and a second substrate. In this case, for example, the plurality of pixels 15, the plurality of first pixel circuits 16, and the plurality of second pixel circuits 17 are arranged on the first substrate 51, and the logic circuit 54 is arranged on the second substrate 52.

[0350] As described above, the light detection device 3 according to this embodiment employs a global shutter method and includes first and second capacitors 31 and 32, which simultaneously initiate exposure for all pixels 15 and hold a voltage signal based on the charge accumulated in the photoelectric conversion element 21. The light detection device 3 according to this embodiment is constructed by stacking two or three substrates. There is a risk that the gates of the first and second sampling transistors 33 and 34, which control the voltage signal held in the first and second capacitors 31 and 32, may cause crosstalk in the channel directly below the gate SF2 of the second source follower circuit 42 in the subsequent stage. In particular, when multiple pixels 15 and multiple first pixel circuits 16 share a single second pixel circuit 17, if the distances from the gates SR and SD of the first and second sampling transistors 33 and 34 to the gate SF2 of the second source follower circuit 42 vary for each shared pixel, the magnitude of the crosstalk also varies for each pixel, potentially leading to degradation in image quality. Taking the above into consideration, in the present embodiment, when a plurality of pixels 15 and a plurality of first pixel circuits 16 share a single second pixel circuit 17, the gates of the plurality of first sampling transistors 33 and the second sampling transistors 34 are arranged at positions that are point-symmetrical or line-symmetrical with respect to the gate of the second source follower circuit 42. Therefore, crosstalk applied by the first sampling transistors 33 and the second sampling transistors 34 of each shared pixel to the channel immediately below the gate SF2 of the second source follower circuit 42 can be made uniform, and improved image quality can be achieved.

[0351] <Application examples for mobile objects>

[0352] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure is implemented as a device to be installed on any type of mobile object such as an automobile, an electric car, a hybrid electric car, a motorcycle, a bicycle, a personal mobility device, an airplane, an unmanned aerial vehicle, a ship, and a robot.

[0353] Figure 54 This is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile object control system to which the technology according to the embodiment of the present disclosure can be applied.

[0354] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 54 In the illustrated example, vehicle control system 12000 includes a drive system control unit 12010, a main body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, as functional components of integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are illustrated.

[0355] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device such as an internal combustion engine or a drive motor that generates the vehicle's drive force, a drive force transmission mechanism that transmits the drive force to the wheels, a steering mechanism that adjusts the vehicle's steering angle, and a braking device that generates braking force for the vehicle.

[0356] The main system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs. For example, the main system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, and various lights such as headlights, taillights, brake lights, turn signals, and fog lights. In this case, instead of pressing buttons, radio waves or signals from various switches transmitted from a portable device can be input to the main system control unit 12020. The main system control unit 12020 receives the input of radio waves or signals and controls the vehicle's door locks, power windows, lights, and the like.

[0357] The vehicle exterior information detection unit 12030 detects information related to the exterior of the vehicle, including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the vehicle exterior and receive the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can detect objects such as people, cars, obstacles, signs, and text on the road, or measure the distance to such objects.

[0358] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as information related to the measured distance. The light received by the imaging unit 12031 can be visible light or invisible light such as infrared light.

[0359] The in-vehicle information detection unit 12040 detects information related to the vehicle interior. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the driver's condition. For example, the driver state detection unit 12041 includes a camera that captures an image of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration, or determine whether the driver has fallen asleep while sitting.

[0360] The microcomputer 12051 can calculate control target values ​​for the driving force generation device, the steering mechanism, or the braking device based on information related to the interior and exterior of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and can output control instructions to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to implement functions of an advanced driver assistance system (ADAS) including collision avoidance or collision mitigation, following driving based on a following distance, speed maintenance driving, collision warning, lane departure warning, and the like.

[0361] In addition, the microcomputer 12051 can coordinate control by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the outside or inside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, so as to achieve automatic driving in which the vehicle travels autonomously without relying on the driver's operation.

[0362] In addition, the microcomputer 12051 can output control instructions to the main system control unit 12020 based on information related to the exterior of the vehicle obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 controls the headlights based on the positions of the preceding vehicle or oncoming vehicles detected by the exterior information detection unit 12030 to perform coordinated control to achieve glare prevention, such as switching the high beam to the low beam.

[0363] The sound / image output unit 12052 transmits at least one of a sound and an image output signal to an output device capable of visually or auditorily notifying a vehicle occupant or information outside the vehicle. Figure 54 In the example of FIG, as output devices, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are shown. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0364] Figure 55 This is a diagram showing an example of the installation position of the imaging unit 12031.

[0365] exist Figure 55 , the imaging unit 12031 includes imaging units 12101 , 12102 , 12103 , 12104 and 12105 .

[0366] Imaging units 12101, 12102, 12103, 12104, and 12105 are located, for example, at the front of the vehicle, in the sideview mirrors, rear bumper, and rear doors, as well as on the upper side of the windshield inside the vehicle. Imaging unit 12101 located in the front of the vehicle and imaging unit 12105 located on the upper side of the windshield inside the vehicle primarily capture images of the front of the vehicle 12100. Imaging units 12102 and 12103 located in the sideview mirrors primarily capture images of the sides of the vehicle 12100. Imaging unit 12104 located in the rear bumper or rear door primarily captures images of the rear of the vehicle 12100. Imaging unit 12105 located on the upper side of the windshield inside the vehicle primarily detects vehicles ahead, pedestrians, obstacles, traffic signals, traffic signs, lanes, and the like.

[0367] By the way, Figure 55 Examples of the imaging ranges of imaging units 12101 to 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101, located at the front of the vehicle. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103, respectively, located at the side mirrors. Imaging range 12114 represents the imaging range of imaging unit 12104, located at the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, a bird's-eye view image of vehicle 12100 can be obtained.

[0368] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or an imaging element having pixels for phase difference detection.

[0369] For example, based on the distance information obtained from imaging units 12101-12104, microcomputer 12051 can determine the distance to each 3D object within imaging ranges 12111-12114 and the temporal change in that distance (relative speed to vehicle 12100), thereby extracting the 3D object located on the travel path of vehicle 12100, particularly the closest 3D object, traveling in the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher), as the leading vehicle. Furthermore, microcomputer 12051 can set a predetermined distance between vehicles in front of the leading vehicle and perform automatic braking control (including tracking stop control) and automatic acceleration control (including tracking start control). This enables coordinated control such as automatic driving, which allows the vehicle to travel autonomously without relying on driver input.

[0370] For example, based on the distance information obtained from the imaging units 12101-12104, the microcomputer 12051 can classify 3D object data into 3D data for two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other 3D objects, extract the classified 3D object data, and use the extracted 3D object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as those that are visually recognizable by the driver of the vehicle 12100 and those that are difficult for the driver to visually recognize. The microcomputer 12051 then determines a collision risk, indicating the degree of risk of collision with each obstacle. If the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 and display unit 12062, or initiates forced deceleration or evasive steering via the drive system control unit 12010. The microcomputer 12051 can assist in driving to avoid collisions.

[0371] At least one of the imaging units 12101-12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether the pedestrian is present in the images captured by the imaging units 12101-12104. For example, pedestrian identification is performed by extracting feature points from the images captured by the imaging units 12101-12104, which are infrared cameras, and performing pattern matching on a series of feature points indicating the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101-12104 and thus identifies the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to display a rectangular outline superimposed on the identified pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon indicating the pedestrian at a desired location.

[0372] An example of a mobile control system to which the technology of the present disclosure can be applied has been described above. The technology of the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, the light detection device 3 according to this embodiment can be applied to the imaging unit 12031. By applying the technology of the present disclosure to the imaging unit 12031, a clearer captured image can be obtained, thereby reducing driver fatigue.

[0373] <Application Examples of Endoscopic Surgery Systems>

[0374] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be applied to an endoscopic surgery system.

[0375] Figure 56 1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0376] exist Figure 56 , a state is shown in which an operator (doctor) 11131 is performing surgery on a patient 11132 on a bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy instrument 11112, a support arm device 11120 on which the endoscope 11100 is supported, and a cart 11200 on which various instruments used for endoscopic surgery are mounted.

[0377] Endoscope 11100 includes a lens barrel 11101 having an area of ​​a predetermined length from its distal end to be inserted into a body cavity of a patient 11132, and a camera 11102 connected to the proximal end of lens barrel 11101. In the example shown in the drawings, endoscope 11100 including a hard scope including rigid lens barrel 11101 is shown. However, endoscope 11100 may also include a soft scope including flexible lens barrel 11101.

[0378] The lens barrel 11101 has an opening at its distal end into which the objective lens is fitted. A light source device 11203 is connected to the endoscope 11100 so that light generated by the light source device 11203 is guided to the distal end of the lens barrel via a light guide extending inside the lens barrel 11101 and irradiated toward an observation object in the body cavity of the patient 11132 via the objective lens. Note that the endoscope 11100 may be a straight-view endoscope, or may be an oblique endoscope or a side-view endoscope.

[0379] The camera head 11102 is equipped with an optical system and an imaging element. Light reflected from the observation object (observation light) is focused onto the imaging element through the optical system. The observation light is photoelectrically converted by the imaging element to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observed image. The image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0380] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), and the like, and comprehensively controls the operations of the endoscope 11100 and the display device 11202. In addition, for example, the CCU 11201 receives an image signal from the camera 11102 and performs various types of image processing such as development processing (demosaic processing) to display an image based on the image signal.

[0381] The display device 11202 displays thereon an image based on an image signal on which image processing has been performed by the CCU 11201 under the control of the CCU 11201 .

[0382] For example, the light source device 11203 includes a light source such as a light emitting diode (LED), and supplies irradiation light used when imaging a surgical area to the endoscope 11100 .

[0383] The input device 11204 is an input interface for the endoscopic surgery system 11000. The user can input various types of information or instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user can input instructions to change the imaging conditions (such as the type of irradiation light, magnification, and focal length) of the endoscope 11100.

[0384] The treatment instrument control device 11205 controls the driving of the energy device 11112 for purposes such as cauterization or incision of tissue and sealing of blood vessels. The pneumoperitoneum device 11206 injects gas into the body cavity of the patient 11132 via the pneumoperitoneum tube 11111 to inflate the cavity, ensuring the field of view of the endoscope 11100 and ensuring the operator's working space. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats, such as text, images, and graphics.

[0385] Note that, for example, the irradiation light supplied to the light source device 11203 of the endoscope 11100 when photographing the surgical area may include a white light source such as an LED, a laser light source, or a combination thereof. In the case where the white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and output timing of each color (each wavelength) can be controlled with high precision, the white balance adjustment of the captured image can be performed by the light source device 11203. In addition, in this case, if the laser light from each RGB laser light source is emitted onto the observed object in a time-division manner and the drive of the imaging element of the camera 11102 is controlled in synchronization with the emission timing. Images corresponding to the RGB colors can be captured in a time-division manner. According to this method, a color image can be obtained even if a color filter is not provided for the imaging element.

[0386] Furthermore, the light source device 11203 can be controlled so that the intensity of the light to be output is changed between each predetermined timing. By controlling the driving of the imaging element of the camera 11102 in synchronization with the timing of the change in light intensity to acquire and synthesize images in a time-division manner, it is possible to generate a high dynamic range image without underexposed shadows or overexposed highlights.

[0387] In addition, the light source device 11203 can supply light of a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by using the wavelength dependence of light absorption in body tissue to emit light having a narrow band compared to the irradiation light (i.e., white light) during ordinary observation, narrow-band observation (narrow-band imaging) is performed to capture predetermined tissues such as blood vessels on the surface of the mucosa with high contrast. In addition, in special light observation, fluorescence observation is performed to obtain an image by fluorescence generated by emitting excitation light. In fluorescence observation, for example, it is possible to irradiate body tissue with excitation light to observe fluorescence from the body tissue (autofluorescence observation), or it is possible to locally inject a reagent such as indocyanine green (ICG) into the body tissue and emit excitation light corresponding to the fluorescence wavelength of the reagent to obtain a fluorescence image. The light source device 11203 can supply narrow-band light and / or excitation light suitable for the above-mentioned special light observation.

[0388] Figure 57It shows Figure 56 A block diagram showing an example of the functional configuration of the camera 11102 and the CCU 11201 is shown.

[0389] The camera 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are connected via a transmission cable 11400 for communication with each other.

[0390] The lens unit 11401 is an optical system provided at a connection portion with the lens barrel 11101. Observation light received from the distal end of the lens barrel 11101 is guided to the camera 11102 and incident on the lens unit 11401. The lens unit 11401 includes a combination of multiple lenses including a zoom lens and a focus lens.

[0391] The number of imaging elements included in the imaging unit 11402 can be one (single-board type) or multiple (multi-board type). When the imaging unit 11402 is constructed as a multi-board type, for example, image signals corresponding to each RGB are generated by the imaging element, and a color image can be obtained by synthesizing the image signals. Alternatively, the imaging unit 11402 can also be constructed to have a pair of imaging elements for acquiring image signals for the right eye and the left eye for three-dimensional (3D) display. If a 3D display is performed, the operator 11131 can more accurately grasp the depth of the body tissue in the surgical site. Note that when the imaging unit 11402 is constructed as a multi-board type, a plurality of lens units 11401 are provided corresponding to the respective imaging elements.

[0392] In addition, the imaging portion 11402 does not necessarily have to be provided on the camera head 11102. For example, the imaging portion 11402 may be provided just behind the objective lens inside the lens barrel 11101.

[0393] The driving section 11403 includes an actuator and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera control section 11405. Therefore, the magnification and focus of the image captured by the imaging section 11402 can be appropriately adjusted.

[0394] The communication section 11404 includes a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication section 11404 transmits the image signal acquired from the imaging section 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0395] In addition, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and supplies the control signal to the camera control unit 11405. The control signal includes information related to imaging conditions, for example, information specifying the frame rate of the captured image, information specifying the exposure value during imaging, and / or information specifying the magnification and focus of the captured image.

[0396] Note that imaging conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user or may be automatically set based on the acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, an automatic exposure (AE) function, an automatic focus (AF) function, and an automatic white balance (AWB) function are incorporated into the endoscope 11100.

[0397] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal received from the CCU 11201 via the communication unit 11404 .

[0398] The communication section 11411 includes a communication device for transmitting and receiving various types of information to and from the camera 11102. The communication section 11411 receives an image signal transmitted from the camera 11102 via the transmission cable 11400.

[0399] Furthermore, the communication unit 11411 transmits a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0400] The image processing unit 11412 performs various types of image processing on the image signal in the RAW data format transmitted from the camera 11102 .

[0401] The control unit 11413 performs various types of control related to imaging of the surgical area, etc., performed by the endoscope 11100 and display of captured images obtained by imaging the surgical area, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera 11102 .

[0402] Furthermore, the control unit 11413 controls the display device 11202 to display a captured image of the surgical area, etc., based on the image signal processed by the image processing unit 11412. In this case, the control unit 11413 can use various image recognition technologies to identify various objects within the captured image. For example, the control unit 11413 can detect the edge shape and / or color of objects within the captured image to identify surgical instruments such as forceps, specific living body parts, bleeding, and fog when using the energy device 11112. When controlling the display device 11202 to display the captured image, the control unit 11413 can use the recognition results to cause the display device 11202 to display various types of surgical support information superimposed on the image of the surgical area. When this superimposed surgical support information is displayed and presented to the operator 11131, the burden on the operator 11131 can be reduced, allowing the operator 11131 to perform the surgery reliably.

[0403] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 to each other is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable for both electrical signals and optical communication.

[0404] Here, in the example shown in the drawing, communication is performed by wired communication using the transmission cable 11400, but communication between the camera 11102 and the CCU 11201 may be performed by wireless communication.

[0405] The above describes an example of an endoscopic surgical system to which the technology of the present disclosure can be applied. For example, the technology of the present disclosure can be applied to the endoscope 11100, camera 11102 (its imaging unit 11402), CCU 11201 (its image processing unit 11412), and the like, among the aforementioned components. Specifically, the light detection device 3 according to this embodiment can be applied to the imaging unit 11402. By applying the technology of the present disclosure to the imaging unit 11402, a clearer image of the surgical site can be obtained, allowing the surgeon to more reliably confirm the surgical site.

[0406] Note that although the description here is given taking an endoscopic surgery system as an example, the technology according to the present disclosure can be applied to, for example, a microscope surgery system.

[0407] Note that the present technology can be configured as follows.

[0408] (1) A light detection device comprising:

[0409] a plurality of pixels each having a photoelectric conversion element configured to accumulate charge according to an amount of incident light;

[0410] a plurality of first pixel circuits configured to hold voltage signals according to charges accumulated in the plurality of pixels at the same timing;

[0411] a plurality of second pixel circuits shared by every two or more first pixel circuits among the plurality of first pixel circuits and configured to sequentially read out voltage signals held by the two or more first pixel circuits and generate pixel signals; and

[0412] a logic circuit configured to perform signal processing on a plurality of pixel signals generated by the plurality of second pixel circuits, wherein

[0413] Each of the plurality of first pixel circuits comprises:

[0414] a first capacitive element configured to hold a voltage signal output from a pixel in a state in which the charge of the first floating diffusion region of the corresponding pixel has been initialized;

[0415] a second capacitance element configured to hold a voltage signal output from a pixel in a state in which the accumulated charge of the photoelectric conversion element has been transferred to the first floating diffusion region of the corresponding pixel;

[0416] a first transistor configured to switch whether to transfer the charge held in the first capacitance element to a second floating diffusion region shared by the two or more first pixel circuits; and

[0417] a second transistor configured to switch whether to transfer the charge held in the second capacitance element to the second floating diffusion region,

[0418] Each of the plurality of second pixel circuits includes a source follower circuit having a third transistor configured to generate a pixel signal according to the charge of the second floating diffusion region, and

[0419] The two or more first transistors and the two or more second transistors included in the two or more first pixel circuits are arranged around one third transistor in a point-symmetrical or line-symmetrical manner.

[0420] (2) The light detection device according to (1), comprising:

[0421] A unit pixel group region having two or more first pixel circuits and one second pixel circuit for every two or more pixels, wherein

[0422] The unit pixel group region includes a third transistor, and the two or more first transistors and the two or more second transistors that are arranged in a point-symmetric or line-symmetric manner with respect to the third transistor.

[0423] (3) The light detection device according to (2), wherein

[0424] The third transistor is arranged in the center of the unit pixel group area, and

[0425] The gates of the two or more first transistors and the two or more second transistors are arranged at equal distances from the gate of the third transistor.

[0426] (4) The light detection device according to (2) or (3), wherein

[0427] A gate length direction of the third transistor disposed in the unit pixel group region is parallel to gate length directions of the two or more first transistors and the two or more second transistors.

[0428] (5) The light detection device according to (2) or (3), wherein

[0429] A gate length direction of the third transistor disposed in the unit pixel group region intersects with gate length directions of the two or more first transistors and the two or more second transistors.

[0430] (6) The light detection device according to any one of (2) to (5), wherein

[0431] The unit pixel group area is a rectangular area arranged in a first direction and a second direction intersecting the first direction.

[0432] The unit pixel group area includes:

[0433] a first region, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along a first direction; and

[0434] a second region arranged apart from the first region in the second direction, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along the first direction;

[0435] The third transistor is arranged between the first region and the second region which are arranged to be separated from each other in the second direction, and

[0436] A gate length direction of the first transistor, the second transistor, and the third transistor is a first direction.

[0437] (7) The light detection device according to (6), wherein

[0438] Each of the plurality of second pixel circuits comprises:

[0439] a fourth transistor configured to output a pixel signal to a signal line; and

[0440] a fifth transistor configured to switch whether to initialize the charge in the second floating diffusion region, and

[0441] The unit pixel group area includes:

[0442] a third region in which the fourth transistor, the third transistor, and the fifth transistor are arranged on one axis along the first direction, and

[0443] The third region is arranged between the first region and the second region which are arranged to be separated from each other in the second direction.

[0444] (8) The light detection device according to (6), wherein

[0445] Each of the plurality of first pixel circuits includes a sixth transistor and a seventh transistor configured to precharge a first capacitance element and a second capacitance element,

[0446] The unit pixel group area includes:

[0447] a fourth region in which two or more sixth transistors and two or more seventh transistors are arranged on one axis along the first direction; and

[0448] a fifth region arranged apart from the fourth region in the second direction, wherein two or more sixth transistors and two or more seventh transistors are arranged on one axis along the first direction, and

[0449] The fourth region is arranged between the fourth region and the fifth region which are arranged to be separated from each other in the second direction.

[0450] (9) The light detection device according to (6), wherein

[0451] The unit pixel group area is a rectangular area arranged in a first direction and a second direction intersecting the first direction.

[0452] The unit pixel group area includes:

[0453] a first region, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along a second direction; and

[0454] a second region arranged apart from the first region in the first direction, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along the second direction;

[0455] The third transistor is arranged between the first region and the second region which are arranged to be separated from each other in the first direction.

[0456] The channels of the first transistor and the second transistor extend in the second direction, and

[0457] A channel of the third transistor extends in the first direction.

[0458] (10) The light detection device according to (9), wherein

[0459] The diffusion layers of the third transistor are arranged on both sides in the second direction with the channel of the third transistor interposed therebetween.

[0460] (11) The light detection device according to (5), wherein

[0461] Each of the plurality of second pixel circuits comprises:

[0462] a fourth transistor configured to output a pixel signal to a signal line; and

[0463] a fifth transistor configured to switch whether to initialize the charge in the second floating diffusion region,

[0464] The unit pixel group area is a rectangular area arranged in a first direction and a second direction intersecting the first direction.

[0465] The unit pixel group area includes:

[0466] a first region, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along a second direction;

[0467] a second region arranged apart from the first region in the first direction, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along the first direction; and

[0468] a third region in which the fourth transistor, the third transistor, and the fifth transistor are arranged along the first direction, and

[0469] The third region is configured to separate the first region and the second region, which are spaced apart from each other in the first direction, at a central portion of the unit pixel group region in the second direction.

[0470] (12) The light detection device according to (5), wherein

[0471] Each of the plurality of first pixel circuits includes a sixth transistor and a seventh transistor configured to precharge a first capacitance element and a second capacitance element,

[0472] Each of the plurality of second pixel circuits comprises:

[0473] a fourth transistor configured to output a pixel signal to a signal line; and

[0474] a fifth transistor configured to switch whether to initialize the charge in the second floating diffusion region,

[0475] The unit pixel group area is a rectangular area arranged in a first direction and a second direction intersecting the first direction.

[0476] The unit pixel group area includes:

[0477] a first region, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along a second direction;

[0478] a second region arranged apart from the first region in the first direction, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along the first direction;

[0479] a third region, wherein the fourth transistor, the third transistor, and the fifth transistor are arranged along the first direction;

[0480] a fourth region in which two or more sixth transistors and two or more seventh transistors are arranged along the first direction; and

[0481] a fifth region arranged apart from the fourth region in the second direction, wherein two or more sixth transistors and two or more seventh transistors are arranged along the first direction, and

[0482] The third region is arranged between the fourth region and the fifth region, which are arranged to be separated from each other in the second direction.

[0483] (13) The light detection device according to any one of (2) to (12), wherein

[0484] The size of the third transistor is larger than that of the first transistor and the second transistor.

[0485] (14) The light detection device according to any one of (2) to (13), wherein

[0486] The unit pixel group region includes a plurality of third transistors arranged in a central portion, and the two or more first transistors and the two or more second transistors arranged in a point-symmetric or line-symmetric manner with respect to the plurality of third transistors.

[0487] (15) The light detection device according to any one of (2) to (13), wherein

[0488] The unit pixel group region includes two first pixel circuits in each of a first direction and a second direction, and includes one second pixel circuit, and

[0489] The unit pixel group region includes two first transistors and two second transistors that are arranged in a point-symmetrical or line-symmetrical manner with respect to a third transistor in a central portion.

[0490] (16) The light detection device according to any one of (2) to (13), wherein

[0491] The unit pixel group region includes one first pixel circuit in the first direction, two first pixel circuits in the second direction, and one second pixel circuit, and

[0492] The two unit pixel group regions arranged in the first direction have two first transistors and two second transistors arranged in a point-symmetrical or line-symmetrical manner with respect to the two third transistors in the center.

[0493] (17) The light detection device according to any one of (1) to (16), comprising:

[0494] a first substrate on which the plurality of pixels are arranged; and

[0495] The second substrate is stacked on the first substrate and has the plurality of first pixel circuits, the plurality of second pixel circuits, and the logic circuit arranged thereon.

[0496] (18) The light detection device according to any one of (1) to (16), comprising:

[0497] a first substrate on which the plurality of pixels are arranged;

[0498] a second substrate stacked on the first substrate and having the plurality of first pixel circuits and the plurality of second pixel circuits arranged thereon, and

[0499] A third substrate is stacked on the second substrate and has the logic circuit configured thereon, wherein

[0500] The first substrate has a plurality of first metal pads arranged opposite to the second substrate and connected to the output nodes of the plurality of pixels.

[0501] The second substrate has

[0502] a semiconductor layer disposed opposite to the third substrate,

[0503] a plurality of second metal pads bonded to the plurality of first metal pads,

[0504] a plurality of first via holes configured to pass through the semiconductor layer from the plurality of second pixel circuits, and

[0505] a plurality of third metal pads configured to be opposite to the third substrate and connected to the plurality of first vias,

[0506] The third substrate has a plurality of fourth metal pads bonded to the third metal pads, and

[0507] Each of the plurality of first via holes is arranged for every two or more pixels.

[0508] (19) The light detection device according to any one of (1) to (18), wherein

[0509] Each of the plurality of pixels has

[0510] a third capacitance element configured to accumulate a portion of the accumulated charge of the photoelectric conversion element;

[0511] an eighth transistor configured to switch whether to accumulate a portion of the accumulated charge of the photoelectric conversion element in a third capacitance element; and

[0512] A ninth transistor is configured to switch whether to discard the accumulated charge of the photoelectric conversion element.

[0513] (20) An electronic device comprising:

[0514] a light detection device configured to generate an image according to an amount of incident light; and

[0515] a processing unit configured to process the image, wherein

[0516] The light detection device comprises:

[0517] a plurality of pixels each having a photoelectric conversion element configured to accumulate charge according to an amount of incident light;

[0518] a plurality of first pixel circuits configured to hold voltage signals according to charges accumulated in the plurality of pixels at the same timing;

[0519] a plurality of second pixel circuits shared by every two or more first pixel circuits among the plurality of first pixel circuits and configured to sequentially read out voltage signals held by the two or more first pixel circuits and generate pixel signals; and

[0520] a logic circuit configured to perform signal processing on a plurality of pixel signals generated by the plurality of second pixel circuits, wherein

[0521] Each of the plurality of first pixel circuits comprises:

[0522] a first capacitive element configured to hold a voltage signal output from a pixel in a state in which the charge of the first floating diffusion region of the corresponding pixel has been initialized;

[0523] a second capacitance element configured to hold a voltage signal output from a pixel in a state in which the accumulated charge of the photoelectric conversion element has been transferred to the first floating diffusion region of the corresponding pixel;

[0524] a first transistor configured to switch whether to transfer the charge held in the first capacitance element to a second floating diffusion region shared by the two or more first pixel circuits; and

[0525] a second transistor configured to switch whether to transfer the charge held in the second capacitance element to the second floating diffusion region,

[0526] Each of the plurality of second pixel circuits includes a source follower circuit having a third transistor configured to generate a pixel signal according to the charge of the second floating diffusion region, and

[0527] The two or more first transistors and the two or more second transistors included in the two or more first pixel circuits are arranged around one third transistor in a point-symmetrical or line-symmetrical manner.

[0528] The present disclosure is not limited to the above-described embodiments and may include various modifications that can be conceived by those skilled in the art, and the advantageous effects of the present disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions may be made without departing from the conceptual ideas and intentions of the present disclosure as defined in the claims and their equivalents.

[0529] [Reference Signs List]

[0530] 1 Electronic equipment

[0531] 2 Imaging lens

[0532] 3. Light detection device

[0533] 3. Light Detection Device According to the Embodiment

[0534] 4Image processing unit

[0535] 5. Records Department

[0536] 6. Control Unit

[0537] 11 Pixel array unit

[0538] 12 vertical drive unit

[0539] 13 and column signal processing unit

[0540] 13-column signal processing unit

[0541] 14 Timing control unit

[0542] 15 pixels

[0543] 16 first pixel circuit

[0544] 17 Second pixel circuit

[0545] 21 Photoelectric conversion element

[0546] 22 pass transistors

[0547] 23 First reset transistor

[0548] 24 First source follower circuit

[0549] 25 first amplifier transistor

[0550] 26 first selection transistor

[0551] 27 Conversion efficiency switching transistor

[0552] 28 Charge retention unit

[0553] 29 voltage switch

[0554] 30-emission transistor

[0555] 31 first capacitor element

[0556] 32 second capacitor element

[0557] 33 first sampling transistor

[0558] 34 Second sampling transistor

[0559] 35 transistor groups

[0560] 36 transistor groups

[0561] 37 diffusion layer

[0562] 41 Second reset transistor

[0563] 42 Second source follower circuit

[0564] 43 second amplifier transistor

[0565] 44 second selection transistor

[0566] 45 current source

[0567] 50 first insulation layer

[0568] 51 first substrate

[0569] 52 second substrate

[0570] 53 third substrate

[0571] 54 logic circuits

[0572] 55 peripheral circuits

[0573] 56 first semiconductor layer

[0574] 57 first wiring layer

[0575] 58 color filters

[0576] 59 on-chip lenses

[0577] 60 light-shielding wall

[0578] 61 Fixed charge membrane

[0579] 62 concave-convex structure

[0580] 63 first metal pad

[0581] 64 second semiconductor layer

[0582] 65 second wiring layer

[0583] 66 third wiring layer

[0584] 67 second insulation layer

[0585] 68 second metal pad

[0586] 70 through holes

[0587] 71 third metal pad

[0588] 72 third semiconductor layer

[0589] 73 fourth wiring layer

[0590] 74 third insulation layer

[0591] 75 fourth metal pad

[0592] 80 Sample and hold transistor

[0593] 81 Charge retention unit

[0594] 82 conversion efficiency switching transistor

[0595] 83 Sample and hold transistor

Claims

1. A light detection device, comprising: a plurality of pixels each having a photoelectric conversion element configured to accumulate charge according to an amount of incident light; a plurality of first pixel circuits configured to hold voltage signals according to charges accumulated in the plurality of pixels at the same timing; a plurality of second pixel circuits shared by every two or more first pixel circuits among the plurality of first pixel circuits and configured to sequentially read out voltage signals held by the two or more first pixel circuits and generate pixel signals; and a logic circuit configured to perform signal processing on a plurality of pixel signals generated by the plurality of second pixel circuits, wherein Each of the plurality of first pixel circuits comprises: a first capacitive element configured to hold a voltage signal output from a pixel in a state in which the charge of the first floating diffusion region of the corresponding pixel has been initialized; a second capacitance element configured to hold a voltage signal output from a pixel in a state in which the accumulated charge of the photoelectric conversion element has been transferred to the first floating diffusion region of the corresponding pixel; a first transistor configured to switch whether to transfer the charge held in the first capacitance element to a second floating diffusion region shared by the two or more first pixel circuits; and a second transistor configured to switch whether to transfer the charge held in the second capacitance element to the second floating diffusion region, Each of the plurality of second pixel circuits includes a source follower circuit having a third transistor configured to generate a pixel signal according to the charge of the second floating diffusion region, and The two or more first transistors and the two or more second transistors included in the two or more first pixel circuits are arranged around one third transistor in a point-symmetrical or line-symmetrical manner.

2. The light detection device according to claim 1, comprising: A unit pixel group region having two or more first pixel circuits and one second pixel circuit for every two or more pixels, wherein The unit pixel group region includes a third transistor, and the two or more first transistors and the two or more second transistors that are arranged in a point-symmetric or line-symmetric manner with respect to the third transistor.

3. The light detection device according to claim 2, wherein The third transistor is arranged in the center of the unit pixel group area, and The gates of the two or more first transistors and the two or more second transistors are arranged at equal distances from the gate of the third transistor.

4. The light detection device according to claim 2, wherein A gate length direction of the third transistor disposed in the unit pixel group region is parallel to gate length directions of the two or more first transistors and the two or more second transistors.

5. The light detection device according to claim 2, wherein A gate length direction of the third transistor disposed in the unit pixel group region intersects with gate length directions of the two or more first transistors and the two or more second transistors. The light detection device according to claim 2 , wherein The unit pixel group area is a rectangular area arranged in a first direction and a second direction intersecting the first direction. The unit pixel group area includes: a first region, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along a first direction; and a second region arranged apart from the first region in the second direction, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along the first direction; The third transistor is arranged between the first region and the second region which are arranged to be separated from each other in the second direction, and A gate length direction of the first transistor, the second transistor, and the third transistor is a first direction.

7. The light detection device according to claim 6, wherein Each of the plurality of second pixel circuits comprises: a fourth transistor configured to output a pixel signal to a signal line; and a fifth transistor configured to switch whether to initialize the charge in the second floating diffusion region, and The unit pixel group area includes: a third region in which the fourth transistor, the third transistor, and the fifth transistor are arranged on one axis along the first direction, and The third region is arranged between the first region and the second region which are arranged to be separated from each other in the second direction.

8. The light detection device according to claim 6, wherein Each of the plurality of first pixel circuits includes a sixth transistor and a seventh transistor configured to precharge a first capacitance element and a second capacitance element, The unit pixel group area includes: a fourth region, wherein two or more sixth transistors and two or more seventh transistors are arranged on one axis along the first direction; and a fifth region arranged apart from the fourth region in the second direction, wherein two or more sixth transistors and two or more seventh transistors are arranged on one axis along the first direction, and The fourth region is arranged between the fourth region and the fifth region which are arranged to be separated from each other in the second direction.

9. The light detection device according to claim 6, wherein The unit pixel group area is a rectangular area arranged in a first direction and a second direction intersecting the first direction. The unit pixel group area includes: a first region, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along a second direction; and a second region arranged apart from the first region in the first direction, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along the second direction; The third transistor is arranged between the first region and the second region which are arranged to be separated from each other in the first direction. The channels of the first transistor and the second transistor extend in the second direction, and A channel of the third transistor extends in the first direction.

10. The light detection device according to claim 9, wherein The diffusion layers of the third transistor are arranged on both sides in the second direction with the channel of the third transistor interposed therebetween. The light detection device according to claim 5 , wherein Each of the plurality of second pixel circuits comprises: a fourth transistor configured to output a pixel signal to a signal line; and a fifth transistor configured to switch whether to initialize the charge in the second floating diffusion region, The unit pixel group area is a rectangular area arranged in a first direction and a second direction intersecting the first direction. The unit pixel group area includes: a first region, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along a second direction; a second region arranged apart from the first region in the first direction, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along the first direction; and a third region in which the fourth transistor, the third transistor, and the fifth transistor are arranged along the first direction, and The third region is configured to separate the first region and the second region, which are spaced apart from each other in the first direction, at a central portion of the unit pixel group region in the second direction.

12. The light detection device according to claim 5, wherein Each of the plurality of first pixel circuits includes a sixth transistor and a seventh transistor configured to precharge a first capacitance element and a second capacitance element, Each of the plurality of second pixel circuits comprises: a fourth transistor configured to output a pixel signal to a signal line; and a fifth transistor configured to switch whether to initialize the charge in the second floating diffusion region, The unit pixel group area is a rectangular area arranged in a first direction and a second direction intersecting the first direction. The unit pixel group area includes: a first region, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along a second direction; a second region arranged apart from the first region in the first direction, wherein the two or more first transistors and the two or more second transistors are arranged on one axis along the first direction; a third region, wherein the fourth transistor, the third transistor, and the fifth transistor are arranged along the first direction; a fourth region in which two or more sixth transistors and two or more seventh transistors are arranged along the first direction; and a fifth region arranged apart from the fourth region in the second direction, wherein two or more sixth transistors and two or more seventh transistors are arranged along the first direction, and The third region is arranged between the fourth region and the fifth region which are arranged to be separated from each other in the second direction.

13. The light detection device according to claim 2, wherein The size of the third transistor is larger than that of the first transistor and the second transistor.

14. The light detection device according to claim 2, wherein The unit pixel group region includes a plurality of third transistors arranged in a central portion, and the two or more first transistors and the two or more second transistors arranged in a point-symmetric or line-symmetric manner with respect to the plurality of third transistors.

15. The light detection device according to claim 2, wherein The unit pixel group region includes two first pixel circuits in each of a first direction and a second direction, and includes one second pixel circuit, and The unit pixel group region includes two first transistors and two second transistors that are arranged in a point-symmetrical or line-symmetrical manner with respect to a third transistor in a central portion.

16. The light detection device according to claim 2, wherein The unit pixel group region includes one first pixel circuit in the first direction, two first pixel circuits in the second direction, and one second pixel circuit, and The two unit pixel group regions arranged in the first direction have two first transistors and two second transistors arranged in a point-symmetrical or line-symmetrical manner with respect to the two third transistors in the center.

17. The light detection device according to claim 1, comprising: a first substrate on which the plurality of pixels are arranged; and The second substrate is stacked on the first substrate and has the plurality of first pixel circuits, the plurality of second pixel circuits, and the logic circuit arranged thereon.

18. The light detection device according to claim 1, comprising: a first substrate on which the plurality of pixels are arranged; a second substrate stacked on the first substrate and having the plurality of first pixel circuits and the plurality of second pixel circuits arranged thereon, and A third substrate is stacked on the second substrate and has the logic circuit configured thereon, wherein The first substrate has a plurality of first metal pads arranged opposite to the second substrate and connected to the output nodes of the plurality of pixels. The second substrate has a semiconductor layer disposed opposite to the third substrate, a plurality of second metal pads bonded to the plurality of first metal pads, a plurality of first via holes configured to pass through the semiconductor layer from the plurality of second pixel circuits, and a plurality of third metal pads configured to be opposite to the third substrate and connected to the plurality of first vias, The third substrate has a plurality of fourth metal pads bonded to the third metal pads, and Each of the plurality of first via holes is arranged for every two or more pixels.

19. The light detection device according to claim 1, wherein Each of the plurality of pixels has a third capacitance element configured to accumulate a portion of the accumulated charge of the photoelectric conversion element; an eighth transistor configured to switch whether to accumulate a portion of the accumulated charge of the photoelectric conversion element in a third capacitor; and A ninth transistor is configured to switch whether to discard the accumulated charge of the photoelectric conversion element.

20. An electronic device comprising: a light detection device configured to generate an image according to an amount of incident light; and a processing unit configured to process the image, wherein The light detection device comprises: a plurality of pixels each having a photoelectric conversion element configured to accumulate charge according to an amount of incident light; a plurality of first pixel circuits configured to hold voltage signals according to charges accumulated in the plurality of pixels at the same timing; a plurality of second pixel circuits shared by every two or more first pixel circuits among the plurality of first pixel circuits and configured to sequentially read out voltage signals held by the two or more first pixel circuits and generate pixel signals; and a logic circuit configured to perform signal processing on a plurality of pixel signals generated by the plurality of second pixel circuits, wherein Each of the plurality of first pixel circuits comprises: a first capacitive element configured to hold a voltage signal output from a pixel in a state in which the charge of the first floating diffusion region of the corresponding pixel has been initialized; a second capacitance element configured to hold a voltage signal output from a pixel in a state in which the accumulated charge of the photoelectric conversion element has been transferred to the first floating diffusion region of the corresponding pixel; a first transistor configured to switch whether to transfer the charge held in the first capacitance element to a second floating diffusion region shared by the two or more first pixel circuits; and a second transistor configured to switch whether to transfer the charge held in the second capacitance element to the second floating diffusion region, Each of the plurality of second pixel circuits includes a source follower circuit having a third transistor configured to generate a pixel signal according to the charge of the second floating diffusion region, and The two or more first transistors and the two or more second transistors included in the two or more first pixel circuits are arranged around one third transistor in a point-symmetrical or line-symmetrical manner.

Images