Interface test starting method and device

Abstract

The embodiment of the invention provides an interface test starting method and device, relates to the technical field of electronics, and is used for synchronously starting interface tests at two ends. The method comprises the following steps: a first core particle sends a first lead code to a second core particle through at least one first interface, the first lead code is used for indicating that the first core particle is about to start a first BIST test, the first core particle is interconnected with the second core particle through a plurality of interfaces, and the plurality of interfaces comprise the at least one first interface; when the sending of the first lead code is completed, the first core particle starts a first BIST test; the second core particle receives the first lead code from the first core particle and detects the first lead code; and when the second core particle successfully detects the first lead code, the second core particle starts the first BIST test.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a method and device for starting an interface test. Background Art

[0002] A chiplet is a small chip with specific functions that can be combined and integrated. This chiplet can also be called a die, crystal, or wafer. Chiplet technology integrates multiple chiplets through advanced packaging technology to form a system-on-chip. Using chiplet technology can improve the performance of system-on-chips while achieving low cost and high yield.

[0003] Chips based on chiplet technology typically contain tens of thousands of interconnected interfaces for high-speed data transmission. Currently, if process defects are introduced into the chiplet interfaces during the manufacturing process, they can cause functional issues with the chiplet, impacting the yield of the entire packaged chip. Furthermore, if these process defects go undetected during chip testing, defective chips can be introduced into the final product, leading to even greater losses. Therefore, interface testing is crucial for testing, yield, and cost considerations. Summary of the Invention

[0004] The present application provides a method and device for starting an interface test, which are used to achieve synchronous starting of the interface test.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a method for starting an interface test is provided, the method comprising: a first chip sending a first preamble code to a second chip via at least one first interface, the first preamble code may be a plurality of data including a certain length, the plurality of data including different data, the first preamble code being used to indicate that the first chip is about to start a first BIST test, the first chip being interconnected with the second chip via a plurality of interfaces, the plurality of interfaces including the at least one first interface, the at least one first interface being any interface among the plurality of interfaces; when the first preamble code is sent, the first chip starting the first BIST test, for example, starting the first BIST test at the end of sending the first preamble code, wherein starting the first BIST test may refer to sending test data.

[0007] In the above technical solution, the first chiplet can send a preamble to the second chiplet via at least one of the interconnected interfaces. After the preamble is sent, the first BIST test is initiated. The first preamble indicates that the first chiplet is about to initiate the first BIST test. This allows the receiving end to initiate the first BIST test upon receiving and successfully detecting the first preamble, thereby achieving synchronous startup of the first and second chiplets and ensuring the effectiveness of the BIST test. Furthermore, this method does not rely on synchronization circuits or critical I / O in the functional modules of the first and second chiplets, making it more versatile.

[0008] In a possible implementation of the first aspect, the at least one first interface includes at least two first interfaces, and the first chiplet sends a first preamble to the second chiplet via the at least one first interface, including: the first chiplet sends the first preamble to the second chiplet via each of the at least two first interfaces; wherein the first preambles sent via different first interfaces may be the same or different. In this possible implementation, the first chiplet sends the first preamble via each of the at least two first interfaces. Thus, as long as the second chiplet successfully detects the first preamble corresponding to one of the second interfaces, it indicates that the first preamble detection is successful. This improves the success rate of synchronous startup of the first and second chiplets, thereby effectively reducing the impact of interface failures on the synchronous startup of interface tests.

[0009] In a possible implementation of the first aspect, the method further includes: the first chip receives and detects a second preamble from the second chip via at least one second interface, the second preamble being used to indicate that the second chip is about to initiate a second BIST test; and when the first chip successfully detects the second preamble, the first chip initiates the second BIST test. In this possible implementation, after the first chip completes the test as a transmitter, the first chip can receive and detect the second BIST test as a receiver, and initiate the second BIST test upon successful detection of the second preamble, thereby enabling synchronous initiation of the first and second chip during both forward and reverse tests.

[0010] In a possible implementation of the first aspect, the at least one second interface includes at least two second interfaces, and the first chip receives the second preamble from the second chip via the at least one second interface, including: the first chip receives the second preamble from the second chip via each of the at least two second interfaces. In this possible implementation, the second chip receives the second preamble via each of the at least two second interfaces, thereby increasing the probability that the first chip successfully receives the first preamble.

[0011] In a possible implementation of the first aspect, for a second preamble corresponding to any second interface of the at least one second interface, the method further includes: the first chip detecting whether the second preamble is consistent with a comparison preamble, and when the second preamble is consistent with the comparison preamble, indicating successful detection of the second preamble. In this possible implementation, as long as the first chip successfully detects the first preamble corresponding to one second interface, the first preamble detection is successful, thereby improving the success rate of synchronous startup of the first chip and the second chip, and effectively reducing the impact of interface failures on the synchronous startup of the interface test.

[0012] In one possible implementation of the first aspect, the method is applied to a chip package comprising multiple cores, wherein the multiple cores are interconnected and packaged using core technology, and the multiple cores include a first core and a second core. This possible implementation enables synchronous startup of the first and second cores in the chip package, thereby ensuring the effectiveness of BIST testing. Furthermore, this method does not rely on synchronization circuits and critical I / O of functional modules in the first and second cores, thus enhancing its versatility.

[0013] In one possible implementation of the first aspect, the first preamble or the second preamble includes multiple data of a certain length, and the multiple data include different data. Optionally, the first preamble or the second preamble is an interleaved code. The above possible implementation can increase the probability of successfully detecting the first preamble or the second preamble.

[0014] In a possible implementation of the first aspect, at least two of the at least one first interface or the at least one second interface have an interface distance greater than a preset distance. In this possible implementation, by selecting interfaces with an interface distance greater than the preset distance to send a preamble, the impact of interface failures on the synchronous start of the interface test can be effectively reduced.

[0015] In a second aspect, a method for starting an interface test is provided, the method comprising: a second chip receives and detects a first preamble code from a first chip through at least one first interface, the first preamble code being used to indicate that the first chip is about to start a first BIST test, the second chip being interconnected with the first chip through multiple interfaces, the multiple interfaces including the at least one first interface; when the second chip successfully detects the first preamble code, the second chip starts the first BIST test.

[0016] In a possible implementation of the second aspect, the at least one first interface includes at least two first interfaces, and the second core particle receives the first preamble code from the first core particle through the at least one first interface, including: the second core particle receives the first preamble code from the first core particle through each first interface of the at least two first interfaces.

[0017] In a possible implementation of the second aspect, for a first preamble code corresponding to any first interface of the at least one first interface, the second core detects the first preamble code, including: the second core detects whether the first preamble code is consistent with the comparison preamble code, and when the first preamble code is consistent with the comparison preamble code, it indicates that the first preamble code is successfully detected.

[0018] In a possible implementation of the second aspect, the method further includes: the second chiplet sending a second preamble to the first chiplet through at least one second interface, where the second preamble is used to indicate that the second chiplet is about to start a second BIST test;

[0019] When the second preamble is completely sent, the second chip starts the second BIST test.

[0020] In a possible implementation of the second aspect, the at least one second interface includes at least two second interfaces, and the second core particle sends the second preamble code to the first core particle through the at least one second interface, including: the second core particle sends the second preamble code to the first core particle through each second interface of the at least two second interfaces.

[0021] In a possible implementation manner of the second aspect, the present invention is applied to a chip package including a plurality of cores, the plurality of cores are interconnected and packaged through core technology, and the plurality of cores include a first core and a second core.

[0022] In a possible implementation manner of the second aspect, the first preamble or the second preamble includes multiple data of a certain length, and different data exist in the multiple data.

[0023] In a possible implementation manner of the second aspect, there are at least two interfaces among the at least one first interface or the at least one second interface whose interface distance is greater than a preset distance.

[0024] In a third aspect, a device for initiating an interface test is provided. The device can implement the function performed by the first chiplet in the above method. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

[0025] In a possible implementation of the third aspect, the device includes a sending unit, a starting unit, a receiving unit and a detection circuit; the detection circuit and the starting unit are configured to support the device in performing the corresponding functions in the above method; the sending unit and the receiving unit are used to support the device in communicating with the second core particle.

[0026] In a fourth aspect, a device for initiating an interface test is provided. The device can implement the function performed by the second core in the above method. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

[0027] In a possible implementation of the fourth aspect, the device includes a receiving unit, a detection circuit, a starting unit, and a sending unit; the detection circuit and the starting unit are configured to support the device in performing the corresponding functions in the above method; the sending unit and the receiving unit are used to support the device in communicating with the second core particle.

[0028] In a fifth aspect, a device for starting an interface test is provided, the device comprising: a processor and a communication interface, the processor and the communication interface being used to support the device in executing the method provided in the first aspect or any possible implementation of the first aspect.

[0029] In a sixth aspect, a device for starting an interface test is provided, the device comprising: a processor and a communication interface, the processor and the communication interface being used to support the device in executing the method provided in the second aspect or any possible implementation of the second aspect.

[0030] In another aspect of the present application, a communication device is provided, which includes a first core particle and a second core particle, the first core particle includes the third aspect, any possible implementation of the third aspect, or the device provided by the fifth aspect, and the first core particle is used to execute the method provided by the first aspect or any possible implementation of the first aspect; the second core particle includes the fourth aspect, any possible implementation of the fourth aspect, or the device provided by the sixth aspect, and the second core particle is used to execute the method provided by the second aspect or any possible implementation of the second aspect.

[0031] In another aspect of the present application, a computer-readable storage medium is provided, in which a computer program or instruction is stored. When the computer program or instruction is executed, the method provided in the first aspect or any possible implementation of the first aspect is implemented.

[0032] In another aspect of the present application, a computer-readable storage medium is provided, in which a computer program or instruction is stored. When the computer program or instruction is executed, the method provided in the second aspect or any possible implementation of the second aspect is implemented.

[0033] In another aspect of the present application, a computer program product is provided, which includes: a computer program (also referred to as code, or instructions), which, when executed, enables a computer to execute the method provided in the first aspect or any possible implementation of the first aspect.

[0034] In another aspect of the present application, a computer program product is provided, which includes: a computer program (also referred to as code, or instructions), which, when executed, enables a computer to execute the method provided in the second aspect or any possible implementation of the second aspect.

[0035] It can be understood that the beneficial effects of other aspects except the first aspect and any possible implementation of the first aspect can refer to the beneficial effects in the above-mentioned first aspect and any possible implementation of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram of the structure of a communication device provided in an embodiment of the present application;

[0037] Figure 2 A schematic structural diagram of a core particle provided in an embodiment of the present application;

[0038] Figure 3 A schematic diagram illustrating the arrangement of multiple interfaces of a core particle provided in an embodiment of the present application;

[0039] Figure 4 A flowchart of a method for starting an interface test provided in an embodiment of the present application;

[0040] Figure 5 A schematic structural diagram of a first core particle and a second core particle provided in an embodiment of the present application;

[0041] Figure 6 A flowchart of another method for starting an interface test provided in an embodiment of the present application;

[0042] Figure 7 A flowchart of a startup interface test provided in an embodiment of the present application;

[0043] Figure 8 A schematic structural diagram of a first core particle provided in an embodiment of the present application;

[0044] Figure 9 A schematic structural diagram of another first core particle provided in an embodiment of the present application;

[0045] Figure 10 A schematic structural diagram of a second core particle provided in an embodiment of the present application;

[0046] Figure 11 A schematic structural diagram of another second core particle provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The following will discuss in detail the making and use of various embodiments. However, it should be understood that many applicable inventive concepts provided herein can be implemented in a variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to implement and use the present application and technology and do not limit the scope of this application.

[0048] Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art.

[0049] Various circuits or other components may be described or referred to as being "configured to" perform one or more tasks. In this case, "configured to" is used to imply structure by indicating that the circuit / component includes structure (e.g., circuitry) that performs the one or more tasks during operation. Thus, even when a specified circuit / component is not currently operational (e.g., not turned on), the circuit / component may be referred to as being configured to perform the task. Circuits / components used with the phrase "configured to" include hardware, such as circuitry that performs an operation, etc.

[0050] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c, a, b and c; where a, b and c can be single or multiple.

[0051] The embodiments of this application use terms such as "first" and "second" to distinguish objects with similar names, functions, or effects. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or order of execution. The term "coupled" is used to indicate an electrical connection, including direct connection via wires or connectors or indirect connection via other devices. Therefore, "coupling" should be considered a broadly defined electronic communication connection.

[0052] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0053] Before introducing the embodiments of the present application, the application scenarios involved in the present application are first introduced and explained.

[0054] A chiplet is a small chip with specific functions that can be combined and integrated. The chiplet can also be called a die, grain, or wafer. Chiplet technology is to integrate multiple chiplets together through advanced packaging technology to form a larger chip. The chip can be a system-level chip, such as a system on chip (SoC). The above-mentioned multiple chiplets can use different processes, have different functions, and even be provided by different suppliers. Integrating multiple chiplets to form a large chip through chiplet technology can reduce chip design time and cost, while improving chip performance and ensuring high yield.

[0055] In the process of interconnecting and packaging multiple cores into a large chip, 2.5D or 3D stacking technology can be used. In a chip based on chiplet technology, there are usually tens of thousands of interconnected interfaces, which can be used to transmit high-speed data. At present, if the interface of the core introduces process defects during the production and manufacturing process, it will cause problems with the function of the core, which in turn affects the yield of the entire packaged chip; further, if the process defects are not discovered during the chip testing process, it will cause defective chips to flow into the product, resulting in greater losses. Therefore, from the perspectives of testing, yield, cost, etc., interface testing is particularly important. This interface test can also be called input output (IO) interface test or IO test.

[0056] When testing the interface between chiplets, a built-in self-test (BIST) approach can be used. This involves the transmitter sending a series of test data (also known as transmitted values), and the receiver completing the test by receiving and comparing the test data with comparison data (also known as expected values). This BIST approach to testing the interface between chiplets can also be referred to as a BIST test. The BIST test's startup method is crucial, requiring synchronized startup between the transmitter and receiver to ensure that both ends simultaneously generate identical transmitted and expected values.

[0057] In one implementation, regarding the synchronous start of the sending end and the receiving end during the IO test, a handshake signal is generally used to achieve this. The handshake signal can also be called a data ready signal or a ready signal. Specifically, the sending end sends the ready signal at the same time as the data is sent. The ready signal is generated by the synchronization circuit in the functional module of the sending end and is sent through the specific IO of the functional module; after receiving the ready signal, the receiving end starts the IO test (i.e., starts the data check). In this way, the sending end and the receiving end can achieve the synchronous start of the IO test through the ready signal, thereby ensuring the synchronization of data at both ends. Therefore, in the IO test, there are some key IOs that will affect the entire test. For example, if the IO that transmits the ready signal has a fault, it will affect the synchronous start of the two ends. Even if there is a repair IO in the core particle, the corresponding repair process cannot be executed, thereby affecting the yield.

[0058] Based on this, an embodiment of the present application provides a method for starting an interface test, which can also be called an IOBIST test, that is, performing an interface test based on a BIST method. Specifically, in this method, the transmitting end can transmit a preamble through at least one of the multiple interconnected interfaces and start the BIST test (i.e., send test data) after the preamble is sent. When the receiving end receives and successfully detects the preamble, it starts the BIST test (i.e., starts receiving and detecting data), thereby achieving synchronous startup of the transmitting end and the receiving end. In addition, this method does not rely on the synchronization circuits and key IOs of the functional modules in the transmitting end and the receiving end, and thus has greater versatility.

[0059] Optionally, the method provided in the embodiment of the present application can be applied to a chip package including multiple core particles, where the multiple core particles are interconnected and packaged through core particle technology. The multiple core particles include a first core particle and a second core particle, and the first core particle and the second core particle can serve as a transmitting end and a receiving end. For example, the method is first executed once with the first core particle as the transmitting end and the second core particle as the receiving end, and then the method is executed again with the second core particle as the transmitting end and the first core particle as the receiving end.

[0060] The technical solution of the present application can be applied to a communication device, which includes a plurality of core particles, and the plurality of core particles can be interconnected through chiplet technology. Optionally, in the communication device, the plurality of core particles can be integrated and packaged using stacking technologies such as 2.5D or 3D. In practical applications, the communication device can be a chip (for example, SoC) or a communication device with a chip. The communication device can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted. The communication device can also be deployed on the water surface (such as ships, etc.), and can also be deployed in the air (for example, on airplanes, balloons and satellites, etc.), and the communication device can be applied to different scenarios.

[0061] Optionally, the communication device may include, but is not limited to: a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile internet device (MID), a camera, a wearable device (such as a smart watch, a smart bracelet, a pedometer, etc.), an audio device, an audio and video player, a set-top box, a game console, a printer, a mouse, a keyboard, a vehicle-mounted device (such as a car, a bicycle, an electric car, an airplane, a ship, a train, a high-speed train, etc.), a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a smart home device (such as a refrigerator, a television, an air conditioner, an electric meter, etc.), an intelligent robot, a workshop device, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, or a smart home. wireless terminals in the home), flying equipment (e.g., intelligent robots, hot air balloons, drones, airplanes), etc.

[0062] Figure 1 A schematic diagram of the structure of a communication device provided in an embodiment of the present application. The communication device includes multiple core particles, each of which may have multiple interfaces. Any core particle in the multiple core particles may be interconnected with one or more core particles through multiple interfaces, and the same core particle may be interconnected with different core particles through different interfaces. In one example, the multiple core particles include three core particles and are represented as D1 to D3. Core particles D1, D2, and 3 each have multiple interfaces, and a portion of the interfaces of core particle D1 are interconnected with multiple interfaces of core particle D2, and another portion of the interfaces of core particle D1 are interconnected with multiple interfaces of core particle D2.

[0063] Optionally, the communication device may include multiple subsystems with different functions, each of which may be integrated on one of the multiple cores. The multiple subsystems include, but are not limited to, a processor subsystem, an audio subsystem, a video subsystem, an artificial intelligence (AI) subsystem, an image processing subsystem, or a modem subsystem. Exemplarily, the communication device may include a processor subsystem integrated on core D1, a video subsystem integrated on core D2, and an AI subsystem integrated on core D3.

[0064] Each of the plurality of core particles may include: a functional circuit, a test circuit, and a plurality of interfaces, wherein the functional circuit and the test circuit are connected to the plurality of interfaces. The functional circuit may be used to implement the logic function of the core particle, such as implementing a data processing function or an image processing function, etc.; the test circuit may be used to test the plurality of interfaces, such as the test circuit may be a BIST circuit. For example, Figure 2 As shown, taking the multiple core particles including core particle D1 and core particle D2 as an example, each core particle in core particle D1 and core particle D2 includes a functional circuit, a BIST circuit and multiple interfaces, and the multiple interfaces of core particle D1 are interconnected with the multiple interfaces of core particle D2.

[0065] In one possible implementation, the BIST circuit includes a generation circuit and a detection circuit. The generation circuit can be used to generate relevant information required for testing, and the detection circuit can be used to detect the relevant information. For example, the relevant information can include the preamble and test data involved in the embodiments of the present application. In one possible example, the BIST circuit can be a linear feedback shift register (LFSR) unit LFSR_UNIT, the generation circuit can include a linear feedback shift register generation circuit LFSR_GEN, and the detection circuit can be a linear feedback shift register detection circuit LFSR_CHK, that is, the LFSR_UNIT can include LFSR_GEN and LFSR_CHK. Furthermore, the test circuit can also include a state machine, which can be used to switch the state of the test circuit. For example, the state machine can be a finite state machine (FSM), which can switch the state of the test circuit based on a valid signal output by the detection circuit in the test circuit when the detection is successful.

[0066] Optionally, the multiple interfaces of any of the multiple core particles can be divided into different types of interface groups (IO groups), that is, the multiple interfaces of each core particle include one or more interface groups, and each interface group can include one or more interfaces. The physical layout of different interface groups can be different, and the same type of interface group can appear multiple times at different positions on the core particle. For example, Figure 3 A schematic diagram showing the distribution of interface groups corresponding to multiple interfaces of a core particle is shown. Figure 3 Interfaces in the same location and using the same padding method belong to the same interface group. Interfaces in different locations and using different padding methods belong to different interface groups. Multiple interface groups of the same type use the same padding method. These interface groups can also be called IOMACROs or interface sets (which can be represented as IOs).

[0067] Figure 4 A flow chart of a method for starting an interface test provided in an embodiment of the present application is provided. The method can be applied to the communication device provided above, and the method includes the following steps.

[0068] S301: A first chiplet sends a first preamble to a second chiplet through at least one first interface. The first preamble is used to indicate that the first chiplet is about to start a first BIST test.

[0069] The first core can be any one of the multiple cores included in the communication device. The first core can be interconnected with the second core via multiple interfaces, and the second core can be any one of the cores interconnected with the first core. The multiple interfaces include the at least one first interface, and the at least one first interface can be any one or more of the multiple interfaces. Exemplarily, the first core can send the first preamble to the second core via some or all of the multiple interfaces. Optionally, the multiple interfaces can be interfaces in an interface group, or interfaces in an IOMACRO.

[0070] In addition, the first preamble may refer to a preamble sent by the first core to the second core. The preamble herein may refer to a data sequence of a certain length, wherein the data sequence includes different data. The different data may refer to 0s and 1s, i.e., the data in the data sequence cannot be all 0s or all 1s. For example, the data sequence may include multiple 0s and multiple 1s arranged in a certain order. The length of the preamble may be fixed or variable, and the specific value may also be achieved through configuration. For example, the length of the preamble may be 12, 15, 16, or 18. For example, the preamble may be 010110101101100001.

[0071] In one possible embodiment, when the interface between a first chiplet and a second chiplet needs to be tested, the first chiplet may send a first preamble to the second chiplet via at least one of the multiple interfaces interconnected with the second chiplet. That is, the first chiplet may send the first preamble on each of the at least one interface. The first preamble indicates that the first chiplet is about to initiate a first BIST test. This can be understood as the first chiplet initiating the first BIST test after completing the transmission of the first preamble, such as at the end of the transmission of the first preamble. This BIST test may refer to an interface test performed using a BIST approach.

[0072] When the at least one first interface includes multiple first interfaces, the first preambles sent by the first chip through the multiple first interfaces may be the same or different, that is, the first preambles corresponding to different first interfaces may be the same or different. When the first preambles corresponding to different first interfaces are different, specifically, the lengths of the first preambles may be different, or the data in the first preambles may be different, or both the lengths and data of the first preambles may be different. The transmission end times of the first preambles corresponding to the multiple first interfaces are the same.

[0073] Optionally, if the at least one first interface includes multiple first interfaces, then there are at least two interfaces among the multiple first interfaces whose interface distance is greater than a preset distance, that is, the physical distance between the at least two interfaces is far. The preset distance can be pre-set, and the preset distance can be the same or different for different core particles. This embodiment of the application does not impose specific limitations on this. For example, the number of the at least one first interface can be 2, 3, 4, or 5, etc.

[0074] Furthermore, before sending the first preamble, the first chip may also generate a first preamble corresponding to the at least one first interface. Figure 5 As shown, the first chiplet may include a BIST circuit, and the BIST circuit includes a generation circuit; the generation circuit may be used to generate a first preamble code corresponding to the at least one first interface and send it to the at least one first interface, so that the at least one first interface transmits the corresponding first preamble code to the second chiplet. For example, the generation circuit in the BIST circuit is the linear feedback shift register generation circuit LFSR_GEN mentioned above. Figure 5 In FIG, the first core particle is represented as DIE A, and the multiple interfaces of the first core particle are represented as IOMACRO.

[0075] S302: The second chip receives and detects a first preamble from the first chip through at least one first interface, where the first preamble indicates that the first chip is about to start a first BIST test.

[0076] The second coreparticle is interconnected with the multiple interfaces of the first coreparticle via multiple interfaces, and the multiple interfaces of the second coreparticle and the multiple interfaces of the first coreparticle can be interconnected in a one-to-one correspondence, so that the at least one first interface of the second coreparticle for receiving the first preamble can correspond one-to-one with the at least one first interface of the first coreparticle for sending the first preamble. The multiple interfaces of the second coreparticle and the multiple interfaces of the first coreparticle can be collectively referred to as multiple interfaces herein, and the first coreparticle and the second coreparticle can send and receive via their respective interfaces. For simplicity, the sending or receiving of any coreparticle via its respective interface is referred to as "sending or receiving by any coreparticle via an interface."

[0077] In a possible embodiment, for a first preamble code received by any first interface of the at least one first interface, the second core detecting the first preamble code may include: the second core detecting whether the first preamble code is consistent with the first comparison preamble code, and when the first preamble code is consistent with the first comparison preamble code, it indicates that the first preamble code is successfully detected.

[0078] Optionally, while receiving the first preamble, the second chip can compare the data in the received first preamble with the corresponding data in the first comparison preamble, that is, perform bit-by-bit detection on the first preamble and the first comparison preamble. When the detection of the last data of the first preamble is completed and the first preamble is completely consistent with the first comparison preamble, it indicates that the first preamble has been successfully detected or the first preamble detection is successful. If the first preamble is inconsistent with the first comparison preamble, it indicates that the first preamble detection has failed, and the second chip can then receive and detect again.

[0079] Furthermore, when the second chip receives the first preamble from the first chip via at least two first interfaces, if the second chip successfully detects the first preamble received at any one of the at least two first interfaces, it indicates successful detection of the first preamble. That is, when the first chip transmits the first preamble via multiple first interfaces, the second chip only needs to successfully detect the first preamble received at one of the first interfaces to indicate successful first preamble detection, rather than having to successfully detect the first preamble received at every first interface. This effectively reduces the impact of interface failures on the synchronous start of interface testing.

[0080] The first comparison preamble mentioned above may also be referred to as an expected preamble. Optionally, the second core particle may generate a first comparison preamble corresponding to the at least one first interface before comparing the first preamble with the first comparison preamble. In one example, Figure 5 As shown, the second core particle may include a BIST circuit, which includes a generation circuit and a detection circuit; the generation circuit can be used to generate a first comparison preamble code corresponding to the at least one first interface; the detection circuit is used to compare the first preamble code with the first comparison preamble code, or is called a preamble code comparison count. Furthermore, the BIST circuit also includes a finite state machine FSM, which can be used to receive a valid signal output by the detection circuit and switch the state of the BIST circuit according to the valid (VLD) signal. Figure 5 In the figure, the second chip is represented as DIE B, multiple interfaces of the second chip are represented as IOMACRO, the detection circuit in the BIST circuit of the chip DIE B is represented as BIST_CHK, and the valid signal output by BIST_CHK is represented as VLD.

[0081] The description of the first comparison preamble used by the second chiplet during comparison is consistent with the description of the first preamble sent by the first chiplet described above. Furthermore, the process by which the second chiplet generates the first comparison preamble corresponding to the at least one first interface can be consistent with the process by which the first chiplet generates the first preamble corresponding to the at least one first interface, which is not described in detail in this embodiment of the application.

[0082] S303a: When the first preamble is sent, the first chip starts the first BIST test. S303b: When the second chip successfully detects the first preamble, the second chip starts the first BIST test.

[0083] Among them, the first chip starting the first BIST test may refer to the first chip sending test data to the second chip, or the first chip is in a test sending state; the second chip starting the first BIST test may refer to the second chip receiving and detecting the test data sent by the first chip, or the second chip is in a test receiving state.

[0084] In a possible embodiment, the first chip starts the first BIST test when the first preamble code is sent, and the second chip starts the first BIST test when the first preamble code is successfully detected, so that the first chip and the second chip can start the first BIST test at the same time, thereby realizing the test of multiple interfaces from the first chip to the second chip.

[0085] Furthermore, after the first core particle and the second core particle complete the first BIST test, the second core particle and the first core particle can also complete the second BIST test in a similar manner as described above. The first BIST test can refer to the first core particle as the transmitter and the second core particle as the receiver, and the second BIST test can refer to the second core particle as the transmitter and the first core particle as the receiver. In the entire process including the first BIST test and the second BIST test, which of the first core particle and the second core particle serves as the transmitter or the receiver can be set in advance or selected by the user at the beginning of the test. This embodiment of the present application does not specifically limit this. For example, Figure 6 As shown, the method also includes: S304-S306b.

[0086] S304: The second chiplet sends a second preamble to the first chiplet through at least one second interface. The second preamble is used to indicate that the second chiplet is about to start a second BIST test.

[0087] The second preamble may refer to a preamble sent by the second core to the first core. The second preamble and the first preamble may be the same preamble. For a detailed description of the second preamble, reference may be made to the description of the first preamble above, and will not be repeated herein in this embodiment of the present application. In addition, the at least one second interface may be part of the multiple interfaces of the second core, and the at least one second interface may be the same as or different from the at least one first interface, and this embodiment of the present application does not impose any specific restrictions on this.

[0088] In one possible embodiment, the second chiplet may send a second preamble to the first chiplet via at least one of a plurality of interfaces interconnected with the first chiplet. That is, the second chiplet may send the second preamble on each of the at least one interface. The second preamble is used to indicate that the second chiplet is about to initiate a second BIST test. This may be understood as the second chiplet initiating the second BIST test after completing the sending of the second preamble, for example, initiating the second BIST test at the end of sending the second preamble.

[0089] When the at least one second interface includes multiple second interfaces, the second preambles sent by the second core particle through the multiple second interfaces can be the same or different, that is, the second preambles corresponding to different second interfaces can be the same or different. The second preambles corresponding to the multiple second interfaces end at the same time. Optionally, if the at least one second interface includes multiple second interfaces, at least two of the multiple second interfaces have an interface distance greater than a preset distance.

[0090] Furthermore, before sending the second preamble, the second chiplet may also generate a second preamble corresponding to the at least one second interface. In one example, in the second chiplet, the generation circuit of the BIST circuit may be configured to generate the second preamble corresponding to the at least one second interface and send the generated preamble to the at least one second interface, so that the at least one second interface transmits the corresponding second preamble to the first chiplet.

[0091] S305: The first chip receives and detects a second preamble from the second chip through at least one second interface, where the second preamble indicates that the second chip is about to start a second BIST test.

[0092] In a possible embodiment, for the second preamble code received by any second interface of the at least one second interface, the first core detecting the second preamble code may include: the first core detecting whether the second preamble code is consistent with the second comparison preamble code, and when the second preamble code is consistent with the second comparison preamble code, it indicates that the second preamble code is successfully detected.

[0093] Optionally, while receiving the second preamble, the first chip can compare the data in the received second preamble with the corresponding data in the second comparison preamble, that is, perform bit-by-bit detection on the second preamble and the second comparison preamble. When the last data of the second preamble is detected and the second preamble is completely consistent with the second comparison preamble, it indicates that the second preamble has been successfully detected, or the second preamble detection is successful. If the second preamble is inconsistent with the second comparison preamble, it indicates that the second preamble detection has failed, and the first chip can then receive and detect again.

[0094] Furthermore, when the first chip receives a second preamble from a second chip via at least two second interfaces, if the first chip successfully detects the second preamble received at any one of the at least two second interfaces, it indicates successful detection of the second preamble. That is, when the second chip transmits the second preamble via multiple second interfaces, the first chip only needs to successfully detect the second preamble received at one of the second interfaces to indicate successful second preamble detection, rather than having to successfully detect the second preamble received at every second interface. This effectively reduces the impact of interface failures on the synchronous start of interface testing.

[0095] The second comparison preamble mentioned above may also be referred to as an expected preamble. Optionally, the first chiplet may generate a second comparison preamble corresponding to the at least one second interface before comparing the second preamble with the second comparison preamble. In one example, the BIST circuit in the first chiplet includes a generation circuit and a detection circuit; the generation circuit may be configured to generate the second comparison preamble corresponding to the at least one second interface; and the detection circuit may be configured to compare the second preamble with the second comparison preamble.

[0096] The description of the second comparison preamble used by the first chiplet during comparison is consistent with the description of the second preamble sent by the second chiplet above. Furthermore, the process by which the first chiplet generates the second comparison preamble corresponding to the at least one second interface can be consistent with the process by which the second chiplet generates the second preamble corresponding to the at least one second interface, which is not described in detail in this embodiment of the application.

[0097] S306a: When the second preamble is sent, the second chip starts the second BIST test. S306b: When the first chip successfully detects the second preamble, the first chip starts the second BIST test.

[0098] Among them, the second chip starting the second BIST test can refer to the second chip sending test data to the first chip, or the second chip is in a test sending state; the first chip starting the second BIST test can refer to the first chip receiving and detecting the test data sent by the second chip, or the first chip is in a test receiving state.

[0099] In a possible embodiment, the second chip starts the second BIST test when the first preamble code is sent. The first chip starts the second BIST test when the second preamble code is successfully detected. Therefore, the first chip and the second chip can start the second BIST test at the same time, thereby realizing the test of multiple interfaces from the second chip to the first chip.

[0100] For ease of understanding, the following is an example of the relevant process of starting the interface test in the embodiment of the present application. Among them, when the first core particle and the second core particle (i.e., DIE at both ends) start the IOBIST test, first select one end as the transmitting end and the other end as the receiving end (for example, the first core particle is the transmitting end and the second core particle is the receiving end), and then execute according to the following process: first start the receiving end and wait for the reception of the preamble code; start the transmitting end and send a string of preamble codes to the receiving end, which indicates that the transmitting end is about to start the BIST test; the receiving end observes the preamble code in real time, and after the comparison of a string of preamble codes is completed, the two ends synchronously start the BIST test and complete the BIST test; after that, the directions of the two ends are reversed (for example, the first core particle is the receiving end and the second core particle is the transmitting end), and repeat the above steps. If both forward and reverse tests are completed, the test ends. Figure 7 As shown, the corresponding process includes: S0. Start; S1. The receiving end starts preamble code reception; S2. The sending end sends the preamble code; S3. Determine whether the receiving end has completed the preamble code comparison, if so, execute S4, if not, return to S2; S4. The sending end and the receiving end synchronously start the BIST test; S5. The test is completed, that is, the forward and reverse tests are completed; S6. End.

[0101] In the embodiment of the present application, the transmitting end in the first and second cores can transmit a preamble through at least one of the interconnected interfaces and initiate a BIST test (i.e., send test data) after the preamble is transmitted. The receiving end can initiate a BIST test upon receiving and successfully detecting the preamble, thereby achieving synchronous initiation of the transmitting and receiving ends and ensuring the effectiveness of the BIST test. This method does not rely on synchronization circuits and key I / O in the functional modules of the transmitting and receiving ends, thus increasing its versatility.

[0102] In a possible embodiment of the present application, the method for starting the interface test includes: the first chip sends a first preamble code to the second chip through at least one first interface, the first preamble code is used to indicate that the first chip is about to start the first BIST test, the first chip is interconnected with the second chip through multiple interfaces, the multiple interfaces include the at least two first interfaces; when the first preamble code is sent, the first chip starts the first BIST test.

[0103] In one possible embodiment of the present application, a method for initiating an interface test includes: a first chiplet sending a first preamble to a second chiplet via at least two first interfaces, the first preamble being used to indicate that the first chiplet is about to initiate a first BIST test; the first chiplet being interconnected with the second chiplet via multiple interfaces, the multiple interfaces including the at least two first interfaces; and upon completion of sending the first preamble, the first chiplet initiating the first BIST test. Optionally, one of the at least two first interfaces has an interface distance greater than a preset distance.

[0104] In a possible embodiment of the present application, the method for starting the interface test includes: the first chip receives and detects a second preamble code from the second chip through at least one second interface, the second preamble code is used to indicate that the second chip is about to start a second BIST test, the first chip is interconnected with the second chip through multiple interfaces, the multiple interfaces include the at least two first interfaces; when the first chip successfully detects the second preamble code, the first chip starts the second BIST test.

[0105] In a possible embodiment of the present application, the method for starting the interface test includes: the first chip receives a second preamble code from the second chip through at least one second interface, the second preamble code is used to indicate that the second chip is about to start a second BIST test, the first chip is interconnected with the second chip through multiple interfaces, and the multiple interfaces include the at least two first interfaces; for the second preamble code corresponding to any second interface of the at least one second interface, the first chip detects whether the second preamble code is consistent with the comparison preamble code, and when the second preamble code is consistent with the comparison preamble code, it indicates that the second preamble code is successfully detected; when the first chip successfully detects the second preamble code, the first chip starts the second BIST test.

[0106] In one possible embodiment of the present application, a method for initiating an interface test includes: a first chip receives a second preamble from a second chip via at least two second interfaces, the second preamble being used to indicate that the second chip is about to initiate a second BIST test; the first chip is interconnected with the second chip via multiple interfaces, the multiple interfaces including the at least two first interfaces; for a second preamble corresponding to any of the at least two second interfaces, the first chip detects whether the second preamble is consistent with a comparison preamble; when the second preamble is consistent with the comparison preamble, it indicates successful detection of the second preamble; when the first chip successfully detects the second preamble, the first chip initiates the second BIST test. Optionally, one of the at least two second interfaces has an interface distance greater than a preset distance.

[0107] In a possible embodiment of the present application, the method for starting the interface test includes: the second chip receives and detects a first preamble code from the first chip through at least one first interface, the first preamble code is used to indicate that the first chip is about to start a first BIST test, and the second chip is interconnected with the first chip through multiple interfaces, the multiple interfaces including the at least two first interfaces; when the second chip successfully detects the first preamble code, the second chip starts the first BIST test.

[0108] In a possible embodiment of the present application, the method for starting the interface test includes: the second chip receives a first preamble code from the first chip through at least one first interface, the first preamble code is used to indicate that the first chip is about to start the first BIST test, and the second chip is interconnected with the first chip through multiple interfaces, and the multiple interfaces include the at least two first interfaces; for the first preamble code corresponding to any first interface of the at least one first interface, the second chip detects whether the first preamble code is consistent with the comparison preamble code, and when the first preamble code is consistent with the comparison preamble code, it indicates that the first preamble code is successfully detected; when the second chip successfully detects the second preamble code, the second chip starts the first BIST test.

[0109] In one possible embodiment of the present application, the method for initiating the interface test includes: a second chip receives a first preamble from a first chip via at least two first interfaces, the first preamble being used to indicate that the first chip is about to initiate a first BIST test; the second chip is interconnected with the first chip via multiple interfaces, the multiple interfaces including the at least two first interfaces; for a first preamble corresponding to any of the at least two first interfaces, the second chip detects whether the first preamble is consistent with a comparison preamble; when the first preamble is consistent with the comparison preamble, it indicates that the first preamble has been successfully detected; when the second chip successfully detects the second preamble, the second chip initiates the first BIST test. Optionally, one of the at least two first interfaces has an interface distance greater than a preset distance.

[0110] In a possible embodiment of the present application, the method for starting the interface test includes: the second chip sends a second preamble code to the first chip through at least one second interface, the second preamble code is used to indicate that the second chip is about to start a second BIST test, the second chip is interconnected with the first chip through multiple interfaces, the multiple interfaces include the at least two first interfaces; when the second preamble code is sent, the second chip starts the second BIST test.

[0111] In one possible embodiment of the present application, the method for initiating the interface test includes: a second chiplet sending a second preamble to a first chiplet via at least two second interfaces, the second preamble being used to indicate that the second chiplet is about to initiate a second BIST test; the second chiplet being interconnected with the first chiplet via multiple interfaces, the multiple interfaces including the at least two first interfaces; and upon completion of sending the second preamble, the second chiplet initiating the second BIST test. Optionally, one of the at least two second interfaces has an interface distance greater than a preset distance.

[0112] In a possible embodiment of the present application, a synchronization scheme is provided, which may include a preamble scheme, which may be applied to the above Figure 5 The diagram shows the chiplet DIE A and chiplet DIE B. IOBIST testing involves aligning the test data in the transmitter's DIE with the comparison data in the receiver. To synchronize the data in the DIEs at both ends, the IOBIST circuits (or BIST circuits) on both ends must be activated synchronously. To synchronize the output values ​​at the receiver with those at the transmitter, a handshake signal is required. This allows the receiver to observe the transmitted signal in real time and determine its activation time based on the received signal.

[0113] To achieve synchronous startup of both ends, the concept of a preamble is introduced. That is, before sending test data, a string of data is first sent to the receiving end. After the receiving end continuously compares the preamble, the BIST check at the receiving end is started, thus completing the synchronous startup of the BIST circuits at both ends.

[0114] The test steps of the asynchronous scenario are introduced. Among them, the specific process of the asynchronous startup scenario is as follows: (a) When the DIE at both ends starts the IOBIST test, first select one end as the transmitter and the other end as the receiver; (b) Start the receiver first and wait for the reception of the preamble code; (c) Start the transmitter and send a string of preamble codes to the receiver, indicating that the transmitter will start the BIST test; (d) The receiver observes the preamble code in real time. After the comparison of a string of preamble codes is completed, the two ends synchronously start the BIST test and complete the BIST test; (e) The direction of the two ends is reversed and steps (b) to (d) are repeated. If both the forward and reverse tests are completed, the test ends. Among them, the synchronous startup process of both ends can be found in Figure 7 shown.

[0115] The above mainly introduces the solution provided by the embodiment of the present application from the perspective of the interaction between the first core particle and the first core particle. It can be understood that in order to realize the above functions, the first core particle and the first core particle include hardware structures and / or software modules corresponding to the execution of each function. It should be easy for those skilled in the art to realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0116] In the embodiment of the present application, the first core particle and the second core particle can be divided into functional modules according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical functional division. There may be other division methods in actual implementation. The following is an example of dividing each functional module according to each function.

[0117] In the case of an integrated unit, Figure 8 A structural schematic diagram of a starting device for an interface test involved in the above embodiment is shown. The device can be a first core particle, and the device includes: a sending unit 401 and a starting unit 402. The sending unit 401 can be used to support the device to execute S301 in the above method embodiment; the starting unit 402 is used to support the device to execute S303a in the above method embodiment. Further, the device also includes a receiving unit 403 and a detection unit 404. The receiving unit 403 is used to support the device to execute the receiving step in S305 of the above method embodiment; the detection unit 404 is used to support the device to execute the detecting step in S305 of the above method embodiment; the starting unit 402 is used to support the device to execute S306b in the above method embodiment. All relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module, and the embodiments of this application will not be repeated here.

[0118] Based on the hardware implementation, the starting unit 402 and the detection unit 404 in the embodiment of the present application can be the processor of the device, the sending unit 401 can be the transmitter of the device, and the receiving unit 403 can be the receiver of the device. The transmitter can usually be integrated with the receiver to be used as a transceiver. The specific transceiver can also be called a communication interface or interface circuit.

[0119] like Figure 9 As shown, it is a structural schematic diagram of another interface test starting device involved in the above-mentioned embodiment provided in the embodiment of the present application. The device can serve as a first core particle. The device includes: a processor 411, and may also include a memory 412, a communication interface 413 and a bus 414. The processor 411, the memory 412 and the communication interface 413 are connected through the bus 414.

[0120] Processor 411 is used to control and manage the actions of the device. In one possible embodiment, processor 411 can be used to support the device in receiving S303a and S306b in the above method embodiment, and / or other technical processes described herein. Communication interface 413 is used to support communication with the device, such as supporting communication between the device and the second chip.

[0121] In the embodiments of the present application, the processor 411 may be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field-programmable gate array, or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. It may implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, and the like. The aforementioned bus 414 may include an address bus, a data bus, a control bus, and the like.

[0122] In the case of an integrated unit, Figure 10A schematic structural diagram of a device for starting an interface test involved in the above-mentioned embodiment is shown. The device can be a second core particle and includes: a receiving unit 501, a detection unit 502, and a starting unit 503. The receiving unit 501 can be used to support the device in executing the receiving step in S302 of the above-mentioned method embodiment; the detection unit 502 can be used to support the device in executing the detecting step in S302 of the above-mentioned method embodiment; and the starting unit 503 can be used to support the device in executing S303b of the above-mentioned method embodiment. Furthermore, the device also includes a sending unit 504. The sending unit 504 is used to support the device in executing S304 of the above-mentioned method embodiment; and the starting unit 503 is also used to support the device in executing S306a of the above-mentioned method embodiment. All relevant content of each step involved in the above-mentioned method embodiment can be referenced to the functional description of the corresponding functional module, and will not be further described in detail in this embodiment of the present application. All relevant content of each step involved in the above-mentioned method embodiment can be referenced to the functional description of the corresponding functional module, and will not be further described in detail in this embodiment of the present application.

[0123] Based on the hardware implementation, the detection unit 502 and the starting unit 503 in the embodiment of the present application can be the processor of the device, the receiving unit 501 can be the receiver of the device, and the sending unit 504 can be the transmitter of the device. The transmitter can usually be integrated with the receiver to be used as a transceiver. The specific transceiver can also be called a communication interface or interface circuit.

[0124] like Figure 11 As shown, it is a structural schematic diagram of another interface test starting device involved in the above-mentioned embodiment provided in the embodiment of the present application. The device can serve as a second core particle. The device includes: a processor 511, and may also include a memory 512, a communication interface 513 and a bus 514. The processor 511, the memory 512 and the communication interface 513 are connected through the bus 514.

[0125] The processor 511 is used to control and manage the operation of the device. In one possible embodiment, the processor 511 can be used to support the device in executing the detection steps in S302, S303b, S306a of the above-mentioned method embodiment, and / or other technical processes described herein. The communication interface 513 is used to support the device in communicating, such as supporting the device in communicating with the first chiplet.

[0126] In the embodiments of the present application, the processor 511 may be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field-programmable gate array, or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. It may implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, and the like. The aforementioned bus 514 may include an address bus, a data bus, a control bus, and the like.

[0127] In another embodiment of the present application, a communication device is provided, which includes a first core particle and a second core particle; wherein the first core particle can be or include the above-mentioned Figure 8 or Figure 9 The device provided is used to perform the steps of the first core particle in the method embodiment provided above; the second core particle can be or include the above Figure 10 or Figure 11 The provided device is used to perform the second core particle step in the method embodiment provided above.

[0128] It can be understood that all relevant contents of each step involved in the above method embodiment can be referred to the embodiment of the starting device of the interface test and the embodiment of the communication device, and the embodiments of the present application will not be repeated here.

[0129] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical functional division. In actual implementation, other division methods may be used, such as combining or integrating multiple units or components into another device, or ignoring or not implementing certain features.

[0130] The units described as separate components may or may not be physically separate, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple places. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0131] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. The readable storage medium may include: a USB flash drive, a mobile hard drive, a read-only memory, a random access memory, a magnetic disk, or an optical disk, etc., which can store program code. Based on this understanding, the technical solution of the embodiment of the present application, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product.

[0132] In another embodiment of the present application, a readable storage medium is also provided, which stores computer execution instructions. When a device (which may be a single-chip microcomputer, chip, etc.) or a processor executes the steps of the first core particle in the above method embodiment.

[0133] In another embodiment of the present application, a readable storage medium is also provided, which stores computer execution instructions. When a device (which may be a single-chip microcomputer, chip, etc.) or a processor executes the steps of the second core particle in the above method embodiment.

[0134] In another embodiment of the present application, a computer program product is also provided, which includes computer instructions stored in a readable storage medium; at least one processor of the device can read the computer instructions from the readable storage medium, and at least one processor executes the computer instructions to enable the device to perform the steps of the first core particle in the above method embodiment.

[0135] In another embodiment of the present application, a computer program product is also provided, which includes computer instructions stored in a readable storage medium; at least one processor of the device can read the computer instructions from the readable storage medium, and at least one processor executes the computer instructions to enable the device to perform the steps of the second core particle in the above method embodiment.

[0136] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for starting an interface test, characterized in that: The method comprises: A first chiplet sends a first preamble to a second chiplet via at least one first interface, where the first preamble indicates that the first chiplet is about to start a first BIST test. The first chiplet is interconnected with the second chiplet via multiple interfaces, where the multiple interfaces include the at least one first interface. When the first preamble is completely sent, the first chip starts the first BIST test.

2. The method according to claim 1, characterized in that The at least one first interface includes at least two first interfaces, and the first core particle sends a first preamble code to the second core particle through the at least one first interface, including: The first core cell sends a first preamble to the second core cell through each of the at least two first interfaces.

3. The method according to claim 1 or 2, characterized in that The method further comprises: The first chip receives and detects a second preamble from the second chip through at least one second interface, where the second preamble indicates that the second chip is about to start a second BIST test; When the first chip successfully detects the second preamble, the first chip initiates the second BIST test.

4. The method according to claim 3, characterized in that The at least one second interface includes at least two second interfaces, and the first core particle receives the second preamble from the second core particle through the at least one second interface, including: The first corelet receives the second preamble from the second corelet through each of the at least two second interfaces.

5. The method according to claim 3 or 4, characterized in that For a second preamble corresponding to any second interface of the at least one second interface, the method further includes: The first core detects whether the second preamble is consistent with the comparison preamble. When the second preamble is consistent with the comparison preamble, it indicates that the second preamble is successfully detected.

6. The method according to any one of claims 1 to 5, characterized in that The invention is applied to a chip package including a plurality of core particles, wherein the plurality of core particles are interconnected and packaged by using core particle technology, and the plurality of core particles include the first core particle and the second core particle.

7. The method according to any one of claims 1 to 6, characterized in that The first preamble or the second preamble includes a plurality of data of a certain length, and the plurality of data includes different data.

8. The method according to any one of claims 1 to 7, characterized in that Among the at least one first interface or the at least one second interface, there are at least two interfaces whose interface distance is greater than a preset distance.

9. A method for starting an interface test, characterized in that: The method comprises: a second chiplet receiving and detecting a first preamble from the first chiplet via at least one first interface, wherein the first preamble is used to indicate that the first chiplet is about to start a first BIST test, and the second chiplet is interconnected with the first chiplet via a plurality of interfaces, wherein the plurality of interfaces include the at least one first interface; When the second chip successfully detects the first preamble, the second chip starts the first BIST test.

10. The method according to claim 9, characterized in that The at least one first interface includes at least two first interfaces, and the second chip receives the first preamble from the first chip through the at least one first interface, including: The second chiplet receives the first preamble from the first chiplet through each first interface of the at least two first interfaces.

11. The method according to claim 9 or 10, characterized in that For a first preamble corresponding to any first interface of the at least one first interface, the second chip detects the first preamble, including: The second chip detects whether the first preamble is consistent with the comparison preamble. When the first preamble is consistent with the comparison preamble, it indicates that the first preamble is successfully detected.

12. The method according to any one of claims 9 to 11, characterized in that: The method further comprises: The second chiplet sends a second preamble to the first chiplet through at least one second interface, where the second preamble is used to indicate that the second chiplet is about to start a second BIST test; When the second preamble is completely sent, the second chip starts the second BIST test.

13. The method according to claim 12, characterized in that The at least one second interface includes at least two second interfaces, and the second core particle sends a second preamble to the first core particle through the at least one second interface, including: The second corelet sends a second preamble to the first corelet through each of the at least two second interfaces.

14. The method according to any one of claims 9 to 13, characterized in that: The invention is applied to a chip package including a plurality of core particles, wherein the plurality of core particles are interconnected and packaged by using core particle technology, and the plurality of core particles include the first core particle and the second core particle.

15. The method according to any one of claims 9 to 14, characterized in that: The first preamble or the second preamble includes a plurality of data of a certain length, and the plurality of data includes different data.

16. The method according to any one of claims 9 to 15, characterized in that: Among the at least one first interface or the at least one second interface, there are at least two interfaces whose interface distance is greater than a preset distance.

17. A device for starting an interface test, characterized in that: The device comprises: a sending unit, configured to send a first preamble to a second chiplet through at least one first interface, wherein the first preamble is used to indicate that the device is about to start a first BIST test, and the device is interconnected with the second chiplet through multiple interfaces, wherein the multiple interfaces include the at least one first interface; A starting unit is configured to start the first BIST test when the first preamble code is sent completely.

18. The device according to claim 17, characterized in that The sending unit is further configured to send a first preamble to the second chiplet through each of the at least two first interfaces.

19. The device according to claim 17 or 18, characterized in that The device also includes a receiving unit and a detecting unit; The receiving unit is configured to receive a second preamble from the second chiplet through at least one second interface, where the second preamble is used to indicate that the second chiplet is about to start a second BIST test; The detection unit is configured to detect the second preamble; The starting unit is further configured to start the second BIST test when the second preamble is successfully detected.

20. The device according to claim 19, characterized in that The at least one second interface includes at least two second interfaces; The receiving unit is further configured to receive a second preamble from the second chiplet through each of the at least two second interfaces.

21. The device according to claim 19 or 20, characterized in that The device further comprises a detection unit; The detection unit is further configured to detect, for a second preamble corresponding to any second interface of the at least one second interface, whether the second preamble is consistent with a comparison preamble; when the second preamble is consistent with the comparison preamble, it indicates that the second preamble is successfully detected.

22. The device according to any one of claims 17 to 21, characterized in that The device is applied to a chip package including a plurality of core particles, wherein the plurality of core particles are interconnected and packaged through core particle technology, the device serves as a first core particle, and the plurality of core particles include the first core particle and the second core particle.

23. The device according to any one of claims 17 to 22, characterized in that The first preamble or the second preamble includes a plurality of data of a certain length, and the plurality of data includes different data.

24. The device according to any one of claims 17 to 23, characterized in that Among the at least one first interface or the at least one second interface, there are at least two interfaces whose interface distance is greater than a preset distance.

25. A device for starting an interface test, characterized in that: The device comprises: a receiving unit, configured to receive a first preamble from a first chiplet through at least one first interface, wherein the first preamble is used to indicate that the first chiplet is about to start a first BIST test, wherein the device is interconnected with the first chiplet through a plurality of interfaces, wherein the plurality of interfaces include the at least one first interface; a detection unit, configured to detect the first preamble; A starting unit is configured to start the first BIST test when the first preamble code is successfully detected.

26. The device according to claim 25, characterized in that The at least one first interface includes at least two first interfaces; The receiving unit is further configured to receive a first preamble from the first chiplet through each of the at least two first interfaces.

27. The device according to claim 25 or 26, characterized in that A first preamble corresponding to any first interface of the at least one first interface; The detection unit is further configured to detect whether the first preamble is consistent with the comparison preamble, and when the first preamble is consistent with the comparison preamble, it indicates that the first preamble is successfully detected.

28. The device according to any one of claims 25 to 27, characterized in that The device further includes a sending unit; The sending unit is configured to send a second preamble to the first chip through at least one second interface, where the second preamble is used to indicate that the device is about to start a second BIST test; The starting unit is further configured to start the second BIST test when the sending of the second preamble is completed.

29. The device according to claim 28, characterized in that The at least one second interface includes at least two second interfaces; The sending unit is further configured to send a second preamble to the first chiplet through each of the at least two second interfaces.

30. The device according to any one of claims 25 to 29, characterized in that The device is applied to a chip package including a plurality of core particles, wherein the plurality of core particles are interconnected and packaged through core particle technology, the device serves as a second core particle, and the plurality of core particles include the first core particle and the second core particle.

31. The device according to any one of claims 25 to 30, characterized in that The first preamble or the second preamble includes a plurality of data of a certain length, and the plurality of data includes different data.

32. The device according to any one of claims 25 to 31, characterized in that Among the at least one first interface or the at least one second interface, there are at least two interfaces whose interface distance is greater than a preset distance.

33. A device for starting an interface test, characterized in that: The device comprises: a processing circuit and a communication interface, wherein the processing circuit and the communication interface are used to support the device in executing the method according to any one of claims 1 to 8.

34. A device for starting an interface test, characterized in that: The device comprises: a processing circuit and a communication interface, wherein the processing circuit and the communication interface are used to support the device to execute the method according to any one of claims 9 to 16.

35. A communication device, characterized in that: The communication device includes a first core particle and a second core particle, the first core particle includes the device according to any one of claims 17 to 24 or the device according to claim 33, and the second core particle includes the device according to any one of claims 25 to 32 or the device according to claim 34.

36. A readable storage medium, characterized in that The readable storage medium stores instructions, and when the instructions are executed on a device, the device is caused to execute the method according to any one of claims 1 to 8.

37. A readable storage medium, characterized in that The readable storage medium stores instructions, and when the instructions are executed on a device, the device executes the method according to any one of claims 9 to 16.

Images