Simulation chip test system and method

Abstract

The invention provides an analog chip test system, which comprises a signal input module, a test module, a signal processing module, a signal acquisition module and an upper computer which are connected in sequence, and is characterized in that the signal acquisition module is connected with one end, connected with the signal input module, of the test module; the test module is used for connecting an analog chip to be tested, the signal input module is used for inputting a signal to the analog chip to be tested through the test module, and the signal processing module is used for receiving an output signal of the analog chip to be tested through the test module, processing the received output signal and outputting the processed output signal to the analog chip to be tested. The signal acquisition module is used for acquiring a signal processed by the signal processing module and a signal input to the analog chip to be tested by the signal input module, and the upper computer is used for receiving the signal acquired by the signal acquisition module and analyzing the signal to obtain a test result of the analog chip to be tested. The practicability of the test system can be improved.

Description

Technical Field

[0001] The present application relates to the field of testing technology, and in particular to an analog chip testing system and method. Background Art

[0002] Analog chip test systems are used to test and verify the performance and reliability of analog chips. As technology advances, the performance of analog chips continues to improve. However, current analog chip test systems struggle to meet the multi-parameter testing requirements of analog chips, such as the ripple rejection ratio of voltage regulators, power supply monitoring timing, and voltage noise of operational amplifiers. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide an analog chip testing system and method.

[0004] Based on the above purpose, the present application provides an analog chip testing system, comprising a signal input module, a test module, a signal processing module, a signal acquisition module and a host computer connected in sequence, wherein the signal acquisition module is connected to one end of the test module connected to the signal input module;

[0005] The test module is used to connect to the analog chip to be tested, the signal input module is used to input signals to the analog chip to be tested through the test module, the signal processing module is used to receive the output signal of the analog chip to be tested through the test module and process the received output signal, the signal acquisition module is used to collect the signal processed by the signal processing module and the signal input to the analog chip to be tested by the signal input module, and the host computer is used to receive the signal collected by the signal acquisition module and analyze the signal to obtain the test result of the analog chip to be tested.

[0006] Furthermore, the test system also includes a low-noise power supply module, which is connected to the signal input module, test module, signal processing module, signal acquisition module, and host computer to provide power to the signal input module, test module, signal processing module, signal acquisition module, and host computer.

[0007] Furthermore, the signal input module includes a first power supply end, a first output end, an arbitrary function generating submodule and a fast pulse generating submodule, the first power supply end and the first output end are both connected to the arbitrary function generating submodule and the fast pulse generating submodule, the first power supply end is connected to the low-noise power supply module, and the first output end is connected to the test module.

[0008] Furthermore, the test module includes a test input terminal, a test output terminal, a test power supply terminal and an adapter sub-module. The adapter sub-module is connected to the test input terminal, the test output terminal and the test power supply terminal. The adapter sub-module is used to connect the analog chip to be tested. The test module is connected to the signal input module through the test input terminal and to the signal processing module through the test output terminal.

[0009] Furthermore, the signal processing module includes a processing power supply terminal, a processing input terminal, a processing output terminal, a connection submodule, a ripple suppression ratio processing submodule and a voltage noise processing submodule;

[0010] The processing power supply end is connected to the low-noise power supply module, the processing input end is connected to the test module, and the processing output end is connected to the signal acquisition module;

[0011] The ripple suppression ratio processing submodule and the voltage noise processing submodule are both connected to the processing power supply end, the processing input end, and the processing output end, and the connection submodule is connected to the processing input end and the processing output end;

[0012] The signal processing module is connected to the testing module via the processing input end, and is connected to the signal acquisition module via the processing output end.

[0013] Furthermore, the signal acquisition module includes an acquisition power supply terminal, an acquisition input terminal, an acquisition output terminal, a voltage and current signal acquisition submodule, and a time signal acquisition submodule;

[0014] The acquisition power supply end is connected to the low-noise power supply module, the acquisition input end is connected to the processing output end, and the acquisition output end is connected to the host computer;

[0015] The voltage and current signal acquisition submodule and the time signal acquisition submodule are both connected to the acquisition power supply end, the acquisition input end and the acquisition output end;

[0016] The signal acquisition module is connected to the signal processing module and the test input terminal of the test module through the acquisition input terminal, and is connected to the host computer through the acquisition output terminal.

[0017] Furthermore, the fast pulse generation submodule includes a fast pulse generation unit and an impedance matching unit connected in sequence, the first power supply end is connected to the fast pulse generation unit, and the first output end is connected to the impedance matching unit.

[0018] Furthermore, the adapter submodule is connected to the test module via a test probe, the test module is provided with a plug-in slot adapted to the test probe, one end of the test probe is fixedly connected to the adapter submodule, and the other end is plugged into the plug-in slot;

[0019] The test input end, the test output end and the test power supply end are connected to the plug slot, and are connected to the adapter submodule through the plug slot and the test probe.

[0020] Based on the same inventive concept, the present application also provides an analog chip testing method, which is applied to the analog chip testing system described above, and the method includes:

[0021] Obtain the analog chip to be tested and determine the test items;

[0022] A test environment is built based on the test items and the test system, and the test items are tested on the simulated chip to be tested in the test environment to obtain test results through the host computer.

[0023] Furthermore, the test items include a voltage regulator ripple rejection ratio test, an operational amplifier noise test, and a power supply monitoring timing test; and the test environment is established based on the test items and the test system, including:

[0024] In response to determining that the test item is a voltage regulator ripple rejection ratio test, the test environment established in the test system is as follows: the arbitrary function generation submodule of the signal input module is connected to the first power supply terminal and the first output terminal, the ripple rejection ratio processing submodule of the signal processing module is connected to the processing power supply terminal, the processing input terminal, and the processing output terminal, the voltage and current signal acquisition submodule of the signal acquisition module is connected to the acquisition power supply terminal, the acquisition input terminal, and the acquisition output terminal, and the acquisition input terminal of the signal acquisition module is connected to the test input terminal of the test module;

[0025] In response to determining that the test item is an operational amplifier noise test, the test environment established in the test system is as follows: the signal input module and the test module are disconnected, the voltage noise processing submodule of the signal processing module is connected to the processing power supply terminal, the processing input terminal, and the processing output terminal, and the voltage and current signal acquisition submodule of the signal acquisition module is connected to the acquisition power supply terminal, the acquisition input terminal, and the acquisition output terminal;

[0026] In response to determining that the test item is a power supply monitoring timing test, the test environment constructed in the test system is: the fast pulse generation submodule of the signal input module is connected to the first power supply end and the first output end, the connection submodule of the signal processing module is connected to the processing input end and the processing output end, and the time signal acquisition submodule of the signal acquisition module is connected to the acquisition power supply end, the acquisition input end and the acquisition output end.

[0027] Furthermore, before building a test environment based on the test items and the test system, the method further includes:

[0028] In response to determining that the test item is a voltage regulator ripple rejection ratio test, performing performance verification on the arbitrary function generation submodule of the signal input module and the ripple rejection ratio processing submodule of the signal processing module;

[0029] In response to determining that the test item is an operational amplifier noise test, performing performance verification on the voltage noise processing submodule of the signal processing module;

[0030] In response to determining that the test item is a power monitoring timing test, performance verification is performed on the fast pulse generation submodule of the signal input module.

[0031] Furthermore, the performance verification of the arbitrary function generation submodule of the signal input module and the ripple suppression ratio processing submodule of the signal processing module includes:

[0032] Connecting the arbitrary function generating submodule of the signal input module to the test module on which the analog chip to be tested is installed;

[0033] Controlling the arbitrary function generation submodule to output an AC signal that meets the first verification condition, and respectively obtaining the AC signal received by the test input terminal when the analog chip to be tested is under no-load and preset load;

[0034] In response to determining that the AC signals received by the test input terminal meet the first verification condition under no-load and preset load conditions of the analog chip to be tested, it is determined that the arbitrary function generation submodule passes the performance verification.

[0035] Furthermore, the performance verification of the arbitrary function generation submodule of the signal input module and the ripple suppression ratio processing submodule of the signal processing module further includes:

[0036] Connecting the arbitrary function generation submodule of the signal input module and the ripple suppression ratio processing submodule of the signal processing module;

[0037] Controlling the arbitrary function generation submodule to output an AC signal that meets a second verification condition, and obtaining the AC signal output by the ripple suppression ratio processing submodule;

[0038] In response to determining that the AC signal output by the ripple suppression ratio processing submodule meets a first preset condition, calculating a gain parameter of the ripple suppression ratio processing submodule;

[0039] In response to determining that the gain parameter meets the second preset condition, determining that the ripple suppression ratio processing submodule passes the gain performance verification;

[0040] In response to determining that the ripple rejection ratio processing submodule passes the gain performance verification, controlling the arbitrary function generation submodule to stepwise output AC signals of different frequencies to the ripple rejection ratio processing submodule to determine an upper limit cutoff frequency and a lower limit cutoff frequency of the ripple rejection ratio processing submodule;

[0041] In response to determining that the frequency of the AC signal that meets the second verification condition is between the upper cutoff frequency and the lower cutoff frequency, it is determined that the ripple suppression ratio processing submodule passes the passband performance verification and the ripple suppression ratio processing submodule passes the performance verification.

[0042] Furthermore, the performance verification of the voltage noise processing submodule of the signal processing module includes:

[0043] Connecting the arbitrary function generation submodule of the signal input module and the voltage noise processing submodule of the signal processing module;

[0044] controlling the arbitrary function generation submodule to output an AC signal that meets a third verification condition, and acquiring the AC signal output by the voltage noise processing submodule;

[0045] In response to determining that the AC signal output by the voltage noise processing submodule meets a third preset condition, calculating a gain parameter of the voltage noise processing submodule;

[0046] In response to determining that the gain parameter meets a fourth preset condition, determining that the voltage noise processing submodule passes gain performance verification;

[0047] In response to determining that the voltage noise processing submodule passes the gain performance verification, controlling the arbitrary function generation submodule to stepwise output AC signals of different frequencies to the voltage noise processing submodule to determine an upper cutoff frequency and a lower cutoff frequency of the voltage noise processing submodule;

[0048] In response to determining that the upper cutoff frequency and the lower cutoff frequency are respectively the same as the maximum value and the minimum value of the processing frequency band of the analog chip to be tested, it is determined that the voltage noise processing submodule passes the passband performance verification, and the voltage noise processing submodule passes the performance verification.

[0049] Furthermore, the performance verification of the fast pulse generation submodule of the signal input module includes:

[0050] Connecting the fast pulse generation submodule of the signal input module to the test module on which the analog chip to be tested is installed;

[0051] Controlling the fast pulse generation submodule to output a pulse signal and a fast edge signal that meet a fifth preset condition, and acquiring the pulse signal and the fast edge signal received by the test input end of the test module;

[0052] In response to determining that the pulse signal and the fast edge signal received by the test input terminal meet the fourth verification condition, it is determined that the fast pulse generation submodule passes the performance verification.

[0053] As can be seen from the above, the present application provides an analog chip testing system, which is formed by setting a signal input module, a test module, a signal processing module, a signal acquisition module and a host computer connected in sequence, and the signal acquisition module is connected to one end of the signal input module connected to the test module, and the test module is used to connect the analog chip to be tested. When the test system tests the test items of different analog chips to be tested, the specific connection conditions of the signal input module, the test module, the signal processing module, the signal acquisition module and the host computer are adjusted, so that the signal acquisition module can obtain the corresponding signal under different connection conditions and send it to the host computer, so that the host computer analyzes the received signal and obtains the test result of the analog chip to be tested; the present application forms a test system by integrating the signal input module, the test module, the signal processing module, the signal acquisition module and the host computer, and when testing the test items of different analog chips to be tested, the connection conditions of the test system are adjusted to adapt to the test requirements of the corresponding test items, so that the signal acquisition module can obtain the corresponding signal and send it to the host computer for analysis to obtain the test result corresponding to the test item, so as to meet the multi-parameter testing requirements of the analog chip, which is conducive to improving the practicality of the test system. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in this application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are merely embodiments of this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0055] Figure 1 This is a schematic diagram of the structure of the test system for simulating a chip according to an embodiment of the present application;

[0056] Figure 2 This is a schematic structural diagram of the signal input module according to an embodiment of the present application;

[0057] Figure 3 This is a schematic diagram of the structure of the test module of the embodiment of the present application;

[0058] Figure 4 This is a schematic diagram of the structure of the signal processing module according to an embodiment of the present application;

[0059] Figure 5 This is a schematic diagram of the structure of the signal acquisition module according to an embodiment of the present application;

[0060] Figure 6 This is a schematic structural diagram of the fast pulse generation submodule according to an embodiment of the present application;

[0061] Figure 7 This is a schematic diagram of the process structure of the simulation chip testing method according to an embodiment of the present application;

[0062] Figure 8 A schematic diagram of the structure of a test system for testing the ripple rejection ratio of a voltage regulator according to an embodiment of the present application;

[0063] Figure 9 This is a schematic diagram of the test system structure for the operational amplifier noise test according to an embodiment of the present application;

[0064] Figure 10 This is a schematic diagram of the test system structure for power monitoring timing testing according to an embodiment of the present application.

[0065] In the figure: 100, signal input module; 110, first power supply terminal; 120, first output terminal; 130, arbitrary function generation submodule; 140, fast pulse generation submodule; 141, fast pulse generation unit; 142, impedance matching unit; 200, test module; 210, test input terminal; 220, test output terminal; 230, test power supply terminal; 240, adapter submodule; 300, signal processing module; 310, processing power supply terminal; 320, processing input terminal; 330, processing output terminal; 340, connection submodule; 350, ripple suppression ratio processing submodule; 360, voltage noise processing submodule; 400, signal acquisition module; 410, acquisition power supply terminal; 420, acquisition input terminal; 430, acquisition output terminal; 440, voltage and current signal acquisition submodule; 450, time signal acquisition submodule; 500, host computer; 600, low noise power supply module. DETAILED DESCRIPTION

[0066] In order to make the objectives, technical solutions and advantages of this application more clear, this application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0067] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should have the usual meanings understood by people with ordinary skills in the field to which this application belongs. The "first", "second" and similar words used in the embodiments of the present application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0068] In the field of analog chip testing and verification, analog chip test systems are the core platform for ensuring that analog chips meet performance standards and maintain reliability. Current mainstream analog chip test systems typically consist of basic units such as power supply modules, load modules, signal generation modules, and oscilloscope modules. These conventional modules have limitations when addressing the complex testing requirements of modern high-speed, high-precision analog chips. As the operating frequency and signal processing accuracy requirements of analog chips continue to increase, traditional test systems are no longer able to meet the multi-parameter testing needs of analog chips.

[0069] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0070] In some embodiments, the present application provides an analog chip testing system, such as Figure 1 As shown, it includes a signal input module 100, a test module 200, a signal processing module 300, a signal acquisition module 400 and a host computer 500 connected in sequence, wherein the signal acquisition module 400 is connected to one end of the test module 200 connected to the signal input module 100;

[0071] The test module 200 is used to connect to the analog chip to be tested, the signal input module 100 is used to input signals to the analog chip to be tested through the test module 200, the signal processing module 300 is used to receive the output signal of the analog chip to be tested through the test module 200, and process the received output signal, the signal acquisition module 400 is used to collect the signal processed by the signal processing module 300 and the signal input to the analog chip to be tested by the signal input module 100, and the host computer 500 is used to receive the signal collected by the signal acquisition module 400, and analyze the signal to obtain the test result of the analog chip to be tested.

[0072] Specifically, the host computer 500 is used to analyze and calculate the signal collected by the signal acquisition module 400 to obtain the test result. The host computer 500 can automatically match and calculate corresponding parameters based on the received signal.

[0073] The test system is suitable for testing multiple parameters. When testing a certain parameter, the modules of the test system are connected according to the connection method corresponding to the parameter, and the corresponding test parameters (i.e., the test results) can be obtained through the host computer 500.

[0074] Exemplarily, the signal input module 100 , the test module 200 , the signal processing module 300 , and the signal acquisition module 400 may be circuit boards, the only difference being that the components and circuits provided thereon are different, and thus the functions they play are different.

[0075] In this embodiment, by setting a signal input module 100, a test module 200, a signal processing module 300, a signal acquisition module 400 and a host computer 500 that are connected in sequence, and the signal acquisition module 400 is connected to one end of the signal input module 100 connected to the test module 200, and the test module 200 is used to connect the analog chip to be tested. When the test system tests the test items of different analog chips to be tested, by adjusting the specific connection conditions of the signal input module 100, the test module 200, the signal processing module 300, the signal acquisition module 400 and the host computer 500, the signal acquisition module 400 can obtain corresponding signals in different connection conditions to send To the host computer 500, so that the host computer 500 analyzes the received signal to obtain the test result of the analog chip to be tested; the present application forms a test system by integrating the signal input module 100, the test module 200, the signal processing module 300, the signal acquisition module 400 and the host computer 500, and when testing different test items of the analog chip to be tested, adjusts the connection status of the test system to adapt to the corresponding test requirements of the test items, so that the signal acquisition module 400 obtains the corresponding signal and sends it to the host computer 500 for analysis to obtain the test result corresponding to the test item, so as to meet the multi-parameter testing requirements of the analog chip, which is conducive to improving the practicality of the test system.

[0076] In some embodiments, as Figure 1 As shown, the test system also includes a low-noise power supply module 600, which is connected to the signal input module 100, the test module 200, the signal processing module 300, the signal acquisition module 400, and the host computer 500 to power the signal input module 100, the test module 200, the signal processing module 300, the signal acquisition module 400, and the host computer 500.

[0077] Specifically, the low-noise power supply module 600 is used to power the various modules of the test system and the host computer 500 to ensure the normal operation of the test system. The setting of the low-noise power supply module 600 can reduce its impact on the test system, which is conducive to improving the test accuracy of the test system.

[0078] In some embodiments, as Figure 2 As shown, the signal input module 100 includes a first power supply terminal 110, a first output terminal 120, an arbitrary function generating submodule 130 and a fast pulse generating submodule 140. The first power supply terminal 110 and the first output terminal 120 are both connected to the arbitrary function generating submodule 130 and the fast pulse generating submodule 140. The first power supply terminal 110 is connected to the low-noise power supply module 600, and the first output terminal 120 is connected to the test module 200.

[0079] Specifically, the signal input module 100 inputs a signal to the test module 200 through the arbitrary function generating submodule 130 and the rapid pulse generating submodule 140, that is, the signal input module 100 outputs a signal through the arbitrary function generating submodule 130 and the rapid pulse generating submodule 140, the first power supply end 110 and the first output end 120 are functional connection ports of the signal input module 100, when the signal input module 100 outputs a signal through the arbitrary function generating submodule 130, the arbitrary function generating submodule 130 is connected to the first power supply end 110 and the first output end 120; when the signal input module 100 outputs a signal through the rapid pulse generating submodule 140, the rapid pulse generating submodule 140 is connected to the first power supply end 110 and the first output end 120.

[0080] Exemplarily, the arbitrary function generating submodule 130 and the fast pulse generating submodule 140 are connected to the first power supply end 110 via a single-pole double-throw switch, and the arbitrary function generating submodule 130 and the fast pulse generating submodule 140 are also connected to the first output end 120 via a single-pole double-throw switch. When the signal input module 100 outputs a signal through the arbitrary function generating submodule 130, the two single-pole double-throw switches can be adjusted to be connected to the arbitrary function generating submodule 130, and the fast pulse generating submodule 140 is disconnected from both the single-pole double-throw switches.

[0081] In some embodiments, as Figure 3 As shown, the test module 200 includes a test input terminal 210, a test output terminal 220, a test power supply terminal 230 and an adapter sub-module 240. The adapter sub-module 240 is connected to the test input terminal 210, the test output terminal 220 and the test power supply terminal 230. The adapter sub-module 240 is used to connect the analog chip to be tested. The test module 200 is connected to the signal input module 100 through the test input terminal 210, and is connected to the signal processing module 300 through the test output terminal 220.

[0082] Specifically, the adapter submodule 240 is detachably connected to the test module 200 so that the test module 200 can be connected to different adapter submodules 240 , thereby enabling the test module 200 to be connected to different analog chips to be tested.

[0083] The test input terminal 210 is used to receive the signal input by the signal input module 100 and transmit it to the analog chip to be tested. The test output terminal 220 is used to output the signal output by the analog chip to be tested. The test power supply terminal 230 is used to supply power to the analog chip to be tested to ensure the normal operation of the analog chip to be tested, thereby facilitating the test system to test the analog chip to be tested.

[0084] In some embodiments, as Figure 4 As shown, the signal processing module 300 includes a processing power supply terminal 310, a processing input terminal 320, a processing output terminal 330, a connection submodule 340, a ripple suppression ratio processing submodule 350 and a voltage noise processing submodule 360;

[0085] The processing power supply terminal 310 is connected to the low-noise power supply module 600 , the processing input terminal 320 is connected to the test module 200 , and the processing output terminal 330 is connected to the signal acquisition module 400 ;

[0086] The ripple suppression ratio processing submodule 350 and the voltage noise processing submodule 360 ​​are both connected to the processing power supply terminal 310, the processing input terminal 320 and the processing output terminal 330, and the connection submodule 340 is connected to the processing input terminal 320 and the processing output terminal 330;

[0087] The signal processing module 300 is connected to the testing module 200 via the processing input terminal 320 , and is connected to the signal acquisition module 400 via the processing output terminal 330 .

[0088] Specifically, the signal processing module 300 is used to process the signal output by the test module 200 and send it to the signal acquisition module 400. The processing power supply end 310 is connected to the ripple suppression ratio processing submodule 350 and the voltage noise processing submodule 360 ​​through a single-pole double-throw switch. The processing input end 320 is connected to the connection submodule 340, the ripple suppression ratio processing submodule 350 and the voltage noise processing submodule 360 ​​through a single-pole triple-throw switch. The processing output end 330 is also connected to the connection submodule 340, the ripple suppression ratio processing submodule 350 and the voltage noise processing submodule 360 ​​through a single-pole triple-throw switch.

[0089] When the signal processing module 300 sends the signal received by the processing input terminal 320 to the signal output terminal through the connecting submodule 340, the two single-pole three-throw switches are controlled to be connected to the connecting submodule 340, and the processing power supply terminal 310 and the ripple suppression ratio processing submodule 350 and the voltage noise processing submodule 360 ​​are all turned off; when the signal processing module 300 processes the signal received by the processing input terminal 320 through the ripple suppression ratio processing submodule 350 and sends it to the signal output terminal, the two single-pole three-throw switches are controlled to be connected to the ripple suppression ratio processing submodule 350, and the single-pole double-throw switch and the ripple suppression ratio processing submodule 350 are connected. The ripple suppression ratio processing submodule 350 is connected so that the processing power supply terminal 310, the processing input terminal 320 and the processing output terminal 330 are all connected to the ripple suppression ratio processing submodule 350; when the signal processing module 300 processes the signal received by the processing input terminal 320 through the voltage noise processing submodule 360 ​​and sends it to the signal output terminal, the two single-pole three-throw switches are controlled to be connected to the voltage noise processing submodule 360, and the single-pole double-throw switch is connected to the voltage noise processing submodule 360, so that the processing power supply terminal 310, the processing input terminal 320 and the processing output terminal 330 are all connected to the voltage noise processing submodule 360.

[0090] In some embodiments, as Figure 5 As shown, the signal acquisition module 400 includes an acquisition power supply terminal 410, an acquisition input terminal 420, an acquisition output terminal 430, a voltage and current signal acquisition submodule 440 and a time signal acquisition submodule 450;

[0091] The acquisition power supply terminal 410 is connected to the low-noise power supply module 600, the acquisition input terminal 420 is connected to the processing output terminal 330, and the acquisition output terminal 430 is connected to the host computer 500;

[0092] The voltage and current signal acquisition submodule 440 and the time signal acquisition submodule 450 are both connected to the acquisition power supply terminal 410, the acquisition input terminal 420 and the acquisition output terminal 430;

[0093] The signal acquisition module 400 is connected to the signal processing module 300 and the test input terminal 210 of the test module 200 via the acquisition input terminal 420 , and is connected to the host computer 500 via the acquisition output terminal 430 .

[0094] Specifically, the signal acquisition module 400 acquires signals through the acquisition input terminal 420 and outputs the acquired signals through the acquisition output terminal 430. The acquisition power supply terminal 410 is connected to the voltage and current signal acquisition submodule 440 and the time signal acquisition submodule 450 through a single-pole double-throw switch. The acquisition input terminal 420 is connected to the voltage and current signal acquisition submodule 440 and the time signal acquisition submodule 450 through a single-pole double-throw switch. The acquisition output terminal 430 is connected to the voltage and current signal acquisition submodule 440 and the time signal acquisition submodule 450 through a single-pole double-throw switch. When the signal acquisition module 400 acquires signals through the voltage and current signal acquisition submodule 440, the three single-pole double-throw switches are controlled to be connected to the voltage and current signal acquisition submodule 440. When the signal acquisition module 400 is connected through the time signal acquisition submodule 450, the three single-pole double-throw switches are controlled to be connected to the time signal acquisition submodule 450.

[0095] It should be noted that the signal input module 100, signal acquisition module 400 and signal processing module 300 in the test system all connect the sub-modules included therein to the ports set thereon through a single-pole double-throw switch or a single-pole triple-throw switch, so as to adjust the sub-modules in the signal input module 100, signal acquisition module 400 and signal processing module 300 that work normally through the single-pole double-throw switch or the single-pole triple-throw switch, which is beneficial to improving the switching and adjustment efficiency of the test system.

[0096] In some embodiments, as Figure 6 As shown, the fast pulse generation submodule 140 includes a fast pulse generation unit 141 and an impedance matching unit 142 connected in sequence, the first power supply end 110 is connected to the fast pulse generation unit 141 , and the first output end 120 is connected to the impedance matching unit 142 .

[0097] Specifically, the fast pulse generating unit 141 is used to generate a pulse signal, and the impedance matching unit 142 matches the fast pulse generating unit 141 to generate fast rising edge / falling edge and fast edge signals to meet the test requirements of the test system.

[0098] In some embodiments, the adapter submodule 240 is connected to the test module 200 via a test probe. The test module 200 is provided with a socket adapted to the test probe. One end of the test probe is fixedly connected to the adapter submodule 240, and the other end is plugged into the socket.

[0099] The test input terminal 210 , the test output terminal 220 and the test power supply terminal 230 are connected to the plug slot, and are connected to the adapter submodule 240 through the plug slot and the test probe.

[0100] Specifically, the adapter submodule 240 is detachably connected to the test module 200 via the test probe and the plug-in slot. The adapter submodule 240 is adapted to the analog chip to be tested so as to connect to the analog chip to be tested. When testing the analog chip to be tested, the test system selects the adapter submodule 240 that matches the analog chip to be tested to install the analog chip to be tested, and connects the adapter submodule 240 to the test module 200 so that the analog chip to be tested is connected to the test module 200. The provision of the test probe and the plug-in slot can simplify the connection between the adapter submodule 240 and the test module 200, which is beneficial to improving the connection efficiency and test efficiency of the test system.

[0101] Based on the same inventive concept, the present application also provides an analog chip testing method, which is applied to the analog chip testing system as described above. Figure 7 As shown, the method includes:

[0102] Step S100, obtaining an analog chip to be tested and determining test items;

[0103] Specifically, before using the test system for testing, it is necessary to obtain the analog chip to be tested, and determine the test items for the test system to test the analog chip to be tested based on the analog chip to be tested, so as to determine the connection status of the test system based on the test items.

[0104] Step S200 : Building a test environment based on the test items and the test system, and performing the test items on the simulated chip to be tested in the test environment to obtain test results through the host computer 500 .

[0105] Specifically, the connection status of each module in the test system is adjusted according to the determined test items to build the test environment, and the simulated chip to be tested is tested in the built test environment to obtain the test results corresponding to the test items through the host computer 500.

[0106] It should be noted that which submodule in each module of the test system plays a role is related to the test item. When setting up the test environment, it includes installing the analog chip to be tested in the test module 200.

[0107] In this embodiment, a test environment matching the test items is built within the test system based on the test items of the analog chip to be tested, so that the test system can complete the test of the analog chip to be tested, and then obtain the test results of the test items of the analog chip to be tested through the host computer 500, which is conducive to improving the diversity and practicality of the test system.

[0108] In some embodiments, the test items include a voltage regulator ripple rejection ratio test, an operational amplifier noise test, and a power supply monitoring timing test; in step S200, establishing a test environment based on the test items and the test system includes:

[0109] Step S201, as Figure 8 As shown, in response to determining that the test item is a voltage regulator ripple rejection ratio test, the test environment constructed in the test system is as follows: the arbitrary function generation submodule 130 of the signal input module 100 is connected to the first power supply terminal 110 and the first output terminal 120, the ripple rejection ratio processing submodule 350 of the signal processing module 300 is connected to the processing power supply terminal 310, the processing input terminal 320, and the processing output terminal 330, the voltage and current signal acquisition submodule 440 of the signal acquisition module 400 is connected to the acquisition power supply terminal 410, the acquisition input terminal 420, and the acquisition output terminal 430, and the acquisition input terminal 420 of the signal acquisition module 400 is connected to the test input terminal 210 of the test module 200;

[0110] Specifically, when it is determined that the test item of the analog chip to be tested is the voltage regulator ripple suppression ratio test, the test system is adjusted to build the test environment. The specific construction process is that the low-noise power supply module 600 is connected to the signal input module 100, the test module 200, the signal processing module 300, the signal acquisition module 400 and the host computer 500, and the arbitrary function generating submodule 130 of the signal input module 100 is adjusted to be connected to the first power supply terminal 110 and the first output terminal 120, so that the arbitrary function generating submodule 130 works to generate and output a signal; the ripple suppression ratio processing submodule 350 of the signal processing module 300 is adjusted to be connected to the processing power supply terminal 310, the processing input terminal 320 and the processing output terminal 330, so that the ripple suppression ratio processing submodule 350 of the signal processing module 300 is adjusted to be connected to the processing power supply terminal 310, the processing input terminal 320 and the processing output terminal 330, so that the ripple suppression ratio processing submodule 350 of the signal processing module 300 is adjusted to be connected to the processing power supply terminal 310, the processing input terminal 320 and the processing output terminal 330, so that the ripple suppression ratio processing submodule 350 of the signal processing module 300 The ripple suppression ratio processing submodule 350 works to receive and process the signal output by the analog chip to be tested of the test module 200; adjusts the voltage and current signal acquisition submodule 440 of the signal acquisition module 400 to be conductive with the acquisition power supply terminal 410, the acquisition input terminal 420 and the acquisition output terminal 430, and conducts the acquisition input terminal 420 and the test input terminal 210 of the test module 200, so that the voltage and current signal acquisition submodule 440 works to acquire the signal output by the signal processing module 300 and the signal input by the test input terminal 210 of the test module 200, and then the voltage and current signal acquisition submodule 440 can send the acquired signal to the host computer 500 so that the host computer 500 can analyze and process the signal to obtain the ripple suppression ratio of the voltage regulator.

[0111] Step S202, as Figure 9 As shown, in response to determining that the test item is an operational amplifier noise test, the test environment established in the test system is as follows: the signal input module 100 and the test module 200 are disconnected, the voltage noise processing submodule 360 ​​of the signal processing module 300 is connected to the processing power supply terminal 310, the processing input terminal 320, and the processing output terminal 330, and the voltage and current signal acquisition submodule 440 of the signal acquisition module 400 is connected to the acquisition power supply terminal 410, the acquisition input terminal 420, and the acquisition output terminal 430;

[0112] Specifically, when it is determined that the test item of the analog chip to be tested is the operational amplifier noise test, the test system is adjusted to build the test environment. The specific construction process is that the low-noise power supply module 600 is connected to the test module 200, the signal processing module 300, the signal acquisition module 400 and the host computer 500, the signal sending module is turned off from the test module 200 and the low-noise shutdown module, and the voltage noise processing submodule 360 ​​of the signal processing module 300 is connected to the processing power supply end 310, the processing input end 320 and the processing output end. The terminal 330 is turned on, so that the voltage noise processing submodule 360 ​​works to receive and process the electrical signal output by the test module 200, and the voltage and current signal acquisition submodule 440 of the signal acquisition module 400 is turned on with the acquisition power supply terminal 410, the acquisition input terminal 420 and the acquisition output terminal 430, so that the voltage and current signal acquisition submodule 440 works to acquire the signal output by the signal processing module 300 and sends it to the host computer 500, and the host computer 500 analyzes and processes the received signal to obtain the operational amplifier noise.

[0113] Step S203, as Figure 10 As shown, in response to determining that the test item is a power supply monitoring timing test, the test environment constructed in the test system is: the fast pulse generation submodule 140 of the signal input module 100 is connected to the first power supply terminal 110 and the first output terminal 120, the connection submodule 340 of the signal processing module 300 is connected to the processing input terminal 320 and the processing output terminal 330, and the time signal acquisition submodule 450 of the signal acquisition module 400 is connected to the acquisition power supply terminal 410, the acquisition input terminal 420 and the acquisition output terminal 430.

[0114] Specifically, when it is determined that the test item of the analog chip to be tested is the power supply monitoring timing test, the test system is adjusted to build the test environment. The specific construction process is that the low-noise power supply module 600 is connected to the signal input module 100, the test module 200, the signal acquisition module 400 and the host computer 500, and is turned off from the signal processing module 300. The fast pulse generation submodule 140 of the signal input module 100 is connected to the first power supply end 110 and the first output end 120, so that the signal input module 100 outputs a signal through the fast pulse generation submodule 140. The connection submodule 340 of the signal processing module 300 is connected to the processing input terminal 320 and the processing output terminal 330 to connect the test module 200 and the signal acquisition module 400. The time signal acquisition submodule 450 of the signal acquisition module 400 is connected to the acquisition power supply terminal 410, the acquisition input terminal 420 and the acquisition output terminal 430, so that the time signal acquisition submodule 450 collects the signal output by the analog chip to be tested of the test module 200 and sends it to the host computer 500, so that the host computer 500 analyzes and calculates the received signal to obtain the voltage monitoring timing.

[0115] In this embodiment, when the test system tests different test items, the connection conditions of each module in the test system are different, thereby clarifying the process of setting up the test environment, which is conducive to improving the practicality of the test system and achieving the effect of testing multiple parameters by the test system.

[0116] In some embodiments, before step S200: establishing a test environment based on the test project and the test system, the method further includes:

[0117] Step S110, in response to determining that the test item is a voltage regulator ripple rejection ratio test, performing performance verification on the arbitrary function generation submodule 130 of the signal input module 100 and the ripple rejection ratio processing submodule 350 of the signal processing module 300;

[0118] Specifically, when determining that the test item is the voltage regulator ripple suppression ratio test, it is necessary to perform performance verification on the arbitrary function generating submodule 130 of the signal input module 100 and the ripple suppression ratio processing submodule 350 of the signal processing module 300 that are related to the test results of the test item in the test system, so as to avoid affecting the test accuracy of the test system due to the performance difference between the arbitrary function generating submodule 130 of the signal input module 100 and the ripple suppression ratio processing submodule 350 of the signal processing module 300.

[0119] Step S120 , in response to determining that the test item is an operational amplifier noise test, performing performance verification on the voltage noise processing submodule 360 ​​of the signal processing module 300 ;

[0120] Specifically, when it is determined that the test item is the operational amplifier noise test, it is necessary to perform performance verification on the voltage noise processing submodule 360 ​​of the signal processing module 300 related to the test result of the test item in the test system, so as to avoid affecting the test accuracy of the test system due to the poor performance of the voltage noise processing submodule 360 ​​of the signal processing module 300.

[0121] Step S130 , in response to determining that the test item is a power monitoring timing test, the performance of the fast pulse generation submodule 140 of the signal input module 100 is verified.

[0122] Specifically, when it is determined that the test item is the power supply monitoring timing test, it is necessary to perform performance verification on the fast pulse generating submodule 140 of the signal input module 100 related to the test result of the test item in the test system to avoid affecting the test accuracy of the test system due to poor performance of the fast pulse generating submodule 140.

[0123] In this embodiment, the performance verification of the modules in the test system is performed based on the test items, which can complete the performance verification of the test system on the basis of maximizing efficiency, thereby facilitating improvement of the test accuracy of the test system.

[0124] In some embodiments, in step S110, the performance verification of the arbitrary function generation submodule 130 of the signal input module 100 and the ripple suppression ratio processing submodule 350 of the signal processing module 300 includes:

[0125] Step S111, connecting the arbitrary function generating submodule 130 of the signal input module 100 to the test module 200 on which the analog chip to be tested is installed;

[0126] Specifically, the signal input module 100 and the test module 200 are both connected to the low-noise power supply module 600 , and the arbitrary function generation submodule 130 of the signal input module 100 is connected to the first power supply terminal 110 and the first output terminal 120 .

[0127] Step S112, controlling the arbitrary function generation submodule 130 to output an AC signal that meets the first verification condition, and respectively obtaining the AC signal received by the test input terminal 210 when the analog chip to be tested is under no-load and preset load;

[0128] Specifically, the signal acquisition module 400 is connected to the low-noise power supply module 600, and the voltage and current signal acquisition submodule 440 of the signal acquisition module 400 is connected to the acquisition power supply terminal 410, the acquisition input terminal 420 and the acquisition output terminal 430. The acquisition input terminal 420 is connected to the test module 200, and the acquisition output terminal 430 is connected to the host computer 500. The voltage and current signal acquisition submodule 440 collects the AC signals received by the test input terminal 210 of the test module 200 under no-load and preset load respectively, and the performance of the arbitrary function generation submodule 130 is verified through the host computer 500.

[0129] In step S113 , in response to determining that the AC signals received by the test input terminal 210 under no-load and preset load conditions of the analog chip to be tested meet the first verification condition, it is determined that the arbitrary function generation submodule 130 passes the performance verification.

[0130] Specifically, the host computer 500 judges the received AC signal. When it is determined that the received AC signal of the analog chip to be tested meets the first verification condition under no-load and preset load, it proves that the operation of the analog chip to be tested does not affect the AC signal generated by the arbitrary function generating submodule 130 to the test module 200, and the arbitrary function generating submodule 130 passes the performance verification.

[0131] Exemplarily, the first verification condition is that the bias voltage of the AC signal is V BIASin , peak-to-peak value is V PPin and frequency F ACin The sinusoidal AC signal is:

[0132]

[0133] F ACin =F AC_DUT

[0134] V BIASin =V BIAS_DUT

[0135] Among them, V IN_MAX The maximum input voltage of the analog chip under test (voltage regulator under test), V IN_MIN The minimum input voltage for the analog chip under test (voltage regulator under test), V BIAS_DUT is the input bias DC voltage, F AC_DUT is the frequency corresponding to the test frequency point.

[0136] In this embodiment, the performance verification of the arbitrary function generating submodule 130 of the signal input module 100 is completed to avoid the performance of the signal input module 100 being related to the load condition of the analog chip to be tested to which it is connected, thereby effectively avoiding the load condition of the analog chip to be tested affecting the AC signal it receives, which is beneficial to improving the test accuracy of the test system.

[0137] In some embodiments, in step S110, the performance verification of the arbitrary function generation submodule 130 of the signal input module 100 and the ripple suppression ratio processing submodule 350 of the signal processing module 300 further includes:

[0138] Step S114, connecting the arbitrary function generation submodule 130 of the signal input module 100 and the ripple suppression ratio processing submodule 350 of the signal processing module 300;

[0139] Specifically, the low-noise power supply module 600 is connected to the signal input module 100 and the signal processing module 300, and the arbitrary function generation submodule 130 of the signal input module 100 is adjusted to be connected to the first power supply terminal 110 and the first output terminal 120, the ripple suppression ratio processing submodule 350 of the signal processing module 300 is connected to the processing power supply terminal 310, the processing input terminal 320 and the processing output terminal 330, and the first output terminal 120 is connected to the processing input terminal 320.

[0140] Step S115, controlling the arbitrary function generation submodule 130 to output an AC signal that meets the second verification condition, and acquiring the AC signal output by the ripple suppression ratio processing submodule 350;

[0141] Specifically, the arbitrary function generating submodule 130 is used to output an AC signal that complies with the second verification adjustment and sends it to the ripple suppression ratio processing submodule 350 of the signal processing module 300. The AC signal output by the ripple suppression ratio processing submodule 350 is obtained through the voltage and current signal acquisition submodule 440 of the signal acquisition module 400 to verify whether the AC signal output by the ripple suppression ratio processing submodule 350 can pass the performance verification.

[0142] It should be noted that the voltage and current signal acquisition submodule 440 of the signal acquisition module 400 is connected to the acquisition power supply terminal 410, the acquisition input terminal 420 and the acquisition output terminal 430, and the low-noise power supply module 600 is connected to the acquisition power supply terminal 410 to provide power.

[0143] Step S116, in response to determining that the AC signal output by the ripple suppression ratio processing submodule 350 meets the first preset condition, calculating the gain parameter of the ripple suppression ratio processing submodule 350;

[0144] Specifically, the signal acquisition module 400 sends the acquired AC signal to the host computer 500 so that the host computer 500 can analyze it. When it is determined that the AC signal meets the first preset condition, the gain parameter verification can be performed on it.

[0145] Exemplarily, the first preset condition is a size judgment. When the value of the AC signal is within the output voltage range of the ripple suppression ratio processing submodule 350, it can be determined that it meets the first preset condition.

[0146] Step S117, in response to determining that the gain parameter meets the second preset condition, determining that the ripple suppression ratio processing submodule 350 passes the gain performance verification;

[0147] Specifically, the host computer 500 calculates the gain parameter by comparing the voltage of the AC signal output by the ripple suppression ratio processing submodule 350 and the voltage of the AC signal output by the arbitrary function generation submodule 130. On this basis, the host computer 500 determines whether the gain parameter meets the second preset condition to determine whether the ripple suppression ratio processing submodule 350 passes the gain performance verification.

[0148] Exemplarily, the host computer 500 compares the calculated gain parameter with the gain parameter required by the analog chip to be tested. If the calculated gain parameter is not less than the gain parameter required by the analog chip to be tested, it is determined that the ripple suppression ratio processing submodule 350 has passed the gain performance verification.

[0149] Step S118, in response to determining that the ripple suppression ratio processing submodule 350 passes the gain performance verification, controlling the arbitrary function generation submodule 130 to stepwise output AC signals of different frequencies to the ripple suppression ratio processing submodule 350, so as to determine the upper limit cutoff frequency and the lower limit cutoff frequency of the ripple suppression ratio processing submodule 350;

[0150] Specifically, based on the gain performance verification of the ripple suppression ratio processing submodule 350, the passband performance of the ripple suppression ratio processing submodule 350 is verified. The arbitrary function generation submodule 130 is controlled to output an AC signal with a gradually increasing frequency in a stepwise manner. By observing the signal output by the ripple suppression ratio processing submodule 350 collected by the signal acquisition module 400, the upper and lower cutoff frequencies of the ripple suppression ratio processing submodule 350 are determined.

[0151] Exemplarily, when the arbitrary function generation submodule 130 outputs an AC signal less than 100 Hz and greater than 200 Hz, the signal acquisition module 400 cannot collect the ripple suppression ratio output signal, and determines that the upper limit cutoff frequency of the ripple suppression ratio processing submodule 350 is 200 Hz and the lower limit cutoff frequency is 100 Hz.

[0152] Step S119, in response to determining that the frequency of the AC signal that meets the second verification condition is between the upper cutoff frequency and the lower cutoff frequency, it is determined that the ripple suppression ratio processing submodule 350 passes the passband performance verification, and the ripple suppression ratio processing submodule 350 passes the performance verification.

[0153] Specifically, if the frequency of the AC signal output by the arbitrary function generating submodule 130 that meets the second verification condition is between the upper cutoff frequency and the lower cutoff frequency, it is determined that the ripple suppression ratio processing submodule 350 passes the passband performance verification, and the ripple suppression ratio processing submodule 350 passes the performance verification.

[0154] Exemplarily, the arbitrary function generation submodule 130 outputs a bias voltage of V to the ripple suppression ratio processing submodule 350. BIASin , peak-to-peak value is V PP_TESTin and frequency F ACin The sinusoidal AC signal satisfies the second verification condition:

[0155]

[0156] Wherein, is the maximum input voltage of the ripple suppression ratio processing submodule 350, is the minimum input voltage of the ripple suppression ratio processing unit. The AC signal output by the ripple suppression ratio processing submodule 350 must meet the second preset condition:

[0157] PSRR DUT =20log 10 (Gain PSRR )

[0158] Gain≥Gain PSRR

[0159] F ACin =F OUT_PSRR

[0160] V OL <V PP_TESTin ×Gain <V OH

[0161] Where PSRR DUT is the PSRR value in the device manual of the analog chip to be tested, Gain is the ripple rejection ratio processing submodule in FACin Gain at frequency, Gain PSRR To pass the device manual PSRR of the analog chip under test DUT The required gain is calculated by OUT_PSRR is the signal frequency output after the ripple suppression ratio processing submodule, V OL is the minimum output voltage of the ripple rejection ratio processing submodule, V OH is the maximum output voltage of the ripple rejection ratio processing submodule.

[0162] In this embodiment, the performance verification of the ripple suppression ratio processing submodule 350 of the signal processing module 300 is completed, including gain parameter performance verification and passband performance verification, to ensure that the ripple suppression ratio processing submodule 350 of the signal processing module 300 can output an AC signal that meets the gain parameter when receiving an AC signal that meets the second verification condition, so as to meet the test requirements of the test system.

[0163] In some embodiments, in step S120, the performance verification of the voltage noise processing submodule 360 ​​of the signal processing module 300 includes:

[0164] Step S121, connecting the arbitrary function generation submodule 130 of the signal input module 100 and the voltage noise processing submodule 360 ​​of the signal processing module 300;

[0165] Specifically, the signal input module 100 and the signal processing module 300 are both connected to the low-noise power supply module 600, the arbitrary function generation submodule 130 is connected to the first power supply terminal 110 and the first output terminal 120, the voltage noise processing submodule 360 ​​is connected to the processing power supply terminal 310, the processing input terminal 320 and the processing output terminal 330, and the first output terminal 120 is connected to the processing input terminal 320.

[0166] Step S122, controlling the arbitrary function generation submodule 130 to output an AC signal that meets a third verification condition, and acquiring the AC signal output by the voltage noise processing submodule 360;

[0167] Specifically, the signal acquisition module 400 is connected to the low-noise power supply module 600, the voltage and current signal acquisition submodule 440 is connected to the acquisition power supply terminal 410, the acquisition input terminal 420 and the acquisition output terminal 430, and the acquisition input terminal 420 is connected to the processing output terminal 330 of the signal processing module 300 to obtain the AC signal output by the voltage noise processing submodule 360.

[0168] For example, the arbitrary function generation submodule 130 outputs a peak-to-peak value of V to the voltage noise processing submodule 360. PPin , frequency F ACin The sinusoidal AC signal satisfies the third verification condition:

[0169]

[0170] Among them, F max 、F min The maximum and minimum values ​​of the noise test frequency band given in the manual of the analog chip to be tested; N OISEin_MIN 、N OISEin_MAX The minimum and maximum input voltage values ​​of the voltage noise processing submodule; N OISEout_MIN 、N OISEout_MAX The minimum and maximum input voltage values ​​output by the voltage noise processing submodule. V PPin_MAX 、V PPin_MIN The maximum and minimum values ​​of the voltage applied by the arbitrary function generation submodule to the input terminal of the voltage noise processing submodule; V PPout_MAX 、V PPout_MIN It is the maximum and minimum voltage output by the signal after passing through the voltage noise processing submodule.

[0171] Step S123, in response to determining that the AC signal output by the voltage noise processing submodule 360 ​​meets the third preset condition, calculating the gain parameter of the voltage noise processing submodule 360;

[0172] Specifically, the host computer 500 analyzes the AC signal sent by the signal acquisition module 400 (ie, the AC signal output by the voltage noise processing submodule 360 ​​) to determine whether it meets the third preset condition.

[0173] Exemplarily, the third preset condition is:

[0174] N OISEin_MIN <V PPin_MAX ,V PPin_MIN <N OISEin_MAX

[0175] N OISEout_MIN <V PPout_MAX ,V PPout_MIN <N OISEout_MAX

[0176] Among them, N OISEin_MIN 、N OISEin_MAX The minimum and maximum input voltage values ​​of the voltage noise processing submodule; N OISEout_MIN 、N OISEout_MAX The minimum and maximum input voltage values ​​output by the voltage noise processing submodule. V PPin_MAX 、VPPin_MIN The maximum and minimum values ​​of the voltage applied by the arbitrary function generation submodule to the input terminal of the voltage noise processing submodule; V PPout_MAX 、V PPout_MIN It is the maximum and minimum voltage output by the signal after passing through the voltage noise processing submodule.

[0177] Step S124, in response to determining that the gain parameter meets the fourth preset condition, determining that the voltage noise processing submodule 360 ​​passes the gain performance verification;

[0178] Specifically, the host computer 500 calculates the gain parameter of the voltage noise processing submodule 360 ​​based on the AC signal sent by the signal acquisition module 400 and the pre-stored AC signal output by the arbitrary function generation submodule 130. If the gain parameter is not less than the gain parameter required by the manual of the analog chip to be tested, it is determined that the voltage noise processing submodule 360 ​​has passed the gain performance verification.

[0179] Step S125: In response to determining that the voltage noise processing submodule 360 ​​passes the gain performance verification, controlling the arbitrary function generation submodule 130 to stepwise output AC signals of different frequencies to the voltage noise processing submodule 360 ​​to determine an upper cutoff frequency and a lower cutoff frequency of the voltage noise processing submodule 360;

[0180] Specifically, based on the gain performance verification of the voltage noise processing submodule 360, the passband performance of the voltage noise processing submodule 360 ​​is verified. By using a step-by-step control method to output an AC signal of increasing frequency from the arbitrary function generation submodule 130, the signal acquisition module 400 determines whether the voltage noise processing submodule 360 ​​can output the AC signal. If the voltage noise processing submodule 360 ​​cannot output the AC signal, the upper and lower cutoff frequencies of the voltage noise processing submodule 360 ​​are determined.

[0181] Step S126, in response to determining that the upper cutoff frequency and the lower cutoff frequency are respectively the same as the maximum value and the minimum value of the processing frequency band of the analog chip to be tested, it is determined that the voltage noise processing submodule 360 ​​passes the passband performance verification, and the voltage noise processing submodule 360 ​​passes the performance verification.

[0182] Specifically, by comparing the upper cutoff frequency and the lower cutoff frequency with the maximum and minimum values ​​of the processing frequency band recorded in the manual of the analog chip to be tested, when the two are the same, it is determined that the voltage noise processing submodule 360 ​​has passed the passband performance verification, and the voltage noise processing submodule 360 ​​has passed the performance verification.

[0183] In this embodiment, the voltage noise processing submodule 360 ​​is subjected to gain parameter performance verification and passband performance verification, and the verification process is clarified to clarify the difference in verification processes of different processing submodules to adapt to different test items, which is conducive to ensuring the test accuracy of the test system.

[0184] In some embodiments, in step S130, the performance verification of the rapid pulse generation submodule 140 of the signal input module 100 includes:

[0185] Step S131, connecting the fast pulse generation submodule 140 of the signal input module 100 to the test module 200 installed with the analog chip to be tested;

[0186] Specifically, the low-noise power supply module 600 is connected to the signal input module 100 and the test module 200 , the fast pulse generation submodule 140 is connected to the first power supply terminal 110 and the first output terminal 120 , and the first output terminal 120 is connected to the test input terminal 210 .

[0187] Step S132, controlling the fast pulse generation submodule 140 to output a pulse signal and a fast edge signal that meet the fourth verification condition, and acquiring the pulse signal and the fast edge signal received by the test input terminal 210 of the test module 200;

[0188] Specifically, the fast pulse generation submodule 140 is controlled to output a pulse signal and a fast edge signal that meet the fourth verification condition, and the voltage and current acquisition submodule of the signal acquisition module 400 is used to acquire the signal of the test module 200 .

[0189] Exemplarily, the rapid pulse generation submodule outputs a single pulse signal P ulse and fast edge signal E dge , the fourth verification condition is:

[0190] T width =T RS

[0191] V MRH <V PMAX <V IOMAX

[0192] V IOMIN <V PMIN <V MRL

[0193] T Echange < <T MD

[0194] V MRH <VEMAX <V IOMAX

[0195] V IOMIN <V EMIN <V MRL

[0196] Where T RS To enter the minimum manual pulse width, T MD The maximum manual reset to reset output delay time, T width P ulse The width of a single pulse; T Echange For E dge The time from low level to high level or from high level to low level; MRH 、V MRL The high level threshold and low level threshold of the manual reset terminal; V EMAX 、V EMIN For E dge The maximum and minimum voltage values; V IOMAX 、V IOMIN are the maximum input voltage and the minimum input voltage of the analog chip to be tested.

[0197] Step S133 , in response to determining that the pulse signal and the fast edge signal received by the test input terminal meet the fifth preset condition, determining that the fast pulse generation submodule passes the performance verification.

[0198] Specifically, the host computer judges the AC signal sent by the signal acquisition module to determine whether the fifth preset condition is met. If the fifth preset condition is met, it is determined that the fast pulse generation submodule has passed the performance verification.

[0199] Exemplarily, the fifth preset condition is:

[0200] V Pin_MAX =V PMAX

[0201] V Pin_MIN =V PMIN

[0202] T widthin =T width

[0203] V Ein_MIN =V EMIN

[0204] V Ein_MAX =V EMAX

[0205] T Echangein =T Echange

[0206] Where V Pin_MAX 、V Pin_MIN P ulse The maximum and minimum values ​​of the pulse voltage received by the test module; T widthin P ulse The actual pulse width received by the test module; V Ein_MAX 、V Ein_MIN For E dge The maximum and minimum values ​​of the fast edge signal received by the test module; T Echangein For E dge When the test module receives a signal, the time it takes for the signal to change from a low level to a high level or from a high level to a low level.

[0207] In this embodiment, the performance verification process of the fast pulse generation submodule is described in detail to clarify the steps of performance verification, avoid the test accuracy of the test system caused by improper operation, and help improve the practicality and test accuracy of the test system.

[0208] The following describes the specific process of the test system performing different test items after completing the corresponding performance verification through specific embodiments:

[0209] 1. Voltage Regulator Ripple Rejection Ratio Test

[0210] First, the test working conditions are set based on the manual of the analog chip to be tested (i.e., the voltage regulator); then the output bias voltage of the arbitrary function generation submodule is controlled to be V BIASin , peak-to-peak value is V PPin and frequency F ACin Sinusoidal AC signal, set the load current I DUT , ensuring that the signal is correctly input according to the test requirements. The test output end of the test module outputs the suppressed ripple signal, which is amplified and filtered by the ripple suppression ratio processing submodule to obtain the signal PSRR VPP , measured by the signal acquisition module and transmitted to the host computer, the power supply rejection ratio PSRR is calculated by the following formula:

[0211]

[0212] 2. Operational Amplifier Noise Test

[0213] First, set the test working conditions according to the manual of the analog chip to be tested (i.e., operational amplifier), then set the reverse input resistor R1 and feedback resistor R2 of the analog chip to be tested, and connect the analog chip to be tested with a gain of G. OPA The test loop must meet the following requirements:

[0214]

[0215] Among them, U R1 、U R2 are the RMS values ​​of the noise voltages generated by resistors R1 and R2 respectively; k = 1.38 × 10 -23 J / K is the Boltzmann constant; T is the temperature coefficient; R is the resistance value; σ is the conversion coefficient between the peak-to-peak value and the effective value of the voltage noise of the analog chip to be measured, which is usually 6; V PPDUT Indicates the peak-to-peak value or equivalent calculated peak-to-peak value of the input voltage noise of the analog chip under test; << indicates much less than.

[0216] Determine the noise test frequency band signal specified in the manual, and the gain of the voltage noise processing submodule is G NOISE , bandwidth is F max -F min , then transmit the output signal of the voltage noise processing submodule to the voltage and current signal acquisition submodule, extract the peak-to-peak value of the input voltage noise signal, and calculate the peak-to-peak value average value V PPOUT .

[0217] During the error compensation process, the Johnson-Nyquist noise from the inverting input resistor R1 and the feedback resistor R2 in the gain network is mainly considered. The impact of input current noise is not directly calculated here. The Johnson-Nyquist noise of R1 and R2 is equivalent to the RMS value of the noise voltage at the output of the analog chip under test as follows:

[0218]

[0219] V PPROUT =V PPR ×G NOISE

[0220] Where V PPR is the peak-to-peak value of the Johnson-Nyquist noise of the two resistors equivalent to the output of the analog chip under test. PPROUT is the peak-to-peak value of the Johnson-Nyquist noise of the two resistors after passing through the voltage noise processing submodule.

[0221] The actual peak-to-peak value of the input voltage noise at the input of the operational amplifier is calculated from this ppres That is:

[0222]

[0223] 3. Power monitoring timing test

[0224] 3.1 Manual reset pulse width test

[0225] First, set the test working conditions according to the manual of the analog chip to be tested (i.e., the power monitoring chip), and output a single pulse signal P with the minimum width of the test condition through the fast pulse generation submodule. ulse , must meet the following requirements:

[0226] T widthin =T RS

[0227] V MRH <V PMAX <V IOMAX

[0228] V IOMIN <V PMIN <V MRL

[0229] This signal outputs a reset signal through the reset terminal of the analog chip to be tested. When a single pulse signal from the manual reset terminal causes the reset terminal output signal to switch from a non-reset state to a reset state, the time signal acquisition submodule of the signal acquisition module synchronously captures the manual reset terminal input signal and the reset terminal output signal. At this time, the input T widthin The test data is then uploaded to the host computer as a test result through a standardized communication protocol.

[0230] 3.2 Manual reset to reset output delay time test

[0231] First, set the power monitoring test working conditions according to the manual of the analog chip to be tested, and output the fast edge signal E through the fast pulse generator submodule. dge , must meet the following requirements:

[0232] T Echangein < <T MD

[0233] V MRH <V EMAX <V IOMAX

[0234] V IOMIN <V EMIN <V MRL

[0235] This signal outputs a reset signal through the reset end of the analog chip to be tested. If the input fast edge signal causes the reset end output signal to switch from a non-reset state to a reset state, the time signal acquisition submodule synchronously captures the manual reset end input signal and the reset end output signal, uploads the test data to the host computer through a standardized communication protocol, and calculates the delay time of the two signals.

[0236] It is understandable that before using the technical solutions of each embodiment of the present disclosure, the type, scope of use, usage scenarios, etc. of the personal information involved will be informed to the user in an appropriate manner, and the user's authorization will be obtained.

[0237] For example, in response to a user's active request, a prompt message is sent to the user to clearly inform the user that the requested operation will require the acquisition and use of the user's personal information. This allows the user to independently choose whether to provide personal information to the electronic device, application, server, storage medium, or other software or hardware that performs the operation of the disclosed technical solution based on the prompt message.

[0238] As an optional but non-limiting implementation, in response to a user's active request, the prompt information may be sent to the user in the form of a pop-up window, in which the prompt information may be presented in text form. Furthermore, the pop-up window may also contain a selection control for the user to select "agree" or "disagree" to provide personal information to the electronic device.

[0239] It is understandable that the above notification and user authorization process are merely illustrative and do not constitute a limitation on the implementation of the present disclosure. Other methods that comply with relevant laws and regulations may also be applied to the implementation of the present disclosure.

[0240] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application is limited to these examples. In line with the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0241] In addition, for simplicity of description and discussion, and in order not to make the embodiment of the application difficult to understand, the known power supply / ground connection with integrated circuit (IC) chip and other components may or may not be shown in the accompanying drawings provided. In addition, the device can be shown in the form of a block diagram to avoid making the embodiment of the application difficult to understand, and this also takes into account the following fact, that is, the details of the embodiment of these block diagram devices are highly dependent on the platform to be implemented in the embodiment of the application (that is, these details should be fully within the scope of understanding of those skilled in the art). When specific details (for example, circuit) are set forth to describe exemplary embodiments of the application, it will be apparent to those skilled in the art that the embodiment of the application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered to be illustrative rather than restrictive.

[0242] Although the present invention has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those skilled in the art based on the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may utilize the embodiments discussed.

[0243] The embodiments of the present application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the present application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. An analog chip testing system, characterized in that: It includes a signal input module, a test module, a signal processing module, a signal acquisition module and a host computer connected in sequence, wherein the signal acquisition module is connected to one end of the test module connected to the signal input module; The test module is used to connect to the analog chip to be tested, the signal input module is used to input signals to the analog chip to be tested through the test module, the signal processing module is used to receive the output signal of the analog chip to be tested through the test module and process the received output signal, the signal acquisition module is used to collect the signal processed by the signal processing module and the signal input to the analog chip to be tested by the signal input module, and the host computer is used to receive the signal collected by the signal acquisition module and analyze the signal to obtain the test result of the analog chip to be tested.

2. The analog chip testing system according to claim 1, characterized in that: It also includes a low-noise power supply module, which is connected to the signal input module, test module, signal processing module, signal acquisition module, and host computer to power the signal input module, test module, signal processing module, signal acquisition module, and host computer.

3. The analog chip testing system according to claim 2, characterized in that: The signal input module includes a first power supply end, a first output end, an arbitrary function generating submodule and a rapid pulse generating submodule. The first power supply end and the first output end are both connected to the arbitrary function generating submodule and the rapid pulse generating submodule. The first power supply end is connected to the low-noise power supply module, and the first output end is connected to the test module.

4. The analog chip testing system according to claim 3, characterized in that: The test module includes a test input terminal, a test output terminal, a test power supply terminal and an adapter sub-module. The adapter sub-module is connected to the test input terminal, the test output terminal and the test power supply terminal. The adapter sub-module is used to connect the analog chip to be tested. The test module is connected to the signal input module through the test input terminal and to the signal processing module through the test output terminal.

5. The analog chip testing system according to claim 4, characterized in that: The signal processing module includes a processing power supply end, a processing input end, a processing output end, a connection submodule, a ripple suppression ratio processing submodule and a voltage noise processing submodule; The processing power supply end is connected to the low-noise power supply module, the processing input end is connected to the test module, and the processing output end is connected to the signal acquisition module; The ripple suppression ratio processing submodule and the voltage noise processing submodule are both connected to the processing power supply end, the processing input end, and the processing output end, and the connection submodule is connected to the processing input end and the processing output end; The signal processing module is connected to the testing module via the processing input end, and is connected to the signal acquisition module via the processing output end.

6. The analog chip testing system according to claim 5, characterized in that: The signal acquisition module includes an acquisition power supply terminal, an acquisition input terminal, an acquisition output terminal, a voltage and current signal acquisition submodule, and a time signal acquisition submodule; The acquisition power supply end is connected to the low-noise power supply module, the acquisition input end is connected to the processing output end, and the acquisition output end is connected to the host computer; The voltage and current signal acquisition submodule and the time signal acquisition submodule are both connected to the acquisition power supply end, the acquisition input end and the acquisition output end; The signal acquisition module is connected to the signal processing module and the test input terminal of the test module through the acquisition input terminal, and is connected to the host computer through the acquisition output terminal.

7. The analog chip testing system according to claim 3, characterized in that: The fast pulse generation submodule includes a fast pulse generation unit and an impedance matching unit connected in sequence, the first power supply end is connected to the fast pulse generation unit, and the first output end is connected to the impedance matching unit.

8. The analog chip testing system according to claim 4, characterized in that: The adapter submodule is connected to the test module via a test probe. The test module is provided with a plug-in slot adapted to the test probe. One end of the test probe is fixedly connected to the adapter submodule, and the other end is plugged into the plug-in slot. The test input end, the test output end and the test power supply end are connected to the plug slot, and are connected to the adapter submodule through the plug slot and the test probe.

9. A method for testing an analog chip, characterized in that: Applied to the analog chip testing system according to any one of claims 1 to 8, the method comprises: Obtain the analog chip to be tested and determine the test items; A test environment is built based on the test items and the test system, and the test items are tested on the simulated chip to be tested in the test environment to obtain test results through the host computer.

10. The analog chip testing method according to claim 9, characterized in that: The test items include voltage regulator ripple rejection ratio test, operational amplifier noise test and power supply monitoring timing test; the test environment is established based on the test items and the test system, including: In response to determining that the test item is a voltage regulator ripple rejection ratio test, the test environment established in the test system is as follows: the arbitrary function generation submodule of the signal input module is connected to the first power supply terminal and the first output terminal, the ripple rejection ratio processing submodule of the signal processing module is connected to the processing power supply terminal, the processing input terminal, and the processing output terminal, the voltage and current signal acquisition submodule of the signal acquisition module is connected to the acquisition power supply terminal, the acquisition input terminal, and the acquisition output terminal, and the acquisition input terminal of the signal acquisition module is connected to the test input terminal of the test module; In response to determining that the test item is an operational amplifier noise test, the test environment established in the test system is as follows: the signal input module and the test module are disconnected, the voltage noise processing submodule of the signal processing module is connected to the processing power supply terminal, the processing input terminal, and the processing output terminal, and the voltage and current signal acquisition submodule of the signal acquisition module is connected to the acquisition power supply terminal, the acquisition input terminal, and the acquisition output terminal; In response to determining that the test item is a power supply monitoring timing test, the test environment constructed in the test system is: the fast pulse generation submodule of the signal input module is connected to the first power supply end and the first output end, the connection submodule of the signal processing module is connected to the processing input end and the processing output end, and the time signal acquisition submodule of the signal acquisition module is connected to the acquisition power supply end, the acquisition input end and the acquisition output end.

11. The analog chip testing method according to claim 10, characterized in that: Before building a test environment based on the test items and the test system, the method further includes: In response to determining that the test item is a voltage regulator ripple rejection ratio test, performing performance verification on the arbitrary function generation submodule of the signal input module and the ripple rejection ratio processing submodule of the signal processing module; In response to determining that the test item is an operational amplifier noise test, performing performance verification on the voltage noise processing submodule of the signal processing module; In response to determining that the test item is a power monitoring timing test, performance verification is performed on the fast pulse generation submodule of the signal input module.

12. The analog chip testing method according to claim 11, characterized in that: The performance verification of the arbitrary function generation submodule of the signal input module and the ripple suppression ratio processing submodule of the signal processing module includes: Connecting the arbitrary function generating submodule of the signal input module to the test module on which the analog chip to be tested is installed; Controlling the arbitrary function generation submodule to output an AC signal that meets the first verification condition, and respectively obtaining the AC signal received by the test input terminal when the analog chip to be tested is under no-load and preset load; In response to determining that the AC signals received by the test input terminal meet the first verification condition under no-load and preset load conditions of the analog chip to be tested, it is determined that the arbitrary function generation submodule passes the performance verification.

13. The analog chip testing method according to claim 12, characterized in that: The performance verification of the arbitrary function generation submodule of the signal input module and the ripple suppression ratio processing submodule of the signal processing module further includes: Connecting the arbitrary function generation submodule of the signal input module and the ripple suppression ratio processing submodule of the signal processing module; Controlling the arbitrary function generation submodule to output an AC signal that meets a second verification condition, and obtaining the AC signal output by the ripple suppression ratio processing submodule; In response to determining that the AC signal output by the ripple suppression ratio processing submodule meets a first preset condition, calculating a gain parameter of the ripple suppression ratio processing submodule; In response to determining that the gain parameter meets the second preset condition, determining that the ripple suppression ratio processing submodule passes the gain performance verification; In response to determining that the ripple rejection ratio processing submodule passes the gain performance verification, controlling the arbitrary function generation submodule to stepwise output AC signals of different frequencies to the ripple rejection ratio processing submodule to determine an upper limit cutoff frequency and a lower limit cutoff frequency of the ripple rejection ratio processing submodule; In response to determining that the frequency of the AC signal that meets the second verification condition is between the upper cutoff frequency and the lower cutoff frequency, it is determined that the ripple suppression ratio processing submodule passes the passband performance verification and the ripple suppression ratio processing submodule passes the performance verification.

14. The analog chip testing method according to claim 11, characterized in that: The performance verification of the voltage noise processing submodule of the signal processing module includes: Connecting the arbitrary function generation submodule of the signal input module and the voltage noise processing submodule of the signal processing module; controlling the arbitrary function generation submodule to output an AC signal that meets a third verification condition, and acquiring the AC signal output by the voltage noise processing submodule; In response to determining that the AC signal output by the voltage noise processing submodule meets a third preset condition, calculating a gain parameter of the voltage noise processing submodule; In response to determining that the gain parameter meets a fourth preset condition, determining that the voltage noise processing submodule passes gain performance verification; In response to determining that the voltage noise processing submodule passes the gain performance verification, controlling the arbitrary function generation submodule to stepwise output AC signals of different frequencies to the voltage noise processing submodule to determine an upper cutoff frequency and a lower cutoff frequency of the voltage noise processing submodule; In response to determining that the upper cutoff frequency and the lower cutoff frequency are respectively the same as the maximum value and the minimum value of the processing frequency band of the analog chip to be tested, it is determined that the voltage noise processing submodule passes the passband performance verification, and the voltage noise processing submodule passes the performance verification.

15. The analog chip testing method according to claim 11, characterized in that: The performance verification of the fast pulse generation submodule of the signal input module includes: Connecting the fast pulse generation submodule of the signal input module to the test module on which the analog chip to be tested is installed; Controlling the fast pulse generation submodule to output a pulse signal and a fast edge signal that meet a fifth preset condition, and acquiring the pulse signal and the fast edge signal received by the test input end of the test module; In response to determining that the pulse signal and the fast edge signal received by the test input terminal meet the fourth verification condition, it is determined that the fast pulse generation submodule passes the performance verification.

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