Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a pixel structure, a gate line structure and a data line structure. The pixel structure comprises a plurality of sub-pixels arranged in an array, a plurality of adjacent sub-pixels in each row form a pixel group, and the plurality of pixel groups comprise at least one first pixel group, at least one second pixel group and at least one third pixel group; the gate line structure comprises a plurality of gate line groups, and each gate line group comprises three gate lines; the three gate lines comprise a first gate line, a second gate line and a third gate line; the data line structure comprises a plurality of data line groups, and each data line group comprises a plurality of data lines which are connected in parallel. The display device comprises the display panel. The display panel adopts a three-grid pixel architecture, and the data lines are connected in parallel, so that the use number of chips is reduced, the power consumption is lower, some display problems are avoided, and the display panel is suitable for severe environments.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display devices, and in particular to a display panel and a display apparatus. Background Art

[0002] Liquid crystal displays (LCDs) are currently the most commonly used flat-panel displays, with thin-film transistor-liquid crystal displays (TFT-LCDs) being the mainstream. TFT-LCDs offer advantages such as thinness, light weight, excellent image quality, low power consumption, long life, digital technology, and zero radiation, making them widely used in a variety of large, medium, and small electronic products. LCDs can also be used in near-eye display devices that utilize virtual reality (VR) and augmented reality (AR) technologies.

[0003] Currently, in order to reduce costs, display panels adopt a multiplexer (MUX) design architecture, or a dual-gate, triple-gate, or other pixel architecture. However, the display panels have a high driving frequency and high power consumption, which can easily cause display problems. Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by the present disclosure is to provide a display panel and a display device that adopt a three-gate pixel architecture and in which data lines are connected in parallel, thereby reducing the number of chips used, lowering power consumption, avoiding some display problems, and being suitable for harsh environments.

[0006] At least one embodiment of the present disclosure provides a display panel, including:

[0007] A pixel structure comprising a plurality of sub-pixels arranged in an array, wherein a plurality of adjacent sub-pixels in each row constitute a pixel group, wherein each row of sub-pixels comprises a plurality of pixel groups, and wherein the plurality of pixel groups comprises at least one first pixel group, at least one second pixel group, and at least one third pixel group;

[0008] A gate line structure comprising a plurality of gate line groups, one gate line group being configured to control a row of sub-pixels, each gate line group comprising three gate lines; the three gate lines comprising a first gate line, a second gate line, and a third gate line, the first gate line being configured to be electrically connected to the first pixel group, the second gate line being configured to be electrically connected to the second pixel group, and the third gate line being configured to be electrically connected to the third pixel group;

[0009] A data line structure includes multiple data line groups, each of which includes multiple data lines connected in parallel. The multiple data lines are arranged to correspond one-to-one with and be electrically connected to at least two pixel groups in each row of the sub-pixels, and at least two sub-pixels in each column of the sub-pixels are arranged to be electrically connected to one data line.

[0010] In some exemplary embodiments, two adjacent sub-pixels in each row of the sub-pixels are set to have different polarities and luminous colors, and each row of the sub-pixels includes multiple target sub-pixels with the same polarity and luminous color, and at least two of the target sub-pixels are set to correspond one-to-one to and be electrically connected to multiple data lines connected in parallel in one of the data line groups.

[0011] In some exemplary embodiments, each pixel group includes a sub-pixels, and the number of data line groups is b, where b=m×a, and m is a positive integer;

[0012] In each row of the sub-pixels, at least two adjacent pixel groups constitute a pixel repeating unit, and each pixel group in a pixel repeating unit is configured to be electrically connected to a data line groups.

[0013] In some exemplary embodiments, the pixel repeating unit includes a first pixel group, a second pixel group, and a third pixel group, the first pixel group, the second pixel group, and the third pixel group are arranged sequentially in a first direction, and one gate line group is configured to control the first pixel group, the second pixel group, and the third pixel group to be lit sequentially;

[0014] There are a plurality of pixel repeating units, and the plurality of pixel repeating units are arranged along the first direction.

[0015] In some exemplary embodiments, each of the pixel groups includes six sub-pixels, and the number of the data line groups is 6×m, where m is a positive integer.

[0016] In some exemplary embodiments, each of the pixel groups includes a first sub-pixel, a second sub-pixel, a third sub-pixel, a fourth sub-pixel, a fifth sub-pixel, and a sixth sub-pixel sequentially arranged along the first direction;

[0017] The first sub-pixel and the fourth sub-pixel are configured to emit light of a first color, and the polarities of the first sub-pixel and the fourth sub-pixel are different; the second sub-pixel and the fifth sub-pixel are configured to emit light of a second color, and the polarities of the second sub-pixel and the fifth sub-pixel are different; the third sub-pixel and the sixth sub-pixel are configured to emit light of a third color, and the polarities of the third sub-pixel and the sixth sub-pixel are different;

[0018] The plurality of data line groups include a first data line group, a second data line group, a third data line group, a fourth data line group, a fifth data line group, and a sixth data line group;

[0019] At least two data lines of the first data line group are arranged to correspond one-to-one to and be electrically connected to the first sub-pixels of at least two pixel groups respectively; at least two data lines of the second data line group are arranged to correspond one-to-one to and be electrically connected to the second sub-pixels of at least two pixel groups respectively; at least two data lines of the third data line group are arranged to correspond one-to-one to and be electrically connected to the third sub-pixels of at least two pixel groups respectively; at least two data lines of the fourth data line group are arranged to correspond one-to-one to and be electrically connected to the fourth sub-pixels of at least two pixel groups respectively; at least two data lines of the fifth data line group are arranged to correspond one-to-one to and be electrically connected to the fifth sub-pixels of at least two pixel groups respectively; and at least two data lines of the sixth data line group are arranged to correspond one-to-one to and be electrically connected to the sixth sub-pixels of at least two pixel groups respectively.

[0020] In some exemplary embodiments, the number of the data line groups is 6, and the plurality of pixel groups in each row of sub-pixels are configured to be electrically connected to six data line groups.

[0021] In some exemplary embodiments, the number of the data line groups is 6×m, where m is a positive integer greater than 1;

[0022] The first data line group, the second data line group, the third data line group, the fourth data line group, the fifth data line group, and the sixth data line group constitute a data line unit, and the data line structure includes m data line units;

[0023] The data line units and the pixel repeating units are arranged in one-to-one correspondence and are electrically connected.

[0024] In some exemplary embodiments, further comprising a substrate;

[0025] The first pixel group, the second pixel group, and the third pixel group are arranged along a first direction, and the first direction is parallel to the substrate;

[0026] The sub-pixels of the first pixel group all include a first pixel electrode and a first transistor, wherein the orthogonal projections of the first transistor and the first pixel electrode on the substrate are both located on the same side of the orthogonal projection of the first gate line on the substrate in a second direction, wherein the second direction is parallel to the substrate and perpendicular to the first direction;

[0027] The sub-pixels of the second pixel group all include a second pixel electrode and a second transistor, and the orthographic projections of the second transistor and the second pixel electrode on the substrate are both located on the same side of the orthographic projection of the second gate line on the substrate in the second direction;

[0028] The sub-pixels of the third pixel group all include a third pixel electrode and a third transistor, and the orthographic projections of the third transistor and the third pixel electrode on the substrate are both located on the same side of the orthographic projection of the third gate line on the substrate in the second direction.

[0029] In some exemplary embodiments, the orthographic projection of the first gate line on the substrate is located on one side of the orthographic projection of the first pixel group on the substrate in the second direction;

[0030] The orthographic projection of the second gate line on the substrate is located on the other side of the orthographic projection of the first pixel group on the substrate in the second direction;

[0031] The orthographic projection of the third gate line on the substrate is located on a side of the orthographic projection of the second gate line on the substrate away from the first pixel group.

[0032] In some exemplary embodiments, the subpixel of the first pixel group further includes a first connecting electrode connecting the first pixel electrode and the first transistor, an orthographic projection of the first connecting electrode on the substrate is a first projection, a projection of a gate line adjacent to the first gate line on the substrate is a second projection, and a minimum distance between the first projection and the second projection in the second direction is L1;

[0033] The subpixel of the second pixel group further includes a second connecting electrode connecting the second pixel electrode and the second transistor, an orthographic projection of the second connecting electrode on the substrate is a third projection, a projection of the third gate line on the substrate is a fourth projection, and a minimum distance between the third projection and the fourth projection in the second direction is L2;

[0034] The subpixel of the third pixel group further includes a third connecting electrode connecting the third pixel electrode and the third transistor, an orthographic projection of the third connecting electrode on the substrate is a fifth projection, a projection of the first gate line on the substrate is a sixth projection, and a minimum distance between the fifth projection and the sixth projection in the second direction is L3;

[0035] L1, L2 and L3 are all greater than or equal to 7 microns.

[0036] In some exemplary embodiments, each row of the sub-pixels is arranged to correspond one-to-one to the data lines, and the orthographic projection of any data line on the substrate is arranged to be located on the same side of the first direction of the orthographic projection of the sub-pixels electrically connected to the data line on the substrate.

[0037] At least one embodiment of the present disclosure provides a display device including the above-mentioned display panel.

[0038] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0040] Figure 1 is a cross-sectional view of a display panel;

[0041] Figure 2 is a plan view of a display panel according to the exemplary embodiment;

[0042] Figure 3 for Figure 2 A partial schematic diagram of the display area;

[0043] Figure 4 for Figure 3 Schematic diagram of sub-pixel arrangement in;

[0044] Figure 5 for Figure 3 Schematic diagram of the first row of sub-pixels in ;

[0045] Figure 6 is a schematic diagram of another display panel according to this exemplary embodiment;

[0046] Figure 7 is a schematic diagram of another display panel according to this exemplary embodiment;

[0047] Figure 8 for Figure 5 A first projection schematic diagram of the display panel in FIG;

[0048] Figure 9 for Figure 3 A partial schematic diagram of a display panel in FIG;

[0049] Figure 10 for Figure 9 A first projection diagram of the display panel;

[0050] Figure 11 for Figure 9 a second projection diagram of the display panel;

[0051] Figure 12 for Figure 9 A third projection diagram of the middle display panel;

[0052] Figure 13 for Figure 3 The first row of sub-pixels of the display panel in FIG. 1 is driven by a timing diagram;

[0053] Figure 14 is a schematic diagram of a related display panel;

[0054] Figure 15 is a schematic diagram of another related display panel;

[0055] Figure 16 is a schematic diagram of another related display panel;

[0056] Figure 17 for Figure 16 A partial schematic diagram of a display panel in FIG.

[0057] Figure 18 for Figure 16 : The first row of sub-pixel driving timing diagram of the display panel.

[0058] Description of the accompanying drawings:

[0059] 1-Pixel structure; 2-Gate line structure; 3-Data line structure;

[0060] 4-substrate; 5-first structural layer; 6-subpixel;

[0061] 7-pixel group; 8-first pixel group; 9-second pixel group;

[0062] 10-third pixel group; 11-gate line group; 12-gate line;

[0063] 13-first gate line; 14-second gate line; 15-third gate line;

[0064] 16-data line group; 17-data line; 18-pixel repeating unit;

[0065] 19 - first sub-pixel; 20 - second sub-pixel; 21 - third sub-pixel;

[0066] 22 - fourth sub-pixel; 23 - fifth sub-pixel; 24 - sixth sub-pixel;

[0067] 25-first grid line projection; 26-second grid line projection; 27-third grid line projection;

[0068] 28-pixel projection; 29-first pixel projection; 30-first pixel electrode;

[0069] 31 - first transistor; 32 - first connecting electrode; 33 - second pixel electrode;

[0070] 34 - second transistor; 35 - second connecting electrode; 36 - third pixel electrode;

[0071] 37 - third transistor; 38 - third connection electrode; 39 - first projection;

[0072] 40-seventh projection; 41-eighth projection; 42-third projection;

[0073] 43-9th projection; 44-10th projection; 45-5th projection;

[0074] 46 - eleventh projection; 47 - twelfth projection; 48 - horizontal data line. DETAILED DESCRIPTION

[0075] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0076] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to this. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display panel and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are only structural schematics, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the figures.

[0077] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0078] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0079] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0080] In this specification, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0081] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0082] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0083] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0084] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0085] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0086] The term "about" in the embodiments of the present disclosure does not strictly define the limits and allows for numerical values ​​within the range of process and measurement errors.

[0087] At present, display panels usually reduce the number of chips used to achieve the purpose of reducing production costs. For example, thin-film transistors manufactured by low-temperature polycrystalline silicon (LTPS) technology adopt a multiplexer (MUX) design architecture, and amorphous silicon oxide (a Si / oxide) process adopts a dual gate or triple gate pixel architecture. The applicant found that although the existing display panels can reduce production costs through the above-mentioned architecture, the power consumption is relatively large. Especially for high-resolution and high-refresh display panels, it is easy for the temperature rise of the chip connected to the data line to be too high, resulting in problems such as black screen. In particular, display panels used in vehicle environments work in outdoor environments for a long time, and the demand for temperature rise is also higher. Display panels have an increasingly higher demand for low power consumption. Low power consumption is also conducive to reducing the temperature rise of the chip, so that the display panel can be used in harsh working environments.

[0088] Figure 1 is a cross-sectional view of a display panel, Figure 2 is a plan view of a display panel of this exemplary embodiment, Figure 3 for Figure 2 A partial schematic diagram of the display area in FIG. , an embodiment of the present disclosure provides a display panel such as Figures 1 to 3 As shown, the display panel may include a pixel structure 1, a gate line structure 2, and a data line structure 3. The pixel structure 1 may include a plurality of sub-pixels 6 arranged in an array. A plurality of adjacent sub-pixels 6 in each row may constitute a pixel group 7. Each row of sub-pixels 6 may include a plurality of pixel groups 7. The plurality of pixel groups 7 may include at least one first pixel group 8, at least one second pixel group 9, and at least one third pixel group 10. The gate line structure 2 may include a plurality of gate line groups 11. Each gate line group 11 is configured to control a row of sub-pixels 6. Each gate line group 11 may include three gate lines 12. The three gate lines 12 may include a first gate line 13, a second gate line 14, and a third gate line 15. The first gate line 13 may be electrically connected to the first pixel group 8, the second gate line 14 may be electrically connected to the second pixel group 9, and the third gate line 15 may be electrically connected to the third pixel group 10. The data line structure 3 may include multiple data line groups 16, each data line group 16 may include multiple data lines 17 connected in parallel. The multiple data lines 17 may correspond one-to-one to and be electrically connected to at least two pixel groups 7 in each row of sub-pixels 6, and at least two sub-pixels 6 in each column of sub-pixels 6 are configured to be electrically connected to one data line 17. The display panel of this example adopts a tri-gate pixel architecture, and the data lines are connected in parallel, thereby reducing the number of chips used, lowering power consumption, avoiding some display issues, and being suitable for harsh environments.

[0089] In some exemplary embodiments, Figure 1 As shown, the display panel may include a first substrate A1 and a second substrate A2 disposed opposite each other, and a liquid crystal layer A3 disposed between the first substrate A1 and the second substrate A2. The first substrate A1 may include a first structural layer 5 disposed on the side of the base 4 facing the second substrate A2. Based on the display mode, the display panel can be classified into a twisted nematic (TN) display mode, an in-plane switching (IPS) display mode, a fringe field switching (FFS) display mode, and an advanced superdimensional switch (ADS) display mode. In an exemplary embodiment, the first structural layer 5 may include gate lines, data lines, thin film transistors, pixel electrodes, and common electrodes, and the second substrate A2 may include a black matrix and a filter unit.

[0090] In some exemplary embodiments, Figure 2 and Figure 3As shown, the display panel may include a display area AA and a frame area BB located around the display area AA. The frame area BB may include a first frame area B1 located on one side of the display area AA and a second frame area B2 located on the remaining sides of the display area AA. For example, the first frame area B1 may include a lower frame of the array substrate, and the second frame area may include an upper frame, a left frame, and a right frame of the array substrate. The display area AA may include a plurality of gate lines 12 and a plurality of data lines 17, the plurality of gate lines 12 extending along a first direction (X-axis direction) and arranged in sequence along a second direction (Y-axis direction), and the plurality of data lines 17 extending along the second direction (Y-axis direction) and arranged in sequence along the first direction (X-axis direction). The sub-pixel 6 may be marked as P i，j , multiple data lines 17 can be D1 to Di, i is a natural number, and multiple gate lines 12 can be G1 to Gj, j is a natural number. The sub-pixels 6 are arranged in a matrix, and the sub-pixels 6 can be arranged in j rows and i columns. The sub-pixels 6 in the first row are Y1, the sub-pixels 6 in the second row are Y2, and so on. The sub-pixels 6 in the jth row are Yj; the sub-pixels 6 in the first column are X1, the sub-pixels 6 in the second column are X2, and so on. The sub-pixels 6 in the i-th column are Yi; the sub-pixels 6 in the jth row and i-th column can be P i，j , for example, the sub-pixel in the first row and the first column is P 1，1 , for example, the sub-pixel in the second row and first column is P 1，2 For example, the sub-pixel in the first row and the 10th column is P 10，1 In an exemplary embodiment, at least one sub-pixel 6 may include a thin film transistor, a pixel electrode, and a common electrode, and the thin film transistor is connected to the gate line, the data line, and the pixel electrode, respectively.

[0091] Figure 4 for Figure 3 Schematic diagram of sub-pixel arrangement in Figure 5 for Figure 3 Schematic diagram of the first row of sub-pixels in FIG. , in some exemplary embodiments, as Figures 3 to 5 As shown, two adjacent sub-pixels 6 in each row of sub-pixels 6 may have different polarities and different luminescent colors. Each row of sub-pixels 6 may include multiple target sub-pixels with the same polarity and luminescent color. At least two target sub-pixels may correspond one-to-one with and be electrically connected to multiple data lines 17 connected in parallel in a data line group 16. Each pixel group 7 may include a sub-pixels 6, and the number of data line groups 16 is b, where b = m × a, and m is a positive integer. In each row of sub-pixels 6, at least two adjacent pixel groups 7 may form a pixel repeating unit 18, and each pixel group 7 in a pixel repeating unit 18 is configured to be electrically connected to a data line group 16.

[0092] In some exemplary embodiments, Figures 3 to 5As shown, each pixel group 7 may include six sub-pixels 6, and the six sub-pixels 6 may include a first sub-pixel 19, a second sub-pixel 20, a third sub-pixel 21, a fourth sub-pixel 22, a fifth sub-pixel 23, and a sixth sub-pixel 24 arranged in sequence along a first direction (X-axis direction). The first sub-pixel 19 and the fourth sub-pixel 22 are configured to emit light of a first color, and the first sub-pixel 19 and the fourth sub-pixel 22 have different polarities; the second sub-pixel 20 and the fifth sub-pixel 23 are configured to emit light of a second color, and the second sub-pixel 20 and the fifth sub-pixel 23 have different polarities; the third sub-pixel 21 and the sixth sub-pixel 24 are configured to emit light of a third color, and the third sub-pixel 21 and the sixth sub-pixel 24 have different polarities. In this example, the first color light is set to red light, the second color light can be green light, and the third color light can be blue light, but the present invention is not limited thereto. For example, the first color light is set to blue light, the second color light can be red light, and the third color light can be green light. For another example, the first color light is set to blue light, the second color light can be green light, and the third color light can be red light. For another example, the first color light is set to red light, the second color light can be blue light, and the third color light can be green light. The polarities of the six sub-pixels 6 in each pixel group 7 are alternately set to positive and negative. For example, the first sub-pixel 19 is positive, the second sub-pixel 20 is negative, the third sub-pixel 21 is positive, the fourth sub-pixel 22 is negative, the fifth sub-pixel 23 is positive, and the sixth sub-pixel 24 is negative. The symbol for positive polarity is "+" and the symbol for negative polarity is "-". Thus, in this example, the first sub-pixel 19 is positive and emits the first color light; the second sub-pixel 20 is negative and emits the second color light; the third sub-pixel 21 is positive and emits the third color light; the fourth sub-pixel 22 is negative and emits the first color light; the fifth sub-pixel 23 is positive and emits the second color light; the sixth sub-pixel 24 is negative and emits the third color light; for example, sub-pixel P 1,1 and sub-pixel P 7,1 and sub-pixel P 13,1 are all first sub-pixels 19, are all positive polarity and emit light of the first color; for example, sub-pixel P 2,1 and sub-pixel P 8,1 and sub-pixel P 14,1 All are second sub-pixels 20, all have negative polarity and emit second color light; sub-pixel P 3,1 and sub-pixel P 9,1 and sub-pixel P 15,1 All are third sub-pixels 21, all have positive polarity and emit light of the third color; sub-pixel P 4,1 and sub-pixel P 10,1 and sub-pixel P 16,1 All are fourth sub-pixels 22 , all have negative polarity and emit the first color light.

[0093] In some exemplary embodiments, Figures 3 to 5 As shown, the pixel repeating unit 18 may include a first pixel group 8, a second pixel group 9, and a third pixel group 10. The first pixel group 8, the second pixel group 9, and the third pixel group 10 are arranged sequentially in a first direction (X-axis direction). The first pixel group 8, the second pixel group 9, and the third pixel group 10 each include six sub-pixels 6, namely, a first sub-pixel 19, a second sub-pixel 20, a third sub-pixel 21, a fourth sub-pixel 22, a fifth sub-pixel 23, and a sixth sub-pixel 24. A gate line group 11 is configured to control the first pixel group 8, the second pixel group 9, and the third pixel group 10 to be illuminated in sequence. For example, gate lines G1, G2, and G3 control the sub-pixels in the first row (Y1). The first gate line 13 (G1) can be electrically connected to the six sub-pixels 6 of the first pixel group 8, the second gate line 14 (G2) can be electrically connected to the six sub-pixels 6 of the second pixel group 9, and the third gate line 15 (G3) can be electrically connected to the six sub-pixels 6 of the third pixel group 10.

[0094] In some exemplary embodiments, Figures 3 to 5 As shown, the number of data line groups 16 is 6×m, where m is a positive integer. The data line group 16 may include a first data line group S1, a second data line group S2, a third data line group S3, a fourth data line group S4, a fifth data line group S5, and a sixth data line group S6. At least two data lines 17 of the first data line group S1 are configured to correspond one-to-one with and be electrically connected to the first sub-pixels 19 of at least two pixel groups 7, respectively. In this example, at least two data lines 17 of the first data line group S1 are configured to correspond one-to-one with and be electrically connected to the first sub-pixels 19 of the first, second, and third pixel groups, respectively. For example, the first data line group S1 may include a first data line D1, a seventh data line D7, and a thirteenth data line D13. The first data line D1, the seventh data line D7, and the thirteenth data line D13 are connected in parallel to each other. The first data line D1 and the first sub-pixel 19 (i.e., the sub-pixel P) in the first pixel group 8 are connected in parallel to each other. 1,1 ) is electrically connected to the seventh data line D7 and the first sub-pixel 19 (ie, sub-pixel P) in the second pixel group 9. 7,1 ) is electrically connected to the thirteenth data line D13 and the first sub-pixel 19 (ie, sub-pixel P) in the third pixel group 10. 13,1 ) is electrically connected. Thus, the first sub-pixel 19 in each pixel group serves as the target sub-pixel of the first data line group S1, that is, the sub-pixel P 1,1 , sub-pixel P 7,1 and sub-pixel P 13,1 As the target sub-pixel of the first data line group S1.

[0095] In some exemplary embodiments, Figures 3 to 5As shown, at least two data lines 17 of the second data line group S2 are respectively corresponding to and electrically connected to the second sub-pixels 20 of at least two pixel groups 7. In this example, at least two data lines 17 of the second data line group S2 are respectively corresponding to and electrically connected to the second sub-pixels 20 of the first, second, and third pixel groups. For example, the second data line group S2 may include a second data line D2, an eighth data line D8, and a fourteenth data line D14. The second data line D2, the eighth data line D8, and the fourteenth data line D14 are connected in parallel to each other. The second data line D2 is connected to the second sub-pixel 20 (i.e., the sub-pixel P) in the first pixel group 8. 2,1 ) is electrically connected to the eighth data line D8 and the second sub-pixel 20 (ie, the sub-pixel P) in the second pixel group 9. 8,1 ) is electrically connected to the fourteenth data line D14 and the second sub-pixel 20 (ie, sub-pixel P) in the third pixel group 10. 14,1 ) is electrically connected. Thus, the second sub-pixel 20 in each pixel group serves as the target sub-pixel of the second data line group S2, that is, the sub-pixel P 2,1 , sub-pixel P 8,1 and sub-pixel P 14,1 As the target sub-pixel of the second data line group S2.

[0096] In some exemplary embodiments, Figures 3 to 5 As shown, at least two data lines 17 of the third data line group S3 are respectively arranged to correspond to and be electrically connected to the third sub-pixels 21 of at least two pixel groups 7. In this example, at least two data lines 17 of the third data line group S3 are respectively arranged to correspond to and be electrically connected to the third sub-pixels 21 of the first, second, and third pixel groups. For example, the third data line group S3 may include a third data line D3, a ninth data line D9, and a fifteenth data line D15. The third data line D3, the ninth data line D9, and the fifteenth data line D15 are connected in parallel to each other. The third data line D3 and the third sub-pixel 21 (i.e., the sub-pixel P15) in the first pixel group 8 are connected in parallel to each other. 3,1 ) is electrically connected to the ninth data line D9 and the third sub-pixel 21 (ie, sub-pixel P) in the second pixel group 9. 9,1 ) is electrically connected to the fifteenth data line D15 and the third sub-pixel 21 (ie, sub-pixel P) in the third pixel group 10. 15,1 ) is electrically connected. Thus, the third sub-pixel 21 in each pixel group serves as the target sub-pixel of the third data line group S3, that is, the sub-pixel P 3,1 , sub-pixel P 9,1 and sub-pixel P 15,1 As the target sub-pixel of the third data line group S3.

[0097] In some exemplary embodiments, Figures 3 to 5As shown, at least two data lines 17 of the fourth data line group S4 are respectively arranged to correspond to and be electrically connected to the fourth sub-pixels 22 of at least two pixel groups 7. In this example, at least two data lines 17 of the fourth data line group S4 are respectively arranged to correspond to and be electrically connected to the fourth sub-pixels 22 of the first, second, and third pixel groups. For example, the fourth data line group S4 may include a fourth data line D4, a tenth data line D10, and a sixteenth data line D16. The fourth data line D4, the tenth data line D10, and the sixteenth data line D16 are connected in parallel to each other. The fourth data line D4 is connected to the fourth sub-pixel 22 (i.e., the sub-pixel P) in the first pixel group 8. 4,1 ) is electrically connected to the tenth data line D10 and the fourth sub-pixel 22 (ie, sub-pixel P) in the second pixel group 9. 10,1 ) is electrically connected to the sixteenth data line D16 and the fourth sub-pixel 22 (ie, sub-pixel P) in the third pixel group 10. 16,1 ) is electrically connected. Thus, the fourth sub-pixel 22 in each pixel group serves as the target sub-pixel of the fourth data line group S4, that is, the sub-pixel P 4,1 , sub-pixel P 10,1 and sub-pixel P 16,1 As the target sub-pixel of the fourth data line group S4.

[0098] In some exemplary embodiments, Figures 3 to 5 As shown, at least two data lines 17 of the fifth data line group S5 are respectively arranged to correspond to and be electrically connected to the fifth sub-pixels 23 of at least two pixel groups 7. In this example, at least two data lines 17 of the fifth data line group S5 are respectively arranged to correspond to and be electrically connected to the fifth sub-pixels 23 of the first, second, and third pixel groups. For example, the fifth data line group S5 may include a fifth data line D5, an eleventh data line D11, and a seventeenth data line D17. The fifth data line D5, the eleventh data line D11, and the seventeenth data line D17 are connected in parallel to each other. The fifth data line D5 is connected to the fifth sub-pixel 23 (i.e., the sub-pixel P) in the first pixel group 8. 5,1 ) is electrically connected to the eleventh data line D11 and the fifth sub-pixel 23 (ie, sub-pixel P) in the second pixel group 9. 11,1 ) is electrically connected to the seventeenth data line D17 and the fifth sub-pixel 23 (ie, sub-pixel P) in the third pixel group 10. 17,1 ) is electrically connected. Thus, the fifth sub-pixel 23 in each pixel group serves as the target sub-pixel of the fourth data line group S4, that is, the sub-pixel P 5,1 , sub-pixel P 11,1 and sub-pixel P 17,1 As the target sub-pixel of the fifth data line group S5.

[0099] In some exemplary embodiments, Figures 3 to 5As shown, at least two data lines 18 of the sixth data line group S6 are respectively corresponding to and electrically connected to the sixth sub-pixels 24 of at least two pixel groups 7. In this example, at least two data lines 17 of the sixth data line group S6 are respectively corresponding to and electrically connected to the sixth sub-pixels 24 of the first, second, and third pixel groups. For example, the sixth data line group S6 may include a sixth data line D6, a twelfth data line D12, and an eighteenth data line D18. The sixth data line D6, the twelfth data line D12, and the eighteenth data line D18 are connected in parallel to each other. The sixth data line D6 is connected to the sixth sub-pixel 24 (i.e., the sub-pixel P) in the first pixel group 8. 6,1 ) is electrically connected to the twelfth data line D12 and the sixth sub-pixel 24 (ie, sub-pixel P) in the second pixel group 9. 12,1 ) is electrically connected to the eighteenth data line D18 and the sixth sub-pixel 24 (ie, sub-pixel P) in the third pixel group 10. 18,1 ) is electrically connected. Thus, the sixth sub-pixel 24 in each pixel group serves as the target sub-pixel of the fourth data line group S4, that is, the sub-pixel P 6,1 , sub-pixel P 12,1 and sub-pixel P 18,1 As the target sub-pixel of the sixth data line group S6.

[0100] In some exemplary embodiments, Figures 3 to 5 As shown, the pixel groups 7 of adjacent rows correspond one-to-one, and the first pixel groups 8 of adjacent rows correspond one-to-one, the second pixel groups 9 of adjacent rows correspond one-to-one, and the third pixel groups 10 of adjacent rows correspond one-to-one. For example, the first pixel group 8 in the first row (Y1) corresponds to the first pixel group 8 in the second row (Y2), so that the first column (X1) is the first pixel group 8. At the same time, the sub-pixels of the multiple first pixel groups 8 in the first column (X1) correspond one-to-one and are all electrically connected to a data line 17. For example, the first sub-pixel 19 in the first pixel group 8 of the first row (Y1) and the first column (X1) and the first sub-pixel 19 in the first pixel group 8 of the second row (Y2) and the first column (X1) are all connected to the first data line D1, that is, the sub-pixel P 1,1 and sub-pixel P 1,2can be electrically connected to the first data line D1. Thus, the display panel of this example can be driven by a column inversion driving method. The column inversion method refers to reversing the polarity of the data voltage signal every specified number of pixel columns. For the column inversion method, the polarity of the data voltage signal on each data line 17 is always the same polarity (positive or negative), wherein the symbol of the positive polarity is "+" and the symbol of the negative polarity is "-". Through the setting of the above-mentioned pixel architecture, when the display panel is driven by a column inversion driving method, the polarity of the data voltage signal on the data lines 17 (for example, S1-S6) arranged along the Y direction can be alternating positive and negative ("+-+-+-"). Therefore, when displaying the same frame image, the sub-pixel columns arranged along the Y direction are charged with the polarity of the data voltage signal in a "positive-negative-positive-negative" cycle. When displaying the same frame image, the polarities of the data voltage signals charged into any two adjacent columns of sub-pixels 6 are opposite, and the brightness can be averaged. For example, the polarities of the sub-pixels controlled by the first data line D1 and the second data line D2 are opposite, that is, the sub-pixels P 1,1 and sub-pixel P 2,1 The polarity is opposite, the sub-pixel P 1,1 is positive polarity, sub-pixel P 2,1 This achieves uniform distribution of pixel polarity, thereby achieving uniform distribution of pixel brightness on the display panel, and avoiding display problems such as shaking head patterns caused by existing dual-gate technology.

[0101] Figure 6 This is a schematic diagram of another display panel of this exemplary embodiment. In some exemplary embodiments, a plurality of pixel repeating units 18 are provided, and the plurality of pixel repeating units 18 are arranged along a first direction (X-axis direction). The pixel repeating units 18 may include a first pixel group 8, a second pixel group 9, and a third pixel group 10. The first pixel group 8, the second pixel group 9, and the third pixel group 10 are arranged sequentially in the first direction (X-axis direction). At the same time, the data line structure has only six groups of data line groups 16, namely S1 to S6, and the plurality of pixel groups in each row of sub-pixels 6 are arranged to be electrically connected to the six data line groups 16. In some exemplary embodiments, as Figure 6As shown, there are two pixel repeating units 18, and each data line group 16 includes six data lines 17 connected in parallel. Six sub-pixels with the same polarity and emitted light color in a pixel repeating unit 18 are each connected to one data line group 16 via the six data lines 17. For example, a first data line group S1 includes six data lines connected in parallel, namely, a first data line D1, a seventh data line D7, a thirteenth data line D13, a nineteenth data line D19, a twenty-fifth data line D25, and a thirty-first data line D31. The first data line D1, the seventh data line D7, and the thirteenth data line D13 are each connected to a first sub-pixel 19 in one pixel repeating unit 18, while the nineteenth data line D19, the twenty-fifth data line D25, and the thirty-first data line D31 are each connected to a first sub-pixel 19 in another pixel repeating unit 18. Thus, each of the six data line groups 16 is connected to a driver chip, and the number of driver chips corresponds to the number of data line groups 16. This reduces the number of chips used, thereby reducing power consumption.

[0102] Figure 7 This is a schematic diagram of another display panel of this exemplary embodiment. In some exemplary embodiments, a plurality of pixel repeating units 18 are provided, and the plurality of pixel repeating units 18 are arranged along the first direction (X-axis direction). The pixel repeating unit 18 may include a first pixel group 8, a second pixel group 9, and a third pixel group 10. The first pixel group 8, the second pixel group 9, and the third pixel group 10 are arranged sequentially in the first direction (X-axis direction). At the same time, the data line structure has only 6×m data line groups 16, where m is a positive integer greater than 1. Each adjacent data line group 16 has two data lines 17 in parallel. Six adjacent data line groups 16 constitute a data line unit S0. The three pixel groups of each pixel repeating unit 18 are configured to be electrically connected to a data line unit S0, forming a one-to-one correspondence and electrical connection between the data line unit S0 and the pixel repeating unit 18. In some exemplary embodiments, as Figure 7As shown, there are two pixel repeating units 18, the number of data line groups 16 is 12, m=2, and the data line structure includes two data line units S0. One data line unit S0 includes six data line groups 16, namely, a first data line group S1, a second data line group S2, a third data line group S3, a fourth data line group S4, a fifth data line group S5, and a sixth data line group S6. The other data line unit S0 includes six data line groups 16, namely, a seventh data line group S7, an eighth data line group S8, a ninth data line group S9, a tenth data line group S10, an eleventh data line group S11, and a twelfth data line group S12. One data line unit S0 (i.e., S1 to S6) is electrically connected to one pixel repeating unit 18. For example, the first data line group S1 includes three parallel data lines: the first data line D1, the seventh data line D7, and the thirteenth data line D13. The first data line D1, the seventh data line D7, and the thirteenth data line D13 are each connected to a first sub-pixel 19 in a pixel repeating unit 18. Another data line unit S0 (i.e., S7 to S12) is electrically connected to another pixel repeating unit 18. For example, the nineteenth data line D19, the twenty-fifth data line D25, and the thirty-first data line D31 are each connected to a first sub-pixel 19 in another pixel repeating unit 18. Thus, the six data line groups 16 are each connected to a driver chip, and the number of driver chips corresponds to the number of data line groups 16. This reduces the number of chips used, thereby reducing power consumption.

[0103] Figure 8 for Figure 5 In a first projection diagram of a display panel, in some exemplary embodiments, the three gate lines controlling a row of sub-pixels are a first gate line 13, a second gate line 14, and a third gate line 15, which are separated by a row of sub-pixels controlled by the gate line. Figure 1 、 Figure 5 and Figure 8 As shown, the orthographic projection of the first gate line 13 on the substrate 4 is a first gate line projection 25, the orthographic projection of the second gate line 14 on the substrate 4 is a second gate line projection 26, and the orthographic projection of the third gate line 15 on the substrate 4 is a third gate line projection 27. The orthographic projection of a row of sub-pixels controlled by the first gate line 13, the second gate line 14, and the third gate line 15 on the substrate 4 is a pixel projection 28, wherein the orthographic projection of the first pixel group 8 on the substrate 4 is a first pixel projection 29, and the first pixel projection 29 may be a part of the pixel projection 28. The first gate line projection 25 is located on one side of the pixel projection 28 in the second direction (Y-axis direction), the second gate line 14 and the third gate line projection 27 are both located on the other side of the pixel projection 28 in the second direction (Y-axis direction), and the third gate line projection 27 is located on the side of the second gate line 14 in the second direction (Y-axis direction) away from the pixel projection 28. The first direction (X-axis direction) and the second direction (Y-axis direction) are both parallel to the substrate 4.

[0104] Figure 9 for Figure 3 A partial schematic diagram of a display panel in FIG. 1 , in some exemplary embodiments, as shown in FIG. Figure 9 As shown, in the j-th row (Yj) sub-pixels, the sub-pixels 6 of the first pixel group 8 may include a first pixel electrode 30, a first transistor 31, and a first connecting electrode 32 connecting the first pixel electrode 30 and the first transistor 31; the sub-pixels 6 of the second pixel group 9 may include a second pixel electrode 33 and a second transistor 34, and a second connecting electrode 35 connecting the second pixel electrode 33 and the second transistor 34; the sub-pixels 6 of the third pixel group 10 may include a third pixel electrode 36 and a third transistor 37, and a third connecting electrode 38 connecting the third pixel electrode 36 and the third transistor 37.

[0105] Figure 10 for Figure 9 A first projection diagram of the display panel is shown in FIG. 1 , in some exemplary embodiments, as shown in FIG. Figure 1 、 Figure 9 and Figure 10 As shown, the orthographic projection of the first gate line 13 on the substrate 4 is the first gate line projection 25, the orthographic projection of the first connecting electrode 32 on the substrate 4 is the first projection 39, the orthographic projection of the first transistor 31 on the substrate 4 is the seventh projection 40, and the orthographic projection of the first pixel electrode 30 on the substrate 4 is the eighth projection 41, wherein the eighth projection 41 and the seventh projection 40 are both located on the same side of the first gate line projection 25 in the second direction, the second direction (Y-axis direction) is parallel to the substrate 4, and the second direction (Y-axis direction) is perpendicular to the first direction (X-axis direction). The projection of the gate line adjacent to the first gate line 13 (i.e., the third gate line 15) on the substrate 4 is the second projection (i.e., the third gate projection 27), and the minimum distance between the first projection 39 and the third gate projection 27 in the second direction (Y-axis direction) is L1, wherein L1 is greater than or equal to 7 microns.

[0106] Figure 11 for Figure 9 A second projection diagram of the display panel is shown in FIG. 1 , in some exemplary embodiments, as shown in FIG. Figure 1 、 Figure 9 and Figure 11As shown, the orthographic projection of the second gate line 14 on the substrate 4 is the second gate line projection 26, the orthographic projection of the second connecting electrode 35 on the substrate 4 is the third projection 42, the orthographic projection of the second transistor 34 on the substrate 4 is the ninth projection 43, and the orthographic projection of the second pixel electrode 33 on the substrate 4 is the tenth projection 44, wherein the ninth projection 43 and the tenth projection 44 are both located on the same side of the second gate line projection 26 in the second direction, the second direction (Y-axis direction) is parallel to the substrate 4, and the second direction (Y-axis direction) is perpendicular to the first direction (X-axis direction). The projection of the gate line adjacent to the second gate line 14 (i.e., the third gate line 15) on the substrate 4 is the fourth projection (i.e., the third gate projection 27), and the minimum distance between the third projection 42 and the third gate projection 27 in the second direction (Y-axis direction) is L2, wherein L2 is greater than or equal to 7 microns.

[0107] Figure 12 for Figure 9 Schematic diagram of a third projection of the display panel, in some exemplary embodiments, as Figure 1 、 Figure 9 and Figure 12 As shown, the orthographic projection of the third gate line 15 on the substrate 4 is the third gate line projection 27, the orthographic projection of the third connecting electrode 38 on the substrate 4 is the fifth projection 45, the orthographic projection of the third transistor 37 on the substrate 4 is the eleventh projection 436, and the orthographic projection of the third pixel electrode 36 on the substrate 4 is the twelfth projection 47. The eleventh projection 46 and the twelfth projection 47 are both located on the same side of the third gate line projection 27 in the second direction (Y-axis direction). The second direction (Y-axis direction) is parallel to the substrate 4, and the second direction (Y-axis direction) is perpendicular to the first direction (X-axis direction). The projection of the gate line adjacent to the third gate line 15 (i.e., the third gate line 15) on the substrate 4 is the sixth projection (i.e., the third gate projection 27). The minimum distance between the third projection 42 and the third gate projection 27 in the second direction (Y-axis direction) is L3, where L3 is greater than or equal to 7 microns. Therefore, the values ​​of L1, L2, and L3 are all equal to or equal to 7 microns.

[0108] Figure 13 for Figure 3 In some exemplary embodiments, as shown in FIG. Figure 3 and Figure 13As shown, the sub-pixels 6 in the first row (Y1) are sequentially turned on and charged by the first gate line 13, the second gate line 14, and the third gate line 15 (i.e., G1, G2, and G3). The first gate line 13 (i.e., G1) applies a positive voltage V1, i.e., Vgh, and the data line groups S1 to S6 are turned on, charging the sub-pixels 6 in the first pixel group 8. The second gate line 14 (i.e., G2) applies a positive voltage V1, i.e., Vgh, and the data line groups S1 to S6 are turned on, charging the sub-pixels 6 in the second pixel group 9. The third gate line 15 (i.e., G3) applies a positive voltage V1, i.e., Vgh, and the data line groups S1 to S6 are turned on, charging the sub-pixels 6 in the third pixel group 10. Similarly, all the sub-pixels in the first row (Y1) are charged. In conventional single-gate driven pixels, a row of pixels is driven by one gate line.

[0109] Figure 14 is a schematic diagram of a related display panel. Figure 15 is another related schematic diagram of a display panel. Figure 16 is a schematic diagram of another related display panel. Figure 17 for Figure 16 A partial schematic diagram of the display panel in FIG. Figure 18 for Figure 16 The first row of sub-pixel driving timing diagram of the display panel in FIG. 1 is shown in FIG. 1 . In some exemplary embodiments, the current display panel has three types of tri-gate pixel architectures. Figure 14 The display panel in the NVIDIA NVIDIA GeForce 500 uses the first three-gate pixel architecture. Figure 15 The display panel in the CMOS image sensor adopts the second three-gate pixel architecture. Figure 16 The display panel in the third three-gate pixel architecture adopts the third three-gate pixel architecture. The applicant found that the display panels of these three three-gate pixel architectures adopt 1+2dot or column inversion drive. When 1+2dot drive is used to achieve dot inversion, the chip driving frequency of the data line is high, the power consumption is large, and there is a risk of monochrome vertical stripes caused by charging differences. When column inversion drive is used, the distribution of pixel polarity space is uneven, which will cause the bad condition of shaking head stripes. From the perspective of aperture ratio, the aperture ratio at the position of sub-pixel 6 is low, among which, Figure 14 The display panel in the display has the lowest aperture ratio. Figure 16 The display panel in the third type of triple-gate pixel structure has the highest aperture ratio. Figure 17 As shown, in order to improve the aperture ratio, the gate line (G1) is adjacent to the pixel electrode (P), so that the connection electrode (P) connecting the pixel electrode (P) and the transistor (T1) 1-1 ) away from the pixel electrode (P), the black matrix portion corresponding to the gate line (G1) can be narrowed, but it will cause the connection electrode (P 1-1 ) and the next row of gate lines (G2) are too close to each other. 2-2 ) is at a distance L5 from the next row of gate lines (G3), L5 is significantly greater than L4, and the connection electrodes are different. Figure 16 The timing diagram of the display panel is shown as Figure 18 As shown, in some exemplary embodiments, Figure 18 As shown, when the gate line (G1) is turned on, the voltage of the sub-pixel connected to the gate line (G1) is pulled high as shown by P1. When the pixel electrode is continuously charged, the pixel voltage is then pulled back. When the gate line (G1) is turned off, the voltage of the transistor will pull the pixel voltage down, forming its own feedback voltage △V1. Similarly, when the gate line (G1) is turned off, the voltage of the sub-pixel connected to the gate line (G1) will be pulled down, forming another feedback voltage △V1', and so on. The feedback voltages of the sub-pixels connected to different gate lines are also different, for example, △V1 and △V2 are different. Since L5 is greater than L4, △V2' will be greater than △V1', and the sub-pixels connected to the gate line (G3) have no other feedback voltages. Therefore, the feedback voltages of the sub-pixels connected to different gate lines are different, and it is impossible to form a unified reference voltage for compensation. Figure 16 and Figure 17 The display panel shown in the figure will form vertical stripes with a width of six sub-pixels as the unit. Figure 3 、 Figure 9 、 Figure 10 As shown, the connecting electrodes (32, 35, 38) are respectively adjacent to the corresponding pixel electrodes (30, 33, 36), so that the distance between the connecting electrodes and the next row of gate lines is increased, reducing the secondary coupling of the next row of gate lines to the drain, thereby reducing the feedback voltage difference, where L≥7um, in order to reduce other feedback voltages and ensure that the feedback voltage of each sub-pixel itself is consistent, so that the storage capacitors are the same.

[0110] In some exemplary embodiments, Figure 17 As shown, the relevant display panel has a transverse data line 48 along the first direction (X axis direction), and the transverse data line 48 affects the aperture ratio. Figure 3 、 Figure 9 As shown, the display panel has no data lines extending along the first direction (X-axis direction) between sub-pixels in two adjacent rows, which reduces the shading of the data lines and improves the aperture ratio.

[0111] In some exemplary embodiments, a display device may include the display panel described above. In some exemplary embodiments, the display device that may include the display panel of this embodiment may be a liquid crystal display device. The display device is a product with an image display function, such as a monitor, television, billboard, digital photo frame, telephone, mobile phone, digital camera, camcorder, navigation system, home appliance, or other device with a display function. The embodiments of this application do not impose any particular restrictions on the specific form of the display device described above.

[0112] In the above embodiment, the display panel of this example adopts a three-gate pixel architecture, and the data lines are connected in parallel, thereby reducing the number of chips used and replacing the existing MUX drive architecture. Compared with the dual-gate architecture, fewer chips can be used, the display panel has lower power consumption, avoids some display problems, and is suitable for harsh environments. The sub-pixels controlled by a gate line are adjacent to each other, and the polarity of the sub-pixels controlled by each data line group is the same, forming a column drive. The display panel of this example can reduce the driving power consumption of the data line group, thereby reducing the overall logic power consumption of the display panel and reducing the temperature rise of the chip. The display panel of this example can have a higher aperture ratio, which can improve the transmittance of the display panel, thereby further reducing the power consumption of the backlight. The display panel of this example can also solve the problem of monochrome vertical stripes caused by charging differences and can solve the problem of shaking head stripes. The display panel of this example uses pixel storage capacitor compensation and the design of the drain electrode adjacent to the pixel electrode to increase the distance between the drain electrode and other adjacent gate lines, thereby reducing the feedback voltage difference, solving the problem of vertical stripes caused by feedback voltage differences, and improving the performance of the display panel.

[0113] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is known to those skilled in the art, the term computer storage medium may include volatile and non-volatile, removable, and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media may include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. A display panel, characterized in that: include: A pixel structure comprising a plurality of sub-pixels arranged in an array, wherein a plurality of adjacent sub-pixels in each row constitute a pixel group, wherein each row of sub-pixels comprises a plurality of pixel groups, and wherein the plurality of pixel groups comprises at least one first pixel group, at least one second pixel group, and at least one third pixel group; A gate line structure comprising a plurality of gate line groups, one gate line group being configured to control a row of sub-pixels, each gate line group comprising three gate lines; the three gate lines comprising a first gate line, a second gate line, and a third gate line, the first gate line being configured to be electrically connected to the first pixel group, the second gate line being configured to be electrically connected to the second pixel group, and the third gate line being configured to be electrically connected to the third pixel group; A data line structure includes multiple data line groups, each of which includes multiple data lines connected in parallel. The multiple data lines are arranged to correspond one-to-one with and be electrically connected to at least two pixel groups in each row of the sub-pixels, and at least two sub-pixels in each column of the sub-pixels are arranged to be electrically connected to one data line.

2. The display panel according to claim 1, wherein: Two adjacent sub-pixels in each row of sub-pixels are set to have different polarities and luminous colors. Each row of sub-pixels includes multiple target sub-pixels with the same polarity and luminous color. At least two of the target sub-pixels are set to correspond one-to-one to and be electrically connected to multiple data lines connected in parallel in one data line group.

3. The display panel according to claim 2, wherein: Each pixel group includes a sub-pixels, the number of data line groups is b, b=m×a, and m is a positive integer; In each row of the sub-pixels, at least two adjacent pixel groups constitute a pixel repeating unit, and each pixel group in a pixel repeating unit is configured to be electrically connected to a data line groups.

4. The display panel according to claim 3, wherein: The pixel repeating unit includes a first pixel group, a second pixel group and a third pixel group, the first pixel group, the second pixel group and the third pixel group are arranged sequentially in a first direction, and one gate line group is configured to control the first pixel group, the second pixel group and the third pixel group to be lit sequentially; There are a plurality of pixel repeating units, and the plurality of pixel repeating units are arranged along the first direction.

5. The display panel according to claim 3, wherein: Each of the pixel groups includes six sub-pixels, and the number of the data line groups is 6×m, where m is a positive integer.

6. The display panel according to claim 5, wherein: Each of the pixel groups includes a first sub-pixel, a second sub-pixel, a third sub-pixel, a fourth sub-pixel, a fifth sub-pixel, and a sixth sub-pixel arranged in sequence along a first direction; The first sub-pixel and the fourth sub-pixel are configured to emit light of a first color, and the polarities of the first sub-pixel and the fourth sub-pixel are different; the second sub-pixel and the fifth sub-pixel are configured to emit light of a second color, and the polarities of the second sub-pixel and the fifth sub-pixel are different; the third sub-pixel and the sixth sub-pixel are configured to emit light of a third color, and the polarities of the third sub-pixel and the sixth sub-pixel are different; The plurality of data line groups include a first data line group, a second data line group, a third data line group, a fourth data line group, a fifth data line group, and a sixth data line group; At least two data lines of the first data line group are arranged to correspond one-to-one to and be electrically connected to the first sub-pixels of at least two pixel groups respectively; at least two data lines of the second data line group are arranged to correspond one-to-one to and be electrically connected to the second sub-pixels of at least two pixel groups respectively; at least two data lines of the third data line group are arranged to correspond one-to-one to and be electrically connected to the third sub-pixels of at least two pixel groups respectively; at least two data lines of the fourth data line group are arranged to correspond one-to-one to and be electrically connected to the fourth sub-pixels of at least two pixel groups respectively; at least two data lines of the fifth data line group are arranged to correspond one-to-one to and be electrically connected to the fifth sub-pixels of at least two pixel groups respectively; and at least two data lines of the sixth data line group are arranged to correspond one-to-one to and be electrically connected to the sixth sub-pixels of at least two pixel groups respectively.

7. The display panel according to claim 6, wherein: The number of the data line groups is 6, and the plurality of pixel groups in each row of sub-pixels are configured to be electrically connected to six data line groups.

8. The display panel according to claim 6, wherein: The number of the data line groups is 6×m, where m is a positive integer greater than 1; The first data line group, the second data line group, the third data line group, the fourth data line group, the fifth data line group, and the sixth data line group constitute a data line unit, and the data line structure includes m data line units; The data line units and the pixel repeating units are arranged in one-to-one correspondence and are electrically connected.

9. The display panel according to claim 1, wherein: Also includes substrate; The first pixel group, the second pixel group, and the third pixel group are arranged along a first direction, and the first direction is parallel to the substrate; The sub-pixels of the first pixel group all include a first pixel electrode and a first transistor, wherein the orthogonal projections of the first transistor and the first pixel electrode on the substrate are both located on the same side of the orthogonal projection of the first gate line on the substrate in a second direction, wherein the second direction is parallel to the substrate and perpendicular to the first direction; The sub-pixels of the second pixel group all include a second pixel electrode and a second transistor, and the orthographic projections of the second transistor and the second pixel electrode on the substrate are both located on the same side of the orthographic projection of the second gate line on the substrate in the second direction; The sub-pixels of the third pixel group all include a third pixel electrode and a third transistor, and the orthographic projections of the third transistor and the third pixel electrode on the substrate are both located on the same side of the orthographic projection of the third gate line on the substrate in the second direction.

10. The display panel according to claim 9, wherein: The orthographic projection of the first gate line on the substrate is located on one side of the orthographic projection of the first pixel group on the substrate in the second direction; The orthographic projection of the second gate line on the substrate is located on the other side of the orthographic projection of the first pixel group on the substrate in the second direction; The orthographic projection of the third gate line on the substrate is located on a side of the orthographic projection of the second gate line on the substrate away from the first pixel group.

11. The display panel according to claim 10, wherein: The subpixel of the first pixel group further includes a first connecting electrode connecting the first pixel electrode and the first transistor, an orthographic projection of the first connecting electrode on the substrate is a first projection, a projection of a gate line adjacent to the first gate line on the substrate is a second projection, and a minimum distance between the first projection and the second projection in the second direction is L1; The subpixel of the second pixel group further includes a second connecting electrode connecting the second pixel electrode and the second transistor, an orthographic projection of the second connecting electrode on the substrate is a third projection, a projection of the third gate line on the substrate is a fourth projection, and a minimum distance between the third projection and the fourth projection in the second direction is L2; The subpixel of the third pixel group further includes a third connecting electrode connecting the third pixel electrode and the third transistor, an orthographic projection of the third connecting electrode on the substrate is a fifth projection, a projection of the first gate line on the substrate is a sixth projection, and a minimum distance between the fifth projection and the sixth projection in the second direction is L3; L1, L2 and L3 are all greater than or equal to 7 microns.

12. The display panel according to claim 9, wherein: Each row of sub-pixels is arranged to correspond to the data lines one by one, and the orthographic projection of any data line on the substrate is arranged to be located on the same side of the first direction of the orthographic projection of the sub-pixels electrically connected to the data line on the substrate.

13. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 12.

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