Code division method, system and equipment for heterogeneous multi-core processor and medium

Abstract

The invention relates to the technical field of servers, and particularly provides a heterogeneous multi-core processor-oriented code division method, system and device and a medium, and the method comprises the following steps: obtaining a code file, and converting the code file into a unified intermediate representation; based on the type of the operation instruction in the intermediate representation, distributing the operation instruction to a processing unit; and based on the intermediate representation corresponding to the operation instruction allocated to each processing unit, generating an executable file containing codes for different processing units. According to the method, the instruction type analysis of the unified intermediate representation is used for dynamically distributing the operation to the adaptive processing unit, so that the manual annotation cost is eliminated, and the development efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of servers, and in particular relates to a code partitioning method, system, device and medium for heterogeneous multi-core processors. Background Art

[0002] With the popularization of heterogeneous multi-core processors (such as CPU+GPU+NPU architecture), traditional compilation technology faces severe challenges: Static partitioning limitations: Existing compilers (such as GCC / LLVM) rely on preset rules to allocate computing tasks and cannot dynamically adapt to the real-time load and architectural characteristics of different processing units, resulting in low resource utilization. Lack of collaborative execution: Manually annotated heterogeneous code (such as OpenCL / CUDA) requires repeated development, and cross-processing unit data synchronization relies on explicit memory copies, introducing up to 30% additional overhead (data source: IEEE Micro 2023); Optimization gap: The lack of a unified intermediate representation between the front-end syntax tree and the back-end machine code hinders cross-architecture joint scheduling optimization.

[0003] While current solutions (such as SyCL) attempt to unify the programming model, they still require developers to manually partition parallel domains, and the segmented binaries generated by compilation require additional linker integration. Therefore, an automated, low-overhead code partitioning approach is urgently needed to achieve end-to-end optimization from a unified intermediate representation to heterogeneous executables. Summary of the Invention

[0004] In view of the above-mentioned deficiencies in the prior art, the present invention provides a code partitioning method, system, device and medium for heterogeneous multi-core processors to solve the above-mentioned technical problems.

[0005] In a first aspect, the present invention provides a code partitioning method for a heterogeneous multi-core processor, comprising: Obtaining a code file and converting the code file into a unified intermediate representation; assigning the operation instruction to a processing unit based on a type of the operation instruction in the intermediate representation; Based on the intermediate representation corresponding to the operation instruction allocated to each processing unit, an executable file containing codes for different processing units is generated.

[0006] In an optional embodiment, the method further comprises: Configure basic parameters, including the number of processing units included in the heterogeneous multi-core processor, the space size of DRAM, the intermediate representation structure, and the type of instructions.

[0007] In an optional embodiment, converting the code file into a unified intermediate representation includes: Convert the code file into a static single-assignment intermediate representation; A circular buffer is established for a variable of each operation instruction in the intermediate representation, and a space size of the circular buffer is twice the data size of the corresponding variable.

[0008] In an optional embodiment, allocating the operation instruction to the processing unit based on the type of the operation instruction in the intermediate representation includes: Reversely traverse the operation instructions in the intermediate representation, add the instructions unique to a specific processing unit to the intermediate representation queue of the processing unit, and continue traversing along the definition-use chain of the instructions; During the traversal process, by determining whether the instruction needs to be read from the DRAM, a loop buffer operation rule is configured for the instruction in the processing unit that calculates the instruction; During the traversal process, by determining whether the instruction needs to be written back to the DRAM, a circular buffer operation rule is configured for the instruction in the processing unit that performs the write operation.

[0009] In an optional embodiment, by determining whether the instruction needs to be read from DRAM, configuring a circular buffer operation rule for the instruction in a processing unit that calculates the instruction includes: Determine whether the instruction needs to be read from DRAM: If so, insert a circular buffer write operation into the intermediate representation of the processing unit assigned to the read operation: first wait for the available space in the circular buffer to be larger than the amount of data to be read; then read the data from DRAM into the circular buffer; finally, modify the available space and the amount of ready data in the circular buffer; If not, insert a circular buffer calculation operation into the intermediate representation of the processing unit assigned to the calculation operation: first wait for the amount of ready data in the input circular buffer to be greater than the amount of data required by the operation; then wait for the available space in the output result circular buffer to be greater than the amount of space required for the result of the operation; then execute the operation instruction; finally reduce the amount of ready data in the input circular buffer and increase its available space, and at the same time increase the amount of ready data in the output circular buffer and reduce its available space.

[0010] In an optional embodiment, by determining whether the instruction needs to be written back to the DRAM, configuring a circular buffer operation rule for the instruction in the processing unit performing the write operation includes: If the confirmed operation instruction requires data to be written back to DRAM, a circular buffer read operation is inserted into the intermediate representation of the processing unit assigned to the write operation: first, wait for the amount of ready data in the circular buffer to be greater than the amount of data required to be written back by the operation; then write the data back to DRAM; finally, increase the available space of the circular buffer and reduce its ready data amount.

[0011] In an optional embodiment, based on the intermediate representation corresponding to the operation instruction allocated to each processing unit, an executable file containing codes for different processing units is generated, including: Call the compiler backend to compile the intermediate representation of each processing unit into the corresponding target file; Link all object files to generate the final executable file.

[0012] In a second aspect, the present invention provides a code partitioning system for heterogeneous multi-core processors, comprising: A conversion module, configured to obtain a code file and convert the code file into a unified intermediate representation; an allocation module, configured to allocate the operation instruction to a processing unit based on a type of the operation instruction in the intermediate representation; The compiling module is used to generate executable files containing codes for different processing units based on the intermediate representation corresponding to the operation instructions allocated to each processing unit.

[0013] According to a third aspect, a device is provided, comprising: A memory for storing a code partitioning program for a heterogeneous multi-core processor; The processor is configured to implement the steps of the code partitioning method for heterogeneous multi-core processors provided in the first aspect when executing the code partitioning program for heterogeneous multi-core processors.

[0014] In a fourth aspect, a computer-readable medium is provided, on which a code partitioning program for a heterogeneous multi-core processor is stored. When the code partitioning program for a heterogeneous multi-core processor is executed by a processor, the steps of the code partitioning method for a heterogeneous multi-core processor provided in the first aspect are implemented.

[0015] The beneficial effects of the present invention are that the code partitioning method, system, device and medium for heterogeneous multi-core processors provided by the present invention dynamically allocate operations to adaptive processing units through instruction type analysis of a unified intermediate representation, eliminating manual labeling costs and improving development efficiency; accurately allocate instructions based on processing unit architecture characteristics (such as GPU parallel cores / NPU vector units), thereby improving hardware computing resource utilization; cross-unit data dependencies are parsed in the intermediate representation layer, and buffer synchronization instructions are automatically inserted, reducing explicit memory copies and lowering communication delays; and heterogeneous executable files are generated end-to-end, avoiding secondary linking and shortening the depth of the tool chain. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] Figure 1 is a schematic flow chart of a method according to an embodiment of the present invention.

[0018] Figure 2 is another schematic flow chart of a method according to an embodiment of the present invention.

[0019] Figure 3 FIG. 4 is a schematic block diagram of a system according to an embodiment of the present invention.

[0020] Figure 4 A schematic structural diagram of a device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0021] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0023] The key terms appearing in the present invention are explained below.

[0024] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. Its main working principle is to use the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0.

[0025] The code partitioning method for heterogeneous multi-core processors provided by the embodiment of the present invention is executed by a computer device. Accordingly, the code partitioning system for heterogeneous multi-core processors runs in the computer device.

[0026] Figure 1 is a schematic flow chart of a method according to an embodiment of the present invention. Figure 1The execution subject may be a code partitioning system for heterogeneous multi-core processors. According to different requirements, the order of the steps in the flowchart can be changed, and some steps can be omitted.

[0027] like Figure 1 As shown, the method includes: S1. Obtain a code file and convert the code file into a unified intermediate representation; S2. Based on the type of operation instruction in the intermediate representation, the operation instruction is assigned to the processing unit; S3. Generate an executable file containing codes for different processing units based on the intermediate representation corresponding to the operation instructions allocated to each processing unit.

[0028] Please refer to Figure 2 , the data processing flow of the present invention is described in detail.

[0029] In an embodiment of the present invention, based on step S1, a possible embodiment will be given below to illustrate its specific implementation scheme in a non-limiting manner.

[0030] First, configure the heterogeneous architecture parameters: define the total number of processing elements (PEs) and the dedicated resources of each PE (such as SRAM size); initialize the intermediate representation (IR) structure corresponding to the number of PEs; and classify instructions by function: memory operation instructions, calculation instructions, control flow instructions (including jumps), and PE-specific instructions.

[0031] In the optimized design of heterogeneous computing architectures, parameter configuration and intermediate representation (IR) processing are key steps in achieving efficient code execution. First, when configuring heterogeneous architecture parameters, the total number of processing elements (PEs) must be determined based on both system performance requirements and hardware resource constraints. By establishing a mathematical model based on task parallelism and resource utilization, heuristic or genetic algorithms are employed for optimization to determine the optimal number of PEs. The configuration of each PE's dedicated resources (such as static random access memory (SRAM)) must be tailored to the characteristics of the computing task it undertakes. Through data locality analysis and memory access pattern prediction, a hierarchical storage architecture design approach is employed to precisely allocate SRAM size to balance storage capacity and access speed. During IR structure initialization, a dynamic IR data structure corresponding to the number of PEs is constructed. Each IR structure contains instruction sequences, operand dependencies, and data flow information, modeled using the directed acyclic graph (DAG) model from graph theory to intuitively reflect the parallelism and dependencies between instructions. Instruction function classification adopts a classification strategy based on semantic analysis. Memory operation instructions are subdivided into subtypes such as load, store, and data copy, and a memory address mapping table is established to optimize memory access efficiency. Computational instructions are classified according to operation type (arithmetic, logical, bitwise operations, etc.), providing a basis for subsequent instruction scheduling and optimization. Control flow instructions are analyzed through control flow graphs (CFGs) to identify jump conditions and branch paths, and predictive execution technology is used to improve execution efficiency. PE-specific instructions are customized according to the hardware characteristics of each PE to ensure efficient matching of their functions and resources.

[0032] S101. Convert the code file into a static single-assignment intermediate representation.

[0033] During the code conversion phase, a dataflow analysis-based conversion algorithm is used to convert the code file into an intermediate representation in the form of static single assignment (SSA). First, the syntax tree is parsed to construct an abstract syntax tree (AST). Then, by solving the dataflow equations, a unique version number is generated for each variable. This ensures that each variable has only one definition point at any location in the program, eliminating multiple variable definitions and improving the code's analyzability and optimization potential. Furthermore, the semantic information of the original code is preserved during the conversion process, and a symbol table and type inference mechanism are established to ensure type consistency and semantic correctness.

[0034] S102 . Create a circular buffer for each variable of an operation instruction in the intermediate representation, where the space size of the circular buffer is twice the data size of the corresponding variable.

[0035] For the construction of a circular buffer, dynamic memory allocation and a double-buffering mechanism are used when establishing a circular buffer for the variables of each operation instruction in the intermediate representation. The buffer space size is set to twice the size of the corresponding variable data. This strategy is based on statistical analysis and prediction of the variable read and write patterns, and can effectively reduce the risk of buffer overflow and underflow. In the specific implementation, by introducing two pointers to point to the read position and write position of the buffer respectively, a circular queue data structure is adopted. When the write pointer reaches the end of the buffer, it automatically wraps back to the starting position, realizing circular storage and efficient access of data. At the same time, to ensure data consistency, a locking mechanism or a lock-free concurrency control algorithm is used during read and write operations to avoid data competition problems in a multi-threaded environment, thereby improving the accuracy of data processing and the stability of the system.

[0036] In an embodiment of the present invention, based on step S2, a possible embodiment will be given below to illustrate its specific implementation scheme in a non-limiting manner.

[0037] S201. Reversely traverse the operation instructions in the intermediate representation, add the instructions unique to a specific processing unit to the intermediate representation queue of the processing unit, and continue traversing along the definition-use chain of the instructions.

[0038] A reverse traversal algorithm based on a dominator tree is used, starting from the exit node of the intermediate representation and traversing the operation instructions in the reverse direction of the control flow. This traversal strategy ensures that when processing each instruction, all its dependent instructions have been processed, providing a basis for the correct classification and mapping of instructions.

[0039] Instructions unique to a specific processing element (PE) are categorized by establishing an instruction-to-PE mapping table. This mapping table is automatically constructed based on the PE feature description file generated by the hardware description language (HDL) and contains information such as instruction type, operand format, and execution cycle. During the traversal process, a pattern matching algorithm is used to compare the current instruction with the mapping table to determine the target PE to which it belongs.

[0040] As the instruction definition-use chain continues to traverse, live variable analysis is used to maintain a set of live variables. When an instruction operating on a live variable is encountered, it is added to the intermediate representation queue of the target PE and its dependent instructions are recursively processed to form a complete computation chain.

[0041] In one example, a workflow diagram that traverses a process definition definition-usage chain: (1) Create a new stack and add the current instruction to the stack.

[0042] (2) Read all operands of the top instruction in the queue, add the definition instruction of each operand, the calculation to the stack and the intermediate representation corresponding to the processor, and mark the definition instruction as determined.

[0043] (3) Pop the head instruction from the stack and check whether the stack is empty. If the stack is not empty, jump to (2).

[0044] (4) For the instruction from the current instruction to the instruction closest to the one added in step (2), add the marked jump instruction in the range to the target instruction queue and mark the instruction as confirmed.

[0045] In the fields of compiler optimization and instruction scheduling, efficient traversal of the define-use chain is crucial for data flow analysis and dependency resolution. This section will detail the workflow of define-use chain traversal from three perspectives: formal definition, algorithm implementation, and data structure design.

[0046] 1. Formal Definition and Theoretical Basis 1.1 Basic Concept Definition Instruction Graph: It is defined as a directed graph G=(V,E), where nodes v∈V represent instructions in the intermediate representation and edges e∈E represent dependencies between instructions.

[0047] Def-Use Chain: For a variable x, the relationship between its definition instruction d and use instruction u is represented as a tuple , where DUC is the definition-use chain set.

[0048] Dominance: Instruction d dominates instruction u if and only if all paths from the entry node to u pass through d, denoted as d dom u.

[0049] 1.2 Formal Constraints The following constraints must be met during the traversal process: Dependency consistency: For any (d,u)∈DUC, d must appear before u in the traversal sequence.

[0050] Completeness: All reachable definition instructions must be traversed once and only once.

[0051] Minimalism: No redundant instructions are introduced during the traversal process, and only necessary dependent instructions are included.

[0052] 2. Algorithm implementation and data structure design 2.1 Core Algorithm Process Initialization phase: Create an empty stack S and an empty tag set MM. The tag set is used to record the instructions that have been processed to avoid repeated operations.

[0053] The current instruction Ic of the input is pushed into the stack S and added to the tag set M. This indicates that the traversal starts from Ic.

[0054] Stack walking phase (processing definition chains): As long as the stack S is not empty, repeat the following steps: a. Pop an instruction from the top of the stack, called the current processing instruction It. b. Get the set of all operands Ot of It (these operands are the data or variables that It depends on). c. For each operand o in Ot: Find the set of instructions Do that define an operand o (these are the "producer" instructions, providing a value for o).

[0055] For each definition directive d in Do: If d has not been marked (ie, d∉M): add d to the mark set M; push d into the stack S for subsequent processing of its operands; find the target processor PE corresponding to d according to the processor mapping table PM d (PM specifies which processor each instruction should be mapped to); add d to the target processor PE d The intermediate representation queue IR[PE d ] (this means that the instruction is dispatched to the execution queue of a specific processor).

[0056] This loop continues until the stack is empty. Essentially, it starts at Ic and, depth-first, iterates through all relevant defined instructions (i.e., sources of operands), marking and dispatching them to the corresponding processor queues. The marking set M ensures that each instruction is processed only once.

[0057] Post-processing stage (processing jump instructions): After the stack walk is complete, the following additional steps are performed: a. Get the earliest added instruction If from the marking set M (in the algorithm, this is called "the earliest added instruction in the initialization process", which actually refers to the first instruction added in the marking process, that is, the initial Ic. Therefore, If is usually Ic).

[0058] b. Get the range R of instructions from the current instruction Ic to If (since If and Ic are usually the same, R may contain only Ic itself, or in a more complex context, it represents the sequence of instructions between Ic and If in program order).

[0059] c. For each instruction i in range R: If i is a jump instruction (such as a conditional branch or an unconditional jump), and i has not been marked (i.e., i∉M): Add i to the target instruction queue Qt.

[0060] Add i to the tag set M to ensure that it is not added repeatedly.

[0061] Output stage: Finally, the algorithm outputs the target instruction queue Qt (containing the processed jump instructions) and the tag set M (containing all processed instructions). These outputs can be used for subsequent scheduling or execution.

[0062] This algorithm is used for instruction scheduling or compiler optimization, dynamically dispatching instructions to multiprocessor systems (via PM mapping) by tracking operand dependencies (definition chains). The stack ensures depth-first traversal, while the marked set prevents infinite loops.

[0063] 2.2 Data Structure Design Instruction Stack: A stack structure implemented using a dynamic array that supports efficient push and pop operations with a time complexity of O(1).

[0064] Mark Set: Implemented using a Hash Set to ensure that the average time complexity of instruction mark checking operations is O(1).

[0065] Processor Mapping Table: This is implemented using a hash map to map instructions to the target processor, supporting fast lookup operations.

[0066] 3. Key technical details and optimization strategies 3.1 Jump Instruction Processing Strategy In step (4), the control flow graph (CFG) analysis technique is used to process the jump instruction: Static branch prediction: Based on historical execution statistics, the branch direction of jump instructions is predicted.

[0067] Delay slot scheduling: inserts independent instructions after jump instructions to reduce the performance loss caused by branch delay.

[0068] Exception handling: For jump instructions that may cause exceptions, insert exception handling code to ensure program robustness.

[0069] 3.2 Dependency Resolution Optimization Data flow analysis: Uses a bit vector-based data flow analysis method to calculate the live range (LiveRange) of variables.

[0070] Value Numbering: Calculates a unique value number for an instruction, which is used to quickly determine the equivalence between instructions.

[0071] Alias ​​analysis: Use type-based alias analysis technology to resolve the dependencies between memory operation instructions.

[0072] 3.3 Concurrency Control Mechanism In a multi-threaded environment, the following concurrency control strategy is adopted: Atomic operations: Use atomic instructions to implement thread-safe operations on marked collections.

[0073] Read-write lock: Access to the intermediate representation queue uses a read-write lock mechanism, which allows multiple threads to read simultaneously but are mutually exclusive when writing.

[0074] Barrier synchronization: Insert memory barriers at key steps to ensure the consistency of instruction execution order.

[0075] 4. Complexity Analysis and Correctness Proof 4.1 Time Complexity Stack operation: Each instruction is pushed and popped at most once, with a time complexity of O(n), where n is the total number of instructions.

[0076] Dependency resolution: The defined instruction set lookup time complexity for each operand is O(1) (assuming a hash table implementation).

[0077] Jump instruction processing: The time complexity of traversing the instruction range is O(m), where m is the length of the instruction range.

[0078] 4.2 Proof of Correctness Completeness: Ensure that all dependent instructions are processed by recursively traversing the definition instructions of all operands.

[0079] No redundancy: Use tag sets to avoid repetitive processing of identified instructions.

[0080] Sequential Correctness: Based on the last-in, first-out (LIFO) feature of the stack, it ensures that the definition instructions are processed before the use instructions.

[0081] S202. During the traversal process, by determining whether the instruction needs to be read from the DRAM, a loop buffer operation rule is configured for the instruction in the processing unit that calculates the instruction.

[0082] Determine whether the instruction needs to be read from DRAM: If so, insert a circular buffer write operation into the intermediate representation of the processing unit assigned to the read operation: first wait for the available space in the circular buffer to be larger than the amount of data to be read; then read the data from DRAM into the circular buffer; finally, modify the available space and the amount of ready data in the circular buffer; If not, insert a circular buffer calculation operation into the intermediate representation of the processing unit assigned to the calculation operation: first wait for the amount of ready data in the input circular buffer to be greater than the amount of data required by the operation; then wait for the available space in the output result circular buffer to be greater than the amount of space required for the result of the operation; then execute the operation instruction; finally reduce the amount of ready data in the input circular buffer and increase its available space, and at the same time increase the amount of ready data in the output circular buffer and reduce its available space.

[0083] Specifically, when determining whether an instruction needs to read data from DRAM, a method combining static data flow analysis with dynamic runtime information is used. By analyzing the source of the instruction's operands and combining memory address analysis and alias analysis techniques, the data storage location is determined.

[0084] When it is confirmed that data needs to be read from DRAM, a circular buffer write operation is inserted into the intermediate representation of the PE assigned to the read operation. This operation consists of three key steps: Space availability check: Atomic operations are used to check the available space in the circular buffer, ensuring data consistency in a multi-threaded environment. Available space is calculated using the following formula: Available space = Total buffer size - Ready data amount - Allocated space. Allocated space refers to space reserved for other read operations but not yet written to.

[0085] Data transfer control: Direct memory access (DMA) technology is used to efficiently transfer data from DRAM to the circular buffer. During the transfer process, a double buffering mechanism is used to ensure that data reading and calculation operations are overlapped.

[0086] State Updates: Memory barriers are used to ensure sequential updates to the circular buffer state, avoiding consistency issues caused by memory reordering. State updates are implemented using atomic increment / decrement operations to ensure thread safety.

[0087] For computation instructions that do not require data to be read from DRAM, a circular buffer computation operation is inserted into the intermediate representation of the PE assigned to the computation operation. This operation consists of four key steps: Input data readiness check: Ensures that sufficient input data is available by comparing the amount of ready data in the input circular buffer with the amount of data required for the current operation. The calculation of the amount of ready data is based on the producer-consumer model and maintained using an atomic counter.

[0088] Output space availability check: Similarly, check whether the available space in the output circular buffer is sufficient to store the computation result. Use the same atomic operation mechanism as the input check to ensure correctness in concurrent environments.

[0089] Instruction execution: After the input and output conditions are met, the computational instruction is executed. To improve execution efficiency, instruction pipelining technology is used, dividing instruction execution into stages such as instruction fetch, decode, execute, and write back.

[0090] State Update: Upon completion, the states of the input and output circular buffers are updated simultaneously. The amount of ready data in the input buffer decreases, and the available space increases accordingly; the amount of ready data in the output buffer increases, and the available space decreases accordingly. These updates utilize transactional memory technology to ensure atomicity.

[0091] S203. During the traversal process, by determining whether the instruction needs to be written back to the DRAM, a circular buffer operation rule is configured for the instruction in the processing unit that performs the write operation.

[0092] If the confirmed operation instruction requires data to be written back to DRAM, a circular buffer read operation is inserted into the intermediate representation of the processing unit assigned to the write operation: first, wait for the amount of ready data in the circular buffer to be greater than the amount of data required to be written back by the operation; then write the data back to DRAM; finally, increase the available space of the circular buffer and reduce its ready data amount.

[0093] When an instruction is confirmed to need to write data back to DRAM, a circular buffer read operation is inserted into the intermediate representation of the PE assigned to the write operation. This operation consists of three key steps: Data readiness check: This atomic operation checks whether the amount of ready data in the circular buffer meets write-back requirements. This uses a check mechanism similar to that used for compute operations to ensure data availability.

[0094] Data transfer control: DMA technology is used to write data from the circular buffer back to DRAM. To optimize memory bandwidth utilization, a burst transfer mode is used to align data transfers along memory page boundaries.

[0095] Status Update: After the writeback is complete, the status of the circular buffer is updated. Atomic operations are used to increase the available space and reduce the amount of ready data to ensure the atomicity and visibility of the status update.

[0096] By configuring the above-mentioned circular buffer operation rules, efficient data flow between DRAM, circular buffer and computing unit is achieved, which reduces memory access latency and improves the overall performance of heterogeneous computing systems.

[0097] In an embodiment of the present invention, based on step S3, a possible embodiment will be given below to illustrate its specific implementation scheme in a non-limiting manner.

[0098] S301. Call the compiler backend to compile the intermediate representation of each processing unit into a corresponding target file.

[0099] During the compiler's back-end processing phase, target-independent intermediate representation optimization is first performed. Constant propagation and folding are implemented through value numbering and data flow analysis techniques, pre-calculating constant values ​​in expressions and reducing runtime computational overhead. Live variable analysis identifies and removes unreachable code blocks, eliminating dead code. Loop structures are optimized using techniques such as loop invariant code motion and strength reduction to improve loop execution efficiency. Target-specific optimization strategies are implemented based on the hardware characteristics of different processing units. For compute-intensive processing units such as GPUs and DSPs, instruction-level parallelism analysis is used for SIMD vectorization, converting scalar operations into vector operations. For memory-constrained processing units such as FPGAs, data layout transformation (DLT) techniques are applied to optimize memory access patterns and reduce memory access latency. For superscalar processors, list scheduling algorithms are used to optimize instruction execution order and improve pipeline utilization. During the code generation phase, the compiler backend uses a tree pattern matching algorithm to map intermediate representation instructions to specific instructions in the target ISA, based on the processor's instruction set architecture (ISA). A graph coloring register allocation algorithm is used to map virtual registers to physical registers, and a critical path-based instruction scheduling algorithm is applied to optimize instruction execution order and reduce pipeline stalls.

[0100] Target file generation follows a unified relocatable file format (e.g., ELF), containing key sections such as .text (executable code segment), .data (initialized global and static variables), .bss (uninitialized global and static variables), and .rodata (read-only data), as well as .symtab (symbol table), .rel.text, and .rel.data (relocation information) for symbol resolution and relocation. To support heterogeneous architectures, processing unit-specific metadata is also added to the target file, including hardware configuration information (processing unit type, resource constraints), memory mapping information (address space layout), and execution constraints (synchronization and communication requirements between processing units).

[0101] S302. Link all target files to generate the final executable file.

[0102] The multi-target file linking mechanism is key to achieving collaborative work in heterogeneous systems. The linker first merges the symbol tables of all target files, uses a hash table to accelerate symbol lookups (with a time complexity of O(1)), and resolves the definitions and references of global symbols. It then allocates virtual address space for each section, corrects address references in code and data based on relocation information, and uses lazy binding technology to optimize dynamic linking performance. In response to the characteristics of heterogeneous architectures, the linking process automatically inserts code required for cross-processing unit communication (such as DMA transfers and message passing), inserts appropriate memory barrier instructions based on the processing unit's memory model to ensure memory consistency, and detects and resolves conflicts between different processing units for shared resources (such as I / O ports and interrupt vectors). The resulting executable file contains a program header table (describing memory mapping rules), a section header table (retaining section information for debugging), initialization code (responsible for initializing each processing unit and global variables), and an executable body that integrates the code and data of all processing units.

[0103] To further improve performance and ensure correctness, Link-Time Optimization (LTO) is implemented during the linking phase. Through full-program data flow analysis and control flow analysis, cross-module optimization opportunities are identified, cross-module inlining technology is applied to eliminate function call overhead, and duplicate code in different target files is detected and removed. At the same time, strict correctness verification is performed, including type consistency checks to ensure interface type matching between different processing units, resource constraint verification to prevent resource usage of each processing unit from exceeding hardware limits, and dependency verification to check whether the synchronization and communication logic between processing units is correct. Through the comprehensive application of this series of technologies, efficient conversion from intermediate representation to executable files is achieved, ensuring the performance and correctness of heterogeneous computing systems.

[0104] In some embodiments, the code partitioning system for heterogeneous multi-core processors may include multiple functional modules composed of computer program segments. The computer program of each program segment in the code partitioning system for heterogeneous multi-core processors may be stored in a memory of a computer device and executed by at least one processor to perform (see Figure 1 Description) Code partitioning for heterogeneous multi-core processors.

[0105] In this embodiment, the code partitioning system for heterogeneous multi-core processors can be divided into multiple functional modules according to the functions it performs, such as Figure 3As shown. The module referred to in the present invention refers to a series of computer program segments that can be executed by at least one processor and can perform fixed functions, which are stored in a memory. In this embodiment, the functions of each module will be described in detail in subsequent embodiments.

[0106] A conversion module, configured to obtain a code file and convert the code file into a unified intermediate representation; an allocation module, configured to allocate the operation instruction to a processing unit based on a type of the operation instruction in the intermediate representation; The compiling module is used to generate executable files containing codes for different processing units based on the intermediate representation corresponding to the operation instructions allocated to each processing unit.

[0107] Figure 4 The code partitioning method for heterogeneous multi-core processors provided in the embodiment of the present application can be applied to devices. Those skilled in the art will understand that the device structure involved in the embodiment of the present invention does not constitute a limitation on the device, and the device may include more or fewer components than shown in the figure, or combine certain components, or arrange different components. In the embodiment of the present invention, the device includes but is not limited to a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the embodiments of the present application described and / or required herein.

[0108] The device 400 may include a processor 410, a memory 420, and a communication unit 430. These components communicate via one or more buses. Those skilled in the art will appreciate that the server structure shown in the figure does not limit the present invention. The server structure may be a bus structure or a star structure, and may include more or fewer components than shown, or combine certain components, or arrange the components differently.

[0109] Memory 420 can be used to store execution instructions of processor 410. Memory 420 can be implemented by any type of volatile or non-volatile memory device, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk. When the execution instructions in memory 420 are executed by processor 410, device 400 can perform some or all of the steps in the following method embodiments.

[0110] The processor 410 is the control center of the storage device, which uses various interfaces and lines to connect various parts of the entire electronic device. It runs or executes software programs and / or modules stored in the memory 420, and calls data stored in the memory to perform various functions of the electronic device and / or process data. The processor can be composed of an integrated circuit (IC), for example, it can be composed of a single packaged IC, or it can be composed of multiple packaged ICs with the same or different functions. For example, the processor 410 can only include a central processing unit (CPU). In an embodiment of the present invention, the CPU can be a single computing core or multiple computing cores.

[0111] The communication unit 430 is configured to establish a communication channel so that the storage device can communicate with other devices, receive user data sent by other devices, or send user data to other devices.

[0112] The present invention also provides a computer medium, wherein the computer medium may store a program that, when executed, may include some or all of the steps of each embodiment provided by the present invention. The medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0113] Those skilled in the art will clearly understand that the techniques in the embodiments of the present invention can be implemented using software and a necessary general-purpose hardware platform. Based on this understanding, the technical solutions in the embodiments of the present invention, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a medium such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, among other media capable of storing program code, and includes instructions for causing a computer device (which can be a personal computer, a server, or a second device, a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention.

[0114] In this specification, the same or similar parts between the various embodiments can be referred to each other. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiment.

[0115] In the several embodiments provided by the present invention, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of systems or modules, and can be electrical, mechanical or other forms.

[0116] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules may be selected to achieve the purpose of the present embodiment according to actual needs.

[0117] In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.

[0118] Although the present invention has been described in detail with reference to the accompanying drawings and in conjunction with preferred embodiments, the present invention is not limited thereto. Without departing from the spirit and essence of the present invention, persons of ordinary skill in the art may make various equivalent modifications or substitutions to the embodiments of the present invention, and such modifications or substitutions shall be within the scope of the present invention. Any changes or substitutions that can be easily conceived by persons skilled in the art within the technical scope disclosed in the present invention shall be within the scope of protection of the present invention.

Claims

1. A code partitioning method for heterogeneous multi-core processors, characterized in that: include: Obtaining a code file and converting the code file into a unified intermediate representation; assigning the operation instruction to a processing unit based on a type of the operation instruction in the intermediate representation; Based on the intermediate representation corresponding to the operation instruction allocated to each processing unit, an executable file containing codes for different processing units is generated.

2. The method according to claim 1, characterized in that The method further comprises: Configure basic parameters, including the number of processing units included in the heterogeneous multi-core processor, the space size of DRAM, the intermediate representation structure, and the type of instructions.

3. The method according to claim 1, characterized in that Convert the code file into a unified intermediate representation, including: Convert the code file into a static single-assignment intermediate representation; A circular buffer is established for a variable of each operation instruction in the intermediate representation, and a space size of the circular buffer is twice the data size of the corresponding variable.

4. The method according to claim 1, wherein Allocating the operation instruction to a processing unit based on a type of the operation instruction in the intermediate representation includes: Reversely traverse the operation instructions in the intermediate representation, add the instructions unique to a specific processing unit to the intermediate representation queue of the processing unit, and continue traversing along the definition-use chain of the instructions; During the traversal process, by determining whether the instruction needs to be read from the DRAM, a loop buffer operation rule is configured for the instruction in the processing unit that calculates the instruction; During the traversal process, by determining whether the instruction needs to be written back to the DRAM, a circular buffer operation rule is configured for the instruction in the processing unit that performs the write operation.

5. The method according to claim 4, characterized in that By determining whether the instruction needs to be read from the DRAM, configuring a circular buffer operation rule for the instruction in a processing unit that calculates the instruction, including: Determine whether the instruction needs to be read from DRAM: If so, insert a circular buffer write operation into the intermediate representation of the processing unit assigned to the read operation: first wait for the available space in the circular buffer to be larger than the amount of data to be read; then read the data from DRAM into the circular buffer; finally, modify the available space and the amount of ready data in the circular buffer; If not, insert a circular buffer calculation operation into the intermediate representation of the processing unit assigned to the calculation operation: first wait for the amount of ready data in the input circular buffer to be greater than the amount of data required by the operation; then wait for the available space in the output result circular buffer to be greater than the amount of space required for the result of the operation; then execute the operation instruction; finally reduce the amount of ready data in the input circular buffer and increase its available space, and at the same time increase the amount of ready data in the output circular buffer and reduce its available space.

6. The method according to claim 4, characterized in that By determining whether the instruction needs to be written back to the DRAM, a circular buffer operation rule is configured for the instruction in the processing unit that performs the write operation, including: If the confirmed operation instruction requires data to be written back to DRAM, a circular buffer read operation is inserted into the intermediate representation of the processing unit assigned to the write operation: first, wait for the amount of ready data in the circular buffer to be greater than the amount of data required to be written back by the operation; then write the data back to DRAM; finally, increase the available space of the circular buffer and reduce its ready data amount.

7. The method according to claim 1, characterized in that Based on the intermediate representation corresponding to the operation instructions assigned to each processing unit, an executable file containing codes for different processing units is generated, including: Call the compiler backend to compile the intermediate representation of each processing unit into the corresponding target file; Link all object files to generate the final executable file.

8. A code partitioning system for heterogeneous multi-core processors, characterized in that: include: A conversion module, configured to obtain a code file and convert the code file into a unified intermediate representation; an allocation module, configured to allocate the operation instruction to a processing unit based on a type of the operation instruction in the intermediate representation; The compiling module is used to generate executable files containing codes for different processing units based on the intermediate representation corresponding to the operation instructions allocated to each processing unit.

9. A code partitioning device for heterogeneous multi-core processors, characterized in that: include: A memory for storing a code partitioning program for a heterogeneous multi-core processor; A processor, configured to implement the steps of the code partitioning method for a heterogeneous multi-core processor as described in any one of claims 1 to 7 when executing the code partitioning program for a heterogeneous multi-core processor.

10. A computer-readable medium storing a computer program, characterized in that: The readable medium stores a code partitioning program for a heterogeneous multi-core processor, and when the code partitioning program for a heterogeneous multi-core processor is executed by a processor, the steps of the code partitioning method for a heterogeneous multi-core processor as described in any one of claims 1 to 7 are implemented.

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