Display pixel circuit and display device thereof

Abstract

The invention relates to a display pixel circuit. The display pixel circuit comprises a light-emitting element; the pulse width modulation module is configured to at least receive a reference signal and a display signal and output a PWM signal; the pulse width modulation module comprises a first capacitor (112, 215 or 315); a first transistor (111, 211 or 311) and a second transistor (113, 213 or 312); a second capacitor (115, 218, or 317); the pulse amplitude modulation module is configured to provide light emitting current for the light emitting element; the pulse amplitude modulation module comprises a third transistor (121, 221 or 321); wherein the first transistor and the third transistor are double-gate transistors. The invention further relates to a display device which comprises the display pixel circuit.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to a display pixel circuit and a display device thereof. Background Art

[0002] Emerging miniaturized LED display technologies are attracting considerable attention. Mini-LED and Micro-LED, for example, are different forms of miniaturized LED displays. Traditional display driver technologies are no longer applicable to miniaturized LED displays. These smaller, miniaturized light-emitting elements experience luminous efficiency degradation and wavelength shift when operating in low-current mode. Therefore, it is necessary to vary the duration of the drive current flowing through the miniaturized LED to control the display grayscale, rather than adjusting the LED drive current as with traditional drive methods. This current pulse width modulation ensures that the light-emitting device always operates at the current with the highest luminous efficiency, thereby maintaining a low overall power consumption for the LED and its driver system.

[0003] Existing pulse-width modulation pixel circuits, after writing the display signal to the pixel, use the comparison result between the display signal and a reference signal as a PWM signal with different duty cycles to convert the display signal from amplitude to duty cycle. (The duty cycle of the PWM signal affects the light-emitting duration of the light-emitting element.) Due to the delay effect of parasitic resistance and capacitance in the signal lines, the reference signal received by the pixel circuit is distorted on the display driver backplane, resulting in differences in the reference signal applied to different pixels. Pixels farthest from the reference signal generation circuit, in particular, receive signals that have undergone significant distortion, which affects pixel driving accuracy. Furthermore, the device characteristics of the driver transistors and switch transistors in the pixel circuit vary over time, or due to panel unevenness, affecting the light-emitting effect. To achieve internal compensation for the threshold voltages of the two transistors, additional transistors and signal lines are typically required, significantly increasing the complexity of the pixel circuit and making it difficult to meet the requirements of high resolution and high yield. Furthermore, the increase in the number of switches in the pixel circuit also significantly increases heat dissipation. Summary of the Invention

[0004] In response to the technical problems existing in the prior art, the present application proposes a display pixel circuit, comprising: a light-emitting element; a pulse width modulation module, configured to receive at least a reference signal and a display signal, and output a PWM signal; the pulse width modulation module comprises a first capacitor (112, 215 or 315); a first transistor (111, 211 or 311), a first electrode of which receives an initialization signal, a first control electrode of which is coupled to a first end of the first capacitor (112, 215 or 315), a second control electrode of which is configured to receive the reference signal, and a second electrode of which is coupled to an output end of the pulse amplitude modulation module; and a second transistor (113, 213 or 312), a first electrode of which is configured to receive the display signal, and a control electrode of which is configured to receive the reference signal. Receive a first scanning signal, the second electrode of which is coupled to the first end or the second end of the first capacitor (112, 215 or 315); a second capacitor (115, 218 or 317), the first end of which is coupled to the second electrode of the first transistor (111, 211 or 311), the second end of which receives a low level; a pulse amplitude modulation module, configured to provide a light-emitting current to the light-emitting element; the pulse amplitude modulation module includes a third transistor (121, 221 or 321), the first control electrode of which is coupled to the pulse width modulation module, the first electrode of which is coupled to a power supply through the light-emitting element, the second control electrode of which is configured to receive a control signal VB, and the second electrode of which is configured to receive a low level; wherein the first transistor and the third transistor are dual-gate transistors.

[0005] In particular, the display pixel circuit, wherein the first control electrode of the second transistor (113) is coupled to its second control electrode and configured to receive a first scanning signal, the first electrode is configured to receive a display signal or an initialization value, and the second electrode is coupled to the first end of the first capacitor (112).

[0006] In particular, the display pixel circuit, wherein, in the initialization phase, the first scanning signal is valid, the display signal transmission line transmits an initialization value during at least part of the initialization phase, the initialization value is at a valid level, and the second transistor (113) is turned on and causes the first terminal potential of the first capacitor (112) to be the initialization value; the first initialization signal is valid, the first electrode potential of the first transistor (111) is the value of the first initialization signal, and the first transistor (111) is turned on.

[0007] In particular, the display pixel circuit, wherein the initialization value is less than twice the value of the first scanning signal when it is valid, and is less than the difference between the threshold voltage of the first transistor (111) and its second control electrode potential and the valid level of the first initialization signal.

[0008] Particularly, in the display pixel circuit, during the initialization phase, the time when the initialization signal is at an invalid level is earlier than the time when the first initialization signal is invalid.

[0009] In particular, the display pixel circuit, wherein, in the display signal writing phase, the first scanning signal is valid, the display signal is transmitted on the display signal transmission line, and the second transistor (113) is turned on and the potential of the first end of the second capacitor (112) is the value of the display signal; the first initialization signal is invalid, the potential of the first electrode of the first transistor (111) is the value of the first initialization signal, the reference signal received by the second control electrode of the first transistor (111) is a low level, and the first transistor (111) is turned off; and the value of the display signal is less than the difference between the threshold voltage of the first transistor (111) and the potential of the reference signal of its second control electrode and the value when the first initialization signal is invalid.

[0010] In particular, the display pixel circuit, wherein the first control electrode of the second transistor (213 or 312) is coupled to its second control electrode and receives a second scanning signal, the first electrode is configured to receive the display signal, and the second electrode is coupled to the second end of the first capacitor (215 or 315).

[0011] In particular, the display pixel circuit, wherein the pulse width modulation module further includes a fourth transistor (217 or 316), the first control electrode of which is coupled to its second control electrode and receives the second scanning signal, the first electrode is coupled to the second electrode of the first transistor (211 or 311), and the second electrode is coupled between the first control electrode of the first transistor (211 or 311) and the first capacitor (215 or 315); and a fifth transistor (212 or 313), the first control electrode of the fifth transistor (212 or 313) is coupled to its second control electrode and receives the third scanning signal, the first electrode is configured to receive the second initialization signal, and the second electrode is coupled to the second end of the first capacitor (215 or 315).

[0012] In particular, the display pixel circuit, wherein the pulse amplitude modulation module further includes: a sixth transistor (323) and a seventh transistor (322) connected in series, the first control electrode of the sixth transistor (323) being coupled to its second control electrode and receiving the second scanning signal, the first electrode receiving the bias current, and the second electrode being coupled to the first electrode of the seventh transistor (322); the first control electrode of the seventh transistor (322) being coupled to its second control electrode and receiving the second scanning signal, and the second electrode being coupled to the first control electrode of the third transistor (321); and an eighth transistor (325), the first control electrode being coupled to the second control electrode and configured to receive a light-emitting control signal, the first electrode being coupled to the light-emitting element, and the second electrode being coupled to the first electrode of the third transistor (321); and a third capacitor (326), the first end of which is coupled to the first control electrode of the third transistor (321), and the second end of which is configured to receive a low level.

[0013] In particular, the display pixel circuit, wherein, in the initialization stage, the third scanning signal and the second initialization signal are valid, the fifth transistor (212 or 313) is turned on, and the second terminal potential of the first capacitor (215 or 315) is made to be the value of the second initialization signal; the first initialization signal is valid, the value of the second initialization signal is higher than the value of the first initialization signal, the first transistor (211 or 311) is turned on, and the first control electrode potential of the third transistor (221 or 321) is the value of the first initialization signal.

[0014] In particular, the display pixel circuit, wherein, in the display signal writing stage, when the second scanning signal is valid, the second transistor (213 or 312) and the fourth transistor (217 or 316) are turned on, and the second end of the first capacitor (215 or 315) is the display signal; and the first control electrode potential of the first transistor (211 or 311) is the sum of the value when the first initialization signal is valid and the threshold voltage of the first transistor.

[0015] In particular, the display pixel circuit, wherein, in the display signal writing stage, when the second scanning signal is invalid and the third scanning signal is valid, the fifth transistor (212 or 313) is turned on, the second initialization signal is invalid, the second end of the first capacitor (215 or 315) is the value of the second initialization signal, and the first end of the first capacitor (215 or 315) is the sum of the value when the first initialization signal is valid and the threshold voltage of the first transistor (211 or 311) and the difference with the display signal.

[0016] In particular, in the display pixel circuit, the first control electrode of the third transistor (121 or 221) receives a control voltage.

[0017] In particular, in the display pixel circuit, during the initialization stage and the display signal writing stage, the control signal is invalid, and the sum of the value of the control signal when it is invalid and the value of the first initialization signal when it is valid is less than the threshold voltage of the third transistor (121 or 221).

[0018] In particular, in the display pixel circuit, in the light-emitting stage, the control signal is valid, the sum of the value of the control signal when it is valid and the value of the first initialization signal when it is valid is greater than the threshold voltage of the third transistor (121 or 221), and the third transistor (121 or 221) is turned on.

[0019] In particular, in the display pixel circuit, during the light-emitting stage, the control signal is valid and the first initial signal is invalid. When the value of the reference signal and the value of the display signal change, the first transistor (111 or 211) is turned on, the first electrode potential of the first transistor (111 or 211) is the same as the second electrode potential, and the third transistor (121 or 221) is turned off.

[0020] In particular, the display pixel circuit, wherein, in the display signal writing phase, the light emitting control signal is invalid; when the second scanning signal is valid, the sixth transistor (323) and the seventh transistor (322) are turned on, and the potential of the first end of the third capacitor (326) is related to the threshold voltage and bias current of the first transistor (321).

[0021] The present application also relates to a display device comprising a display pixel array of M rows and N columns, a gate driving circuit and a data driving circuit coupled to the display pixel array, wherein the display pixel array comprises any of the display pixel circuits described above, wherein M and N are both integers greater than 1. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein: Figure 1A This is a schematic diagram of the structure of a miniaturized LED display pixel circuit according to one embodiment of the present application; Figure 1B yes Figure 1A The working timing diagram of the miniaturized LED pixel circuit shown; Figure 2A is a schematic diagram of a miniaturized LED display pixel circuit structure according to another embodiment of the present application; Figure 2B yes Figure 2A The working timing diagram of the miniaturized LED display pixel circuit shown; Figure 3Ais a schematic diagram of a miniaturized LED display pixel circuit structure according to another embodiment of the present application; and Figure 3B yes Figure 3A The working timing diagram of the miniaturized LED display pixel circuit shown is shown. DETAILED DESCRIPTION

[0023] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0024] In the detailed description that follows, reference may be made to the various drawings that form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Each specific embodiment of the present application is described below in sufficient detail to enable a person of ordinary skill in the art to implement the technical solutions of the present application. It should be understood that other embodiments may be utilized or that structural, logical, or electrical changes may be made to the embodiments of the present application.

[0025] Technologies, methods, and devices known to persons of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be considered part of the specification. The lines between the elements in the drawings are merely for ease of explanation, indicating that at least the elements at both ends of the line are communicating with each other, and are not intended to limit the unconnected elements from being unable to communicate. Furthermore, the number of lines between two elements is intended to indicate at least the number of signals involved in the communication between the two elements or at least the number of outputs provided, and is not intended to limit the two elements to communicating only with the signals shown in the figure.

[0026] A transistor may refer to a transistor of any structure, such as a field effect transistor (FET) or a bipolar junction transistor (BJT). When the transistor is a field effect transistor, it may be hydrogenated amorphous silicon, metal oxide, low-temperature polysilicon, organic transistor, etc., depending on the channel material. Depending on whether the carriers are electrons or holes, it can be divided into N-type transistors and P-type transistors. Its control electrode refers to the gate of the field effect transistor, the first electrode may be the drain or source of the field effect transistor, the corresponding second electrode may be the source or drain of the field effect transistor, and the control electrode or third electrode may be the gate; when the transistor is a bipolar transistor, its control electrode refers to the base of the bipolar transistor, the first electrode may be the collector or emitter of the bipolar transistor, the corresponding second electrode may be the emitter or collector of the bipolar transistor, and the control electrode or third electrode may be the base. The transistor can be manufactured using oxide semiconductors, polycrystalline silicon, amorphous silicon, organic semiconductors, NMOS / PMOS processes, or CMOS processes.

[0027] The following description uses a thin film transistor as an example, and the drain and source of the transistor in the embodiment of the present application can vary depending on the bias state of the transistor. For a thin film field effect transistor with a dual-gate structure, its first control electrode refers to the bottom gate electrode of the field effect transistor, and the second control electrode corresponds to the top gate electrode of the field effect transistor. The first electrode can be the drain or source of the field effect transistor, and the corresponding second electrode can be the source or drain of the field effect transistor. However, it cannot be considered that the present application example is limited to the application of thin film transistors. Although the transistor size, voltage and current range of the driving backplane vary greatly due to the significant differences in display application scenarios, the pulse width modulation module disclosed in the embodiment of the present application can also be implemented using complementary field effect transistor technology on a single crystal silicon substrate, or thin film transistor technology on a flexible substrate, as well as other field effect transistor technologies. Furthermore, the embodiment of the present application is based on the active array display of Micro-LED as an example, but due to the similarity of the basic display principles, the embodiment of the present application can also be applied to single crystal silicon CMOS processes and other active display arrays.

[0028] In recent years, a dual-gate oxide transistor has been proposed, which has two control electrodes. By controlling the voltages of the two control electrodes of the dual-gate oxide transistor, the coupling between the two control electrodes can be used to more effectively control the channel layer, thereby providing more precise current control. In the pixel circuit, the compensation error increases with the increase in the change in the threshold voltage of the driving tube, while the stability of the dual-gate transistor is higher than that of the single-gate transistor, and no additional process steps are required. In addition, compared with conventional transistors, it adds a controllable gate, which is equivalent to being able to adjust the threshold voltage of the transistor, greatly increasing the flexibility of circuit design. The dual-gate oxide transistor can be turned on under the joint action of its first control electrode and the second control electrode, and its threshold voltage change is linearly related to the potential change on its second control electrode, and decreases with the increase of the potential on the second control electrode.

[0029] The present application proposes a display pixel circuit that not only has a streamlined structure but also significantly reduces thermal power consumption within the pixel, can reduce the load of the reference signal, and has good compensation characteristics to compensate for the effects of transistor threshold voltage drift and other factors on the possible uneven characteristics of the display pixel circuit.

[0030] The transistors in the pixel circuit proposed in this application are not limited to n-type dual-gate TFTs. Based on the similarity of basic display principles, the pixel circuit disclosed in this application can be applied to applications with dual-gate structures such as LTPO, single-crystal silicon CMOS processes, and other active display arrays.

[0031] In existing display devices, the reference signals applied to different pixels can vary due to parasitic resistance and capacitance on signal lines. Pixels farthest from the reference signal generation circuit, in particular, receive severely distorted reference signals, impacting pixel drive accuracy. Furthermore, in the pixel circuit, the reference signal is first applied to one end of a capacitor and then coupled to the other end using capacitive coupling. This design increases the reference signal's load.

[0032] Figure 1A This is a schematic diagram of the structure of a miniaturized LED display pixel circuit according to an embodiment of the present application.

[0033] According to one embodiment, Figure 1A As shown, the pixel circuit 100 may include a pulse width modulation module 110, a pulse amplitude modulation module 120, and a light-emitting element 130. The pulse width modulation module 110 is configured to receive at least a reference signal and a display signal and output a PWM signal. The pulse amplitude modulation module 120 receives the PWM signal output by the pulse width modulation module 110 and provides a driving current to the light-emitting element 130.

[0034] In one embodiment, the pulse width modulation module 110 receives, at different times during operation, a scan signal SCAN1[n], an initialization value VINI or a display signal DATA[j], a reference signal SWEEP, and an initialization signal REF. The reference signal SWEEP, the initialization signal REF, and the control voltage VB are global signals, and the scan signal SCAN1[n] is a progressive scan signal.

[0035] According to one embodiment, the display signal DATA[j] may include, for example, a voltage value corresponding to the value of the display data. In a typical embodiment of the present application, the display signal DATA[j] has a value range of -5V to 0V, the reference signal SWEEP has a value range of 0V to 5V, and the threshold voltage of the transistor 111 is 0.5V.

[0036] According to one embodiment, during the initialization phase of the pixel circuit, the initialization signal REF is at a high level VON. During the display signal writing and threshold voltage compensation phases and the light-emitting phase of the pixel circuit, the initialization signal REF is at a low level VOFF. According to one embodiment, during the light-emitting phase of the pixel array, the voltage value of the reference signal SWEEP gradually increases over time.

[0037] According to one embodiment, the pulse width modulation module 110 includes a main switching transistor 111 and a capacitor 112. A first control electrode of the main switching transistor 111 is coupled to a first terminal (point B) of the capacitor 112. A second control electrode receives a reference signal SWEEP. A first electrode receives an initialization signal REF. A second electrode serves as an output terminal (point A) of the pulse width modulation module 110. A second terminal of the capacitor 112 receives a low voltage level VSS.

[0038] In the display pixel circuit proposed in this application, the reference signal is directly applied to the second control electrode of the main switch transistor. The load of the reference signal in the pixel circuit is only the gate capacitance of the second control electrode of the main switch transistor, thereby reducing the load of the reference signal.

[0039] According to one embodiment, the pulse width modulation module 110 further includes a transistor 113, whose first control electrode receives the scan signal SCAN1[n] and is coupled to its second control electrode. The first electrode receives the initialization value VINI or the display signal DATA[j], and the second electrode is coupled between the first control electrode of the main switching transistor 111 and the first end of the capacitor 112. According to one embodiment, the pulse width modulation module 110 further includes a capacitor 115, whose first end is coupled to the second end of the main switching transistor 111 and the second end receives the low level VSS.

[0040] According to one embodiment, the high level VH of the scan signal SCAN1[n] satisfies VINI<2VH, which can multiply the driving capability of the transistor 113 .

[0041] In one embodiment of the present application, the display signal transmission line coupled to the first electrode of the transistor 113 transmits the initialization value VINI during at least part of the initialization phase of the pixel circuit, and transmits the display signal DATA[j] during the display signal writing and threshold voltage compensation phase of the pixel circuit.

[0042] According to one embodiment, during the initialization phase of the pixel circuit, the potential at point B is an initialization value VINI. The first initialization signal received by the first electrode of the main switching transistor 111 is at a high level VON. The reference signal SWEEP applied to the second control electrode of the main switching transistor 111 is at a low level VLOW. The initialization value VINI applied to the first control electrode of the main switching transistor 111 is VINI. The higher initialization value VINI can drive the main switching transistor 111 to conduct and transmit the higher high level VON of the initialization signal REF to point A. According to one embodiment, the initialization value VINI should satisfy VINI < Vtht1 - VLOW - VON, where Vtht1 is the threshold voltage of the transistor 111.

[0043] According to one embodiment, the value transmitted on the display signal transmission line changes from the initialization value VINI to the low level 0 before the initialization signal REF jumps to the low level, thereby avoiding the influence of the potential change of the initialization signal REF on point A.

[0044] According to one embodiment, during the light-emitting phase, the initialization signal REF received by the first electrode of the main switching transistor 111 is at a low level, VOFF. As the reference signal SWEEP applied to the second control electrode of the main switching transistor 111 gradually increases in level, the threshold voltage of the main switching transistor 111 gradually decreases. For display signals corresponding to intermediate grayscales, when the sum of the potentials at the first and second control electrodes of the main switching transistor 111 exceeds its threshold voltage, Vtht1, the main switching transistor 111 is turned on under the coordinated control of the first and second control electrodes, and the potential at point A decreases.

[0045] According to one embodiment, the pixel circuit 100 further includes a light emitting element 130 . A first electrode of the light emitting element 130 receives a high level VDD, and a second electrode thereof is coupled to the pulse amplitude modulation module 120 .

[0046] According to an embodiment, the pulse amplitude modulation module 120 in the pixel circuit 100 includes a main driving transistor 121 that controls the magnitude of the current flowing through the light-emitting element 130 and terminates the light emission of the light-emitting element 130. The first control electrode of the main driving transistor 121 receives a control voltage VB. The second control electrode of the main driving transistor 121 is coupled to the output terminal of the pulse width modulation module 110 to receive a PWM signal and controls the turn-off of the main driving transistor 221. The current flowing through the main driving transistor 121 is jointly determined by the potentials applied to its first control electrode and second control electrode. The first pole of the main driving transistor 121 is coupled to the second pole of the light-emitting element 130, and its second pole receives a low level VSS. By regulating the value of the control voltage VB, the magnitude of the light-emitting current I flowing through the light-emitting element is controlled. LED of the light-emitting element.

[0047] According to an embodiment, within one frame, during the initialization of the pixel circuit and the display signal writing and threshold voltage compensation phase, the control voltage VB can be a low level VBL. When the potential applied to the second control electrode of the main driving transistor 121 is the high level VON of the first initialization signal, VBL satisfies VBL + VON < Vtht2, and the main driving transistor 121 is turned off, where Vtht2 is the threshold voltage of the main driving transistor 121. During the light-emitting phase of the pixel circuit, the control voltage VB is a high level VBH, and the duration of the high level is the longest light-emitting time within one frame.

[0048] In a typical embodiment of the present application, the value of the high level VBH of the control voltage VB is 5 V, and the value of the high level VON of the initialization signal REF is 3 V.

[0049] In an embodiment of the present application, the display signal DATA[j] satisfies the expression Vtht1 + k1 * DATA[j] + k2 * VSWEEP > VREF (1) where k1 and k2 are the modulation coefficients of the voltages applied to the first control electrode and the second control electrode of the main switching transistor 111 with respect to its threshold voltage, respectively. VSWEEP is the value of the reference signal SWEEP. VREF is the value of the initialization signal REF, whose high level value is VON and low level value is VOFF. According to an embodiment, during the light-emitting phase, the value of the initialization signal REF is the low level VOFF, k1 and k2 are ideal values of -1, and the display signal DATA[j] should satisfy DATA[j] < Vtht1 - VSWEEP - VOFF.

[0050] In one embodiment, when the display signal DATA[j] reaches its maximum value, the corresponding grayscale is 0. When the control signal VB transitions to a high level, the potential at the first control electrode of the main switching transistor 111 is equal to the value of the display signal DATA[j]. The reference signal SWEEP applied to the second control electrode of the main switching transistor 111 is at a low level VLOW. The main switching transistor 111 is turned on, and the light-emitting element does not emit light. In this case, the display signal DATA[j] satisfies DATA[j] > Vtht1 - VLOW - VOFF.

[0051] In one embodiment, when the display signal DATA[j] is at its minimum value, the corresponding grayscale is the highest. When the control signal VB is high, the potential at the first control electrode of the main switching transistor 111 is equal to the value of the display signal DATA[j]. When the reference signal SWEEP applied to the second control electrode of the main switching transistor 111 rises from a low potential VLOW to a maximum value VHIGH, the main switching transistor 111 is always off. In this case, the display signal DATA[j] satisfies DATA[j] < Vtht1 - VHIGH - VOFF.

[0052] According to one embodiment of the present application, when the main driving transistor 121 is turned on, the light emitting current I flowing through the light emitting element 130 controlled by the main driving transistor 121 is LED Size (2) in, , Cox, W, and L are respectively the effective mobility, unit area gate dielectric layer capacitance, channel width, and channel length of the main driving transistor 121.

[0053] According to one embodiment, a larger capacitor 115 facilitates the stability of the light-emitting current flowing through the light-emitting element 130 within a frame. A larger capacitor 112 facilitates improved accuracy in writing the display signal DATA[j], enabling the capacitor 112 to withstand larger display signals. The size of the main driver transistor 121 is related to the magnitude of the light-emitting current flowing through the light-emitting element.

[0054] In one embodiment, the main switching transistor 111 , the transistor 113 , and the main driving transistor 121 may be metal oxide TFTs having a dual-gate structure, such as a dual-gate indium gallium zinc oxide (IGZO) TFT.

[0055] The present application utilizes dual-gate transistors to compare the display signal with the reference signal, thereby controlling the duty cycle of the PWM output by the pulse width modulation module 110 based on the display signal DATA[j], and ultimately converting the size of the display signal into the PWM width.

[0056] The main driving tube in the pixel circuit of this embodiment not only controls the size of the constant current, but also serves as a switch tube to control the on and off of the constant current. There is no switch tube on the light-emitting device driving branch, and there is no additional cross-voltage on the light-emitting branch, thereby achieving extremely low heat loss.

[0057] This application compensates for the drift and unevenness of the threshold voltages of the main switching transistor and the main driver transistor by regulating the control voltage, reference voltage, and display signal DATA[j] received by the pixel circuit. This achieves internal compensation of transistor threshold voltages in the pixel circuit with a relatively small number of transistors. Furthermore, the main driver transistor can function as both the switching transistor and the driver transistor in the pulse amplitude modulation module, significantly reducing the number of transistors in the pixel circuit and also lowering its power consumption.

[0058] Figure 1B yes Figure 1A The following is an explanation of the driving process of the pixel circuit.

[0059] (1) Initialization phase During this phase, the reference signal SWEEP is at a low level VLOW. The scan signal SCAN1[n] is at a high level VH, transistor 113 is turned on, and the initialization value VINI is transmitted to the display signal data line. Through transistor 113, the potential at point B is set to the initialization value VINI. At this point, the high level VON of the initialization signal REF received by the first electrode of the main control transistor 111 causes the initialization value VINI applied to the first control electrode of the main switch transistor 111 to be high, turning the main switch transistor 111 on. The main switch transistor 111 transmits the value of the initialization signal REF to point A, and the potential level at point A is VON, initializing the pixel circuit and facilitating subsequent discharge.

[0060] Before the end of this phase, the value transmitted on the display signal data line jumps from the initialization value VINI to a low level of 0. At this point, transistor 113 remains on, and the low level 0 on the display signal data line is transmitted to point B, turning off the main switch transistor 111. The potential at point A remains at the VON level. Subsequently, the initialization signal REF jumps to a low level of VOFF.

[0061] At this stage, the control voltage VB received by the first control electrode of the main driving transistor 121 in the pulse amplitude modulation module 120 is always at the low level VBL, the sum of the voltages applied to the first control electrode and the second control electrode of the main driving transistor 121 is less than its threshold voltage Vtht2, and the light-emitting element 130 does not emit light.

[0062] (2) Display signal writing and threshold compensation stage The pixel circuit in row n receives scan signal SCAN1[n] at a high level (VH). The value transmitted on the display signal transmission line is display signal DATA[j]. Transistor 113 in the pulse width modulation module is turned on, and the value of display signal DATA[j] is transmitted to point B through transistor 113, thus writing the display signal to the pixel circuit.

[0063] During this process, the reference signal SWEEP is always at the low level VLOW, and the first control electrode of the main switch transistor 111 cooperates with its second control electrode to make it unable to turn on, so the main switch transistor 111 remains turned off.

[0064] In this stage, the control voltage VB received by the first control electrode of the main driving transistor 121 in the pulse amplitude modulation module 120 is still at the low level VBL, and the light-emitting element 130 does not emit light.

[0065] (3) Lighting stage The scanning signal SCAN1[n] is at a low level, and the main driving transistor 111 and the transistor 113 are turned off. The control signal VB is at a high level VBH, and the main driving transistor 121 in the pulse amplitude modulation circuit is turned on under the combined action of the control signal VB and the potential Von at point A, and the light emitting element 130 emits light with a current I LED The brightness corresponding to the size of the light begins to glow.

[0066] At the beginning of this phase, reference voltage SWEEP gradually rises from a low level VLOW and eventually reaches a high level VHIGH. Initialization signal REF is at a low level VOFF. The threshold voltage of main switching transistor 111 gradually decreases under the action of its second control electrode. When the sum of the value of reference signal SWEEP received by the first control electrode of switching transistor 111 and the value of display signal DATA[j] received by its second control electrode is greater than the threshold voltage of main switching transistor 111, main switching transistor 111 turns on. Through main switching transistor 111, the potential at point A drops to the low level VOFF of initialization signal REF, and the PWM signal output by the pulse width modulation module is at a low level.

[0067] The second control electrode of the main driving transistor 121 receives a low-level PWM signal, which is equivalent to increasing the threshold voltage of the main driving transistor 121. The control voltage VB can no longer drive the main driving transistor 121 to turn on, and the main driving transistor 121 is turned off, and the light-emitting element 130 stops emitting light.

[0068] In another embodiment of the present application, compensation circuits may be designed for the main switch transistor and the main drive transistor respectively to perform threshold voltage compensation to improve circuit functions.

[0069] Figure 2AThis is a schematic diagram of the structure of a miniaturized LED display pixel circuit according to another embodiment of the present application.

[0070] According to one embodiment, the pixel circuit 200 includes a pulse width modulation module 210 , a pulse amplitude modulation module 220 and a light emitting element 230 .

[0071] In one embodiment, the pulse width modulation module 210 receives scan signals SCAN2[n] and SCAN3[n], a display signal DATA[j], a reference signal SWEEP, an initialization signal REF, and an initialization signal REF2. The scan signals SCAN2[n] and SCAN3[n] are progressive scan signals.

[0072] According to one embodiment, the high level V1 of the initialization signal REF2 is higher than the high level VON of the initialization signal REF. The high levels VH of the scan signals SCAN2[n] and SCAN3[n] are higher than V1.

[0073] According to one embodiment, the pulse width modulation module 210 includes a main switching transistor 211 and a capacitor 215. A first electrode of the main switching transistor 211 receives an initialization signal REF, a second electrode serves as an output terminal (point A) of the pulse width modulation module 210, a first control electrode of the main switching transistor 211 is coupled to a first terminal (point B) of the capacitor 215, and a second control electrode receives a reference signal SWEEP.

[0074] According to one embodiment, pulse width modulation module 210 includes a transistor 212 and a transistor 213 connected in series. A first control electrode of transistor 212 receives scan signal SCAN3[n] and is coupled to a second control electrode thereof. A first electrode of transistor 212 receives initialization signal REF2. A first control electrode of transistor 213 receives scan signal SCAN2[n] and is coupled to a second control electrode thereof. A first electrode of transistor 213 receives display signal DATA[j]. A second electrode of transistor 212 is coupled to a second electrode of transistor 213 (point C) and is coupled to a second terminal of capacitor 215.

[0075] According to one embodiment, the scan signal SCAN3[n] and the scan signal SCAN2[n] are not at a high level at the same time.

[0076] According to one embodiment, when scan signal SCAN3[n] is high, transistor 212 turns on and transmits the value of initialization signal REF2 to point C. Due to capacitor coupling, the potential level of its first terminal is equal to the value of initialization signal REF2. Transistor 212 places main switch transistor 211 in a suitable initial state, facilitating discharge during subsequent operation.

[0077] According to one embodiment, when the scan signal SCAN2[n] is at a high level, the transistor 213 is turned on and transmits the value of the display signal DATA[j] to point C, writing the display signal into the pixel circuit.

[0078] According to one embodiment, the pulse width modulation module 210 further includes a transistor 217, wherein a first control electrode of the transistor 217 is coupled to a second control electrode thereof and receives a scan signal SCAN2[n], a first electrode of the transistor 217 is coupled to the second electrode of the main switch transistor 211, and a second electrode of the transistor 217 is coupled between the first control electrode of the main switch transistor 211 and the first end of the capacitor 215.

[0079] According to one embodiment, when scan signal SCAN2[n] is at a high level VH, transistor 217 is turned on. Transistor 217 is configured to form a diode connection with main switch transistor 211, thereby extracting the threshold voltage Vtht3 of main switch transistor 211. In this case, the potentials at points A and B both contain the threshold voltage Vtht3 of main switch transistor 211. Regardless of how the threshold voltage of the main switch transistor varies, the potential applied to the first control electrode of main switch transistor 211 and point A always contains information about the threshold voltage of the main switch transistor. Consequently, the relationship between display signal DATA[j] and the duty cycle of the PWM signal in the pixel circuit, as well as the light-emitting duration of the light-emitting element, are independent of the threshold voltage drift of main switch transistor 211.

[0080] According to one embodiment, the pulse width modulation module 210 further includes a capacitor 218 , a first terminal of which is coupled to the output terminal of the pulse width modulation module 210 , and a second terminal of which receives the low level VSS.

[0081] In one embodiment of the present application, the main switch transistor 211 of the pixel circuit is a depletion-mode transistor. In another embodiment of the present application, the main switch transistor 211 is an enhancement-mode transistor. The pixel circuit proposed in the present application is applicable to a wide range of transistor types.

[0082] According to one embodiment, the pixel circuit 200 includes a light emitting element 230 . A first electrode of the light emitting element 230 receives a high level VDD, and a second electrode thereof is coupled to the pulse amplitude modulation module 220 .

[0083] According to one embodiment, the pulse amplitude modulation module 220 includes a main driver transistor 221 that controls the current flowing through the light-emitting element 230. A first control electrode of the main driver transistor 221 receives a control voltage VB. A second control electrode of the main driver transistor 221 is coupled to the output terminal of the pulse width modulation module 210, receives a PWM signal, and controls the turning off of the main driver transistor 221. A first electrode of the main driver transistor 221 is coupled to a second electrode of the light-emitting element 130, and a second electrode of the main driver transistor 221 receives a low voltage level VSS.

[0084] In one embodiment, all transistors in the pixel circuit 200 may be TFTs having a dual-gate structure, such as dual-gate indium gallium zinc oxide (IGZO) TFTs.

[0085] According to one embodiment, when the light emitting element 230 emits light, the light emitting current flowing through the light emitting element 230 is expressed as (3) in, , Cox, W, and L are the effective mobility, gate capacitance per unit area, channel width, and channel length of the main driver transistor, respectively. Vtht3 and ΔVtht3 are the threshold voltage and threshold voltage offset of the main switching transistor 211, respectively. Vtht4 and ΔVtht4 are the threshold voltage and threshold voltage offset of the main driver transistor 221, respectively.

[0086] According to one embodiment, when the main switch transistor 211 and the main drive transistor 221 have the same structure and size, the stability of the two transistors is similar, and the threshold voltage offsets of the two transistors are consistent. When the main drive transistor 221 is turned on, the pixel circuit starts to emit light, and the threshold voltage information of the main switch transistor 211 is stored on the capacitor 215 and the capacitor 218. Therefore, the voltage applied to the first control electrode of the main drive transistor 221 includes the threshold voltage offset of the main switch transistor 211. When the threshold voltage offsets of the main switch transistor 211 and the main drive transistor 221 are the same, the magnitude of the current flowing through the light-emitting element 230 is independent of the threshold voltage offsets of the main switch transistor 211 and the main drive transistor 221. The expression for the light-emitting current is: (4) In this case, the pixel circuit realizes coordinated compensation of the threshold voltages of the main switching transistor and the main driving transistor.

[0087] Taking advantage of the structural advantages of the dual-gate transistor, the present application only uses a diode connection structure to achieve coordinated threshold voltage compensation between the main driving tube and the main switching tube, thereby reducing the impact of the threshold voltage offset on the luminous current flowing through the light-emitting element and achieving high-stability and high-resolution display.

[0088] Figure 2B yes Figure 2A The following is an explanation of the driving process of the pixel circuit.

[0089] (1) Initialization phase During this phase, the scan signal SCAN3[n] is at a high level VH, the initialization signal REF is at a high level VON, the initialization signal REF2 is at a high level V1, and the reference signal SWEEP and the scan signal SCAN2[n] are at a low level. At this point, transistors 213 and 217 in the pulse width modulation module are off, transistor 212 is on, and the potential at point C is at the high level V1 of the initialization signal REF2. At this point, point B is in a floating state, and the potential at point B is also at the level V1 due to the coupling effect of the capacitor. In this case, the potential level applied to the first control electrode of the main switch transistor 211 is higher than the potential level of its second control electrode. The potential V1 at point B is higher than the potential level of the initialization signal REF received by the first electrode of the main switch transistor 211, thereby driving the main switch transistor 211 to conduct, and the high level VON of the initialization signal REF is transmitted to point A through the main switch transistor 211.

[0090] In the pulse amplitude modulation module 220 , the control signal VB received by the first control electrode of the main driving transistor 221 is at a low level VBL, the main driving transistor 221 is turned off, and the light emitting element 230 does not emit light.

[0091] (2) Display signal writing and threshold voltage compensation stage At this stage, the initialization signal REF2 received by the pixel circuit in the nth row is at a low level VOFF, and the initialization signal REF is at a high level VON. At the beginning of this stage, the scan signal SCAN3[n] is at a low level VL, and the scan signal SCAN2[n] is at a high level VH. The transistors 213 and 217 in the pulse width modulation module 210 are turned on, and the transistor 212 is turned off. The transistor 213 transmits the value of the display signal DATA[j] to point C. At the same time, the main switch transistor 211 forms a diode connection, and point B begins to discharge through the main switch transistor 211 and transistor 217 until the potential of point B reaches VON+Vtht3. At this time, the potentials of points A and B are the same. In this case, the pixel circuit completes the display signal writing and threshold voltage compensation.

[0092] Afterwards, scan signal SCAN2[n] transitions to a low level (VL), and scan signal SCAN3[n] transitions to a high level (VH). In the pulse width modulation module, transistors 213 and 217 are turned off, while transistor 212 is turned on. The potential at point C is the low level (VOFF) of initialization signal REF2. Through capacitive coupling, the potential at point B is coupled to VON + Vtht3 - VDATA. In this case, the potential applied to the first control electrode of main switching transistor 211 includes its threshold voltage and the value of display signal DATA[j].

[0093] In the pulse amplitude modulation module 220 , the control signal VB applied to the first control electrode of the main driving transistor 221 is still at the low level VBL, the main driving transistor 221 is turned off, and the light emitting element does not emit light.

[0094] In the pixel circuit, at this stage, all row pixel circuits complete display signal writing and threshold voltage compensation row by row.

[0095] (3) Lighting stage In this stage, the control voltage VB is at a high level VBH, the main driving transistor 221 in the pulse amplitude modulation module is turned on under the control of the potential at point A and the control voltage VB, and the light emitting element 130 starts to emit light.

[0096] The reference voltage SWEEP gradually rises from the low level at the beginning of this phase and eventually reaches the high level VHIGH. The initialization signal REF and the initialization signal REF2 are at the low level VOFF. The value of the reference signal SWEEP applied to the first control electrode of the main switch transistor 211 works together with the potential at point B to turn on the main switch transistor 211, and discharge point A to the low level VOFF through the main switch transistor 211. In this case, the main drive transistor 221 is turned off, and the light-emitting element 230 stops emitting light. Prior to this, the light-emitting unit continues to emit light at a current I LED The brightness of the light corresponds to the size.

[0097] Figure 3A This is a schematic diagram of the structure of a miniaturized LED display pixel circuit according to another embodiment of the present application.

[0098] According to one embodiment, the pixel circuit 300 includes a pulse width modulation module 310 , a pulse amplitude modulation module 320 and a light emitting element 330 .

[0099] According to one embodiment, pixel circuit 300 includes a pulse width modulation module 310, a pulse amplitude modulation module 320, and a light-emitting element 330. In one embodiment, pulse width modulation module 210 receives scan signals SCAN2[n] and SCAN3[n], display signal DATA[j], reference signal SWEEP, initialization signal REF, and initialization signal REF2. Scan signals SCAN2[n] and SCAN3[n] are progressive scan signals. Pulse amplitude modulation module 320 receives a light-emitting control signal EM, whose high-level duration is the maximum light-emitting time within a frame.

[0100] According to one embodiment, the pulse width modulation module 310 includes a main switching transistor 311 and a capacitor 315. A first electrode of the main switching transistor 311 receives an initialization signal REF, a second electrode serves as an output terminal (point A) of the pulse width modulation module 310, a first control electrode of the main switching transistor 311 is coupled to a first terminal (point B) of the capacitor 315, and a second control electrode receives a reference signal SWEEP.

[0101] According to one embodiment, pulse width modulation module 310 includes a transistor 312 and a transistor 313 connected in series. A first control electrode of transistor 312 receives scan signal SCAN2[n] and is coupled to a second control electrode thereof. A first electrode of transistor 312 receives display signal DATA[j]. A first control electrode of transistor 313 receives scan signal SCAN3[n] and is coupled to a second control electrode thereof. A first electrode of transistor 313 receives initialization signal REF2. A second electrode of transistor 312 is coupled to a second electrode of transistor 313 (point C) and is coupled to a second terminal of capacitor 315.

[0102] According to one embodiment, the pulse width modulation module 310 further includes a transistor 316. A first control electrode of the transistor 316 is coupled to a second control electrode thereof and receives a scan signal SCAN2[n]. A first electrode of the transistor 316 is coupled to the second electrode of the main switch transistor 311, and a second electrode is coupled between the first control electrode of the main switch transistor 311 and the first end of the capacitor 315. According to one embodiment, the pulse width modulation module 310 further includes a capacitor 317. A first end of the capacitor 317 is coupled to the output end of the pulse width modulation module 310, and a second end receives a low voltage level VSS.

[0103] According to one embodiment, the scan signal SCAN2[n] and the scan signal SCAN3[n] are not at a high level at the same time.

[0104] According to one embodiment, during the initialization phase, when scan signal SCAN3[n] is at a high level VH and scan signal SCAN2[n] is at a low level, transistor 313 is turned on, while transistors 312 and 316 are turned off. Transistor 313 transmits the value of initialization signal REF2 to point C and, through capacitive coupling, sets the potential of the first control electrode of main switch transistor 311 to the value of initialization signal REF2. Transistor 313 places main switch transistor 311 in a suitable initial state, facilitating discharge during subsequent operation.

[0105] According to one embodiment, during the display signal writing and threshold voltage compensation phase, when the scan signal SCAN2[n] is at a high level VH, the transistor 312 is turned on and transmits the value of the display signal DATA[j] to point C, writing the display signal into the pixel circuit.

[0106] According to one embodiment, when scan signal SCAN2[n] is at a high level VH, transistor 316 is turned on. Transistor 316 is configured to form a diode connection with main switch transistor 311, thereby extracting the threshold voltage of main switch transistor 311. In this case, the potentials at points A and B both contain the threshold voltage Vtht5 of main switch transistor 311. Regardless of how the threshold voltage of the main switch transistor varies, the potential applied to the first control electrode of main switch transistor 311 and point A always contains information about the threshold voltage of the main switch transistor. Consequently, the relationship between display signal DATA[j] and the duty cycle of the PWM signal in the pixel circuit, as well as the light-emitting duration of the light-emitting element, are independent of the threshold voltage drift of main switch transistor 311.

[0107] In one embodiment, the main switch transistor 311 may be a depletion-mode transistor. In another embodiment of the present application, the main switch transistor 311 is an enhancement-mode transistor.

[0108] According to one embodiment, the pixel circuit 200 includes a light-emitting element 330. A first electrode of the light-emitting element 330 receives a high voltage VDD, and a second electrode of the light-emitting element 330 is coupled to a pulse amplitude modulation module 320. According to one embodiment, the pulse amplitude modulation module 320 further includes a main driver transistor 321, as well as transistors 322 and 323. A first control electrode of the main driver transistor 321 is coupled to a second electrode of the transistor 322. A second control electrode of the main driver transistor 321 is coupled to an output terminal of the pulse width modulation module 310 and receives a PWM signal. A first electrode of the main driver transistor 321 is coupled to a first electrode of the transistor 322, and a second electrode receives a low voltage. A first electrode of the transistor 323 receives a bias current IBIAS from a bias current source (not shown), and a second electrode is coupled to a first electrode of the transistor 322. The first control electrodes of the transistor 323 and the transistor 322 are respectively coupled to their respective second control electrodes and receive a scan signal SCAN2[n].

[0109] According to one embodiment, the pulse amplitude modulation module 320 further includes a capacitor 326 , a first terminal of which is coupled between the first control electrode and the second electrode of the main driving transistor 321 , and a second terminal of which receives the low level VSS.

[0110] In one embodiment, during the display signal writing and threshold voltage compensation phase, when the scan signal SCAN2[n] is at a high level, transistors 323 and 322 are turned on, so that the main drive transistor 321 forms a diode connection. The bias current IBIAS flows to the first electrode and the first control electrode of the main drive transistor 321 through the turned-on transistors 323 and 322, and turns on the main drive transistor 321. The threshold voltage drift of the main drive transistor is compensated by the bias current, so that the transconductance of the main drive transistor in each pixel circuit in the pixel array is the same. In this case, the potential of the first end of the capacitor 326 contains information about the threshold voltage Vtht6 of the main drive transistor 321 and the bias current IBIAS. The potential V C326 It can be expressed as (5) Wherein, k is the conductivity factor of the main driving transistor 321, and IBIAS is the bias current of the external bias current source.

[0111] According to one embodiment, the pulse amplitude modulation module 320 may further include a transistor 325, whose first electrode is coupled to the second electrode of the light-emitting element 330, whose second electrode is coupled to the first electrode of the main driving transistor 321, and whose first control electrode is coupled to the second control electrode thereof and receives the light-emission control signal EM. When EM is at a low level, the transistor 325 is turned off, the pixel circuit does not emit light, and the threshold voltage extraction process of the transistor 321 is not disturbed.

[0112] According to one embodiment, when the EM signal is at a high level, the pixel circuit enters a light emitting stage.

[0113] The threshold voltage of the main switching transistor is compensated by connecting it to a diode. The pulse amplitude modulation module controls the amount of light-emitting current flowing through it by writing bias current row by row. At the same time, the potential at the first terminal of the capacitor is adjusted to include the threshold voltage of the main driving transistor, thus achieving threshold compensation for the main driving transistor.

[0114] Figure 3B yes Figure 3A The following is an explanation of the driving process of the pixel circuit.

[0115] (1) Initialization phase During this phase, scan signal SCAN3[n] is at a high level VH, initialization signal REF is at a high level VON, initialization signal REF2 is at a high level V1, reference signal SWEEP is at a low level VLOW, and scan signal SCAN2[n] is at a low level VL. In pulse width modulation module 310, transistor 313 is turned on, while transistors 312 and 316 are turned off. The high level V1 of initialization signal REF2 is transmitted to point C via transistor 313. At this point, point B is floating. Capacitive coupling causes the potential at point B to reach V1, driving main switch transistor 311 to conduct. The high level VON of initialization signal REF is transmitted to point A.

[0116] The light emitting control signal EM received by the pulse amplitude modulation module 320 is at a low level VL, the transistor 325 is turned off, and the transistors 322 and 323 are turned off under the control of the scan signal SCAN2[n], and the light emitting element 330 does not emit light.

[0117] (2) Display signal writing and threshold voltage compensation stage During this phase, the initialization signal REF2 is at a low level (VOFF), the scan signal SCAN3[n] is at a low level (VL), and the scan signal SCAN2[n] is at a high level (VH). Transistors 312 and 316 in the pulse width modulation module 310 are turned on, while transistor 313 is turned off. The display signal DATA[j] is written into the pixel circuit. The potential at point C is the level of the display signal DATA[j]. The main switching transistor 311 forms a diode connection, causing the potential at point B to reach the level of Von + Vtht5, where Vtht5 is the threshold voltage of the main switching transistor 311.

[0118] In the pulse amplitude modulation module 320, transistors 322 and 323 are turned on under the control of the scan signal SCAN2[n], the main driving transistor 321 forms a diode connection, and the bias current IBIAS is applied to the first control electrode and the first electrode of the main driving transistor 321 to drive the main driving transistor 321 to be turned on, so that the potential of the first end of the capacitor 326 includes the threshold voltage Vtht6 of the main driving transistor 321 and the bias current IBIAS.

[0119] Afterwards, scan signal SCAN2[n] transitions to a low level (VL), and scan signal SCAN3[n] transitions to a high level (VH). In pulse width modulation module 310, transistors 312 and 316 are turned off, while transistor 313 is turned on. The potential at point C is the low level (VOFF) of initialization signal REF2. Through capacitive coupling, the potential at point B is coupled to VON + Vtht5 - DATA[j]. At this point, the potential applied to the first control electrode of main switching transistor 311 includes its threshold voltage and the value of display signal DATA[j]. In pulse amplitude modulation module 320, transistors 322 and 323 are turned off under control of scan signal SCAN2[n].

[0120] The light emitting control signal EM is still at the low level VL, the transistor 325 in the pulse amplitude modulation module 320 is turned off, and the light emitting element 330 does not emit light.

[0121] (3) Lighting stage During this phase, the emission control signal EM is at a high level VH, turning on transistor 325 in the pulse amplitude modulation module. The scan signal SCAN2[n] is at a low level, turning off transistors 322 and 323. The main driver transistor 321 is turned on by the combined action of the potential at point A and the potential at the first terminal of capacitor 326, causing the light-emitting element 330 to begin emitting light.

[0122] Initialization signal REF2 is at a low level VOFF. The value of reference signal SWEEP at the first control electrode of main switching transistor 311 in pulse width modulation module 310 gradually increases from a low level VLow. This, in conjunction with the potential at point B, turns on main switching transistor 311. At this point, point A discharges through main switching transistor 311, and the PWM signal output by pulse width modulation module 316 is at a low level.

[0123] Under the control of the PWM signal, the pulse amplitude modulation module 320 turns off the main driving transistor 321 and the light emitting element 330 stops emitting light.

[0124] The threshold compensation method of the main switching transistor and the main driving transistor in the pixel circuit proposed in this application is not limited to voltage compensation, current compensation or other forms of implementation, and can control the light-emitting duration of the pixel circuit with high precision and high stability.

[0125] This application leverages the advantages of dual-gate transistors. The pixel circuit writes a reference signal into one of the gates of the dual-gate device, significantly reducing the reference signal load and improving the control accuracy of pixel driving at different positions on the panel. The proposed pixel circuit has a streamlined structure and low heat loss within the pixel circuit. The pixel circuit also incorporates transistor threshold voltage compensation, enabling precise modulation of the light emission duration and improving display quality.

[0126] The present application also provides a display device comprising a Micro-LED display pixel array having M rows and N columns, and a gate driver circuit and a data driver circuit coupled to the display pixel array. The display pixel array comprises any of the display pixel circuits described above, wherein M and N are both integers greater than 1.

[0127] The above embodiments are only used to illustrate the present application and are not intended to limit the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. A display pixel circuit, comprising: Light-emitting element; a pulse width modulation module configured to receive at least a reference signal and a display signal and output a PWM signal; The pulse width modulation module includes A first capacitor (112, 215, or 315); a first transistor (111, 211 or 311), wherein a first electrode thereof receives an initialization signal, a first control electrode thereof is coupled to a first end of a first capacitor (112, 215 or 315), a second control electrode thereof is configured to receive the reference signal, and a second electrode thereof is coupled to an output end of the pulse amplitude modulation module; as well as a second transistor (113, 213 or 312), a first electrode of which is configured to receive the display signal, a control electrode of which is configured to receive the first scanning signal, and a second electrode of which is coupled to the first end or the second end of the first capacitor (112, 215 or 315); A second capacitor (115, 218 or 317), a first end of which is coupled to the second electrode of the first transistor (111, 211 or 311), and a second end of which receives a low level; a pulse amplitude modulation module configured to provide a light-emitting current to the light-emitting element; The pulse amplitude modulation module includes a third transistor (121, 221 or 321), having a first control electrode coupled to the pulse width modulation module, a first electrode coupled to a power supply via the light-emitting element, a second control electrode configured to receive a control signal VB, and a second electrode configured to receive a low level; Wherein, the first transistor and the third transistor are dual-gate transistors.

2. The display pixel circuit according to claim 1, wherein: The first control electrode of the second transistor (113) is coupled to its second control electrode and configured to receive a first scan signal, the first electrode is configured to receive a display signal or an initialization value, and the second electrode is coupled to the first end of the first capacitor (112).

3. The display pixel circuit according to claim 2, wherein: In the initialization phase, the first scanning signal is valid, the display signal transmission line transmits an initialization value during at least part of the initialization phase, the initialization value is a valid level, and the second transistor (113) is turned on and causes the potential of the first terminal of the first capacitor (112) to be the initialization value; The first initialization signal is valid, the first electrode potential of the first transistor (111) is the value of the first initialization signal, and the first transistor (111) is turned on.

4. The display pixel circuit according to claim 3, wherein: The initialization value is less than twice the value of the first scanning signal when it is valid, and is less than the difference between the threshold voltage of the first transistor (111), the potential of its second control electrode, and the valid level of the first initialization signal.

5. The display pixel circuit according to claim 4, wherein: In the initialization phase, the time when the initialization signal is at an invalid level is earlier than the time when the first initialization signal is invalid.

6. The display pixel circuit according to claim 5, wherein: In the display signal writing phase, the first scanning signal is valid, the display signal is transmitted on the display signal transmission line, and the second transistor (113) is turned on and the potential of the first end of the second capacitor (112) is the value of the display signal; The first initialization signal fails, the potential of the first electrode of the first transistor (111) is the value of the first initialization signal, the reference signal received by the second control electrode of the first transistor (111) is at a low level, and the first transistor (111) is turned off; as well as The value of the display signal is smaller than the difference between the threshold voltage of the first transistor (111), the potential of the second control electrode reference signal thereof, and the value when the first initialization signal fails.

7. The display pixel circuit according to claim 1, wherein: The first control electrode of the second transistor (213 or 312) is coupled to its second control electrode and receives a second scan signal. The first electrode is configured to receive the display signal, and the second electrode is coupled to the second end of the first capacitor (215 or 315).

8. The display pixel circuit according to claim 7, wherein: The pulse width modulation module further includes a fourth transistor (217 or 316), a first control electrode coupled to its second control electrode and receiving the second scanning signal, a first electrode coupled to the second electrode of the first transistor (211 or 311), and a second electrode coupled between the first control electrode of the first transistor (211 or 311) and the first capacitor (215 or 315); as well as A fifth transistor (212 or 313), wherein the first control electrode of the fifth transistor (212 or 313) is coupled to its second control electrode and receives the third scan signal, the first electrode is configured to receive the second initialization signal, and the second electrode is coupled to the second end of the first capacitor (215 or 315).

9. The display pixel circuit according to claim 8, wherein: The pulse amplitude modulation module also includes: a sixth transistor (323) and a seventh transistor (322) connected in series, wherein the first control electrode of the sixth transistor (323) is coupled to its second control electrode and receives the second scanning signal, the first electrode receives a bias current, and the second electrode is coupled to the first electrode of the seventh transistor (322); the first control electrode of the seventh transistor (322) is coupled to its second control electrode and receives the second scanning signal, and the second electrode is coupled to the first control electrode of the third transistor (321); and an eighth transistor (325), wherein the first control electrode and the second control electrode are coupled to each other and configured to receive a light emitting control signal, the first electrode of the eighth transistor (325) being coupled to the light emitting element, and the second electrode of the eighth transistor (325) being coupled to the first electrode of the third transistor (321); The third capacitor (326) has a first end coupled to the first control electrode of the third transistor (321), and a second end configured to receive a low level.

10. The display pixel circuit according to claim 8, wherein: During the initialization phase, The third scanning signal and the second initialization signal are valid, the fifth transistor (212 or 313) is turned on, and the second terminal potential of the first capacitor (215 or 315) is the value of the second initialization signal; the first initialization signal is valid, the value of the second initialization signal is higher than the value of the first initialization signal, the first transistor (211 or 311) is turned on, and the first control electrode potential of the third transistor (221 or 321) is the value of the first initialization signal.

11. The display pixel circuit according to claim 10, wherein: During the display signal writing phase, When the second scanning signal is valid, the second transistor (213 or 312) and the fourth transistor (217 or 316) are turned on, and the second end of the first capacitor (215 or 315) is a display signal; and the first control electrode potential of the first transistor (211 or 311) is the sum of the value when the first initialization signal is valid and the threshold voltage of the first transistor.

12. The display pixel circuit according to claim 11, wherein: During the display signal writing phase, When the second scanning signal is invalid and the third scanning signal is valid, the fifth transistor (212 or 313) is turned on, the second initialization signal is invalid, the second end of the first capacitor (215 or 315) is the value of the second initialization signal, and the first end of the first capacitor (215 or 315) is the sum of the value when the first initialization signal is valid and the threshold voltage of the first transistor (211 or 311) and the difference with the display signal.

13. The display pixel circuit according to claim 2 or 8, wherein: The first control electrode of the third transistor (121 or 221) receives a control voltage.

14. The display pixel circuit according to claim 13, wherein: During the initialization phase and the display signal writing phase, The control signal is invalid, and a sum of a value of the control signal when invalid and a value of the first initialization signal when valid is smaller than a threshold voltage of the third transistor (121 or 221).

15. The display pixel circuit according to claim 14, wherein in the light emitting phase, The control signal is valid, and the sum of the value of the control signal when valid and the value of the first initialization signal when valid is greater than the threshold voltage of the third transistor (121 or 221), and the third transistor (121 or 221) is turned on.

16. The display pixel circuit according to claim 15, wherein in the light emitting phase, The control signal is valid and the first initial signal is invalid. When the value of the reference signal and the value of the display signal change, the first transistor (111 or 211) is turned on, the first electrode potential of the first transistor (111 or 211) is the same as the second electrode potential, and the third transistor (121 or 221) is turned off.

17. The display pixel circuit according to claim 9, wherein: During the display signal writing phase, The light emitting control signal is invalid; when the second scanning signal is valid, the sixth transistor (323) and the seventh transistor (322) are turned on, and the potential of the first end of the third capacitor (326) is related to the threshold voltage and bias current of the first transistor (321).

18. A display device comprising a display pixel array having M rows and N columns, a gate driving circuit and a data driving circuit coupled to the display pixel array, the display pixel array comprising the display pixel circuit according to any one of claims 1 to 14, wherein M and N are both integers greater than 1.

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