Display panel and display device
By setting the projection spacing difference between the data lines and the active layer corresponding to the light-emitting devices of different colors in the display panel, the problem of uneven charging speed is solved, the scanning signal access period is unified, and the display effect of the display panel is improved.
Patent Information
- Application Number
- CN202510615813.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-13
- Publication Date
- 2025-09-23
AI Technical Summary
The difference in data voltage signals required by pixel circuits corresponding to light-emitting devices of different colors leads to uneven charging speeds, affecting the working timing design.
By setting the minimum distance between the orthographic projection of the first and second types of data signal lines and the orthographic projection of the active layer, adopting different technical solutions, combining the above technical solutions, and combining the above-mentioned charging speed difference problem, the projection distance between the orthographic projection of the first and second types of data signal lines and the active layer is designed, so that the difference between the charging process duration of the first type of data lines and the charging process duration of the second type of data lines is reduced, and the difference in the duration of the scanning signal access period is also reduced accordingly.
The charging speed of light-emitting devices of different colors is balanced, the working timing design is simplified, and the display effect of the display panel is improved.
Smart Images
Figure CN120690135A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art
[0002] In the prior art, the voltage of the data voltage signal received by the pixel circuit often needs to reach a target value. Therefore, before the pixel circuit receives the data voltage signal, the voltage of the data voltage signal transmitted in the data line changes from an initial value to a target value (this process can be called a charging process).
[0003] It should be noted that, based on considerations of luminous efficiency, the pixel circuits corresponding to light-emitting devices of different colors need to receive data voltage signals with different target values. For the data lines corresponding to different pixel circuits, the gaps between the above-mentioned initial values and the above-mentioned target values are different, which may easily lead to different durations of the charging processes corresponding to different data lines, and thus cause large differences in the charging speeds of different pixels. Summary of the Invention
[0004] In view of this, the present application provides a display panel and a display device to solve the above-mentioned problem of charging speed difference.
[0005] In a first aspect, the present application provides a display panel comprising a plurality of pixel circuits and a plurality of data signal lines.
[0006] The plurality of pixel circuits include a first type of pixel circuit and a second type of pixel circuit. The light-emitting devices driven by the first type of pixel circuit and the light-emitting devices driven by the second type of pixel circuit correspond to different light-emitting colors.
[0007] The plurality of data signal lines include first-type data lines and second-type data lines. During a data write phase, the first-type data lines transmit data signals to the first-type pixel circuits, and the second-type data lines transmit data signals to the second-type pixel circuits. During a data conditioning phase, the voltage variation range of the data signals transmitted by the first-type data lines is greater than the voltage variation range of the data signals transmitted by the second-type data lines. The data conditioning phase occurs before the data write phase.
[0008] The minimum distance between the orthographic projection of the first type data line and the orthographic projection of the active layer of the first type pixel circuit is c1, and the minimum distance between the orthographic projection of the second type data line and the orthographic projection of the active layer of the second type pixel circuit is c2, c1>c2.
[0009] In a second aspect, the present application provides a display device, comprising the display panel provided in the first aspect.
[0010] In the present application, by setting c1>c2, the coupling capacitance corresponding to the first-class data line is reduced, thereby helping to offset the impact of the large charging voltage difference on the charging speed of the first-class data line, and helping to reduce the difference between the charging process duration of the first-class data line and the charging process duration of the second-class data line. Furthermore, it is beneficial to reduce the difference in the duration of the scanning signal access period corresponding to the first-class pixel circuit and the scanning signal access period corresponding to the second-class pixel circuit, relatively extending the appropriate period for the first scanning line to transmit the scanning signal to its first-class pixel circuit, and facilitating the operation timing design of the first-class pixel circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0012] Figure 1 Schematic diagram of voltage changes in data lines corresponding to light-emitting devices of different colors; Figure 2 is an equivalent circuit diagram of a pixel circuit related to the present application; Figure 3 A schematic diagram of a partial structure of a display panel provided in this application; Figure 4 This is a schematic diagram of voltage changes in some data signal lines in this application; Figure 5 A schematic diagram of a partial structure of a display panel provided in this application; Figure 6 A schematic diagram of a partial structure of a display panel provided in this application; Figure 7 This is a schematic diagram of voltage changes in some data signal lines in this application; Figure 8 A schematic diagram of a partial structure of a display panel provided in this application; Figure 9 A schematic diagram of a partial structure of a display panel provided in this application; Figure 10 A schematic diagram of a partial structure of a display panel provided in this application; Figure 11 A schematic diagram of a display device provided in this application. DETAILED DESCRIPTION
[0013] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.
[0014] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.
[0015] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.
[0016] It should be understood that the term "and / or" as used herein simply describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. Furthermore, the character " / " in this document generally indicates an "or" relationship between the associated objects.
[0017] In the prior art, before a pixel circuit receives a data voltage signal (for example, before the data voltage signal in the data line is written to the input terminal of the pixel driving transistor), the voltage value of the data voltage signal transmitted by the data line usually needs to go through a process of changing from an initial value to a target value (which can be called a charging process). The duration t of this charging process can be determined by the following factors: 1. The current I in the data line; 2. The voltage difference ΔV between the initial value and the target value (hereinafter referred to as the charging voltage difference); 3. The coupling capacitance C between the data line and other structures. The above factors and the duration t of the charging process can satisfy the following relationship: t = C ΔV / I.
[0018] Figure 1 Schematic diagram of voltage changes in data lines corresponding to light-emitting devices of different colors. Figure 2 is an equivalent circuit diagram of a pixel circuit related to this application; for ease of understanding, Figure 1 The figure shows how the voltage values of the electrical signals transmitted by the existing multiple data lines during the data adjustment phase change over time. The multiple curves in the figure correspond to the voltage value change curves of the blue data line (the data line corresponding to the blue light-emitting device), the red data line (the data line corresponding to the red light-emitting device), and the green data line (the data line corresponding to the green light-emitting device). Figure 1 The vertical axis in the image represents the voltage value of the electrical signal in the data line, and the horizontal axis represents time.
[0019] It should be noted that there are differences in the luminous efficiency corresponding to light-emitting devices of different colors, such as Figure 1 As shown, in the prior art, different charging voltage differences are usually set for the data lines corresponding to different color light emitting devices to improve the difference in luminous efficiency. For example, compared with other color light emitting devices, the luminous efficiency of the blue light emitting device is lower, so the target value in the blue data line corresponding to the blue light emitting device is usually smaller, so that the gate voltage of the driving transistor M0 in the pixel circuit of the blue light emitting device written in the data writing phase T1 is lower (please refer to Figure 2 , taking a P-type transistor as an example), the turn-on efficiency of the driving transistor M0 is improved, thereby improving the luminous efficiency of the blue light-emitting device.
[0020] However, considering that the current I within the data line is affected by chip performance, and that the coupling capacitors C corresponding to different data lines in existing designs are of similar size, the primary factor affecting the duration of the data line charging process is the aforementioned charging voltage difference ΔV. Therefore, the differentiated setting of the aforementioned charging voltage difference can easily lead to differences in charging duration (i.e., charging speed) between data lines (corresponding to pixel circuits of light-emitting devices of different colors).
[0021] The aforementioned charging speed difference problem is likely to affect the working timing settings of different pixel circuits, and may easily cause differences in working states between pixel circuits corresponding to light-emitting devices of different colors.
[0022] For example, see Figure 1 and Figure 2 , in the data writing stage T1, the control end of the first transistor M1 in the pixel circuit receives the scanning signal transmitted by the first scanning line S1, the first transistor M1 is turned on, and the data voltage signal in the data line O1 can be written to the input end of the driving transistor M0. Taking into account the coupling capacitance between the first scanning line S1 and other structures, in order to ensure that the first transistor M1 is turned on in time, the time point when the first scanning line S1 starts to transmit the scanning signal must be before the data writing stage T1. At the same time, in order to avoid writing the data voltage signal that does not reach the target value into the pixel circuit, it is also necessary to ensure that the time point when the first scanning line S1 starts to transmit the scanning signal is also after the data voltage signal in the data line O1 reaches the target value. Then, the time point when the first scanning line S1 starts to transmit the scanning signal can be within the scanning signal access period t0 in the figure (such as Figure 1 As shown). It should be noted that, the larger the charging voltage difference ΔV, the longer the charging process, the shorter the corresponding scanning signal access period t0, and the less conducive it is to the transmission of the scanning signal in the first scanning line S1. Figure 1As shown in the figure, the charging voltage difference ΔVc corresponding to the blue data line is the largest compared to the charging voltage difference ΔVa corresponding to the green data line and the charging voltage difference ΔVb corresponding to the red data line. Therefore, the scanning signal access period t01 corresponding to the blue light-emitting device is the shortest compared to the scanning signal access period t02 corresponding to the red light-emitting device and the scanning signal access period t03 corresponding to the green light-emitting device. Therefore, during the operation of the pixel circuit of the blue light-emitting device, the appropriate period for the first scan line S1 to transmit the scanning signal to its pixel circuit is the shortest, which is not conducive to the operation timing arrangement of the pixel circuit of the blue light-emitting device.
[0023] like Figure 2 As shown, the pixel circuit may include a driving transistor M0, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a first capacitor Cst. The pixel circuit may also be electrically connected to a first scan line S1, a second scan line S2, a third scan line S3, a data line O1, a power supply voltage signal line O2, a reset line O3, etc. The connection between the above transistors, capacitors, wiring and light emitting device 04 is detailed in Figure 2 , I will not go into details here.
[0024] Figure 3 A schematic diagram of a partial structure of a display panel provided in this application.
[0025] In response to the above problems, Figure 3 As shown, the present application provides a display panel 10, including a plurality of pixel circuits 1, wherein the plurality of pixel circuits 1 include a first type of pixel circuit 11 and a second type of pixel circuit 12. The light-emitting devices driven by the first type of pixel circuit 11 and the light-emitting devices driven by the second type of pixel circuit 12 correspond to different luminous colors. The luminous efficiency of the light-emitting devices driven by the first type of pixel circuit 11 and the luminous efficiency of the light-emitting devices driven by the second type of pixel circuit 12 may be different.
[0026] In addition, the pixel circuit 1 may include a driving transistor M0, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a first capacitor Cst. The pixel circuit may also be electrically connected to a first scan line S1, a second scan line S2, a third scan line S3, a data line O1, a power supply voltage signal line O2, a reset line O3, etc. The connection between the above transistors, capacitors, wiring, and light-emitting device 04 can be seen in FIG. Figure 2 The power supply voltage signal line 02 may include a first sub-line 021 and a second sub-line 022 electrically connected to each other, and the extension directions of the two sub-lines may cross.
[0027] Figure 4This is a schematic diagram of the voltage changes in some data signal lines in this application, for easy understanding, Figure 4 The figure shows how the voltages corresponding to the first and second data lines change with time during the data adjustment stage. The short dashed line refers to the voltage change curve of the first data line, and the solid line refers to the voltage change curve of the second data line. The vertical axis in the figure represents the voltage value of the electrical signal in the data signal line, and the horizontal axis represents time.
[0028] Combine Figure 3 and Figure 4 The display panel 10 further includes a plurality of data signal lines 01, including first-type data lines 011 and second-type data lines 012. During a data writing phase T1, the first-type data lines 011 transmit data signals to the first-type pixel circuits 11, and the second-type data lines 012 transmit data signals to the second-type pixel circuits 12. During a data adjustment phase T2, the voltage variation range of the data signals transmitted by the first-type data lines 011 is greater than the voltage variation range of the data signals transmitted by the second-type data lines 012. That is, the charging voltage difference ΔV1 of the first-type data lines 011 is greater than the charging voltage difference ΔV2 of the second-type data lines 012. The data adjustment phase T2 occurs before the data writing phase T1.
[0029] At this time, if the difference between the coupling capacitors corresponding to the first-type data lines 011 and the coupling capacitors corresponding to the second-type data lines 012, and the difference in current between the first-type data lines 011 and the second-type data lines 012, is not considered, the charging process corresponding to the first-type data lines 011 is likely to be longer than the charging process corresponding to the second-type data lines 012. Therefore, to avoid this situation, the embodiment of the present application has made the following design: Among them, such as Figure 3 As shown, the minimum spacing between the orthographic projection of the first-type data line 011 and the projection of the active layer of the first-type pixel circuit 11 is c1, wherein the first part P1 on the active layer of the first-type pixel circuit 11 is closest to the first-type data line 011, that is, the spacing between the projections corresponding to the first-type data line 011 and the first part P1 can be c1; the minimum spacing between the orthographic projection of the second-type data line 012 and the orthographic projection of the active layer of the second-type pixel circuit 12 is c2, wherein the second part P2 on the active layer of the second-type pixel circuit 12 is closest to the second-type data line 012, that is, the spacing between the projections corresponding to the second-type data line 012 and the second part P2 can be c2; c1>c2.
[0030] It should be noted that the data signal line 01 can be coupled with the active layer of the pixel circuit 1 and generate a coupling capacitance C. The larger the distance between the orthographic projection of the data signal line 01 and the orthographic projection of the active layer, the smaller the corresponding coupling capacitance C. Combined with the above-mentioned charging process time relationship t = C ΔV / I shows that, when the charging voltage difference ΔV and the current I in the data line are fixed, the smaller the capacitance of the coupling capacitor C, the shorter the charging process time t. In other words, increasing the distance between the orthographic projection of the data signal line 01 and the orthographic projection of the active layer can shorten the charging process time t corresponding to the data signal line 01. Therefore, if Figure 4 As shown, in the present application, by setting c1>c2, the coupling capacitance C corresponding to the first-type data line 011 is reduced, thereby helping to offset the impact of the large charging voltage difference ΔV1 on the charging speed of the first-type data line 011, and helping to reduce the difference between the charging process duration of the first-type data line 011 and the charging process duration of the second-type data line 012. Furthermore, it is helpful to reduce the difference in duration between the scanning signal access period ta corresponding to the first-type pixel circuit 11 and the scanning signal access period tb corresponding to the second-type pixel circuit 12, relatively extending the appropriate period for the first scanning line S1 to transmit the scanning signal to its first-type pixel circuit 11, and facilitating the operation timing design of the first-type pixel circuit 11.
[0031] In one possible implementation, Figure 4 As shown, the charging process duration of the first-type data line 011 is the same as the charging process duration of the second-type data line 012. Under this design, the duration of the scanning signal access period ta corresponding to the first-type pixel circuit 11 and the scanning signal access period tb corresponding to the second-type pixel circuit 12 can be the same, which helps to unify the design of the working timing.
[0032] In one embodiment of the present application, the light emitting color of the light emitting device corresponding to the first type of pixel circuit 11 is blue, and the light emitting color of the light emitting device corresponding to the second type of pixel circuit 12 is red or green.
[0033] It is known that the charging process duration corresponding to the blue light-emitting device is longer than the charging process duration corresponding to the green light-emitting device and the red light-emitting device respectively. The setting method of this embodiment helps to reduce the time difference between the scanning signal access period corresponding to the blue light-emitting device and the scanning signal access period corresponding to the red light-emitting device and the green light-emitting device respectively, and relatively extend the appropriate time period for the first scanning line S1 to transmit the scanning signal to the pixel circuit 1 used to drive the blue light-emitting device, thereby facilitating the working timing design.
[0034] In one embodiment of the present application, 109%≤c1 / c2≤180%.
[0035] In the embodiment of the present application, the design of 109%≤c1 / c2≤180% helps to maximize the spacing between the first-class data line 011 and the active layer, and reduce the coupling capacitance C between the first-class data line 011 and the active layer; at the same time, it is conducive to adaptively adjusting the setting position of the first-class data line 011 and maintaining the rationality of the overall layout of various structures in the display panel 10.
[0036] Figure 5 A schematic diagram of a partial structure of a display panel provided in this application.
[0037] In one embodiment of the present application, Figure 5 As shown, the orthographic projection width d1 of the first type of data line 011 is smaller than the orthographic projection width d2 of the second type of data line 012 .
[0038] As is known, the data signal line 01 can generate a coupling electric field when transmitting a data signal. When other structures within the display panel 10 are affected by this coupling electric field, coupling occurs between the data signal line 01 and the other structures. The range of influence of this coupling electric field can be related to the projected area of the data signal line 01. The smaller the projected area of the data signal line 01, the smaller the range of influence of the coupling electric field. Therefore, by setting d1 < d2 in this embodiment, it is beneficial to achieve a relatively small positive projection area of the first-class data line 011, reducing the range of influence of the coupling electric field of the first-class data line 011, and thus reducing the coupling capacitance corresponding to the first-class data line 011. This helps to improve the charging speed of the first-class data line 011 and reduce the difference in charging speed between the first-class data line 011 and the second-class data line 012.
[0039] In one embodiment of the present application, 65%≤d1 / d2≤95%.
[0040] In the embodiment of the present application, the setting of 65%≤d1 / d2≤95% helps to minimize the charging speed difference between the first-class data lines 011 and the second-class data lines 012 as much as possible, while limiting the width difference between the first-class data lines 011 and the second-class data lines 012, thereby avoiding the first-class data lines 011 having too small a width, which may lead to a decrease in their ability to transmit data signals.
[0041] Figure 6 A schematic diagram of a partial structure of a display panel provided in this application.
[0042] In one embodiment of the present application, Figure 6 As shown, the multiple pixel circuits 1 also include a third type of pixel circuit 13. The luminous color of the light-emitting device driven by the third type of pixel circuit 13 is different from the luminous color of the light-emitting device driven by the first type of pixel circuit 11 and the luminous color of the light-emitting device driven by the second type of pixel circuit 12.
[0043] Figure 7 This is a schematic diagram of the voltage changes in some data signal lines in this application, for easy understanding, Figure 7 The figure shows how the voltages corresponding to the first, second, and third types of data lines respectively change with time during the data adjustment stage; the short dashed line refers to the voltage change curve of the first type of data line, the solid line refers to the voltage change curve of the second type of data line, and the long dashed line refers to the voltage change curve of the third type of data line. The vertical axis in the figure represents the voltage value of the electrical signal in the data line, and the horizontal axis represents time.
[0044] Combine Figure 6 and Figure 7 The plurality of data signal lines 01 also includes a third-type data line 013. During the data writing phase T1, the third-type data line 013 transmits a data signal to the third-type pixel circuit 13. During the data adjustment phase T2, the voltage variation range of the data signal transmitted by the third-type data line 013 is smaller than the voltage variation range of the data signal transmitted by the second-type data line 012. That is, the charging voltage difference ΔV1 of the first-type data line 011, the charging voltage difference ΔV2 of the second-type data line 012, and the charging voltage difference ΔV3 of the third-type data line 013 can satisfy the following relationship: ΔV1>ΔV2>ΔV3.
[0045] Among them, such as Figure 6 As shown, the minimum distance between the orthographic projection of the first-type data line 011 and the orthographic projection of the active layer of the first-type pixel circuit 11 is c3, wherein the third part P3 on the active layer of the third-type pixel circuit 13 is closest to the third-type data line 013, that is, the distance between the projections corresponding to the third-type data line 013 and the third part P3 can be c3; c1>c2>c3.
[0046] like Figure 7 As shown, in the present application, by setting c1>c2>c3, the coupling capacitance corresponding to the first-class data line 011 and the second-class data line 012, respectively, is reduced. This, in turn, helps offset the impact of the relatively large charging voltage differences ΔV1 and ΔV2 on the charging speed of the first-class data line 011 and the second-class data line 012. This helps reduce the difference between the charging process duration of the first-class data line 011 and the charging process duration of the third-class data line 013, as well as the difference between the charging process duration of the second-class data line 012 and the charging process duration of the third-class data line 013. Furthermore, this helps reduce the difference in duration between the scan signal access period ta corresponding to the first-class pixel circuit 11, the scan signal access period tb corresponding to the second-class pixel circuit 12, and the scan signal access period tc corresponding to the third-class pixel circuit 13. This relatively extends the appropriate time period for the first scan line S1 to transmit the scan signal to the first-class pixel circuit 11 and the appropriate time period for transmitting the scan signal to the second-class pixel circuit 12, thereby facilitating the design of the working timing.
[0047] In one possible implementation, Figure 7 As shown, the charging process durations of the first-type data line 011, the second-type data line 012, and the third-type data line 013 are all the same. With this design, the durations of the scan signal access period ta corresponding to the first-type pixel circuit 11, the scan signal access period tb corresponding to the second-type pixel circuit 12, and the scan signal access period tc corresponding to the third-type pixel circuit 13 can be the same, facilitating a unified design of the operating timing.
[0048] In one embodiment of the present application, the light-emitting color of the light-emitting device corresponding to the first type of pixel circuit 11 is blue, the light-emitting color of the light-emitting device corresponding to the second type of pixel circuit 12 is green, and the light-emitting color of the light-emitting device corresponding to the third type of pixel circuit 13 is red.
[0049] It is known that the charging process duration corresponding to the blue light-emitting device is longer than that corresponding to the green light-emitting device, which is longer than that corresponding to the red light-emitting device. The setting method of this embodiment helps to reduce the time difference between the scan signal access periods corresponding to the blue light-emitting device, the red light-emitting device, and the green light-emitting device, respectively, and relatively extend the appropriate time period for the first scan line S1 to transmit the scan signal to the pixel circuit 1 for driving the blue light-emitting device, thereby facilitating the working timing design.
[0050] Figure 8 A schematic diagram of a partial structure of a display panel provided in this application.
[0051] In one embodiment of the present application, c1 / c2≥c2 / c3.
[0052] like Figure 6 As shown, c1 / c2=c2 / c3. If c2 can be regarded as obtained by increasing c3, and c1 can be regarded as obtained by increasing c2, then this setting means that the gap between the orthographic projection of the data signal line 01 and the orthographic projection of the active layer is enlarged proportionally in sequence, which helps to reduce the difficulty of preparation.
[0053] like Figure 8 As shown, c1 / c2>c2 / c3, if c2 can be regarded as obtained by increasing c3, and c1 can be regarded as obtained by increasing c2, then this arrangement means that the expansion degree of the gap corresponding to the first type of data line 011 is greater than the expansion degree of the gap corresponding to the second type of data line 012 (the above gap may refer to the gap between the orthographic projection of the data signal line 01 and the orthographic projection of the active layer), which is more conducive to enhancing the increase in the charging speed of the first type of data line 011.
[0054] Figure 9A schematic diagram of a partial structure of a display panel provided in this application.
[0055] In one embodiment of the present application, Figure 9 As shown, the orthographic projection width of the first type data line 011 is d1, the orthographic projection width of the second type data line 012 is d1, and the orthographic projection width of the third type data line 013 is d3, d1<d2<d3.
[0056] By setting d1 < d2 < d3 in this embodiment, the orthographic projection area of the first-type data lines 011 is minimized, the orthographic projection area of the second-type data lines 012 is second, and the orthographic projection area of the third-type data lines 013 is largest. This arrangement helps reduce the influence range of the coupled electric fields generated by the first-type data lines 011 and the second-type data lines 012, thereby reducing the coupling capacitance corresponding to the first-type data lines 011 and the second-type data lines 012, respectively. This helps improve the charging speed of the first-type data lines 011 and the second-type data lines 012, and reduces the difference in charging speed between the three types of data signal lines 01.
[0057] Figure 10 A schematic diagram of a partial structure of a display panel provided in this application.
[0058] In one embodiment of the present application, d2 / d1≥d3 / d2.
[0059] like Figure 9 As shown, d2 / d1=d3 / d2. If d1 can be regarded as a reduction of d2, and d2 can be regarded as a reduction of d3, then this setting means that the width of the positive projection of the data signal line 01 is reduced in equal proportion, which helps to reduce the difficulty of preparation. like Figure 10 As shown, d2 / d1>d3 / d2. If d1 can be regarded as obtained by reducing d2, and d2 can be regarded as obtained by reducing d3, then this setting means that relative to the width reduction degree of the second-type data line 012, the width reduction degree of the first-type data line 011 is greater, which is more conducive to reducing the coupling capacitance of the first-type data line 011.
[0060] Figure 11 A schematic diagram of a display device provided in this application.
[0061] The present application provides a display device 20, such as Figure 11 As shown, the display device 20 includes the above-mentioned display panel 10. The display device 20 can be a mobile phone. In addition, the display device 20 can also be an electronic device such as a computer or a television.
[0062] In the display device 20 provided by the embodiment of the present application, the difference in charging speed between the data lines corresponding to the pixels of different colors is greatly reduced.
[0063] In this specification, reference can be made to the same or similar parts between the various embodiments. In particular, for the device embodiment and the terminal embodiment, since they are basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description in the method embodiment.
Claims
1. A display panel, characterized in that: include: a plurality of pixel circuits, including a first type of pixel circuit and a second type of pixel circuit, wherein the light-emitting devices driven by the first type of pixel circuit and the light-emitting devices driven by the second type of pixel circuit correspond to different luminous colors; a plurality of data signal lines, including a first type of data lines and a second type of data lines, wherein in a data writing phase, the first type of data lines transmit data signals to the first type of pixel circuits, and the second type of data lines transmit the data signals to the second type of pixel circuits; in a data adjustment phase, a voltage variation range of the data signals transmitted by the first type of data lines is greater than a voltage variation range of the data signals transmitted by the second type of data lines; the data adjustment phase occurs before the data writing phase; The minimum distance between the orthographic projection of the first type of data line and the orthographic projection of the active layer of the first type of pixel circuit is c1, and the minimum distance between the orthographic projection of the second type of data line and the orthographic projection of the active layer of the second type of pixel circuit is c2, c1>c2.
2. The display panel according to claim 1, wherein: The light emitting color of the light emitting device corresponding to the first type of pixel circuit is blue, and the light emitting color of the light emitting device corresponding to the second type of pixel circuit is red or green.
3. The display panel according to claim 1, wherein: 109%≤c1 / c2≤180%.
4. The display panel according to claim 1, wherein: The orthographic projection width d1 of the first-type data line is smaller than the orthographic projection width d2 of the second-type data line.
5. The display panel according to claim 4, wherein: 65%≤d1 / d2≤95%.
6. The display panel according to claim 1, wherein: The plurality of pixel circuits further include a third type of pixel circuit, wherein the light emitting device driven by the third type of pixel circuit emits light of a color different from the light emitting device driven by the first type of pixel circuit and the light emitting device driven by the second type of pixel circuit; The plurality of data signal lines further include a third type of data line, and in the data writing phase, the third type of data line transmits the data signal to the third type of pixel circuit; In the data adjustment stage, a voltage variation range of the data signal transmitted by the third type of data line is smaller than a voltage variation range of the data signal transmitted by the second type of data line; The minimum distance between the orthographic projection of the first type of data line and the orthographic projection of the active layer of the first type of pixel circuit is c3, and c1>c2>c3.
7. The display panel according to claim 6, wherein: The light emitting color of the light emitting device corresponding to the first type of pixel circuit is blue, the light emitting color of the light emitting device corresponding to the second type of pixel circuit is green, and the light emitting color of the light emitting device corresponding to the third type of pixel circuit is red.
8. The display panel according to claim 6, wherein: c1 / c2≥c2 / c3.
9. The display panel according to claim 6, wherein: The orthographic projection width of the first type of data line is d1, the orthographic projection width of the second type of data line is d2, and the orthographic projection width of the third type of data line is d3, where d1<d2<d3.
10. The display panel according to claim 9, wherein: d2 / d1≥d3 / d2.
11. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 10.