Display method, shift register, scanning driving circuit, display panel and electronic equipment

Abstract

The invention provides a display method, a shift register, a scanning drive circuit, a display panel and electronic equipment, relates to the technical field of electronic equipment, and is used for reducing the power consumption of the electronic equipment. The method comprises the following steps: in the display process of the display panel, refreshing an image of a first display area at a first refresh rate, and refreshing an image of a second display area at a second refresh rate; the first refresh rate is smaller than the second refresh rate.

Description

Technical Field

[0001] Embodiments of the present application relate to the technical field of electronic devices, and in particular to a display method, a shift register, a scan drive circuit, a display panel, and an electronic device. Background Art

[0002] Mobile phones, tablets, and other electronic devices are ubiquitous in our daily lives. Display panels are one of the main power-consuming components of these electronic devices, and reducing their power consumption is a pressing technical challenge. Summary of the Invention

[0003] Embodiments of the present application provide a display method, a shift register, a scan drive circuit, a display panel, and an electronic device, for solving the problem of high power consumption of a display panel.

[0004] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, a display method is provided. The method is applied to an electronic device having a display panel, the display panel including a first display area and a second display area, the first display area and the second display area not overlapping. The method includes: during a display process on the display panel, refreshing an image in the first display area at a first refresh rate, and refreshing an image in the second display area at a second refresh rate; the first refresh rate is lower than the second refresh rate.

[0006] In this application, by reducing the refresh rate of the areas of the display panel where the image remains unchanged, while maintaining the refresh rate of the areas where the image changes, the display quality of the areas where the image changes can be maintained while reducing the refresh power consumption of the areas where the image remains unchanged. While maintaining the display quality of the display panel, the power consumption of the display panel can be reduced, thereby reducing the power consumption of the electronic device.

[0007] In a possible implementation of the first aspect, the display panel includes a plurality of scan signal lines, each scan signal line extending along a first direction, and the plurality of scan signal lines arranged side by side along a second direction. The first direction intersects the second direction. In the second direction, the first display area is located on at least one side of the second display area.

[0008] In another possible implementation of the first aspect, the plurality of scan signal lines include a first scan signal line and a second scan signal line, the first scan signal line being at least partially located in the first display area, and the second scan signal line being at least partially located in the second display area. Refreshing an image in the first display area at a first refresh rate, and refreshing an image in the second display area at a second refresh rate, includes: within a refresh period of the display panel, the second scan signal line controlling the plurality of connected sub-pixels to emit light based on a data signal received in a current period, and the first scan signal line controlling the plurality of connected sub-pixels to emit light based on a data signal received in a previous period.

[0009] In this application, during a refresh cycle of a display panel, subpixels in an area with a reduced refresh rate are controlled to emit the same light as in the previous frame according to the previous data signal, and subpixels in an area with a maintained refresh rate are controlled to emit light according to the data signal received in the current frame. This ensures that each subpixel in the display panel emits light reliably, avoids problems with the display panel displaying abnormal images, and improves the reliability of the display panel and electronic device display.

[0010] In another possible implementation of the first aspect, the first refresh rate is less than or equal to 10 Hz. The smaller the first refresh rate, the more the power consumption of the display panel is reduced, thereby further reducing the power consumption of the display panel and the electronic device.

[0011] In a second aspect, the present application provides a shift register. The shift register includes a first output circuit and a second output circuit. The first output circuit is coupled to an input signal terminal, a first clock signal terminal, a second clock signal terminal, a first voltage terminal, and a second voltage terminal. The first output circuit is configured to output a first output signal under the common control of an input signal output from the input signal terminal, a first clock signal output from the first clock signal terminal, and a second clock signal output from the second clock signal terminal. The second output circuit is coupled to the first output circuit, a third voltage terminal, a fourth voltage terminal, and a control signal terminal. The second output circuit is configured to output a second output signal under the control of at least a signal provided by the first output circuit and a control signal output from the control signal terminal. The change state of the second output signal is the same as the change state of the first output signal, or the second output signal is an invalid signal.

[0012] In the present application, the control signal terminal controls the second output circuit of the shift register to output a second output signal identical to the first output signal or an invalid signal. When the second output signal is identical to the first output signal, the shift register can control the connected sub-pixels to perform normal refresh, maintaining the sub-pixel refresh frequency; when the second output signal is an invalid signal, the shift register can control the connected sub-pixels to stop refreshing, reducing the sub-pixel refresh frequency.

[0013] In this way, the shift register can flexibly control the refresh frequency of the connected sub-pixels according to actual needs; and while reducing the refresh frequency of the sub-pixels, it avoids changes in the first node level in the pixel circuit inside the sub-pixels, ensuring that the sub-pixels can emit the same light as the previous frame, thereby improving the reliability of the display panel and electronic device display.

[0014] In another possible implementation of the second aspect, the second output circuit includes a logic subcircuit and an output subcircuit. The logic subcircuit is coupled to at least the control signal terminal and the first node of the first output circuit. The logic subcircuit is configured to output a logic signal under the control of a control signal output by the control signal terminal and a level signal provided by the first node. The output subcircuit is coupled to the third voltage terminal, the fourth voltage terminal, the logic subcircuit, and the second node of the first output circuit. The output subcircuit is configured to output a second output signal under the control of the logic signal output by the logic subcircuit and the level signal provided by the second node.

[0015] In another possible implementation of the second aspect, the logic sub-circuit is coupled to the control signal terminal, the output terminal of the first output circuit, the first voltage terminal and the first node respectively; the logic sub-circuit is configured to output a logic signal under the control of the first output signal output by the first output circuit, the control signal provided by the control signal terminal and the level signal provided by the first node.

[0016] In another possible implementation of the second aspect, the logic subcircuit includes a first logic transistor, a second logic transistor, and a third logic transistor. A first electrode of the first logic transistor is coupled to the first voltage terminal, and a control electrode of the first logic transistor is coupled to the output terminal of the first output circuit. A first electrode of the second logic transistor is coupled to the second voltage terminal, a control electrode of the second logic transistor is coupled to the first node of the first output circuit, and a second electrode of the second logic transistor is coupled to a fourth node. A first electrode of the third logic transistor is coupled to the second electrode of the first logic transistor, a control electrode of the third logic transistor is coupled to the control signal terminal, and a second electrode of the third logic transistor is coupled to the fourth node.

[0017] In another possible implementation of the second aspect, the logic sub-circuit is coupled to the control signal terminal, the first node and the third node of the first output circuit, and the second voltage terminal respectively; the logic sub-circuit is configured to output a logic signal under the control of a control signal provided by the control signal terminal, a level signal provided by the first node, and a level signal provided by the third node.

[0018] In another possible implementation of the second aspect, the logic sub-circuit includes a fourth logic transistor and a fifth logic transistor. A first electrode of the fourth logic transistor is coupled to the third node of the first output circuit, a control electrode of the fourth logic transistor is coupled to the control signal terminal, and a second electrode of the fourth transistor is coupled to the fourth node. A first electrode of the fifth logic transistor is coupled to the second voltage terminal, a control electrode of the fifth logic transistor is coupled to the first node of the first output circuit, and a second electrode of the fifth logic transistor is coupled to the fourth node.

[0019] In another possible implementation of the second aspect, the output subcircuit includes a first output transistor and a second output transistor. A first electrode of the first output transistor is coupled to the fourth voltage terminal, a control electrode of the first output transistor is coupled to the fourth node, and a second electrode of the first output transistor is coupled to the output terminal of the second output circuit. A first electrode of the second output transistor is coupled to the third voltage terminal, a control electrode of the second output transistor is coupled to the second node of the first output circuit, and a second electrode of the second output transistor is coupled to the output terminal of the second output circuit.

[0020] In a third aspect, the present application provides a scan driving circuit. The scan driving circuit includes a plurality of shift registers cascaded to each other. The shift registers are any of the shift registers described in the second aspect above.

[0021] In a fourth aspect, the present application provides a display panel. The display panel includes a plurality of sub-pixels and a scan driver circuit. The plurality of sub-pixels are arranged in a multi-row and multi-column array. The scan driver circuit is coupled to the plurality of sub-pixels via a plurality of scan signal lines, with each scan signal line coupled to a plurality of sub-pixels in the same row. The scan driver circuit includes the scan driver circuit described in the third aspect above.

[0022] In a fifth aspect, the present application provides an electronic device. The electronic device includes a display panel and a battery. The display panel includes the display panel described in the fourth aspect. The battery is coupled to the display panel. The battery is configured to supply power to the display panel.

[0023] It can be understood that the beneficial effects that can be achieved by the scanning driving circuit described in the third aspect, the display panel described in the fourth aspect, and the electronic device described in the fifth aspect provided above can refer to the beneficial effects in the second aspect and any possible design method thereof, and will not be repeated here.

[0024] In a sixth aspect, an electronic device is provided, comprising a display panel, a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of any one of the methods described in the first aspect.

[0025] In a seventh aspect, a computer-readable storage medium is provided, wherein a computer program / instruction is stored on the computer-readable storage medium, and when the computer program / instruction is executed by a processor, the method according to any one of the above-mentioned first aspects is implemented.

[0026] In an eighth aspect, a computer program product comprising instructions is provided. The computer program product comprises a computer program / instructions, and when the computer program / instructions are executed by a processor, the method according to any one of the above-mentioned first aspects is implemented.

[0027] In a ninth aspect, an embodiment of the present application provides a chip, the chip including a processor, the processor being used to call a computer program in a memory to execute any method as in the first aspect.

[0028] It can be understood that the beneficial effects that can be achieved by the electronic device described in the sixth aspect, the computer-readable storage medium described in the seventh aspect, the computer program product described in the eighth aspect, and the chip described in the ninth aspect provided above can refer to the beneficial effects in the first aspect and any possible design method thereof, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A diagram showing two screens displayed by a video playback application on a child device;

[0030] Figure 2 A schematic diagram of the structure of a display panel provided in some embodiments of the present application;

[0031] Figure 3 for Figure 2 Circuit structure diagram of a sub-pixel in the middle AA area;

[0032] Figure 4 for Figure 3 The timing diagram of multiple signals when the sub-pixel shown in FIG is refreshed normally within a frame refresh period;

[0033] Figure 5 for Figure 2 A schematic structural diagram of the second scan drive circuit;

[0034] Figure 6 A schematic structural diagram of a shift register provided in some embodiments of the present application;

[0035] Figure 7 for Figure 6 A structural schematic diagram of a first output circuit;

[0036] Figure 8 for Figure 6 A structural diagram of a shift register shown in FIG.

[0037] Figure 9 for Figure 8 A structural diagram of a shift register shown in FIG.

[0038] Figure 10 A schematic diagram of a working timing of a shift register;

[0039] Figure 11 for Figure 6 Another structural diagram of the shift register shown;

[0040] Figure 12 for Figure 11 A structural diagram of a shift register shown in FIG.

[0041] Figure 13 Another working timing diagram of the shift register;

[0042] Figure 14 1 is another working timing diagram of the shift register;

[0043] Figure 15 A schematic diagram of the working timing of signals output by multiple shift registers in a display panel within a frame refresh period;

[0044] Figure 16 Schematic diagram of signal transmission between multiple shift registers and multiple rows of sub-pixels in the AA area within a frame refresh cycle;

[0045] Figure 17 This is a schematic diagram of the working timing of the control signal terminal in three scenarios;

[0046] Figure 18 A possible structural diagram of an electronic device involved in some embodiments of the present application;

[0047] Figure 19 A schematic diagram of a possible structure of a controller involved in some embodiments of the present application. DETAILED DESCRIPTION

[0048] The following will describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0049] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of this application, unless otherwise specified, "plurality" means two or more.

[0050] In addition, in this application, directional terms such as "up", "down", "left", and "right" may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts. They are used for relative descriptions and clarifications, and they may change accordingly according to changes in the orientation of the components in the drawings.

[0051] When describing some embodiments, the terms "connected," "connected," and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct or indirect physical contact with each other. For example, "A and B are connected" may mean that A and B are connected directly, or that A and B are connected through other components. In addition, the term "coupled" may refer to a method of electrical connection for signal transmission, and coupling may refer to direct coupling or indirect coupling.

[0052] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0053] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0054] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0055] The transistors mentioned herein may be thin film transistors (TFTs), triodes, or metal-oxide-semiconductor field-effect transistors (MOSFETs, MOS tubes for short), etc., without limitation herein.

[0056] In addition, the high-level signal and low-level signal mentioned in this article are just relative concepts. A high-level signal can be a signal greater than 0V or a signal less than 0V; similarly, a low-level signal can be a signal greater than 0V or a signal less than 0V.

[0057] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0058] Figure 1 Schematic diagram showing two screens displayed by a video playback application in an electronic device.

[0059] At present, when displaying images, the entire display panel is refreshed at the same frequency. Figure 1 (a) in the display to display Figure 1 In the middle (b) screen, although there are actual changes in the video playback area 01, since the entire display panel is refreshed at the same frequency, the information display area 02 where the screen does not change is also refreshed at the same frequency as the video playback area 01.

[0060] Therefore, if Figure 1 As shown, the areas where the image has not changed are also refreshed at a relatively high frequency (eg, 60 Hz or 120 Hz), which causes unnecessary power consumption waste of the display panel.

[0061] Based on this, the embodiments of the present application provide a shift register, a scan drive circuit, a display panel, an electronic device, and a display method applied to the electronic device, by reducing the Figure 1 The refresh rate of the area where the picture does not change is shown to reduce the power consumption of the display panel.

[0062] The structure of the display panel is introduced below.

[0063] Figure 2 FIG. 1 is a schematic diagram of the structure of a display panel according to some embodiments. Figure 2As shown, the display panel includes a display area (i.e., a pixel array area) AA and a peripheral area SA located on at least one side (e.g., the left side, the right side, or all four sides) of the display area AA. The display area AA may include: a plurality of rows and columns of sub-pixels arranged in an array, and a plurality of scan signal lines respectively connected to the plurality of rows of sub-pixels. For example, the plurality of scan signal lines include a plurality of enable signal lines L-EM respectively connected to the plurality of rows of sub-pixels, a plurality of first reset signal lines L-ResetN respectively connected to the plurality of rows of sub-pixels, a plurality of second reset signal lines L-ResetP respectively connected to the plurality of rows of sub-pixels, a plurality of first gate lines L-GateP respectively connected to the plurality of rows of sub-pixels, and a plurality of second gate lines L-GateN respectively connected to the plurality of rows of sub-pixels.

[0064] The display area AA may further include a plurality of data signal lines L-Data respectively connected to a plurality of columns of sub-pixels.

[0065] Each sub-pixel may include a pixel circuit and a light-emitting element having a circuit structure such as 7T1C, 7T2C, 8T1C, 8T2C or 4T1C in the art.

[0066] It should be noted that the direction indicated by the above lines is the same as Figure 2 The first direction X is the same as Figure 2 Any one of the enable signal line L-EM, the first reset signal line L-ResetN, the second reset signal line L-ResetP, the first gate line L-GateP, and the second gate line L-GateN extends along the first direction X, and the plurality of lines are arranged side by side along the second direction Y.

[0067] in addition, Figure 2 In the description, the first direction X and the second direction Y are perpendicular to each other. In other examples, the first direction X and the second direction Y may also form an angle of 80°, 75° or other angles, which is not limited here.

[0068] like Figure 2 As shown, the peripheral area SA may include a first scan driving circuit 21 , a second scan driving circuit 22 , a third scan driving circuit 23 , a fourth scan driving circuit 24 and a fifth scan driving circuit 25 .

[0069] In some examples, the first scan driver circuit 21 can be connected to multiple enable signal lines L-EM to provide enable signals to multiple rows of sub-pixels. Because the first scan driver circuit 21 is used to drive the enable sub-circuits of the sub-pixels, the first scan driver circuit 21 can also be called an emission gate driver array (EM GOA).

[0070] In some examples, the second scan driver circuit 22 can be located on a side of the first scan driver circuit 21 near the display area AA and connected to multiple reset signal lines L-ResetN to provide first reset signals to multiple rows of sub-pixels. The second scan driver circuit 22 is used to drive the N-type thin film transistors (TFTs) in the sub-pixels. Therefore, the second scan driver circuit 22 can also be referred to as an N-type reset scan driver circuit Reset-N GOA.

[0071] In some examples, the third scan driver circuit 23 can be located on a side of the second scan driver circuit 22 that is close to the display area AA and connected to multiple first gate lines L-GateP to provide first gate signals to multiple rows of sub-pixels. For example, the third scan driver circuit 23 provides first gate signals to P-type transistors in the sub-pixels, and therefore the third scan driver circuit 23 can also be referred to as a P-type gate scan driver circuit Gate-P GOA.

[0072] In some examples, the peripheral area SA may further include a fourth scan driver circuit 24. The fourth scan driver circuit 24 is located on a side of the display area AA away from the first scan driver circuit 21. The fourth scan driver circuit 24 may be connected to a plurality of second reset signal lines L-ResetP to provide second reset signals to multiple rows of sub-pixels. The fourth scan driver circuit 24 is configured to drive the P-type thin film transistors in the sub-pixels. Therefore, the fourth scan driver circuit 24 may also be referred to as a P-type reset scan driver circuit Reset-P GOA.

[0073] In some examples, the peripheral area SA may further include a fifth scan driver circuit 25. The fifth scan driver circuit 25 is located on a side of the fourth scan driver circuit 24 that is close to the display area AA and is connected to a plurality of second gate lines L-GateN to provide second gate signals to a plurality of rows of sub-pixels. For example, the fifth scan driver circuit 25 provides second gate signals to N-type transistors in the sub-pixels. Therefore, the fifth scan driver circuit 25 may also be referred to as an N-type gate scan driver circuit, Gate-N GOA.

[0074] like Figure 2 As shown, in some examples, a portion of the third scan driving circuit 23 may be located between the first scan driving circuit 21 and the display area AA, and another portion may be located between the fourth scan driving circuit 24 and the display area AA.

[0075] like Figure 2As shown, the non-display area SA may further include a source integrated circuit (Source IC) 26. The source driver circuit 26 is coupled to the data line L-Data that passes through the AA area along the second direction, and provides data signals to the multiple sub-pixels in the AA area through the data line L-Data. One data line L-Data provides a data signal for a column of sub-pixels arranged in an array, and multiple data lines L-Data provide data signals for sub-pixels in different columns. For example, the pixel circuit in the sub-pixel operates under the control of the data signal transmitted through the data line and the gate signal and enable signal transmitted through the scanning signal line to drive the light-emitting element to emit light to achieve display and other operations. The light-emitting element can be, for example, an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED), and the embodiments of the present disclosure are not limited to this.

[0076] like Figure 2 As shown, the non-display area SA may further include a control line L-Ctrl. The control line L-Ctrl may pass through the non-display area SA along the second direction. For example, the control line L-Ctrl may be coupled to an N-type reset scan driver circuit Reset-N GOA, and the control line L-Ctrl may also be coupled to an N-type gate scan driver circuit.

[0077] Figure 3 for Figure 2 The circuit structure diagram of a sub-pixel in the AA area. Figure 3 As shown, the sub-pixel P includes a light-emitting element E and a pixel circuit M that drives the light-emitting element E to emit light. The pixel circuit M includes a driving sub-circuit 71, a data writing sub-circuit 72, a compensation sub-circuit 73, a reset sub-circuit 74, an enable sub-circuit 75 and a storage capacitor Cst.

[0078] The reset subcircuit 74 includes a first reset subcircuit 741, which includes a first reset transistor BT1. The compensation subcircuit 73 includes a compensation transistor BT2. The drive subcircuit 71 includes a drive transistor BT3. The data write subcircuit 72 includes a data write transistor BT4. The enable subcircuit 75 includes a first enable subcircuit 751 and a second enable subcircuit 752, wherein the first enable subcircuit 751 includes a first enable transistor BT5 and the second enable subcircuit 752 includes a second enable transistor BT6. The reset subcircuit 74 also includes a second reset subcircuit 742, which includes a second reset transistor BT7. The reset subcircuit 74 may further include a third reset subcircuit 743, which includes a third reset transistor BT8. For example, the first reset transistor BT1 and the compensation transistor BT2 are N-type transistors, and the data write transistor BT4 and the second reset transistor BT7 are P-type transistors. The connection relationship and operating principle of the pixel unit in the embodiments of the present disclosure are merely examples. The pixel unit may also adopt other structures as needed, and the present disclosure is not limited thereto.

[0079] like Figure 3 As shown, in some embodiments, the pixel circuit M is described as a whole:

[0080] A control electrode of the first reset transistor BT1 is coupled to the reset signal line L-ResetN, and a first electrode of the first reset transistor BT1 is coupled to the first initialization signal line L-Vinit1. The first reset transistor BT1 is configured to transmit a first initialization signal provided by the first initialization signal line L-Vinit1 to the first node N1 under control of a first reset signal provided by the reset signal line L-ResetN.

[0081] A control electrode of the compensation transistor BT2 is coupled to the second gate line L-GateN, a first electrode of the compensation transistor BT2 is coupled to the third node N3, and a second electrode of the compensation transistor BT2 is coupled to the first node N1. The compensation transistor BT2 is configured to form a path between the first node N1 and the third node N3 under the control of a second gate signal provided by the second gate line L-GateN.

[0082] The control electrode of the driving transistor BT3 is coupled to the first node N1, the first electrode of the driving transistor BT3 is coupled to the second node N2, and the second electrode of the driving transistor BT3 is coupled to the third node N3. The driving transistor BT3 is configured to form a path between the second node N2 and the third node N3 under the control of the potential of the first node N1.

[0083] A control electrode of the data write transistor BT4 is coupled to the first gate line L-GateP, a first electrode of the data write transistor BT4 is coupled to the data line L-Data, and a second electrode of the data write transistor BT4 is coupled to the second node N2. The data write transistor BT4 is configured to transmit a data signal provided by the data line L-Data to the second node N2 under the control of a first gate signal provided by the first gate line L-GateP.

[0084] A control electrode of the first enabling transistor BT5 is coupled to the enable signal line L-EM, a first electrode of the first enabling transistor BT5 is coupled to the first power line L-VDD, and a second electrode of the first enabling transistor BT5 is coupled to the second node N2. The first enabling transistor BT5 is configured to transmit the first power signal provided by the first power line L-VDD to the second node N2 under the control of the enable signal provided by the enable signal line L-EM.

[0085] A control electrode of the second enabling transistor BT6 is coupled to the enable signal line L-EM, a first electrode of the second enabling transistor BT6 is coupled to the third node N3, and a second electrode of the second enabling transistor BT6 is coupled to the fourth node N4. The second enabling transistor BT6 is configured to form a path between the third node N3 and the fourth node N4 under the control of an enable signal provided by the enable signal line L-EM.

[0086] A control electrode of the second reset transistor BT7 is coupled to the second reset signal line L-ResetP, a first electrode of the second reset transistor BT7 is coupled to the second initialization signal line L-Vinit2, and a second electrode of the second reset transistor BT7 is coupled to the fourth node N4. The second reset transistor BT7 is configured to transmit the second initialization signal provided by the second initialization signal line L-Vinit2 to the fourth node N4 under the control of the second reset signal provided by the second reset signal line L-ResetP.

[0087] A control electrode of the third reset transistor BT8 is coupled to the second reset signal line L-ResetP, a first electrode of the third reset transistor BT8 is coupled to the third initialization signal line L-Vinit3, and a second electrode of the third reset transistor BT8 is coupled to the second node N2. The third reset transistor BT8 is configured to transmit the third initialization signal provided by the third initialization signal line L-Vinit3 to the fourth node N2 under the control of the second reset signal provided by the second reset signal line L-ResetP.

[0088] In some embodiments, any scan driving circuit includes multiple cascaded shift registers, each of which is used to drive one or more rows of sub-pixels. This embodiment of the disclosure is described using an example in which each shift register is used to drive a row of sub-pixels, but this embodiment of the disclosure is not limited thereto.

[0089] For example, the peripheral area may further include a first voltage signal line ( Figure 2 Not shown) and a second voltage signal line ( Figure 2 (not shown), the first voltage signal line is configured to provide a first voltage signal, and the second voltage signal line is configured to provide a second voltage signal, and the level of the first voltage signal is less than the level of the second voltage signal. The first scan driving circuit 21 is coupled to the first voltage signal line to output the first voltage signal as the first part of the enable signal. For example, the first voltage signal line is connected to multiple first shift registers in the first scan driving circuit 21. The first part of the enable signal is, for example, a low potential part of the enable signal. For example, the low potential part of the enable signal can cause the first enable transistor BT5 and the second enable transistor BT6 to be in a conductive state during the light-emitting phase. The first scan driving circuit 21 is also coupled to the second voltage signal line to output a second voltage as the second part of the enable signal. For example, the second voltage signal line is coupled to multiple first shift registers in the first scan driving circuit 21. The second part of the enable signal is, for example, a high potential part of the enable signal. For example, the high potential part of the enable signal can cause the first enable transistor BT5 and the second enable transistor BT6 to be in a cut-off state during the light-emitting phase.

[0090] Figure 4 Shown Figure 3 The timing diagram of multiple signals when the sub-pixel shown in FIG is refreshed normally within a frame refresh cycle. Figure 4 The multiple signal timings shown are Figure 3 The working process of the sub-pixel in one frame refresh cycle is described as follows. It can be seen that the pixel circuit M has five stages in one frame refresh cycle.

[0091] In the first phase P1, the enable signal EM is high, and the first enable transistor BT5 and the second enable transistor BT6 are both in the off state. The first reset signal Reset-N is low, and the first reset transistor BT1 is also in the off state. The second reset signal Reset-P is low, and the second reset transistor BT7 is in the on state. The second initialization signal Vinit2 initializes the fourth node N4, and the third reset transistor BT8 is in the on state. The third initialization signal Vinit3 initializes the second node N2. The first gate signal Gate-P is high, and the data write transistor BT4 is in the off state. The second gate signal Gate-N is high, and the compensation transistor BT2 is in the on state, and the first node N1 and the third node N3 are conductive.

[0092] At this time, the first node N1 is at a low level, controlling the driving transistor BT3 to be in a conductive state. The second node N2 is conductively connected to the third node N3 via the driving transistor BT3. Since the first node N1 is conductively connected to the third node N3, the third initialization signal Vinit3 flows sequentially through the second node N2 and the third node N3 into the first node N1.

[0093] In the first phase P1, the third initialization signal Vinit3 gradually increases the level of the first node N1. As the level of the first node N1 increases, the conduction level of the driving transistor BT3 gradually decreases. Until the level of the first node N1 equals the level of the third initialization signal Vinit3, the driving transistor BT3 is turned off.

[0094] In the second phase P2: the enable signal EM is a high-level signal, and the first enable transistor BT5 and the second enable transistor BT6 continue to be in the off state. The first reset signal Reset-N is a high-level signal, the first reset transistor BT1 is in the on state, and the first initialization signal Vinit1 enters the first node N1, pulling down the level of the first node N1 to the same level as the first initialization signal Vinit1. The second reset signal Reset-P is a high-level signal, and the second reset transistor BT7 and the third reset transistor BT8 are both in the off state. The first gate signal Gate-P is a high-level signal, and the data write transistor BT4 is in the off state. The second gate signal Gate-N is a low-level signal, and the compensation transistor BT2 is in the off state.

[0095] During the process of pulling down the level of the first node N1 , the first node N1 can control the driving transistor BT3 to be in a conducting state, and the second node N2 and the third node N3 are conducted to each other.

[0096] In the third phase P3, the enable signal EM is high, and the first enable transistor BT5 and the second enable transistor BT6 remain in the off state. The first reset signal Reset-N is low, and the first reset transistor BT1 is also in the off state. The second reset signal Reset-P is high, and the second reset transistor BT7 and the third reset transistor BT8 are both in the off state. The first gate signal Gate-P is low, and the data write transistor BT4 is on. The data signal Data is written to the second node N2. The second gate signal Gate-N is high, and the compensation transistor BT2 is on. The third node N3 is electrically connected to the first node N1.

[0097] During the second phase P2, the first node N1 controls the driving transistor BT3 to be in a conductive state, and the second node N2 and the third node N3 are conductive. Therefore, during the third phase P3, after the data signal Data is written to the second node N2, it can flow through the third node N3 and enter the first node N1 for storage. Therefore, the third phase P3 can also be called the data writing phase.

[0098] In the fourth phase P4, the enable signal EM is high, and the first enable transistor BT5 and the second enable transistor BT6 remain in the off state. The first reset signal Reset-N is low, and the first reset transistor BT1 is also in the off state. The second reset signal Reset-P is low, and the second reset transistor BT7 is in the on state. The second initialization signal Vinit2 initializes the fourth node N4, and the third reset transistor BT8 is in the on state. The third initialization signal Vinit3 initializes the second node N2. The first gate signal Gate-P is high, and the data write transistor BT4 is in the off state. The second gate signal Gate-N is low, and the compensation transistor BT2 is in the off state.

[0099] In the fifth phase P5, the enable signal EM is low, and the first enable transistor BT5 and the second enable transistor BT6 are both in the on state. The first reset signal Reset-N is low, and the first reset transistor BT1 is in the off state. The second reset signal Reset-P is high, and the second reset transistor BT7 and the third reset transistor BT8 are both in the off state. The first gate signal Gate-P is high, and the data write transistor BT4 is in the off state. The second gate signal Gate-N is low, and the compensation transistor BT2 is in the off state.

[0100] In the fifth stage P5, the first enabling transistor BT5, the second enabling transistor BT6, and the driving transistor BT3 are all in the on state, so that the second voltage source VDD is connected to the light-emitting device E, so that current is injected into the light-emitting device E, driving the light-emitting device E to emit light. Therefore, the fifth stage P5 can also be called a light-emitting stage.

[0101] The degree of conduction of the driving transistor BT3 in the fifth phase P5 is related to the data signal previously written into the first node N1 , so the data signal can control the magnitude of the current injected into the light emitting device E.

[0102] It should be noted that Figure 3The pixel circuit M shown is only an example. In some other examples, the pixel circuit M may not have the third reset transistor BT8. In the case where the pixel circuit M does not have the third reset transistor BT8, the pixel circuit M may not go through the fourth stage P4.

[0103] Figure 3 The pixel circuit M shown utilizes the fourth stage P4 primarily to initialize the levels of the second node N2 and the fourth node N4. In different pixel circuits, due to differences in the previous frame of image display, the levels of the second node N2 and the fourth node N4 may have some impact on the performance of the drive transistor BT3, resulting in poor uniformity in the performance of the drive transistor BT3 across different pixel circuits. Initializing the levels of the second node N2 and the fourth node N4 in the fourth stage P4 can improve the uniformity of the performance of the drive transistor BT3 across different pixel circuits, thereby improving the uniformity of the display effect of the display panel.

[0104] It can be understood that in the fourth stage P4, the levels of the second node N2 and the fourth node N4 are not initialized. In the fifth stage, the first enabling transistor BT5, the second enabling transistor BT6 and the driving transistor BT3 are all in the on state, and current is injected into the light-emitting device E to drive the light-emitting device E to emit light.

[0105] In some current solutions, to control the refresh rate of a portion of a display panel's sub-pixels within a frame refresh cycle while not refreshing others, thereby reducing power consumption, a source IC typically controls the data line L-Data to stop supplying data signals to sub-pixels that do not need to be refreshed, and only provides data signals for the current frame refresh cycle to sub-pixels that do need to be refreshed. This reduces power consumption of the display panel and electronic device by reducing the output signal of the source IC.

[0106] However, combined with the above Figure 2 and Figure 3 In the description of the operation of the pixel circuit in a frame refresh cycle, it can be found that when the pixel circuit M does not receive a new data signal in the above-mentioned writing phase P3, the first node N1 in the pixel circuit M is connected to the data line L-Data, which does not provide a data signal, through the third node N3 and the second node N2, causing the voltage level of the first node N1 to change. As a result, the sub-pixel without a data signal can no longer continue to emit the same light as the previous frame in the current frame, resulting in an abnormal image displayed by the display panel.

[0107] The shift register and scan driver circuit provided in the embodiments of the present application can maintain the level of the first node N1 in the sub-pixel unchanged when the Source IC controls the data line L-Data to stop providing data signals to sub-pixels that do not need to be refreshed. This allows the sub-pixels with data signals to emit the same light in the current frame as in the previous frame, thereby reducing the power consumption of the Source IC while ensuring that the display does not exhibit abnormalities.

[0108] The structures of the second scan driving circuit 22 for providing the first reset signal to the first reset transistor BT1 in the pixel circuit M and the fifth scan driving circuit 25 for providing the second gate signal to the compensation transistor BT2 in the pixel circuit M are described in detail below.

[0109] See also Figure 5 , Figure 5 A structural schematic diagram of a second scan driving circuit provided in some embodiments of the present application is shown.

[0110] The second scan driving circuit 22 includes n stages of cascaded shift registers (RS1, RS2, ..., RS(n)). In this case, the display panel includes n stages of cascaded shift registers (RS1, RS2, ..., RS(n)) coupled one-to-one to n first reset signal lines (L-ResetN).

[0111] In addition, if Figure 5 As shown, the shift register (RS1, RS2...RS(n)) of the second scanning driving circuit 22 of some embodiments of the present disclosure is also provided with an input signal terminal Vin, a first clock signal terminal CK, a second clock signal terminal CB, a first voltage terminal VGL, a second voltage terminal VGH, a control signal terminal Ctrl, a first output terminal OUT and a second output terminal OUT-N, and the circuit structure of the shift registers at each level in the second scanning driving circuit 22 can be the same.

[0112] On this basis, in the above-mentioned second scanning driving circuit 22, the signal input terminal Vin of the previous stage or multiple stages of the shift register is coupled to the frame start signal terminal STV, and except for the shift register coupled to the frame start signal terminal STV, the signal input terminal Vin of the subsequent stage shift register is coupled to the signal input terminal OUT of the previous stage shift register; the previous stage shift register and the subsequent stage shift register here may be shift registers located at adjacent stages, or may not be shift registers located at adjacent stages.

[0113] For example, Figure 5As shown, in the above-mentioned second scan driving circuit 22, the signal input terminal Vin of the first-stage shift register RS1 can be coupled to the frame start signal terminal STV, the signal input terminal Vin of the second-stage shift register RS2 can be coupled to the signal output terminal OUT of the first-stage shift register RS1, and the signal output terminal Oput of the i-th stage shift register RSi can be coupled to the signal input terminal Vin of the i+1-th stage shift register RS(i+1), where 2≤i≤N-1 is a positive integer.

[0114] For example, Figure 5 As shown, the first clock signal terminal CK of the shift register is coupled to the first system clock signal line L-CK extending along the second direction Y; the second clock signal terminal CB of the shift register is coupled to the second system clock signal line L-CB extending along the second direction Y; the first voltage terminal VGL of the shift register is coupled to the first voltage line L-VGL extending along the second direction Y; the second voltage terminal VGH of the shift register is coupled to the second voltage line L-VGH extending along the second direction Y; and the control signal terminal Ctrl of the shift register is coupled to the control signal line L-Ctrl extending along the second direction Y.

[0115] The structure of the fifth scan driving circuit 25 may be substantially the same as that of the second scan driving circuit 22 , and will not be further described herein.

[0116] The shift register provided in the embodiment of the present application can be used with Figure 3 The pixel circuit is coupled to the transistor in the pixel circuit, thereby controlling the transistor in the pixel circuit to be in an on state or an off state.

[0117] Below Figure 6 The structure of the shift register shown in is described in detail.

[0118] Figure 6 shows a schematic structural diagram of a shift register provided in some embodiments of the present application; Figure 7 Shown Figure 6 A structural diagram of a first output circuit 31; Figure 8 Shown Figure 6 A structural diagram of a shift register shown in FIG.

[0119] See also Figure 6 , the shift register 30 may include a first output circuit 31 and a second output circuit 32. The second output circuit 32 is coupled to the first output circuit 31.

[0120] The first output circuit 31 may have a circuit structure such as 8T2C, 9T2C, 11T3C, 14T3C, 16T3C, or 17T3C, and the embodiments of the present application are not limited thereto. For ease of understanding, the following description of the first output circuit 31 will use the 17T3C circuit structure as an example, but it should be understood that other circuit structures are also applicable to the first output circuit 31.

[0121] See also Figure 7 , Figure 7 Shown Figure 6 The first output circuit 31 is shown as a schematic structural diagram. The first output circuit 31 may include 17 transistors (T1, T2, ..., T17) and 3 capacitors (C1, C2, and C3). For example, all 17 transistors are P-type transistors.

[0122] A first electrode of the first transistor T1 is coupled to the input signal terminal Vin, a control electrode of the first transistor T1 is coupled to the first clock signal terminal CK, and a second electrode of the first transistor T1 is coupled to the first node S1. The input signal terminal Vin is used to receive the first output signal output by the first output circuit 31 in the previous stage shift register as an input signal, or to receive the frame start signal STV.

[0123] A first electrode of the second transistor T2 is coupled to the first voltage terminal VGL, and a control electrode of the second transistor T2 is coupled to the first clock signal terminal CK.

[0124] A first electrode of the third transistor T3 is coupled to the first clock signal terminal CK, and a control electrode of the third transistor T3 is coupled to the first node S1.

[0125] A first electrode of the fourth transistor T4 is coupled to the second electrode of the third transistor T3 , a control electrode of the fourth transistor T4 is coupled to the first node S1 , and a second electrode of the fourth transistor T4 is coupled to the second electrode of the second transistor T2 .

[0126] A first electrode of the fifth transistor T5 is coupled to the second voltage terminal VGH, and a control electrode of the fifth transistor T5 is coupled to the second electrode of the second transistor T2.

[0127] A first electrode of the sixth transistor T6 is coupled to the second clock signal terminal CB, and a second electrode of the sixth transistor T6 is coupled to the second electrode of the fifth transistor T5 .

[0128] A first electrode of the seventh transistor T7 is coupled to the second clock signal CB, and a control electrode of the seventh transistor T7 is coupled to the second electrode of the second transistor T2.

[0129] A first plate of the first capacitor C1 is coupled to the control electrode of the seventh transistor T7 , and a second plate of the first capacitor C1 is coupled to the second electrode of the seventh transistor T7 .

[0130] A first electrode of the eighth transistor T8 is coupled to the second electrode of the seventh transistor T7 , a control electrode of the eighth transistor T8 is coupled to the second clock signal CB, and a second electrode of the eighth transistor T8 is coupled to the third node S3 .

[0131] A first electrode of the ninth transistor T9 is coupled to the second voltage terminal VGH, a control electrode of the ninth transistor T9 is coupled to the first node S1 , and a second electrode of the ninth transistor T9 is coupled to the third node S3 .

[0132] The first electrode of the tenth transistor T10 is coupled to the second voltage terminal VGH, the control electrode of the tenth transistor T10 is coupled to the third node S3, and the second electrode of the tenth transistor T10 is coupled to the output terminal OUT of the first output circuit 31. Figure 5 The middle shift register is used to provide an output port of the input signal Vin to the next stage shift register.

[0133] A first plate of the second capacitor C2 is coupled to the second voltage terminal VGH, and a second plate of the second capacitor C2 is coupled to the third node S3.

[0134] A first electrode of the eleventh transistor T11 is coupled to the first voltage terminal VGL, a control electrode of the eleventh transistor T11 is coupled to the second node S2 , and a second electrode of the eleventh transistor T11 is coupled to the output terminal OUT of the first output circuit 31 .

[0135] A first electrode of the twelfth transistor T12 is coupled to the second electrode of the second transistor T2 , a control electrode of the twelfth transistor T12 is coupled to the first voltage terminal VGL, and a second electrode of the twelfth transistor T12 is coupled to the control electrode of the seventh transistor T7 .

[0136] A first electrode of the thirteenth transistor T13 is coupled to the first node S1 , a control electrode of the thirteenth transistor T13 is coupled to the first voltage terminal VGL, and a second electrode of the thirteenth transistor T13 is coupled to the second node S2 .

[0137] A first electrode of the fourteenth transistor T14 is coupled to the second voltage terminal VGH, a control electrode of the fourteenth transistor T14 is coupled to the protection signal terminal BH, and a second electrode of the fourteenth transistor T14 is coupled to the first node S1.

[0138] A first electrode of the fifteenth transistor T15 is coupled to the input signal terminal Vin, and a control electrode of the first transistor T1 is coupled to the first clock signal terminal CK.

[0139] A first electrode of the sixteenth transistor T16 is coupled to the second electrode of the fifteenth transistor T15 , and a control electrode of the sixteenth transistor T16 is coupled to the first voltage terminal.

[0140] A first electrode of the seventeenth transistor T17 is coupled to the second electrode of the sixteenth transistor T16 , a control electrode of the seventeenth transistor T17 is coupled to the control electrode of the sixth transistor T6 , and a second electrode of the seventeenth transistor T17 is coupled to the second node S2 .

[0141] A first electrode of the third capacitor C3 is coupled to the second electrode of the sixth transistor T6 , and a second electrode of the third capacitor C3 is coupled to the control electrode of the sixth transistor T6 and the first electrode of the seventeenth transistor T17 .

[0142] On this basis, based on the circuit structure of 17T3C, in some embodiments, the first output circuit 31 may further have some modified structures.

[0143] In some embodiments, the third transistor T3 and the fourth transistor T4 are both P-type transistors, and are configured to control the conduction or disconnection between the first clock signal terminal and the second electrode of the second transistor T2 under the control of the voltage level of the first node S1. In this case, the third transistor T3 and the fourth transistor T4 can be reduced to only one transistor, which does not affect the solution and can save the cost of the electronic device.

[0144] In some embodiments, the twelfth transistor T12 is controlled by the low-level signal provided by the first voltage terminal VGL to keep the conductive state. If there is no twelfth transistor T12 in the circuit, directly coupling the second electrode of the second transistor T2 to the control electrode of the seventh transistor T7, the two solutions have the same effect as that with the twelfth transistor T12. Figure 7 The twelfth transistor T12 may be omitted from the first output circuit 31 shown.

[0145] Similarly, the thirteenth transistor T13 is controlled by the low level signal provided by the first voltage terminal VGL and remains in the on state. Figure 7 The thirteenth transistor T13 may also be omitted from the first output circuit 31 shown.

[0146] Similarly, the sixteenth transistor T16 is kept in the on state under the control of the low level signal provided by the first voltage terminal VGL. Figure 7 The sixteenth transistor T16 may also be omitted from the first output circuit 31 shown.

[0147] In some embodiments, the fourteenth transistor T14 is a P-type transistor. The specific function of the protection signal terminal BH and the fourteenth transistor T14 is that before the display panel is illuminated, the protection signal terminal BH provides a low-level signal to the fourteenth transistor T14, so that the high-level signal provided by the second voltage terminal VGH pulls up the level of the first node S1, controlling the eleventh transistor T11 to be in a cut-off state, thereby preventing the first output circuit 31 from outputting a low-level signal.

[0148] During the process of refreshing the displayed image on the display panel, the protection signal terminal BH outputs a high-level signal for a long time, so that the fourteenth transistor T14 is in the cut-off state. This will not affect the implementation of the first output circuit 31. Therefore, only for the process of refreshing the displayed image on the display panel, Figure 7 The fourteenth transistor T14 and the protection signal terminal BH may also be omitted from the first output circuit 31 shown.

[0149] In the embodiment of the present application, the variation of the first output circuit 31 is not limited. Figure 7 This is just an example of the first output circuit 31 .

[0150] The second output circuit 32 is coupled to the third voltage terminal VGL′, the fourth voltage terminal VGH′, the first output circuit 31 and the control signal terminal Ctrl respectively. When receiving a corresponding control signal, the second output circuit 32 outputs a second output signal.

[0151] For example, the control signal output by the control signal terminal Ctrl can be used to control the change state of the second output signal output by the second output circuit 32 to be the same as the change state of the first output signal output by the first output circuit 31. The change state includes the change trend (level increase or level decrease) and the time point of the change. For example, if the levels of two signals increase at the same time, it means that the change states of the two signals are the same.

[0152] Alternatively, the control signal output by the control signal terminal Ctrl can control the second output signal output by the second output circuit 32 to be a failure signal. The failure signal refers to a signal that controls the transistor to be in the off state, and correspondingly, the signal that controls the transistor to be in the on state can be called a valid signal.

[0153] It should be noted that the third voltage terminal VGL' can have the same level as the first voltage terminal VGL, and the fourth voltage terminal VGH' can have the same level as the second voltage terminal VGH. Alternatively, the third voltage terminal VGL' can have a different level than the first voltage terminal VGL; or the fourth voltage terminal VGH' can have a different level than the second voltage terminal VGH. For example, the first voltage terminal VGL is -7V, the second voltage terminal VGH is +7V, the third voltage terminal VGL' is -10V, and the fourth voltage terminal VGH' is +7V.

[0154] For ease of understanding, the following description will take the first voltage terminal VGL as the third voltage terminal VGL' and the second voltage terminal VGH as the fourth voltage terminal VGH' as an example, but this should not be considered as a limitation on the third voltage terminal VGL' and the fourth voltage terminal VGH'.

[0155] like Figure 8 As shown, the second output circuit 32 may include a logic sub-circuit 321 and an output sub-circuit 322. The logic sub-circuit 321 is coupled to the first output circuit 31 and the control signal terminal, respectively. When the logic sub-circuit 321 receives the corresponding control signal Ctrl, the logic sub-circuit 321 outputs a logic signal to the output sub-circuit 322.

[0156] At the same time, the output sub-circuit 322 is also coupled to the first output circuit 31. The output sub-circuit 322 outputs a second output signal based on the signal provided by the first output circuit 31 and the logic signal provided by the logic sub-circuit 321.

[0157] In some examples, such as Figure 8 As shown, the logic sub-circuit 321 is coupled to the output terminal OUT of the first output circuit 31, the first node S1, and the control signal terminal Ctrl. The logic sub-circuit 321 is configured to output a logic signal under the control of the first output signal output from the output terminal OUT of the first output circuit 31, the voltage level provided by the first node S1, and the control signal provided by the control signal terminal Ctrl.

[0158] The output sub-circuit 322 is coupled to the logic sub-circuit 321 and the second node S2 of the first output circuit 31. The output sub-circuit 322 is configured to output a second output signal under the control of the logic signal output by the logic sub-circuit 321 and the voltage level provided by the second node S2, so that the output terminal OUT-N of the second output circuit 32 outputs the second output signal.

[0159] See also Figure 9 , Figure 9 for Figure 8 A structural diagram of a shift register shown in FIG. Figure 9The output sub-circuit 322 includes an eighteenth transistor T18, a nineteenth transistor T19, and a fourth capacitor C4. The logic sub-circuit 321 includes a twentieth transistor T20, a twenty-first transistor T21, and a twenty-second transistor T22. For ease of explanation, the following description assumes that the twentieth transistor T20 is an N-type transistor and the other transistors (T18, T19, T21, and T22) are P-type transistors.

[0160] A first electrode of the twentieth transistor T20 is coupled to the first voltage terminal VGL, and a control electrode of the twentieth transistor T20 is coupled to the output terminal OUT of the first output circuit 31. That is, the twentieth transistor T20 is a first logic transistor.

[0161] The first electrode of the 21st transistor T21 is coupled to the second electrode of the 20th transistor T20, the control electrode of the 21st transistor T21 is coupled to the control signal terminal Ctrl, and the second electrode of the 21st transistor T21 is coupled to the fourth node S4. That is, the 21st transistor T21 is a third logic transistor.

[0162] The first electrode of the 22nd transistor T22 is coupled to the second voltage terminal VGH, the control electrode of the 22nd transistor T22 is coupled to the first node S1 in the first output circuit 31, and the second electrode of the 22nd transistor T22 is coupled to the fourth node S4. That is, the 22nd transistor T22 is a second logic transistor.

[0163] A first electrode of the eighteenth transistor T18 is coupled to the second voltage terminal VGH, a control electrode of the eighteenth transistor T18 is coupled to the fourth node S4, and a second electrode of the eighteenth transistor T18 is coupled to the output terminal OUT-N of the second output circuit 32. That is, the eighteenth transistor T18 is a first output transistor.

[0164] A first plate of the fourth capacitor C4 is coupled to the second voltage terminal VGH, and a second plate of the fourth capacitor C4 is coupled to a fourth node S4.

[0165] A first electrode of the nineteenth transistor T19 is coupled to the first voltage terminal VGL, a control electrode of the nineteenth transistor T19 is coupled to the second node S2 in the first output circuit 31, and a second electrode of the nineteenth transistor T19 is coupled to the output terminal OUT-N of the second output circuit 32. The nineteenth transistor T19 is a second output transistor.

[0166] The following is for Figure 9 The shift register shown in the figure specifically describes the working process of the shift register during the image display process of the display panel in detail.

[0167] See also Figure 10 , Figure 10 A working timing diagram of a shift register. Figure 10 The figure shows the signal timing changes of the input signal terminal Vin, the first clock signal terminal CK, the second clock signal terminal CB, the control signal terminal Ctrl, the third node S3, the second node S2, the output terminal OUT of the first output circuit 31, the first node S1, the fourth node S4 and the output terminal OUT-N of the second output circuit 32.

[0168] like Figure 10 As shown, Figure 9 The shift register shown has multiple working stages. It should be noted that, as previously explained, the protection signal terminal BH always provides a high-level signal during the image display process of the display panel, so the fourteenth transistor T14 is continuously in the off state, and the state of the fourteenth transistor T14 will not be described in subsequent stages.

[0169] In the first phase H1, the first clock signal CK is high, so that the first transistor T1, the second transistor T2, and the fifteenth transistor T15 are all in the off state. Therefore, no new signal is written into the first node S1, and the first node S1 and the second node S2 maintain the low level of the previous phase.

[0170] The first node S1 turns on the third transistor T3 and the fourth transistor T4 , and the high-level signal is transmitted to the control electrode of the seventh transistor T7 and the control electrode of the fifth transistor T5 , so that the seventh transistor T7 and the fifth transistor T5 are also turned off.

[0171] The first node S1 also turns on the ninth transistor T9. The ninth transistor T9 is in the on state, causing the high-level signal from the second voltage terminal VGH to be written to the third node S3. The high level of the third node S3 turns off the tenth transistor T10. The low level of the second node S2 turns on the eleventh transistor T11. Thus, the output terminal OUT of the first output circuit 31 is connected to the first voltage terminal VGL, and the output terminal OUT of the first output circuit 31 outputs a low-level signal.

[0172] The output terminal OUT of the first output circuit 31 outputs a low-level signal to control the twentieth transistor T20 to be in a cut-off state, and the control signal terminal Ctrl provides a high-level signal to control the twenty-first transistor T21 to be in a cut-off state.

[0173] The first node S1 also controls the 22nd transistor T22 to be in the on state, so that the high level signal provided by the second voltage terminal is written into the fourth node S4, causing the 18th transistor T18 to be in the off state.

[0174] The second node S2 controls the nineteenth transistor T19 to be in a conducting state, the first voltage terminal is connected to the output terminal OUT-N of the second output circuit 32, and the output terminal OUT-N of the second output circuit 32 outputs a low level signal.

[0175] In the second phase H2, the first clock signal CK is a low-level signal, so that the first transistor T1, the second transistor T2, and the fifteenth transistor T15 are all in the on state. Therefore, the input signal as a high-level signal is written into the first node S1, the second node S2, and the first electrode of the seventeenth transistor T17.

[0176] The first node S1 turns off the third and fourth transistors T3 and T4. The low-level signal provided by the first voltage terminal VGL turns on the fifth and seventh transistors T5 and T7. When the fifth transistor T5 is on, the high-level signal provided by the second voltage terminal VGH is transmitted to the first plate of the third capacitor C3. The seventh transistor T7 is on, but because the second clock signal CB is high, the eighth transistor T8 is off, preventing the second clock signal CB from being transmitted to the third node S3.

[0177] The first node S1 also turns off the ninth transistor T9. Since both the eighth and ninth transistors T8 and T9 are in the off state, no new signal is written to the third node S3. Therefore, the third node S3 maintains a high level in the first phase H1. Thus, the third node S3 controls the tenth transistor T10 to be in the off state. The high level of the second node S2 also controls the eleventh transistor T11 to be in the off state. Thus, the output terminal OUT of the first output circuit 31 maintains the first phase H1 and continues to output a low-level signal.

[0178] The output terminal OUT of the first output circuit 31 outputs a low-level signal to control the twentieth transistor T20 to be in a cut-off state, and the control signal terminal Ctrl provides a high-level signal to control the twenty-first transistor T21 to be in a cut-off state.

[0179] The first node S1 also controls the twenty-second transistor T22 to be in the off state. No new signal is written to the fourth node S4, so the fourth node S4 maintains the high level of the first phase H1, causing the eighteenth transistor T18 to be in the off state.

[0180] The second node S2 controls the nineteenth transistor T19 to be in a cut-off state. In this way, the output terminal OUT-N of the second output circuit 32 maintains the first stage H1 and continues to output a low-level signal.

[0181] In the third phase H3, the first clock signal CK is high, so that the first transistor T1, the second transistor T2, and the fifteenth transistor T15 are all in the off state. Therefore, no new signal is written into the first node S1, and the first node S1 and the second node S2 maintain the high level of the second phase H2.

[0182] The first node S1 turns off the third and fourth transistors T3 and T4. Since no new signal is written to the second electrode of the fourth transistor T4, the second phase H2 remains low, turning on the fifth and seventh transistors T5 and T7. When the fifth transistor T5 is on, the high-level signal provided by the second voltage terminal is written to the first plate of the third capacitor C3. When the seventh transistor T7 is on and the second clock signal CB is low, the eighth transistor T8 is turned on, causing the second clock signal CB to be written to the third node S3, which then remains low.

[0183] The second node S2 is at a high level, turning off the eleventh transistor T11. The third node S3 is at a low level, turning on the tenth transistor T10. Thus, the output terminal OUT of the first output circuit 31 outputs a high level signal provided by the second voltage terminal VGH.

[0184] The output terminal OUT of the first output circuit 31 outputs a high-level signal to control the twentieth transistor T20 to be in a conductive state. The control signal terminal Ctrl outputs a low-level signal to turn on the twenty-first transistor T21. Therefore, the low-level signal provided by the first voltage terminal VGL can be transmitted to the fourth node S4.

[0185] The first node S1 also controls the twenty-second transistor T22 to be in the off state. The fourth node S4 is only written to a low-level signal, so the fourth node S4 is at a low level, controlling the eighteenth transistor T18 to be in the on state. The second node S2 controls the nineteenth transistor T19 to be in the off state. The output terminal OUT-N of the second output circuit 32 is connected to the second voltage terminal VGH, and the output terminal OUT-N of the second output circuit 32 outputs the high-level signal provided by the second voltage terminal VGH.

[0186] In the fourth phase H4, the first clock signal CK is a low-level signal, so that the first transistor T1, the second transistor T2, and the fifteenth transistor T15 are all in the on state. Therefore, the input signal as a high-level signal is written into the first node S1, the second node S2, and the first electrode of the seventeenth transistor T17.

[0187] The first node S1 turns off the third and fourth transistors T3 and T4. The low-level signal provided by the first voltage terminal VGL turns on the fifth and seventh transistors T5 and T7. When the fifth transistor T5 is on, the high-level signal provided by the second voltage terminal VGH is transmitted to the first plate of the third capacitor C3. When the seventh transistor T7 is on, the second clock signal CB is high, and the eighth transistor T8 is off, preventing the second clock signal CB from being transmitted to the third node S3.

[0188] The first node S1 also turns off the ninth transistor T9. Since both the eighth and ninth transistors T8 and T9 are in the off state, no new signal is written to the third node S3. Therefore, the third node S3 maintains a low level in the third stage H3. Thus, the third node S3 turns on the tenth transistor T10. The high level of the second node S2 also turns off the eleventh transistor T11. Thus, the output terminal OUT of the first output circuit 31 is connected to the second voltage terminal VGH, and the output terminal OUT of the first output circuit 31 outputs the high-level signal provided by the second voltage terminal VGH.

[0189] The output terminal OUT of the first output circuit 31 outputs a high-level signal, turning on the twentieth transistor T20. The control signal terminal Ctrl first outputs a low-level signal, turning on the twenty-first transistor T21. The low-level signal provided by the first voltage terminal VGL is written to the fourth node S4. Subsequently, the control signal terminal Ctrl first outputs a high-level signal, turning off the twenty-first transistor T21.

[0190] Since the first node S1 controls the twenty-second transistor T22 to be in the off state, no new signal is written to the fourth node S4. Therefore, the fourth node S4 maintains a low level, controlling the eighteenth transistor T18 to be in the on state. The second node S2 controls the nineteenth transistor T19 to be in the off state. In this way, the output terminal OUT-N of the second output circuit 32 is connected to the second voltage terminal VGH, and the output terminal OUT-N of the second output circuit 32 outputs the high-level signal provided by the second voltage terminal VGH.

[0191] In the fifth stage H5 , the operation process of the first output circuit 31 is substantially the same as that in the third stage H3 , and will not be described again here.

[0192] The output terminal OUT of the first output circuit 31 outputs a high-level signal to turn on the twentieth transistor T20. The control signal terminal Ctrl also outputs a high-level signal to turn off the twenty-first transistor T21. Therefore, the low-level signal provided by the first voltage terminal VGL cannot be transmitted to the fourth node S4.

[0193] The first node S1 also controls the twenty-second transistor T22 to be in the off state. Since no new signal is written to the fourth node S4, the fourth node S4 maintains a low level in the fourth stage H4, controlling the eighteenth transistor T18 to be in the on state. The second node S2 controls the nineteenth transistor T19 to be in the off state. The output terminal OUT-N of the second output circuit 32 is connected to the second voltage terminal VGH, and the output terminal OUT-N of the second output circuit 32 outputs the high-level signal provided by the second voltage terminal VGH.

[0194] In the sixth stage H6 , the operation process of the first output circuit 31 is substantially the same as that in the fourth stage H4 , and will not be described again here.

[0195] The output terminal OUT of the first output circuit 31 outputs a high-level signal to turn on the twentieth transistor T20. The control signal terminal Ctrl also outputs a high-level signal to turn off the twenty-first transistor T21. Therefore, the low-level signal provided by the first voltage terminal VGL cannot be transmitted to the fourth node S4.

[0196] The first node S1 also controls the twenty-second transistor T22 to be in the off state. Since no new signal is written to the fourth node S4, the fourth node S4 maintains a low level in the fourth stage H4, controlling the eighteenth transistor T18 to be in the on state. The second node S2 controls the nineteenth transistor T19 to be in the off state. The output terminal OUT-N of the second output circuit 32 is connected to the second voltage terminal VGH, and the output terminal OUT-N of the second output circuit 32 outputs the high-level signal provided by the second voltage terminal VGH.

[0197] In the seventh stage H7 , the operation process of the shift register 30 is substantially the same as that in the fifth stage H5 , and will not be described again here.

[0198] In the eighth stage H8 , the operation process of the shift register 30 is substantially the same as that in the sixth stage H6 , and will not be described again here.

[0199] In the ninth stage H9 , the operation process of the shift register 30 is substantially the same as that in the fifth stage H5 , and will not be described again here.

[0200] In the tenth stage H10, the first clock signal CK is a low-level signal, so that the first transistor T1, the second transistor T2, and the fifteenth transistor T15 are all in a conductive state. Therefore, the input signal as a low-level signal is written into the first node S1, the second node S2, and the first electrode of the seventeenth transistor T17.

[0201] The first node S1 turns on the third and fourth transistors T3 and T4. The low-level signal provided by the first voltage terminal VGL turns on the fifth and seventh transistors T5 and T7. When the fifth transistor T5 is on, the high-level signal provided by the second voltage terminal VGH is transmitted to the first plate of the third capacitor C3. When the seventh transistor T7 is on, the second clock signal CB is high, and the eighth transistor T8 is off, preventing the second clock signal CB from being transmitted to the third node S3.

[0202] The first node S1 also turns on the ninth transistor T9. When the ninth transistor T9 is in the on state, the high-level signal provided by the second voltage terminal VGH is written to the third node S3, causing the third node S3 to be at a high level. Consequently, the third node S3 turns off the tenth transistor T10. The low-level second node S2 turns on the eleventh transistor T11. Thus, the output terminal OUT of the first output circuit 31 is connected to the first voltage terminal VGL, and the output terminal OUT of the first output circuit 31 outputs the low-level signal provided by the first voltage terminal VGL.

[0203] The output terminal OUT of the first output circuit 31 outputs a low-level signal to control the twentieth transistor T20 to be in the off state. The control signal terminal Ctrl outputs a high-level signal to turn off the twenty-first transistor T21. Therefore, the low-level signal provided by the first voltage terminal VGL cannot be transmitted to the fourth node S4.

[0204] The first node S1 also turns on the twenty-second transistor T22. The high-level signal provided by the second voltage terminal VGH is written to the fourth node S4, causing the fourth node S4 to be at a high level, turning off the eighteenth transistor T18. The second node S2 turns on the nineteenth transistor T19. The output terminal OUT-N of the second output circuit 32 is connected to the first voltage terminal VGL, and the output terminal OUT-N of the second output circuit 32 outputs the low-level signal provided by the first voltage terminal VGL.

[0205] After the tenth stage H10 , the working process of the tenth stage H10 is maintained until the input signal of the next frame arrives and then the first stage H1 to the tenth stage H10 are cycled again.

[0206] See also Figure 11 , Figure 11 for Figure 6 Another structural diagram of the shift register shown; Figure 12 for Figure 11 A structural diagram of a shift register shown in FIG.

[0207] In some examples, such as Figure 11As shown, the logic sub-circuit 321 is coupled to the third node S3 and the first node S1 of the first output circuit 31, as well as the control signal terminal Ctrl. The logic sub-circuit 321 is configured to output a logic signal under the control of the voltage level provided by the third node S3 of the first output circuit 31, the voltage level provided by the first node S1, and the control signal provided by the control signal terminal Ctrl.

[0208] The output sub-circuit 322 is coupled to the logic sub-circuit 321 and the second node S2 of the first output circuit 31. The output sub-circuit 322 is configured to output a second output signal under the control of the logic signal output by the logic sub-circuit 321 and the voltage level provided by the second node S2, so that the output terminal OUT-N of the second output circuit 32 outputs the second output signal.

[0209] like Figure 12 As shown, the output sub-circuit 322 includes an eighteenth transistor T18, a nineteenth transistor T19, and a fourth capacitor C4, and the logic sub-circuit 321 includes a twenty-fourth transistor T24 and a twenty-fifth transistor T25. For ease of description, the following description uses the example that the eighteenth transistor T18, the nineteenth transistor T19, the twenty-fourth transistor T24, and the twenty-fifth transistor T25 are all P-type transistors.

[0210] The first electrode of the 24th transistor T24 is coupled to the third node S3 of the first output circuit 31, the control electrode of the 24th transistor T24 is coupled to the control signal terminal Ctrl, and the second electrode of the 24th transistor T24 is coupled to the fourth node S4. The 24th transistor T24 is a fourth logic transistor.

[0211] The first electrode of the 25th transistor T25 is coupled to the second voltage terminal VGH, the control electrode of the 25th transistor T25 is coupled to the first node S1 in the first output circuit 31, and the second electrode of the 25th transistor T25 is coupled to the fourth node S4. The 25th transistor T25 is a fifth logic transistor.

[0212] A first electrode of the eighteenth transistor T18 is coupled to the second voltage terminal VGH, a control electrode of the eighteenth transistor T18 is coupled to the fourth node S4, and a second electrode of the eighteenth transistor T18 is coupled to the output terminal OUT-N of the second output circuit 32. That is, the eighteenth transistor T18 is a first output transistor.

[0213] A first plate of the fourth capacitor C4 is coupled to the second voltage terminal VGH, and a second plate of the fourth capacitor C4 is coupled to a fourth node S4.

[0214] A first electrode of the nineteenth transistor T19 is coupled to the first voltage terminal VGL, a control electrode of the nineteenth transistor T19 is coupled to the second node S2 in the first output circuit 31, and a second electrode of the nineteenth transistor T19 is coupled to the output terminal OUT-N of the second output circuit 32. In other words, the nineteenth transistor T19 serves as a second output transistor.

[0215] The following is for Figure 12 The shift register shown in the figure will explain in detail the working process of the display panel during the image display process. Figure 10 , Figure 10 A working timing diagram of a shift register. Figure 10 The figure shows the signal timing changes of the input signal terminal Vin, the first clock signal terminal CK, the second clock signal terminal CB, the control signal terminal Ctrl, the third node S3, the second node S2, the output terminal OUT of the first output circuit 31, the first node S1, the fourth node S4 and the output terminal OUT-N of the second output circuit 32.

[0216] like Figure 10 As shown, Figure 12 The shift register shown has multiple working stages. It should be noted that Figure 12 The working process of the first output circuit 31 in each stage (H1-H10) is similar to Figure 9 The working process of the first output circuit 31 in each stage (H1-H10) is basically the same and will not be described here in detail. Only the working process of the second output circuit 32 in each stage (H1-H10) will be described.

[0217] In the first phase H1 , the output terminal OUT of the first output circuit 31 outputs a low-level signal.

[0218] The high-level signal provided by the control signal terminal Ctrl controls the twenty-fourth transistor T24 to be in the off state. The first node S1 of the first output circuit 31 is at a low level, controlling the twenty-fifth transistor T25 to be in the on state. The high-level signal provided by the second voltage terminal VGH is written into the fourth node S4, controlling the eighteenth transistor T18 to be in the off state.

[0219] The second node S2 of the first output circuit 31 is at a low level, controlling the nineteenth transistor T19 to be in a conductive state, and the first voltage terminal VGL is connected to the output terminal OUT-N of the second output circuit 32. The output terminal OUT-N of the second output circuit 32 outputs the low level signal provided by the first voltage terminal VGL.

[0220] In the second phase H2 , the output terminal OUT of the first output circuit 31 maintains the first phase H1 and continues to output the low-level signal.

[0221] The high-level signal provided by the control signal terminal Ctrl turns off the twenty-fourth transistor T24. The first node S1 of the first output circuit 31 is at a high level, turning off the twenty-fifth transistor T25. No new signal is written to the fourth node S4, which maintains the high level of the first stage H1, turning off the eighteenth transistor T18.

[0222] The second node S2 of the first output circuit 31 is at a high level, controlling the nineteenth transistor T19 to be in a cut-off state. No new signal is written into the output terminal OUT-N of the second output circuit 32, maintaining the low level signal of the first stage H1.

[0223] In the third phase H3 , the output terminal OUT of the first output circuit 31 outputs a high level signal provided by the second voltage terminal VGH.

[0224] The second node S2 of the first output circuit 31 is at a high level, which controls the nineteenth transistor T19 to be in a cut-off state.

[0225] The first node S1 of the first output circuit 31 is at a high level, turning off the twenty-fifth transistor T25. The low-level signal provided by the control signal terminal Ctrl turns on the twenty-fourth transistor T24. The third node S3 of the first output circuit 31 is connected to the fourth node S4. The third node S3 is at a low level, causing the fourth node S4 to also be at a low level, turning on the eighteenth transistor T18. Thus, the second voltage terminal VGH is connected to the output terminal OUT-N of the second output circuit 32, and the output terminal OUT-N of the second output circuit 32 outputs the high-level signal output by the second voltage terminal VGH.

[0226] In the fourth stage H4 , the output terminal OUT of the first output circuit 31 outputs a high level signal provided by the second voltage terminal VGH.

[0227] The second node S2 of the first output circuit 31 is at a high level, which controls the nineteenth transistor T19 to be in a cut-off state.

[0228] The control signal terminal Ctrl first provides a low-level signal, which turns on the twenty-fourth transistor T24. The third node S3 of the first output circuit 31 is connected to the fourth node S4. The third node S3 is at a low level, causing the fourth node S4 to also be at a low level. Subsequently, the control signal terminal Ctrl provides a high-level signal, which turns off the twenty-fourth transistor T24. The first node S1 of the first output circuit 31 is at a high level, turning off the twenty-fifth transistor T25. Thus, the fourth node S4 is at a low level, turning on the eighteenth transistor T18. As a result, the second voltage terminal VGH is connected to the output terminal OUT-N of the second output circuit 32, and the output terminal OUT-N of the second output circuit 32 outputs the high-level signal output by the second voltage terminal VGH.

[0229] In the fifth stage H5 , the output terminal OUT of the first output circuit 31 outputs a high level signal provided by the second voltage terminal VGH.

[0230] The second node S2 of the first output circuit 31 is at a high level, which controls the nineteenth transistor T19 to be in a cut-off state.

[0231] The high-level signal provided by the control signal terminal Ctrl turns off the twenty-fourth transistor T24. The first node S1 of the first output circuit 31 is at a high level, turning off the twenty-fifth transistor T25. Consequently, no new signal is written to the fourth node S4, and the fourth node S4 maintains a low level in the fourth phase S4, turning on the eighteenth transistor T18. Consequently, the second voltage terminal VGH is connected to the output terminal OUT-N of the second output circuit 32, and the output terminal OUT-N of the second output circuit 32 outputs the high-level signal output by the second voltage terminal VGH.

[0232] In the sixth stage H6 , the seventh stage H7 , the eighth stage H8 and the ninth stage H9 , the working process of the second output circuit 32 is substantially the same as the working process in the fifth stage H5 , and will not be described again here.

[0233] In the tenth stage H10 , the output terminal OUT of the first output circuit 31 outputs the low level signal provided by the first voltage terminal VGL.

[0234] The high-level signal provided by the control signal terminal Ctrl controls the twenty-fourth transistor T24 to be in the off state. The first node S1 of the first output circuit 31 is at a low level, controlling the twenty-fifth transistor T25 to be in the on state. The high-level signal of the second voltage terminal VGH is written into the fourth node S4, controlling the eighteenth transistor T18 to be in the off state.

[0235] The second node S2 of the first output circuit 31 is at a low level, controlling the nineteenth transistor T19 to be in a turned-on state. The first voltage terminal VGL is coupled to the output terminal OUT-N of the second output circuit 32, and the output terminal OUT-N of the second output circuit 32 outputs the low-level signal provided by the first voltage terminal VGL.

[0236] After the tenth stage H10 , the working process of the tenth stage H10 is maintained until the input signal of the next frame arrives and then the first stage H1 to the tenth stage H10 are cycled again.

[0237] The above is Figure 9 and Figure 12 The shift register shown corresponds to Figure 10 The timing diagram shown in FIG. 1 shows the specific working process of a frame refresh cycle. In which, when the sub-pixels of a part of the display panel are refreshed and the sub-pixels of another part of the display panel are not refreshed, Figure 10 The timing diagram shown is a timing diagram of the shift register corresponding to the sub-pixel refresh.

[0238] Please read Figure 13 and Figure 14 , Figure 13 This is another working timing diagram of the shift register. Figure 14 This is another working sequence diagram of the shift register. Figure 13 The control signals provided by the control signal terminal Ctrl are all high-level signals. Figure 14 The control signals provided by the control signal terminal Ctrl are all low level signals. The level changes of the third node S3, the second node S2, the first node S1 and the output terminal OUT belonging to the first output circuit 31 in the shift register are related to the Figure 10 The above descriptions are consistent with those in the previous section and will not be repeated here.

[0239] in, Figure 13 The corresponding timing diagram is for the shift register corresponding to the sub-pixels in the display panel that are not refreshed. By setting the control signal provided by the control signal terminal Ctrl to a high level, the fourth node S4 in the second output circuit 32 is continuously at a high level, controlling the eighteenth transistor T18 to be in the off state. Consequently, the output terminal OUT-N of the second output circuit 32 continuously outputs a low level signal.

[0240] Figure 14 The corresponding timing diagram is a timing diagram of the shift register corresponding to the refreshed sub-pixels in the display panel. By setting the control signal provided by the control signal terminal Ctrl to a low-level signal, the fourth node S4 in the second output circuit 32 is synchronized with the third node S3 in the first output circuit 31. In this way, the output terminal OUT-N of the second output circuit 32 and the output terminal OUT of the first output circuit 31 are continuously synchronized.

[0241] It can be seen that the control signal provided by the control signal terminal Ctrl is mainly used to affect the level change of the fourth node S4. Figure 13 As shown, when the control signals are all high-level signals, Figure 9 The twenty-first transistor T21 or Figure 12 The twenty-fourth transistor T24 is always in the off state, and the fourth node S4 cannot be written with a low-level signal, so it is always at a high level, controlling the eighteenth transistor T18 to be in the off state. In this way, the output terminal OUT-N of the second output circuit 32 cannot be written with a high-level signal, and is always at a low level.

[0242] And as Figure 14 As shown, when the control signals are all low-level signals, the level state of the fourth node S4 is the same as the level state of the third node S3. Figure 7 and Figure 9 The eighteenth transistor T18 and the tenth transistor T10 are turned on or off simultaneously, and the nineteenth transistor T19 and the eleventh transistor T11 are turned on or off simultaneously (because they are all controlled by the second node S2 in the first output circuit 31). This allows the output terminal OUT of the first output circuit 31 and the output terminal OUT-N of the second output circuit 32 to output the same level.

[0243] In the case where the output terminal OUT-N of the second output circuit 32 in the second scan driving circuit 22 and the fifth scan driving circuit outputs a low level, as shown in FIG. Figure 3 In the pixel circuit M shown, the first reset transistor BT1 and the compensation transistor BT2 are both in the cut-off state.

[0244] Figure 9 and Figure 12 The shift register shown may be a shift register of the second scan driving circuit 22. In this case, the output terminal OUT-N of the second output circuit 32 in the shift register may be connected to the first reset line L-ResetN. Figure 3 The control electrode of the first reset transistor BT1 in the pixel circuit is coupled.

[0245] in addition, Figure 9 The shift register shown in the figure may also be the shift register of the fifth scan driving circuit 25. In this case, the output terminal OUT-N of the second output circuit 32 in the shift register may be connected to the output terminal OUT-N of the second output circuit 32 through the second gate line L-GateN. Figure 3 The control electrode of the compensation transistor BT2 in the pixel circuit is coupled.

[0246] In the following, in combination with the working process of the pixel circuit M, the normal refresh situation and the situation where the output terminal OUT-N of the second output circuit 32 outputs a low level signal are compared to illustrate the influence of the output terminal OUT-N of the second output circuit 32 outputting a low level signal on the sub-pixel refresh.

[0247] In the first phase P1: normal refresh, the second node N2 is connected to the third node N3, and the third node N3 is connected to the first node N1. Thus, the third initialization signal Vinit3 simultaneously initializes the second node N2, the third node N3, and the first node N1. However, since the second gate signal outputted by the output terminal OUT-N of the second output circuit 32 in the fifth scan driving circuit 25 is a low-level signal, the compensation transistor BT2 is in the off state, the first node N1 is disconnected from the third node N3, and the third initialization signal Vinit3 cannot initialize the first node N1.

[0248] In the second phase P2: normal refresh, the first transistor BT1 is turned on, and the first initialization signal Vinit1 is written into the first node N1 to initialize the first node N1. However, since the first reset signal outputted from the output terminal OUT-N of the second output circuit 32 in the second scan driving circuit 22 is a low-level signal, the first reset transistor BT1 is turned off, the first node N1 is disconnected from the first initialization signal terminal, and the first initialization signal Vinit1 cannot initialize the first node N1.

[0249] In the third phase P3: normal refresh, the second node N2 is connected to the third node N3, and the third node N3 is connected to the first node N1. In this way, the data signal is sequentially written into the first node N1 through the second node N2 and the third node N3. However, since the second gate signal outputted by the output terminal OUT-N of the second output circuit 32 in the fifth scan driving circuit 25 is a low-level signal, the compensation transistor BT2 is in the off state, and the data signal of the second node N1 cannot be written into the first node N1.

[0250] In the fourth stage P4: normal refresh, the compensation transistor BT2 is in the cut-off state, so it is consistent with the normal refresh process and has no impact.

[0251] In the fifth phase P5: normal refresh, the data signal written into the first node N1 in the third phase P3 is required to control the magnitude of the current injected into the light-emitting device E. However, since no new signal is written into the first node N1 in any of the four phases, the first node N1 retains the data signal of the previous frame, causing the light-emitting device E to inject a current substantially equal to that of the previous frame, and thus the light-emitting device E emits the same light as that of the previous frame.

[0252] It can be understood that the second scanning drive circuit 22 and the fifth scanning drive circuit 25 jointly output a low-level signal, which will cause the first node N1 in the pixel circuit M to maintain the level of the previous frame, and the actual sub-pixel light emission has no obvious change from the previous frame, thereby achieving the display panel not refreshing the display image of part of the display area.

[0253] Based on the above description that the control signal provided by the control signal terminal Ctrl can control the second output terminal OUT-N of a single shift register to output a high-level signal or a low-level signal, since the n shift registers in the scan driver circuit operate sequentially, by adjusting the timing of the low-level signal in the control signal provided by the control signal terminal Ctrl, it is possible to control a portion of the n shift registers in the scan driver circuit to output a low-level signal, thereby preventing the sub-pixels in a portion of the rows of the display panel from being refreshed, and to control another portion of the shift registers in the scan driver circuit to output a high-level signal, thereby preventing the sub-pixels in another portion of the rows of the display panel from being refreshed.

[0254] Figure 15 The figure shows a schematic diagram of the working timing of signals output by multiple shift registers in a display panel within a frame refresh period. Figure 15 The figure shows the signal timing changes of the input signal terminal Vin, the first clock signal terminal CK, the second clock signal terminal CB, the control signal terminal Ctrl, the third node S3, the second node S2, the output terminal OUT of the first output circuit 31, the first node S1, the fourth node S4 and the output terminal OUT-N of the second output circuit 32.

[0255] Figure 15 Where OUT(i) is the first output signal output by the first output circuit 31 in the i-th shift register, and OUT-N(i) is the second output signal output by the second output circuit 32 in the i-th shift register. Similarly, OUT(j) is the first output signal output by the first output circuit 31 in the j-th shift register, and OUT-N(j) is the second output signal output by the second output circuit 32 in the j-th shift register. i and j are positive integers and are not equal to each other.

[0256] from Figure 15It can be seen that when the rising edge of the first output signal output by the first output circuit 31 in the shift register is when the control signal is a low-level signal, the second output signal output by the second output circuit 32 has the same change as the first output signal. When the rising edge of the first output signal output by the first output circuit 31 in the shift register is when the control signal is a high-level signal, the second output signal output by the second output circuit 32 is a low-level signal. Since the shift register controls the N-type transistors in the pixel circuit M, a low-level signal cannot turn on the transistors. Therefore, the low-level signal output by the second output circuit 32 can also be called an invalid signal.

[0257] Based on this, the timing of the control signal can be adjusted so that the control signal is a high-level signal that covers the rising edge period of the shift register corresponding to the sub-pixel row that does not need to be refreshed, and the control signal is a low-level signal that covers the rising edge period of the shift register corresponding to the sub-pixel row that needs to be refreshed, thereby controlling the sub-pixels of some rows in the display panel to be refreshed, and the sub-pixels of the remaining rows are not refreshed.

[0258] Figure 16 A schematic diagram shows signal transmission between multiple shift registers and multiple rows of sub-pixels in the AA region during a frame refresh cycle. A thick line connecting the shift register RS ​​to the signal line indicates that the second output signal output by the second output circuit 32 in the shift register is a high-level signal; a thin line connecting the shift register RS ​​to the signal line indicates that the second output signal output by the second output circuit 32 in the shift register is a low-level signal.

[0259] In this way, by adjusting the respective timings of the low-level signal and the high-level signal in the control signal, the first scanning signal line (for example, the second gate line or the first reset signal line) L1 in the display panel that is at least partially located in the first display area FL can be controlled to provide a low-level signal, so that the sub-pixels in the first display area FL are not refreshed and continue to display the content displayed in the previous frame; the control signal can also control the second scanning signal line (for example, the second gate line or the first reset signal line) L2 in the display panel that is at least partially located in the second display area FH to provide a high-level signal, so that the sub-pixels in the second display area FH are refreshed, thereby displaying a new picture based on the data signal received in the current frame period.

[0260] Each scan signal line is coupled to the sub-pixels in the same row of the AA area, so the refresh rates of the sub-pixels in the same row are equal, while the refresh rates of the sub-pixels in different rows may be different. Therefore, the first display area FL and the second display area FH do not overlap in the second direction Y.

[0261] In some embodiments, the refresh frequency of the sub-pixels in the first display area FL is lower than the refresh frequency of the sub-pixels in the second display area FH.

[0262] For example, the refresh frequency of the sub-pixels in the first display area FL may be 1 Hz, 10 Hz, 20 Hz, or 30 Hz. The refresh frequency of the first sub-pixels in the second display area FL may be 60 Hz or 120 Hz.

[0263] It should be noted that, when the refresh frequency of the sub-pixels in the first display area FL is 30 Hz, Figure 3 In the illustrated pixel circuit M, the first reset transistor BT1 and the compensation transistor BT2 may be low-temperature polysilicon (LTPS) transistors. When the refresh frequency of the subpixels in the first display region FL is less than 30 Hz, to reduce the impact of transistor leakage on the first node N1, the first reset transistor BT1 and the compensation transistor BT2 in the pixel circuit M may be low-temperature polycrystalline oxide (LTPO) transistors.

[0264] in addition, Figure 16 This is just an example of two display areas with different refresh frequencies. In other examples, based on the same control distance of the shift register, three or more display areas can also be configured with different refresh frequencies, which is not limited here.

[0265] As previously explained, when the rising edge of the first output signal output by the first output circuit 31 in the shift register occurs when the control signal is a low-level signal, the second output signal output by the second output circuit 32 has the same variation as the first output signal. Furthermore, when the rising edge of the first output signal output by the first output circuit 31 in the shift register occurs when the control signal is a high-level signal, the second output signal output by the second output circuit 32 is an invalid signal. The following describes the timing variation of the control signal output by the control signal terminal Ctrl in conjunction with specific display panel usage scenarios.

[0266] In scenario 1, all sub-pixels of the display panel are refreshed at 60Hz. The timing changes of the control signal output by the control signal terminal Ctrl can be found in Figure 17 The timing changes of the control signal corresponding to full-screen high refresh.

[0267] The electronic device can set the control signal output by the control signal terminal Ctrl to a low-level signal during each frame refresh cycle, so that during each frame refresh cycle, the second output signal output by the second output circuit 32 in all shift registers has the same change as the first output signal. As a result, all sub-pixels of the display panel are refreshed during each frame refresh cycle and emit light based on the data signal received in the current cycle. This allows all sub-pixels of the display panel to be refreshed at 60 Hz.

[0268] In scenario 2, all sub-pixels of the display panel are refreshed at 1Hz. For details on the timing changes of the control signal output by the control signal terminal Ctrl, please refer to Figure 17 The timing changes of the control signal corresponding to the low refresh rate of the full screen.

[0269] The electronic device can set the control signal outputted by the control signal terminal Ctrl to a low-level signal during the first frame refresh period, so that during the first frame refresh period, the second output signal outputted by the second output circuit 32 in all the shift registers has the same change as the first output signal, thereby achieving refresh of all sub-pixels of the display panel during the first frame refresh period. Thereafter, the electronic device can set the control signal outputted by the control signal terminal Ctrl to a high-level signal during the second frame refresh period to the sixtieth frame refresh period, so that during the second frame refresh period to the sixtieth frame refresh period, the second output signal outputted by the second output circuit 32 in all the shift registers is an invalid signal, thereby achieving non-refresh of all sub-pixels of the display panel during the second frame refresh period to the sixtieth frame refresh period, maintaining the same light emission as the first frame, thereby achieving refresh of all sub-pixels of the display panel at 1 Hz.

[0270] In scenario 3, the first display area FL in the display panel is refreshed at 1 Hz and the second display area FH is refreshed at 60 Hz. The timing change of the control signal output by the control signal terminal Ctrl can be referred to Figure 17 The timing changes of the control signal corresponding to the local low refresh.

[0271] The electronic device can set the control signal output by the control signal terminal Ctrl to a low-level signal during the first frame refresh cycle, so that during the first frame refresh cycle, the second output signal output by the second output circuit 32 in all shift registers has the same variation as the first output signal, thereby achieving refresh of all sub-pixels on the display panel during the first frame refresh cycle. Subsequently, the electronic device can set the control signal output by the control signal terminal Ctrl to a high-level signal for a portion of the time and a low-level signal for another portion of the time during the second frame refresh cycle through the 60th frame refresh cycle. This ensures that during each frame refresh cycle from the second frame refresh cycle through the 60th frame refresh cycle, the second output signal output by the second output circuit 32 in the shift register corresponding to the second display region FH has the same variation as the first output signal, and the second output signal output by the second output circuit 32 in the shift register corresponding to the first display region FL is an invalid signal. The sub-pixels in the first display region FL of the display panel are not refreshed during the second frame refresh cycle through the 60th frame refresh cycle, maintaining the same light emission as in the first frame. The sub-pixels in the second display region FH are refreshed during each frame refresh cycle and emit light based on the data signal received during the current cycle. In this way, it is possible to achieve that in each frame refresh period from the second frame refresh period to the sixtieth frame refresh period, the first display area FL in the display panel is refreshed at 1 Hz and the second display area FH is refreshed at 60 Hz.

[0272] From the above three scenarios, it can be determined that, based on the shift register including the second output circuit 32, by adjusting the timing of the control signal output by a control signal terminal Ctrl, it is possible to flexibly control all sub-pixels of the display panel to refresh at a higher frequency or a lower frequency, as well as to refresh a part of the sub-pixels at a higher frequency and another part of the sub-pixels at a lower frequency.

[0273] In this way, the electronic device can flexibly control the refresh rate of each display area of ​​the display panel. When the display image of the display panel remains unchanged at least partially, the refresh rate of the sub-pixels in the area where the display image remains unchanged can be reduced by cooperating with the Source IC, thereby achieving the effect of reducing the display power consumption of the display panel and improving the reliability of the display image of the display panel.

[0274] An embodiment of the present application further provides an electronic device. The electronic device may include a battery and the display panel described above. The battery may power the display panel, thereby causing the display panel to emit light and display.

[0275] The electronic device may include at least one of a mobile phone, a foldable electronic device, a tablet computer, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a personal digital assistant (PDA), an augmented reality (AR) device, a virtual reality (VR) device, an artificial intelligence (AI) device, a wearable device, an in-vehicle device, a smart home device, or a smart city device. The embodiment of the present application does not impose any particular limitation on the specific type of the electronic device 100.

[0276] Figure 18 A possible structural diagram of the electronic device involved in the above embodiments is shown. Figure 18 The electronic device 2100 shown includes a controller 201 and a storage module 203 .

[0277] The controller 201 may be a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The controller may include an application processor and a baseband processor. It may implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The controller may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like. The storage module 203 may be a memory, such as a register.

[0278] Figure 19 A possible structural diagram of the controller involved in the above embodiment is shown.

[0279] The present application also provides a controller (eg, SoC), such as Figure 19As shown, the controller may include at least one processor 701 and at least one interface circuit 702. The processor 701 and the interface circuit 702 may be interconnected via lines. For example, the interface circuit 702 may be used to receive signals from other devices (such as a storage module of an electronic device). For another example, the interface circuit 702 may be used to send signals to other devices (such as the processor 701 or an antenna assembly). Exemplarily, the interface circuit 702 may read instructions stored in the memory and send the instructions to the processor 701. When the instructions are executed by the processor 701, the electronic device may execute the various steps in the above embodiments. Of course, the controller may also include other discrete components, which are not specifically limited in the embodiments of the present application.

[0280] An embodiment of the present application also provides a computer-readable storage medium, which includes computer instructions. When the computer instructions are executed on the above-mentioned electronic device, the electronic device executes the various functions or steps executed by the electronic device in the above-mentioned method embodiment.

[0281] The present application also provides a computer program product, which, when executed on a computer, enables the computer to execute the functions or steps executed by the electronic device in the above method embodiment. For example, the computer may be the above electronic device.

[0282] Through the description of the above implementation methods, technical personnel in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0283] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0284] Units described as separate components may or may not be physically separate, and components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0285] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0286] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0287] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0288] The above is only a specific embodiment of the present application, but the scope of protection of this application is not limited to this. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A display method, characterized in that: Applicable to an electronic device having a display panel, the display panel including a first display area and a second display area, the first display area and the second display area not overlapping each other; the method comprising: During the display process of the display panel, the picture of the first display area is refreshed at a first refresh rate, and the picture of the second display area is refreshed at a second refresh rate; the first refresh rate is lower than the second refresh rate.

2. The method according to claim 1, characterized in that The display panel includes a plurality of scan signal lines, each scan signal line extending along a first direction, the plurality of scan signal lines being arranged side by side along a second direction, and the first direction intersecting the second direction; In the second direction, the first display area is located on at least one side of the second display area.

3. The method according to claim 2, characterized in that The plurality of scan signal lines include a first scan signal line and a second scan signal line, wherein the first scan signal line is at least partially located in the first display area, and the second scan signal line is at least partially located in the second display area; The step of refreshing the image of the first display area at a first refresh rate and refreshing the image of the second display area at a second refresh rate includes: During a frame refresh cycle of the display panel, the second scan signal line controls the connected multiple sub-pixels to emit light based on the data signal received in the current cycle, and the first scan signal line controls the connected multiple sub-pixels to emit light based on the data signal received in the previous cycle.

4. The method according to any one of claims 1 to 3, characterized in that The first refresh rate is less than or equal to 10 Hz.

5. A shift register, characterized in that: include: A first output circuit is coupled to the input signal terminal, the first clock signal terminal, the second clock signal terminal, the first voltage terminal and the second voltage terminal; The first output circuit is configured to output a first output signal under common control of the input signal output by the input signal terminal, the first clock signal output by the first clock signal terminal, and the second clock signal output by the second clock signal terminal; a second output circuit coupled to the first output circuit, the third voltage terminal, the fourth voltage terminal, and the control signal terminal; the second output circuit being configured to output a second output signal under the control of at least a signal provided by the first output circuit and a control signal output by the control signal terminal; The change state of the second output signal is the same as the change state of the first output signal, or the second output signal is an invalid signal.

6. The shift register according to claim 5, wherein: The second output circuit includes: a logic sub-circuit coupled to at least the control signal terminal and the first node of the first output circuit; the logic sub-circuit being configured to output a logic signal under the control of a control signal outputted from the control signal terminal and a level signal provided by the first node; An output sub-circuit is coupled to the third voltage terminal, the fourth voltage terminal, the logic sub-circuit and the second node of the first output circuit; the output sub-circuit is configured to output the second output signal under the control of the logic signal output by the logic sub-circuit and the level signal provided by the second node.

7. The shift register according to claim 6, wherein: The logic sub-circuit is coupled to the control signal terminal, the output terminal of the first output circuit, the first voltage terminal and the first node respectively; the logic sub-circuit is configured to output the logic signal under the control of the first output signal output by the first output circuit, the control signal provided by the control signal terminal and the level signal provided by the first node.

8. The shift register according to claim 7, wherein: The logic sub-circuit comprises: a first logic transistor, wherein a first electrode of the first logic transistor is coupled to the first voltage terminal, and a control electrode of the first logic transistor is coupled to the output terminal of the first output circuit; a second logic transistor, wherein a first electrode of the second logic transistor is coupled to the second voltage terminal, a control electrode of the second logic transistor is coupled to the first node of the first output circuit, and a second electrode of the second logic transistor is coupled to a fourth node; A third logic transistor, wherein a first electrode of the third logic transistor is coupled to the second electrode of the first logic transistor, a control electrode of the third logic transistor is coupled to the control signal terminal, and a second electrode of the third logic transistor is coupled to the fourth node.

9. The shift register according to claim 6, wherein: The logic sub-circuit is coupled to the control signal terminal, the first node and the third node of the first output circuit, and the second voltage terminal respectively; the logic sub-circuit is configured to output the logic signal under the control of the control signal provided by the control signal terminal, the level signal provided by the first node, and the level signal provided by the third node.

10. The shift register according to claim 9, wherein: The logic sub-circuit comprises: a fourth logic transistor, wherein a first electrode of the fourth logic transistor is coupled to the third node of the first output circuit, a control electrode of the fourth logic transistor is coupled to the control signal terminal, and a second electrode of the fourth logic transistor is coupled to the fourth node; A fifth logic transistor, wherein a first electrode of the fifth logic transistor is coupled to the second voltage terminal, a control electrode of the fifth logic transistor is coupled to the first node of the first output circuit, and a second electrode of the fifth logic transistor is coupled to the fourth node.

11. The shift register according to any one of claims 6 to 10, characterized in that: The output sub-circuit comprises: a first output transistor, wherein a first electrode of the first output transistor is coupled to the fourth voltage terminal, a control electrode of the first output transistor is coupled to the fourth node, and a second electrode of the first output transistor is coupled to the output terminal of the second output circuit; A second output transistor, wherein a first electrode of the second output transistor is coupled to the third voltage terminal, a control electrode of the second output transistor is coupled to the second node of the first output circuit, and a second electrode of the second output transistor is coupled to the output terminal of the second output circuit.

12. A scan driving circuit, characterized in that: The invention comprises a plurality of mutually cascaded shift registers, wherein the shift register is the shift register according to any one of claims 5 to 11.

13. A display panel, characterized in that: include: A plurality of sub-pixels, wherein the plurality of sub-pixels are arranged in an array of multiple rows and columns; A scan driving circuit is coupled to the plurality of sub-pixels via a plurality of scan signal lines, each of the scan signal lines being coupled to a plurality of sub-pixels located in the same row; wherein the scan driving circuit comprises the scan driving circuit as claimed in claim 12.

14. An electronic device, characterized in that: include: A display panel comprising the display panel according to claim 13; A battery is coupled to the display panel; the battery is used to supply power to the display panel.

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