Display driving device and display comprising same
By introducing multiple drivers and relay controllers with low signal processing capabilities into the display driving device, the high cost problem caused by too many timing controllers in the prior art is solved, and the layout cost and size are reduced while maintaining the picture driving effect.
Patent Information
- Application Number
- CN202411567252.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-03-20
- Filing Date
- 2024-11-05
- Publication Date
- 2025-09-23
AI Technical Summary
In existing display driving devices, the architecture of disposing a timing controller for each display area results in excessively high overall layout costs.
Multiple drivers and a relay controller with low signal processing capability are used to receive and parse the output display image through the relay controller, reducing the number of timing controllers used and reducing layout size and cost.
By using a relay controller, the layout cost and size of the display driver device are reduced while maintaining the screen driving function, achieving cost-effectiveness.
Smart Images
Figure CN120690156A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a driving device, in particular to a display driving device. Background Art
[0002] In the current display driver architecture, a master chip typically scales and cuts the image before transmitting it to a timing controller. The timing controller then amplifies and compensates the received image data and outputs it to subsequent driver components for display. A timing controller is required for each display area.
[0003] However, the architecture of setting a timing controller for each display area will result in excessively high overall layout costs. Summary of the Invention
[0004] In view of the above, the present invention provides a display driving device and a display.
[0005] According to one embodiment of the present invention, a display driver device is applicable to at least one display area and includes multiple drivers, at least one timing controller, and at least one relay controller. The relay controller is connected to the at least one timing controller and the multiple drivers. The multiple drivers are respectively used to drive multiple pixels in the at least one display area. The at least one timing controller is used to obtain a first addressing display signal for the multiple pixels and generate a second addressing display signal based on the first addressing display signal. The relay controller is used to transmit at least a portion of the second addressing display signal to the multiple drivers to drive the at least one display area based on multiple address information in the second addressing display signal. The signal processing capability of the relay controller is lower than that of the timing controller.
[0006] A display according to an embodiment of the present invention includes the display driving device and at least one display area, wherein the at least one display area is connected to and controlled by the display driving device.
[0007] Through the above structure, the display driving device and display disclosed in this case can receive and analyze the output display screen by using a relay controller with lower signal processing capabilities than the timing controller, and then output the analyzed display screen to multiple drivers to drive at least one display area. This display driving device can reduce the number of timing controllers used and the device cost and effectively reduce the layout size and layout cost.
[0008] The above description of the content of the present invention and the following description of the embodiments are intended to demonstrate and explain the spirit and principles of the present invention, and to provide further explanation of the claims of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Figure 1 FIG. 1 is a block diagram of a display driving device according to an embodiment of the present invention.
[0010] Figure 2 FIG. 1 is a block diagram of a relay controller according to an embodiment of the present invention.
[0011] Figure 3 FIG. 2 is a block diagram of a display driving device according to another embodiment of the present invention.
[0012] Figure 4 FIG. 4 is a block diagram of a relay controller according to another embodiment of the present invention.
[0013] Figure 5 FIG. 4 is a block diagram of a display driving device according to yet another embodiment of the present invention.
[0014] Figure 6 FIG. 1 is a block diagram of a display according to an embodiment of the present invention. DETAILED DESCRIPTION
[0015] The following detailed description of the features and advantages of the present invention is sufficient to enable any person skilled in the art to understand the technical content of the present invention and implement it accordingly. Furthermore, based on the disclosure of this specification, the claims, and the accompanying drawings, any person skilled in the art can easily understand the relevant objects and advantages of the present invention. The following examples further illustrate the concepts of the present invention but are not intended to limit the scope of the present invention in any way.
[0016] Please refer to Figure 1 , Figure 1 FIG. 1 is a block diagram of a display driving device according to an embodiment of the present invention. Figure 1 As shown, the display driving device 1 is applicable to at least one display area DA and includes a timing controller 11, at least one relay controller 12 and a plurality of drivers 13. The relay controller 12 is connected to the timing controller 11 and the plurality of drivers 13, and the plurality of drivers 13 are connected to the display area DA to respectively drive a plurality of pixels in the display area DA. It should be noted that Figure 1 While the number of drivers is 2 for the present example, the present invention is not limited thereto. Specifically, the number of drivers may depend on the number of pixels in each display area. Assuming each display area has P pixels, the number of drivers is P, where P is a natural number greater than 1.
[0017] The timing controller 11 is used to obtain first addressing display signals for multiple pixels in the display area DA and generate second addressing display signals based on the first addressing display signals. Specifically, after obtaining the first addressing display signals for the multiple pixels from the main control chip, the timing controller 11 can amplify and compensate the first addressing display signals to increase pixel resolution and generate the second addressing display signals. The main control chip can also be called a scaler. Furthermore, the timing controller 11 can temporarily store the data obtained from the amplification and compensation of the multiple pixels in a memory (e.g., dynamic random access memory or read-only memory).
[0018] The relay controller 12 is used to transmit at least a portion of the second addressing display signal to multiple drivers 13 to drive the display area DA based on multiple address information in the second addressing display signal. Specifically, the multiple address information of the second addressing display signal may be the arrangement positions (display positions) of the pixels driven by the multiple drivers, such as coordinates. In one embodiment, each driver 13 can capture a target portion of at least a portion of the second addressing display signal based on partial address information of at least a portion of the second addressing display signal received from the relay controller 12, and drive the corresponding pixel in the display area DA based on the target portion. In this embodiment, the driver 13 may have a processing unit for performing the above-mentioned capture, such as a microcontroller. In another embodiment, the relay controller 12 may divide at least a portion of the second addressing display signal into multiple sub-signals based on the multiple address information of the second addressing display signal, and transmit these sub-signals to the multiple drivers 13 respectively.
[0019] The relay controller 12 has lower signal processing capabilities than the timing controller 11. Furthermore, the relay controller 12 may not perform image enhancement or compensation, meaning it lacks these capabilities. Therefore, the relay controller 12 can be smaller than the timing controller 11, reducing the overall circuit layout cost of the display.
[0020] Please refer to Figure 2 , Figure 2 FIG1 is a block diagram of a relay controller according to an embodiment of the present invention. The relay controller 12 may include a signal input port 121, a decoder 122, a serial-to-parallel converter 123, and a plurality of signal output ports 124. The signal input port 121 may be connected to Figure 1 The decoder 122 can be connected to the signal input port 121 and the serial-to-parallel converter 123, and the serial-to-parallel converter 123 can also be connected to the plurality of signal output ports 124. The plurality of signal output ports 124 can be connected to Figure 1 The multiple drivers 13.
[0021] The signal input port 121 is used to receive the signal from Figure 1 The decoder 122 is used to generate a third addressing display signal according to the multiple address information of the second addressing display signal and the second addressing display signal. Specifically, the decoder 122 can parse the address information carried by the second addressing display signal, extract the partial signal corresponding to the address information of the connected driver 13 from the second addressing display signal (as the aforementioned third addressing display signal), and transmit the extracted partial signal to the serial-to-parallel converter 123. The serial-to-parallel converter 123 is used to convert the third addressing display signal from the decoder 122 into a plurality of parallel signals to realize high-speed to low-speed signal transmission, and output the plurality of parallel signals to the plurality of signal output ports 124 through the plurality of signal output ports 124. Figure 1 The plurality of drivers 13 in the relay port 121. Furthermore, the signal input port 121 and the signal output port 124 can use low-voltage differential signaling (LVDS) transmission technology to transmit signals. LVDS is applicable to different electronic signal systems and uses low swing and low current operation to drive signal transmission and uses a data transmission rate ranging from Mbps to Gbps and a 2 volt system voltage to transmit signals at a high data transmission rate and low system voltage, thereby achieving low noise, low power consumption and low interference. In another embodiment, the relay controller 12 may further include a control interface in addition to the above components. The control interface can be connected to the decoder 122 and can allow the user to set the address information used by the decoder 122 for signal acquisition.
[0022] Please refer to Figure 3 , Figure 3 FIG. 1 is a block diagram of a display driving device according to another embodiment of the present invention. Figure 3 As shown, the display driving device 2 may include a timing controller 21, a plurality of relay controllers 22_A and 22_B, and a plurality of drivers 23. The relay controller 22_A may be connected to the timing controller 21, the relay controller 22_B, and the first part of the plurality of drivers 23, and the first part of the plurality of drivers 23 may be connected to the display area DA1; the relay controller 22_B may be connected to the second part of the plurality of drivers 23, and the second part of the plurality of drivers 23 may be connected to the display area DA2. The timing controller 21, the plurality of relay controllers 22_A and 22_B, the plurality of drivers 23, and the display areas DA1 and DA2 may be connected to the display area DA1. Figure 1The structures, connection relationships and functions of the corresponding elements of the embodiment are roughly the same, and the same parts will not be repeated here. In this embodiment, the signal output port in the relay controller 22_A can be connected to the signal input port in the relay controller 22_B, and the relay controller 22_A can be used to transmit at least a portion of the second addressing display signal to the relay controller 22_B. Specifically, the signal transmitted from the relay controller 22_A to the relay controller 22_B can be a complete second addressing display signal or a remaining signal after removing the signal required by the relay controller 22_A from the second addressing display signal according to the address information. In this embodiment, the timing controller 11 can respectively enhance, compensate and output the display images of the multiple display areas DA1 and DA2 to generate a second addressing display signal, which is then handed over to the multiple relay controllers 22_A and 22_B for analysis and conversion and then transmitted to the subsequent driver 23. It should be particularly noted here that, Figure 3 In this example, two relay controllers are provided, and each relay controller is connected to two drivers, but the present invention is not limited thereto. As previously mentioned, the number of drivers may depend on the number of pixels in each display area. The number of timing controllers may also depend on the number of display areas.
[0023] Please refer to Figure 3 and Figure 4 , Figure 4 FIG. 1 is a block diagram of a relay controller according to another embodiment of the present invention. Figure 4 As shown, the relay controller 22 includes a signal input port 221, a decoder 222, a serial-to-parallel converter 223, a first output port 224_1, and a plurality of second output ports 224_2. The signal input port 221 can be connected to the first output port 224_1, the decoder 222 can be connected to the signal input port 221 and the serial-to-parallel converter 223, and the serial-to-parallel converter 223 can also be connected to the plurality of second output ports 224_2. The signal input port 221, the decoder 222, and the serial-to-parallel converter 223 can be connected to the plurality of second output ports 224_2. Figure 2 The structures, connection relationships and functions of the corresponding elements in the embodiments are substantially the same, and the similarities are not repeated here.
[0024] In this embodiment, the relay controller 22 is connected to the signal input port of another relay controller through the first output port 224_1, and is connected to multiple drivers through multiple second output ports 224_2. Figure 3For example, the relay controller 22_A in the embodiment of the present invention is used as an example. The first output port 224_1 can be connected to the signal input port of the relay controller 22_B, and the second output port 224_2 can be connected to the driver 23. The relay controller 22_A can receive the second addressing display signal from the timing controller 21 through the signal input port 221, and transmit the second addressing display signal to the relay controller 22_B through the first output port 224_1. The second addressing display signal is parsed and converted by the decoder 222 and the serial-to-parallel converter 223, and the parsed and converted parallel signal is then transmitted to the driver 23 through the second output port 224_2 to drive the display area DA1. The specific implementation of the parsing and conversion is as described above. Figure 2 The embodiments are described in detail and will not be described in detail here.
[0025] Please refer to Figure 5 , Figure 5 It is a block diagram of a display driving device according to another embodiment of the present invention. The display driving device 3 includes a plurality of timing controllers 31_A and 31_B, a plurality of relay controllers 32_A and 32_B and a plurality of drivers 33. Among them, the relay controller 32_A and the relay controller 32_B are connected to the main control chip M1, the relay controller 32_A can be connected to the timing controller 31_A and the first part of the plurality of drivers 33, and the first part of the plurality of drivers 33 can be respectively connected to the display area DA3; the relay controller 32_B can be connected to the timing controller 31_B and the second part of the plurality of drivers 33, and the second part of the plurality of drivers 33 can be respectively connected to the display area DA4. The respective implementation methods of the timing controllers 31_A / 31_B, the relay controllers 32_A / 32_B and the drivers 33 connected to the relay controllers 32_A / 32_B and their coordinated operation with each other can be roughly the same as those in the aforementioned embodiment, and the same parts will not be repeated here. It should be particularly noted here that, Figure 5 By way of example, the number of timing controllers and relay controllers is 2, and the number of drivers connected to each relay controller is 2, but the present invention is not limited thereto. As mentioned above, the number of drivers may depend on the number of pixels in each display area. The number of timing controllers and relay controllers may depend on the number and arrangement of display areas. For a plurality of display areas arranged in an M×N matrix, the number of timing controllers may be M and the number of relay controllers may be N, or the number of timing controllers may be N and the number of relay controllers may be M, where M and N are both natural numbers greater than 1.
[0026] In this embodiment, the timing controllers 31_A and 31_B can be connected in parallel to the main control chip M1, each receiving a first addressing display signal from the main control chip M1. Specifically, the main control chip M1 can generate a first addressing display signal corresponding to display area DA3 and a first addressing display signal corresponding to display area DA4, transmit the first addressing display signal corresponding to display area DA3 to the relay controller 32_A, and transmit the first addressing display signal corresponding to display area DA4 to the relay controller 32_B. In another embodiment, the timing controllers 31_A and 31_B can be connected in series to the main control chip M1. When the timing controller 31_A receives a display signal, it transmits the display signal to the timing controller 31_B. Specifically, the main control chip M1 generates a first addressing display signal carrying the address information corresponding to display area DA3 and the address information corresponding to display area DA4, and transmits it to the timing controller 31_A. The timing controller 31_A can extract a signal segment containing address information corresponding to the display area DA3 from the first address display signal and generate a second address display signal accordingly. The timing controller 31_A then transmits the first address display signal to the serially connected timing controller 31_B. The timing controller 31_B can extract a signal segment containing address information corresponding to the display area DA4 from the first address display signal and generate a second address display signal accordingly.
[0027] Please refer to Figure 6 , Figure 6 This is a block diagram of a display according to one embodiment of the present invention. Display 100 may include a display driver device 1 and at least one display area DA, connected to and controlled by display driver device 1. Display driver device 1 may be implemented as any of the display driver devices described in the preceding embodiments. Furthermore, the size of display area DA can be adjusted as needed and is not limited to a fixed size.
[0028] Through the above structure, the display driving device and display disclosed in this case can receive and analyze the output display screen by using a relay controller with lower signal processing capabilities than the timing controller, and then output the analyzed display screen to multiple drivers to drive at least one display area. This display driving device can reduce the number of timing controllers used and the device cost and effectively reduce the layout size and layout cost.
[0029]
Explanation of symbols
[0030] 1,2,3: Display driver
[0031] 11,21,31_A,31_B: Timing controller
[0032] 12,22_A,22_B,32_A,32_B: Relay controller
[0033] 13,23,33:Drive
[0034] 100: Display
[0035] 121,221:Signal input port
[0036] 122,222:Decoder
[0037] 123,223:Serial-to-parallel converter
[0038] 124:Signal output port
[0039] 224_1: First output port
[0040] 224_2: Second output port
[0041] DA,DA1,DA2,DA3,DA4: Display area
[0042] M1: main control chip.
Claims
1. A display driving device, applicable to at least one display area, characterized in that: Include: a plurality of drivers, each for driving a plurality of pixels in the at least one display area; At least one timing controller, configured to obtain a first addressing display signal of the plurality of pixels and generate a second addressing display signal according to the first addressing display signal; as well as at least one relay controller connected to the at least one timing controller, configured to transmit at least a portion of the second addressing display signal to the plurality of drivers to drive the at least one display area according to a plurality of address information in the second addressing display signal; The signal processing capability of the at least one relay controller is lower than that of the timing controller.
2. The display driving device according to claim 1, wherein the at least one relay controller comprises: a signal input port connected to the at least one timing controller, and configured to receive the second addressing display signal; Multiple signal output ports; a decoder connected to the signal input port and configured to generate a third addressing display signal according to the plurality of address information and the second addressing display signal; as well as A serial-to-parallel converter is connected to the decoder and at least a portion of the multiple signal output ports, and is used to convert the third addressing display signal into a plurality of parallel signals, and output the plurality of parallel signals to the multiple drivers through the at least a portion of the multiple signal output ports. 3 . The display driving device according to claim 2 , wherein the signal input port and the plurality of signal output ports utilize a low voltage differential signal transmission technology.
4. The display driving device according to claim 2 , wherein the number of the at least one relay controller is plural, and the plurality of signal output ports of one of the at least one relay controller comprises: a first output port connected to the signal input port and the signal input port of the other of the at least one relay controller; and A plurality of second output ports are connected to the serial-to-parallel converter and are respectively connected to the plurality of drivers.
5. The display driving device according to claim 1, wherein the number of the at least one relay controller is multiple, the signal output port of the first relay controller among the at least one relay controller is connected to the signal input port of the second relay controller among the at least one relay controller, and the first relay controller is also used to transmit at least a part of the second addressing display signal to the second relay controller.
6. The display driving device according to claim 1, wherein each of the plurality of drivers is configured to capture a target portion of the at least a portion of the second addressing display signal according to a portion of the plurality of address information in the at least a portion of the second addressing display signal, and drive the at least one display area according to the target portion.
7. The display driving device according to claim 1, wherein the at least one relay controller is used to divide the at least a portion of the second addressed display signal into a plurality of sub-signals according to the plurality of address information, and transmit the plurality of sub-signals to the plurality of drivers respectively. 8 . The display driving device according to claim 1 , wherein the at least one relay controller does not perform image enhancement and compensation.
9. A display, characterized in that: Include: The display driving device according to any one of claims 1 to 8; and The at least one display area is connected to and controlled by the display driving device.