Memory, operation method thereof and memory system

Abstract

The embodiment of the invention provides a memory, an operation method thereof and a memory system. The memory includes a memory cell array including: a plurality of memory cells; a peripheral circuit coupled to the memory cell array through a plurality of bit lines and a plurality of word lines; the peripheral circuit is configured to: in response to a read command, apply a bit line compensation read voltage to a first bit line of the plurality of selected bit lines; wherein in the plurality of selected memory cells coupled with the selected word line, the threshold voltage of at least one selected memory cell adjacent to the selected memory cell coupled with the first bit line is greater than a preset voltage; applying a bit line read voltage to the second bit line in response to the read command; wherein the second bit line is a bit line except the first bit line in the plurality of selected bit lines; the bit line compensation read voltage is greater than the bit line read voltage.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a memory, an operating method thereof, and a memory system. Background Art

[0002] The semiconductor integrated circuit industry has experienced rapid growth in recent years. With the continuous advancement of semiconductor manufacturing processes, the feature sizes of semiconductor devices have continued to shrink, and the integration density of memory has also increased. For example, non-volatile semiconductor memory is widely used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and various other electronic devices. With the advancement of informatization, the amount of data used by these devices has also increased rapidly, driving the demand for larger storage capacities and faster access speeds.

[0003] During a memory read operation, a read voltage applied to a word line is used to determine the threshold voltage of a memory cell, thereby obtaining the information stored in the memory cell. However, as the demand for memory performance continues to increase, many problems still exist when performing memory read operations. Summary of the Invention

[0004] The present disclosure provides a memory, an operating method thereof, and a memory system.

[0005] In a first aspect, the present disclosure provides a memory, comprising:

[0006] A memory cell array, comprising: a plurality of memory cells;

[0007] A peripheral circuit is coupled to the memory cell array via a plurality of bit lines and a plurality of word lines; the peripheral circuit is configured as follows:

[0008] In response to a read command, applying a bit line compensation read voltage to a first bit line among a plurality of selected bit lines; wherein, among a plurality of selected memory cells coupled to a selected word line, a threshold voltage of at least one of the selected memory cells adjacent to the selected memory cell coupled to the first bit line is greater than a predetermined voltage;

[0009] In response to the read command, a bit line read voltage is applied to a second bit line; wherein the second bit line is a bit line other than the first bit line among the plurality of selected bit lines; and the bit line compensation read voltage is greater than the bit line read voltage.

[0010] In some embodiments, the peripheral circuit is further configured to:

[0011] In response to the read command, the first bit line and the second bit line of the plurality of selected bit lines are determined.

[0012] In some embodiments, the peripheral circuit is specifically configured as follows:

[0013] Applying the preset voltage to the selected word line to obtain pre-read results of the plurality of selected memory cells; wherein the pre-read results include a first logic value, the first logic value being used to indicate that a threshold voltage of the memory cell is greater than the preset voltage;

[0014] In response to the pre-read result, the first bit line and the second bit line among the plurality of selected bit lines are determined.

[0015] In some embodiments, the peripheral circuit includes a control logic circuit; the control logic circuit is configured to:

[0016] Performing a logical operation on the pre-read result to generate an operation result; wherein the operation result includes first identification information, the first identification information being used to indicate that the number of the selected memory cells adjacent to the selected memory cell and having a threshold voltage greater than the preset voltage is greater than or equal to a preset value;

[0017] In response to the first identification information, a selected bit line coupled to the selected memory cell is determined to be the first bit line.

[0018] In some embodiments, the control logic circuit is specifically configured to:

[0019] In response to the pre-read result, determining the number of first logic values ​​corresponding to a plurality of the selected memory cells adjacent to the selected memory cell;

[0020] In response to the number of first logic values ​​corresponding to a plurality of the selected memory cells adjacent to one of the selected memory cells being greater than or equal to the preset value, the first identification information is generated.

[0021] In some embodiments, the operation result further includes second identification information, where the second identification information is used to indicate that the number of the selected memory cells adjacent to another selected memory cell and having a threshold voltage greater than the preset voltage is less than the preset value; and the control logic circuit is further configured to:

[0022] In response to the second identification information, a selected bit line coupled to another selected memory cell is determined to be the second bit line.

[0023] In some embodiments, the control logic circuit is specifically configured to:

[0024] In response to the pre-read result, determining the number of first logic values ​​corresponding to a plurality of the selected memory cells adjacent to another selected memory cell;

[0025] The second identification information is generated in response to the number of first logic values ​​corresponding to a plurality of the selected memory cells adjacent to another selected memory cell being smaller than the preset value.

[0026] In some embodiments, the peripheral circuit further includes:

[0027] A latch circuit is coupled to the control logic circuit; the latch circuit is configured to latch the operation result.

[0028] In some embodiments, the control logic circuit is further configured to:

[0029] determining the number of the selected memory cells adjacent to the selected memory cell and having a threshold voltage greater than the preset voltage;

[0030] The bit line compensation read voltage of the first bit line coupled to the selected memory cell is determined in response to the number of the selected memory cells adjacent to the selected memory cell and having a threshold voltage greater than the preset voltage.

[0031] In some embodiments, the pre-read result further includes a second logic value; and the peripheral circuit is specifically configured as follows:

[0032] generating the first logic value in response to a threshold voltage of the selected memory cell being greater than the preset voltage;

[0033] or,

[0034] In response to a threshold voltage of the selected memory cell being lower than the preset voltage, the second logic value is generated.

[0035] In some embodiments, the peripheral circuit is specifically configured as follows:

[0036] The preset voltage is applied to the selected word line, and the bit line read voltage is applied to the plurality of selected bit lines to obtain the pre-read result.

[0037] In some embodiments, the peripheral circuit is further configured to:

[0038] In response to the read command, a word line read voltage is applied to the selected word line, and the bit line compensation read voltage and the bit line read voltage are applied to the first bit line and the second bit line, respectively, to obtain a read result; wherein the word line read voltage is less than the preset voltage.

[0039] In a second aspect, the present disclosure provides a method for operating a memory, wherein the memory includes a memory cell array and a peripheral circuit coupled to the memory cell array, wherein the memory cell array includes a plurality of memory cells; the operating method includes:

[0040] In response to a read command, applying a bit line compensation read voltage to a first bit line among a plurality of selected bit lines; wherein, among a plurality of selected memory cells coupled to a selected word line, a threshold voltage of at least one of the selected memory cells adjacent to the selected memory cell coupled to the first bit line is greater than a predetermined voltage;

[0041] In response to the read command, a bit line read voltage is applied to a second bit line; wherein the second bit line is a bit line other than the first bit line among the plurality of selected bit lines; and the bit line compensation read voltage is greater than the bit line read voltage.

[0042] In some embodiments, the method further comprises:

[0043] In response to the read command, the first bit line and the second bit line of the plurality of selected bit lines are determined.

[0044] In some embodiments, determining the first bit line and the second bit line among the plurality of selected bit lines includes:

[0045] Applying the preset voltage to the selected word line to obtain pre-read results of the plurality of selected memory cells; wherein the pre-read results include a first logic value, the first logic value being used to indicate that a threshold voltage of the memory cell is greater than the preset voltage;

[0046] In response to the pre-read result, the first bit line and the second bit line among the plurality of selected bit lines are determined.

[0047] In some embodiments, determining the first bit line among the plurality of selected bit lines in response to the pre-read result includes:

[0048] Performing a logical operation on the pre-read result to generate an operation result; wherein the operation result includes first identification information, the first identification information being used to indicate that the number of the selected memory cells adjacent to the selected memory cell and having a threshold voltage greater than the preset voltage is greater than or equal to a preset value;

[0049] In response to the first identification information, a selected bit line coupled to the selected memory cell is determined to be the first bit line.

[0050] In some embodiments, performing a logical operation on the pre-read result to generate an operation result includes:

[0051] In response to the pre-read result, determining the number of first logic values ​​corresponding to a plurality of the selected memory cells adjacent to the selected memory cell;

[0052] In response to the number of first logic values ​​corresponding to a plurality of the selected memory cells adjacent to one of the selected memory cells being greater than or equal to the preset value, the first identification information is generated.

[0053] In some embodiments, the operation result further includes second identification information, where the second identification information is used to indicate that the number of the selected memory cells adjacent to another selected memory cell and having a threshold voltage greater than the preset voltage is less than the preset value; and the method further includes:

[0054] In response to the second identification information, a selected bit line coupled to another selected memory cell is determined to be the second bit line.

[0055] In some embodiments, performing a logical operation on the pre-read result to generate an operation result further includes:

[0056] In response to the pre-read result, determining the number of first logic values ​​corresponding to a plurality of the selected memory cells adjacent to another selected memory cell;

[0057] The second identification information is generated in response to the number of first logic values ​​corresponding to a plurality of the selected memory cells adjacent to another selected memory cell being smaller than the preset value.

[0058] In some embodiments, the method further comprises:

[0059] The operation result is latched.

[0060] In some embodiments, the method further comprises:

[0061] determining the number of the selected memory cells adjacent to the selected memory cell and having a threshold voltage greater than the preset voltage;

[0062] The bit line compensation read voltage of the first bit line coupled to the selected memory cell is determined in response to the number of the selected memory cells adjacent to the selected memory cell and having a threshold voltage greater than the preset voltage.

[0063] In some embodiments, the pre-read result further includes a second logic value; and obtaining the pre-read result of the plurality of selected memory cells includes:

[0064] generating the first logic value in response to a threshold voltage of the selected memory cell being greater than the preset voltage;

[0065] or,

[0066] In response to a threshold voltage of the selected memory cell being lower than the preset voltage, the second logic value is generated.

[0067] In some embodiments, applying the preset voltage to the selected word line to obtain pre-read results of the plurality of selected memory cells includes:

[0068] The preset voltage is applied to the selected word line, and the bit line read voltage is applied to the plurality of selected bit lines to obtain the pre-read result.

[0069] In some embodiments, the method further comprises:

[0070] In response to the read command, a word line read voltage is applied to the selected word line, and the bit line compensation read voltage and the bit line read voltage are applied to the first bit line and the second bit line, respectively, to obtain a read result; wherein the word line read voltage is less than the preset voltage.

[0071] In a third aspect, the present disclosure provides a memory system, comprising:

[0072] The memory according to any one of the above embodiments;

[0073] A memory controller is coupled to the memory.

[0074] In an embodiment of the present disclosure, the threshold voltage of at least one selected memory cell adjacent to a selected memory cell coupled to a first bit line is greater than a preset voltage. A peripheral circuit can apply a bit line compensation read voltage to a first bit line among the plurality of selected bit lines, and apply a bit line read voltage to a second bit line among the plurality of selected bit lines, wherein the bit line compensation read voltage is greater than the bit line read voltage. Thus, during a read operation, although the higher threshold voltage of an adjacent selected memory cell results in a higher voltage on the adjacent selected bit line, the bit line compensation read voltage applied to the first bit line can reduce the influence of the coupling effect caused by the higher voltage on the adjacent selected bit line, thereby increasing the read margin and improving the reliability of the memory in performing a read operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] Figure 1 A schematic diagram of a system with a memory provided in an embodiment of the present disclosure;

[0076] Figure 2a A schematic diagram of a memory card provided in an embodiment of the present disclosure;

[0077] Figure 2b A schematic diagram of a solid state drive (SSD) provided in an embodiment of the present disclosure;

[0078] Figure 3 A schematic diagram of a storage unit arrangement provided in an embodiment of the present disclosure;

[0079] Figure 4 A schematic diagram of a memory provided in an embodiment of the present disclosure;

[0080] Figure 5 A schematic diagram of a pre-read result and a calculation result generated by a peripheral circuit according to an embodiment of the present disclosure;

[0081] Figure 6 A schematic diagram of applying a preset voltage to a selected word line in a pre-pulse phase according to an embodiment of the present disclosure;

[0082] Figure 7 A schematic diagram of a flow chart of a peripheral circuit applying different bit line voltages to a first bit line and a second bit line, respectively, according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0083] To facilitate understanding of the present disclosure, exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0084] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of an actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0085] Generally, terms can be understood, at least in part, from their use in context. For example, depending, at least in part, on the context, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "the" can likewise be understood to convey singular usage or to convey plural usage, depending, at least in part, on the context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending, at least in part, on the context.

[0086] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0087] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0088] Figure 1 A schematic diagram of a system 100 having memory according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having memory therein.

[0089] like Figure 1 As shown in FIG, system 100 may include a host 108 and a memory system 102 having one or more memories 104 and a memory controller 106. Host 108 may be a processor (e.g., a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP))) of an electronic device. Host 108 may be configured to send data to or receive data from memory 104.

[0090] According to some embodiments, the memory controller 106 is coupled to the memory 104 and the host 108 and is configured to control the memory 104. The memory controller 106 can manage data stored in the memory 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital Memory Card (SD Card), a Compact Flash Card (CFCard), a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as a solid-state drive or an embedded Multi Media Card (eMMC), which is used as data storage for mobile devices such as smartphones, tablet computers, laptops, etc., as well as enterprise storage arrays.

[0091] The memory controller 106 may be configured to control operations of the memory 104, such as read, erase, and write (also known as programming) operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is further configured to process error correction codes (ECC) for data read from or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with a host (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with the host 108 through at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI Express (PCIE) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced System Device Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the Firewire protocol, etc.

[0092] The memory controller 106 and the one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash memory package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. Figure 2aIn one example shown in FIG, the memory controller 106 and the single memory 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (Personal Computer Memory Card International Association, PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a Multi Media Card (MMC), a Reduced-Size MMC (RS-MMC), a Micro Multi Media Card (MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a Universal Flash Storage (UFS), etc. The memory card 202 may also include a computer that connects the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in FIG. Figure 2b In another example shown in , the memory controller 106 and the plurality of memories 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0093] In the embodiments of the present disclosure, the memory may be a NAND flash memory, but it should be understood that the solution or technology of the present disclosure is not limited to application in NAND flash memory, and can be applied to other types of memory devices, such as Electrically Erasable Programmable Read-Only Memory (EEPROM), NOR flash memory, Phase Change Random Access Memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc.

[0094] In some embodiments, the read operation of the memory can be performed in a "page-by-page" manner, where a "page" corresponds to all memory cells coupled to a wordline (WL) in the memory cell array. Exemplarily, the peripheral circuit of the memory applies a wordline read voltage to a selected wordline among a plurality of wordlines, and applies a bitline read voltage to a selected bitline among a plurality of bitlines (BL), and then obtains the information stored in the selected memory cell by sensing the current on the selected bitline, wherein the selected wordline and the selected bitline are coupled to the selected memory cell. It should be noted that when performing a read operation, the peripheral circuit of the memory will only select one wordline at a time, but can select multiple bitlines, thereby simultaneously reading the information stored in multiple selected memory cells (i.e., "page-by-page reading"). In some embodiments, the selected word line may also be a word line layer among multiple word line layers stacked in a three-dimensional memory (such as 3D NAND), wherein each word line layer may be coupled to a plurality of memory cells arranged in an array along a first direction and a second direction, the first direction intersecting the second direction, and both the first direction and the second direction being parallel to the plane where the word line layer is located.

[0095] like Figure 3 As shown, the peripheral circuit applies a word line read voltage to the selected word line and a plurality of selected bit lines (not shown in FIG. Figure 3 (shown in the figure) applying a bitline read voltage can determine multiple selected memory cells (the selected memory cells correspond to the selected bitlines one-to-one), thereby reading the information in the multiple selected memory cells at the same time. However, in the case where there is at least one selected memory cell with a higher threshold voltage (such as greater than the preset voltage) among the multiple selected memory cells C2 (white markings) adjacent to a certain selected memory cell C1 (black markings), the voltage on the selected bitline coupled to the adjacent selected memory cell with a higher threshold voltage cannot drop or drops slowly during the sensing process (at this time, the voltage on the selected bitline coupled to the selected memory cell C2 is greater than the voltage on the selected bitline coupled to the selected memory cell C1). Due to the coupling effect between the bitlines (Bitline Coupling), the sensing process of the bitline coupled to the selected memory cell C1 will be affected, thereby reducing the read margin (Read Margin) and reducing the reliability of the memory. It can be understood that regardless of Figure 3Whether the threshold voltage of the selected memory cell C1 is greater than a preset voltage, as long as the threshold voltage of at least one selected memory cell C2 adjacent to the selected memory cell C1 is greater than the preset voltage, coupling will occur to the selected bit line coupled to the selected memory cell C1 during the sensing process, thereby affecting the read margin. In some embodiments, the memory can reduce the problem of reduced read margin caused by the larger threshold voltages of adjacent selected memory cells and the bit line coupling effect by performing multiple reads. However, this method increases the read operation time, resulting in a decrease in memory access speed.

[0096] like Figure 4 As shown, the present disclosure provides a memory 100, which includes: a memory cell array 110, including: a plurality of memory cells; a peripheral circuit 120, coupled to the memory cell array 110 through a plurality of bit lines and a plurality of word lines; the peripheral circuit 120 is configured to: apply a bit line compensation read voltage to a first bit line among a plurality of selected bit lines in response to a read command; wherein, among a plurality of selected memory cells coupled to a selected word line, a threshold voltage of at least one of the selected memory cells adjacent to the selected memory cell coupled to the first bit line is greater than a preset voltage; apply a bit line read voltage to a second bit line in response to the read command; wherein, the second bit line is a bit line other than the first bit line among the plurality of selected bit lines; and the bit line compensation read voltage is greater than the bit line read voltage.

[0097] In the embodiment of the present disclosure, the peripheral circuit 120 may be coupled to each memory cell in the memory cell array 110 through a plurality of word lines and a plurality of bit lines. Figure 4 As shown, the peripheral circuit 120 may include a page buffer (PB) 121, a column decoder / bit line driver 122, a row decoder / word line driver 123, a voltage generator 124, a control logic circuit 125, a register 126, an interface 127 and a data bus 128. In other embodiments, the peripheral circuit 120 may also include Figure 4Additional peripheral circuits not shown in the figure are also provided. The voltage generator 124 can generate operating voltages of various levels. For example, during a read operation, the voltage generator 124 can generate operating voltages of various levels, such as a read voltage and a pass voltage. The row decoder / word line driver 123 can electrically communicate with the voltage generator 124 and the memory cell array 110. The row decoder 123 can select one of the multiple word lines (i.e., the selected word line in the above embodiment) in response to a row address generated by the control logic circuit 125 and transmit the operating voltage provided by the voltage generator 124 to the selected word line. The page buffer 121 can electrically communicate with the memory cell array 110 via bit lines. In response to page buffer control signals generated by the control logic circuit 125, the page buffer 121 can precharge the bit lines with corresponding voltages, transmit and receive data to and from selected memory cells during programming and read operations, or temporarily store transmitted data. The column decoder / bit line driver 122 can transmit and receive data to and from the page buffer 121 or exchange data with the data bus 128. The interface 127 may transmit commands and addresses received from an external device (e.g., a memory controller) to the control logic circuit 125. The interface 127 may also transmit data from the external device to the column decoder 122 or output data from the column decoder 122 to the external device via the data bus 128. The control logic circuit 125 may control the peripheral circuits in response to the commands and addresses. The register 126 may be coupled to the control logic circuit 125 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit.

[0098] Before performing a read operation, the peripheral circuit 120 may first obtain the threshold voltages of a plurality of selected memory cells coupled to the selected word line and the selected bit line, and determine whether the threshold voltages of these selected memory cells are greater than a preset voltage. The preset voltage may be determined based on actual test results of the product or a reference value provided by the designer. For any selected memory cell (e.g. Figure 3 The selected memory cell C1 in the example is selected, if at least one selected memory cell adjacent to it (such as Figure 3 If the threshold voltage of the selected memory cell C2 in the memory is greater than the preset voltage, the bit line coupled to the selected memory cell (C1) can be determined as the first bit line. Figure 3As just one example, in an actual read operation, if the threshold voltage of the selected memory cell C1 is also greater than a preset voltage, the bit line coupled to the selected memory cell C2 can also be determined as the first bit line. In this way, the peripheral circuit 120 can determine all first bit lines and determine the other selected bit lines among the selected bit lines except the first bit line as second bit lines. The peripheral circuit 120 can apply a bit line compensation read voltage to the first bit line in response to a read command, and apply a bit line read voltage to the second bit line in response to a read command, and the bit line compensation read voltage is greater than the bit line read voltage. In other words, the peripheral circuit 120 can perform a compensation read on the first bit line affected by the larger threshold voltage of the adjacent selected memory cell and the bit line coupling effect during the read operation, thereby making the final read result more accurate and improving the read margin. Here, the bit line compensation read voltage can be determined based on the bit line read voltage, such as the bit line compensation read voltage can be obtained by adding the compensation voltage to the bit line read voltage. The specific compensation voltage value can be adjusted according to actual conditions.

[0099] It is understood that because the threshold voltage of at least one selected memory cell adjacent to the selected memory cell coupled to the first bit line is greater than a preset voltage, the coupling effect between the selected bit line coupled to the at least one adjacent selected memory cell and the first bit line may cause an error in the read result of the selected memory cell coupled to the first bit line. In this case, the peripheral circuit 120 may apply a bit line compensation read voltage to a first bit line among the multiple selected bit lines, and apply a bit line read voltage to a second bit line among the multiple selected bit lines, wherein the bit line compensation read voltage is greater than the bit line read voltage. In this way, during a read operation, although the higher threshold voltage of the adjacent selected memory cell may result in a higher voltage on the adjacent selected bit line, the bit line compensation read voltage applied to the first bit line can reduce the impact of the coupling effect caused by the higher voltage on the adjacent selected bit line, thereby improving the read margin and enhancing the reliability of the memory read operation.

[0100] In some embodiments, the peripheral circuit 120 is further configured to: determine the first bit line and the second bit line of the plurality of selected bit lines in response to the read command.

[0101] In the embodiment of the present disclosure, the peripheral circuit 120 may also be configured to determine the first bit line and the second bit line among the plurality of selected bit lines in response to a read command. Here, the read command may come from outside the memory, such as a memory controller or a host, and the peripheral circuit 120 may determine the selected word line and the selected bit line based on the read command and the corresponding address. In addition, when the peripheral circuit 120 receives the read command, it may first obtain the threshold voltages of the plurality of selected memory cells coupled to the selected word line and the selected bit line before performing the read operation, and determine whether the threshold voltages of the selected memory cells are greater than a preset voltage. For any selected memory cell (such as Figure 3 The selected memory cell C1 in the example is selected, if at least one selected memory cell adjacent to it (such as Figure 3 If the threshold voltage of the selected memory cell (C2) in the memory is greater than a preset voltage, the bit line coupled to the selected memory cell (C1) can be determined as the first bit line. The peripheral circuit 120 can also determine other selected bit lines among the selected bit lines except the first bit line as second bit lines, so that during a read operation, a bit line compensation read voltage and a bit line read voltage are applied to the first bit line and the second bit line, respectively.

[0102] In some embodiments, the peripheral circuit 120 is specifically configured to: apply the preset voltage to the selected word line to obtain a pre-read result of the multiple selected memory cells; wherein the pre-read result includes a first logic value, and the first logic value is used to indicate that the threshold voltage of the memory cell is greater than the preset voltage; in response to the pre-read result, determine the first bit line and the second bit line among the multiple selected bit lines.

[0103] In some embodiments, the pre-read result also includes a second logic value; the peripheral circuit 120 is specifically configured to: generate the first logic value in response to the threshold voltage of the selected memory cell being greater than the preset voltage; or generate the second logic value in response to the threshold voltage of the selected memory cell being less than the preset voltage.

[0104] In an embodiment of the present disclosure, the peripheral circuit 120 can determine the first bit line and the second bit line among a plurality of selected bit lines by pre-reading. For example, before performing a read operation, the peripheral circuit 120 can apply a preset voltage to the selected word line, thereby obtaining a pre-read result of a plurality of selected memory cells. If the threshold voltage of the selected word line is greater than the preset voltage, a first logic value of the pre-read result is generated; if the threshold voltage of the selected word line is less than the preset voltage, a second logic value of the pre-read result is generated. Among them, the first logic value can be "1" and the second logic value can be "0"; in some other embodiments, the first logic value can also be "0" and the second logic value can be "1". For ease of understanding, the present disclosure uses the first logic value as "1" and the second logic value as "0" for illustrative purposes. That is, the first logic value "1" indicates that the threshold voltage of the corresponding selected memory cell is greater than the preset voltage, and in a selected memory cell (such as Figure 3 When the pre-read result of at least one selected memory cell adjacent to the selected memory cell C1 in the example is the first logic value "1", the peripheral circuit 120 may determine that the selected memory cell (e.g. Figure 3 The selected bit line coupled to the selected memory cell C1 in the memory cell 10 is the first bit line. It is understood that the peripheral circuit 120 can simultaneously determine multiple first bit lines based on the pre-read results of all selected memory cells, and determine the selected bit lines other than the first bit line among the multiple selected bit lines as the second bit lines.

[0105] In some embodiments, the peripheral circuit 120 includes a control logic circuit 125; the control logic circuit 125 is configured to: perform a logical operation on the pre-read result to generate an operation result; wherein the operation result includes first identification information, and the first identification information is used to indicate that the number of the selected storage cells adjacent to one of the selected storage cells and whose threshold voltage is greater than the preset voltage is greater than or equal to a preset value; in response to the first identification information, determine that a selected bit line coupled to one of the selected storage cells is the first bit line.

[0106] In the embodiment of the present disclosure, the control logic circuit 125 in the peripheral circuit 120 can perform a logic operation on the first logic value and / or the second logic value in the pre-read results of all selected memory cells to generate an operation result, wherein the operation result includes first identification information, and the first identification information is used to indicate the first logic value associated with a selected memory cell (such as Figure 3The number of adjacent selected memory cells (selected memory cell C1) whose threshold voltage is greater than a preset voltage is greater than or equal to a preset value. The preset value can be determined based on actual product test results or provided as a reference value by the designer. If the number of adjacent selected memory cells (selected memory cells C2) whose threshold voltage is greater than the preset voltage is greater than or equal to the preset value, it indicates that in subsequent read operations, the coupling effect of multiple adjacent bit lines will significantly affect the sensing of the first bit line, and it is necessary to apply a bit line compensation read voltage to the first bit line for compensatory reading to improve the read margin. The first identification information in the present disclosure may also be a binary logic value, such as a logic value of "1" or "0."

[0107] Here Figure 3 The storage unit arrangement shown in FIG and the preset value is equal to 3 are used as an example for explanation. Figure 3 Among the six selected memory cells C2 adjacent to the selected memory cell C1, if the pre-read results of three or more selected memory cells are the first logic value "1" (i.e., the threshold voltage is greater than the preset voltage), then the peripheral circuit 120 performs a logical operation on the pre-read results of the six selected memory cells C2, and the operation result generated is the first identification information. In this way, the peripheral circuit 120 can determine the selected bit line coupled to the selected memory cell C1 as the first bit line in response to the first identification information. It should be noted that in an actual product, the number of selected memory cells adjacent to each selected memory cell can also be other than 6, and the preset value is not limited to 3, and the present disclosure does not impose too many restrictions on this. In addition, the peripheral circuit 120 performs a logical operation on the pre-read result to generate an operation result, which is an operation for all selected memory cells, that is, the peripheral circuit 120 will generate an operation result corresponding to each selected memory cell through a logical operation, thereby determining whether the selected bit line coupled to each selected memory cell needs to be compensated read (i.e., determining all first bit lines).

[0108] In some embodiments, the control logic circuit 125 is specifically configured to: determine the number of first logic values ​​corresponding to multiple selected storage cells adjacent to one selected storage cell in response to the pre-read result; and generate the first identification information in response to the number of first logic values ​​corresponding to multiple selected storage cells adjacent to one selected storage cell being greater than or equal to the preset value.

[0109] In the embodiment of the present disclosure, the control logic circuit 125 may determine the memory cell (eg, Figure 3The number of first logic values ​​corresponding to the multiple selected memory cells adjacent to the selected memory cell C1 in the control logic circuit 125 is determined. For example, the peripheral circuit 120 may pre-read all selected memory cells and, based on the pre-read results of all selected memory cells, determine the number of first logic values ​​corresponding to the multiple selected memory cells adjacent to each selected memory cell, i.e., how many of the multiple adjacent selected memory cells have threshold voltages greater than a preset voltage. Thus, if the number of first logic values ​​corresponding to the multiple selected memory cells adjacent to a selected memory cell is greater than or equal to a preset value, the control logic circuit 125 generates a logical operation result as first identification information, i.e., the selected bit line coupled to the selected memory cell requires a compensation read. Here, the first identification information may also be a binary value.

[0110] In some embodiments, the operation result also includes second identification information, and the second identification information is used to indicate that the number of the selected storage cells adjacent to another selected storage cell and having a threshold voltage greater than the preset voltage is less than the preset value; the control logic circuit 125 is also configured to: in response to the second identification information, determine that the selected bit line coupled to the other selected storage cell is the second bit line.

[0111] In the embodiment of the present disclosure, the control logic circuit 125 in the peripheral circuit 120 can perform a logical operation on the first logic value and / or the second logic value in the pre-read results of all selected memory cells to generate an operation result, wherein the operation result includes second identification information, and the second identification information is used to indicate the first logic value and / or the second logic value of the pre-read results of all selected memory cells. Figure 3 The number of adjacent selected memory cells (the selected memory cell C1 in the memory) and whose threshold voltage is greater than the preset voltage is less than a preset value. The preset value here can be determined based on the actual test results of the product, or a reference value provided by the designer. If the number of selected memory cells with a threshold voltage greater than the preset voltage in the adjacent selected memory cell C2 is less than the preset value, it means that in the subsequent read operation, the influence caused by the coupling effect of the selected bit line coupled to the multiple adjacent selected memory cells C2 is small, and there is no need to perform a compensatory reading on the selected bit line coupled to the selected memory cell C1, that is, the selected bit line coupled to the selected memory cell C1 can be determined as the second bit line. The second identification information in the present disclosure can also be a binary logic value, such as a logic value of "1" or "0". It should be noted that the first identification information and the second identification information are different logic values. If the first identification information is "1", the second identification information is "0".

[0112] Here Figure 3 The storage unit arrangement shown in FIG and the preset value is equal to 3 are used as an example for explanation. Figure 3Among the six selected memory cells C2 adjacent to the selected memory cell C1, only less than three of the selected memory cells have a pre-read result of the first logic value "1" (i.e., the threshold voltage is greater than the preset voltage), then the peripheral circuit 120 performs a logical operation on the pre-read results of the six selected memory cells C2 to generate an operation result as the second identification information. In this way, the peripheral circuit 120 can determine the selected bit line coupled to the selected memory cell C1 as the second bit line in response to the second identification information. It should be noted that in actual products, the number of selected memory cells adjacent to each selected memory cell can also be other than 6, and the preset value is not limited to 3, and the present disclosure does not impose too many restrictions on this. In addition, the peripheral circuit 120 performs a logical operation on the pre-read result to generate an operation result, which is an operation for all selected memory cells, that is, the peripheral circuit 120 will generate an operation result corresponding to each selected memory cell through a logical operation, thereby determining whether the selected bit line coupled to each selected memory cell needs to be compensated read.

[0113] In some embodiments, the control logic circuit 125 is specifically configured to: determine the number of first logic values ​​corresponding to multiple selected storage cells adjacent to another selected storage cell in response to the pre-read result; and generate the second identification information in response to the number of first logic values ​​corresponding to multiple selected storage cells adjacent to another selected storage cell being less than the preset value.

[0114] In the embodiment of the present disclosure, the control logic circuit 125 may determine the memory cell (eg, Figure 3 The number of first logic values ​​corresponding to the multiple selected memory cells adjacent to the selected memory cell C1 in the control logic circuit 125 is determined. For example, the peripheral circuit 120 may pre-read all selected memory cells and, based on the pre-read results of all selected memory cells, determine the number of first logic values ​​corresponding to the multiple selected memory cells adjacent to each selected memory cell, i.e., how many of the multiple adjacent selected memory cells have threshold voltages greater than a preset voltage. Thus, if the number of first logic values ​​corresponding to the multiple selected memory cells adjacent to a selected memory cell is less than a preset value, the control logic circuit 125 generates a logical operation result as the second identification information, i.e., the selected bit line coupled to the selected memory cell does not need to undergo a compensation read.

[0115] Figure 5 FIG. 1 is a schematic diagram of a pre-read result and an operation result generated by the peripheral circuit 120 in an exemplary embodiment. It should be noted that, for ease of understanding, Figure 5 The arrangement of the actual selected storage cells and selected bit lines is simplified. Figure 5Each selected memory cell is adjacent to only two selected memory cells, that is, the selected bit line coupled to each selected memory cell is adjacent to only two selected bit lines. In this case, the preset value may be 2. Specifically, referring to Figure 5 For the pre-read results shown in the second row, if the pre-read results of the selected memory cells coupled to the two adjacent selected bit lines (BL1 and BL3) of a selected bit line (such as BL2) are both the first logic value "1" (the threshold voltage is greater than the preset voltage), then the operation result of the selected bit line (BL2) generated by the peripheral circuit 120 through the logic operation is the first identification information "1", that is, the selected bit line BL2 needs to be compensated read, the selected bit line BL2 can be determined by the peripheral circuit 120 as the first bit line, and the selected bit line BL2 can be applied with a bit line compensation read voltage (such as V BL +△V), where V BL It can be the default bit line read voltage in the memory, and △V can be the compensation voltage. If the number of the first logic value "1" in the pre-read results of the selected memory cells coupled to the two adjacent selected bit lines (BL5 and BL7) of a selected bit line (such as BL6) is less than 2 (wherein the pre-read result corresponding to BL5 is "1", and the pre-read result corresponding to BL7 is "0"), then the operation result of the selected bit line (BL6) generated by the peripheral circuit 120 through the logical operation is the second identification information "0", that is, the selected bit line BL6 does not need to be compensated for reading, and the selected bit line BL6 can be determined by the peripheral circuit 120 as the second bit line, and the bit line read voltage (such as V BL ).

[0116] In some embodiments, as Figure 4 As shown, the peripheral circuit 120 further includes a latch circuit 129 coupled to the control logic circuit 128 ; the latch circuit 129 is configured to latch the operation result.

[0117] In an embodiment of the present disclosure, the peripheral circuit 120 may further include a latch circuit 129, which is coupled to the control logic circuit 128 and is used to latch the operation result. In some embodiments, the latch circuit 129 may be located in the page buffer 121. The page buffer 121 may include multiple latch circuits, wherein the data latch circuit can be used to latch data information to be programmed into multiple logical pages of the memory (such as the low page LP, middle page MP, upper page UP and extra page XP in the QLC memory); the low voltage latch circuit can be used to latch program inhibition information and verification information; the sense latch circuit can be used to latch the data information sensed and read from the bit line corresponding to the memory cell; and the cache latch circuit can be used to exchange data with the outside. It should be noted that the latch circuit 129 used to latch the operation result in the present disclosure can be a latch circuit different from the above-mentioned data latch circuit, low voltage latch circuit, sense latch circuit and cache latch circuit. In other embodiments, the latch circuit 129 can also be set at other locations in the peripheral circuit 120 and not located in the page buffer 121.

[0118] In some embodiments, the control logic circuit 128 is further configured to: determine the number of the selected memory cells adjacent to the selected memory cell and having a threshold voltage greater than the preset voltage; and determine the bit line compensation read voltage of the first bit line coupled to the selected memory cell in response to the number of the selected memory cells adjacent to the selected memory cell and having a threshold voltage greater than the preset voltage.

[0119] In the embodiment of the present disclosure, the control logic circuit 128 can determine the Figure 3 A plurality of adjacent selected storage cells (such as the selected storage cell C1 in Figure 3 The number of first logic values ​​corresponding to the selected storage cell C2 in the example, and the number of first logic values ​​corresponding to the adjacent plurality of selected storage cells are used to determine a selected storage cell (such as Figure 3The magnitude of the bit line compensation read voltage to be applied to the first bit line coupled to the selected memory cell C1 in the memory cell C1 is determined. For example, if the pre-read results of three selected memory cells C2 among the six selected memory cells C2 adjacent to the selected memory cell C1 are the first logic value "1" (i.e., the threshold voltage is greater than the preset voltage), then the first bit line compensation read voltage may be applied to the first bit line coupled to the selected memory cell C1. If the pre-read results of four selected memory cells C2 among the six selected memory cells C2 adjacent to the selected memory cell C1 are the first logic value "1," then a second bit line compensation read voltage may be applied to the first bit line coupled to the selected memory cell C1, and the second bit line compensation read voltage may be greater than the first bit line compensation read voltage. That is to say, among the multiple selected memory cells C2 adjacent to the selected memory cell C1, the more selected memory cells C2 whose threshold voltage is greater than the preset voltage, the greater the bit line compensation read voltage applied to the first bit line coupled to the selected memory cell C1 in the subsequent read operation, thereby accurately performing compensation reading, further reducing the read margin, improving the reliability of the memory 100, and helping to save power consumption of the memory 100.

[0120] In some embodiments, the peripheral circuit 120 is specifically configured to: apply the preset voltage to the selected word line, and apply the bit line read voltage to the plurality of selected bit lines to obtain the pre-read result.

[0121] In the embodiment of the present disclosure, the peripheral circuit 120 may perform a pre-read operation before the read operation, thereby obtaining pre-read results of all selected memory cells. Figure 6 , the peripheral circuit 120 can apply a preset voltage V to the selected word line in the pre-pulse phase (Prepulse) level3 , and apply a bit line read voltage to multiple selected bit lines, so as to roughly determine whether the threshold voltage of each selected memory cell is greater than the preset voltage V level3 , and generates a corresponding pre-read result (if the threshold voltage is greater than the preset voltage, a first logic value "1" is generated, and if it is less than, a second logic value "0" is generated). It can be understood that the non-selected word lines in the pre-pulse phase can be applied with a pass voltage V pass , and the top select gate (TSG) can also apply a corresponding turn-on voltage V TSG , so that the memory string is turned on, so by sensing the current on the selected bit line, it can be determined whether the threshold voltage of the selected memory cell is greater than the preset voltage V level3 .

[0122] In some embodiments, the peripheral circuit 120 is further configured to: apply a word line read voltage to the selected word line in response to the read command, and apply the bit line compensation read voltage and the bit line read voltage to the first bit line and the second bit line, respectively, to obtain a read result; wherein the word line read voltage is less than the preset voltage.

[0123] In the embodiments of the present disclosure, reference Figure 6 , the peripheral circuit 120 can also apply a word line read voltage V to the selected word line in response to a read command (formal read phase after the pre-pulse phase). read , and apply the bit line compensation read voltage and the bit line read voltage to the first bit line and the second bit line respectively ( Figure 6 The situation of compensating the read voltage of the bit line is not shown in FIG), thereby performing a read operation on all selected memory cells to obtain a read result. It can be understood that the word line read voltage V read Less than the preset voltage V level3 , that is, if the threshold voltage of a selected memory cell is much higher than the word line read voltage V read , the selected memory cell is more likely to be affected by the coupling effect between adjacent bit lines on the reading of adjacent selected memory cells, so the preset voltage V level3 Set to be greater than the word line read voltage V read voltage value, thereby effectively compensating for reading and further improving the reading margin.

[0124] Figure 7 Schematic diagram of a process in which a peripheral circuit determines a first bit line and a second bit line and applies different bit line voltages to the first bit line and the second bit line in a read operation in an exemplary embodiment. Figure 3 The memory cell arrangement shown in FIG. 1 and the preset value is equal to 3 are used as an example to illustrate that the peripheral circuit 120 can determine whether the threshold voltage of each selected memory cell is greater than the preset voltage in the pre-pulse stage. If a selected memory cell (such as Figure 3 The six adjacent selected storage cells (such as Figure 3 If there are three or more selected memory cells C2 in the selected memory cell C1 whose threshold voltage is greater than the preset voltage, a bit line compensation reading voltage is applied to the selected bit line (first bit line) coupled to the selected memory cell C1; if a selected memory cell (such as Figure 3 The six adjacent selected storage cells (such as Figure 3If fewer than three of the selected memory cells C2 have threshold voltages greater than a predetermined voltage, a bitline read voltage is applied to the selected bitline (the second bitline) coupled to the selected memory cell C1. The bitline read voltage is less than the bitline compensation read voltage. This allows the peripheral circuitry to perform a compensatory read on the first bitline affected by the larger threshold voltages of adjacent selected memory cells and bitline coupling effects during a read operation, resulting in a more accurate final read result and improved read margin.

[0125] In some embodiments, regardless of whether the selected memory cell is in the programmed state or the selected memory cell is in the erased state (here, the selected memory cell C1 is in the programmed state or the erased state), the threshold voltage of the adjacent selected memory cell is larger and the bit line coupling effect will cause the threshold voltage distribution of the memory cells in the programmed state and the erased state to be widened, which will affect the total width of the threshold voltage distribution interval (E sum By applying a bit line compensation read voltage to the first bit line using the peripheral circuit of the memory in the above embodiment, the influence of the bit line coupling effect can be effectively reduced, thereby converging the threshold voltage distributions of the memory cells in the programmed state and the erased state, thereby improving the read margin and enhancing the reliability of the memory.

[0126] The present disclosure provides an operating method for a memory, wherein the memory includes a memory cell array and a peripheral circuit coupled to the memory cell array, wherein the memory cell array includes a plurality of memory cells; the operating method includes: applying a bit line compensation read voltage to a first bit line among a plurality of selected bit lines in response to a read command; wherein, among a plurality of selected memory cells coupled to a selected word line, a threshold voltage of at least one of the selected memory cells adjacent to the selected memory cell coupled to the first bit line is greater than a preset voltage; applying a bit line read voltage to a second bit line in response to the read command; wherein, the second bit line is a bit line other than the first bit line among the plurality of selected bit lines; and the bit line compensation read voltage is greater than the bit line read voltage.

[0127] In the embodiment of the present disclosure, before performing a read operation, the peripheral circuit can first obtain the threshold voltages of the selected memory cells coupled to the selected word line and the selected bit line, and determine whether the threshold voltages of these selected memory cells are greater than a preset voltage. The preset voltage here can be determined based on the actual test results of the product, or a reference value provided by the designer. For any selected memory cell (such as Figure 3 The selected memory cell C1 in the example is selected, if at least one selected memory cell adjacent to it (such as Figure 3If the threshold voltage of the selected memory cell C2 in the memory is greater than the preset voltage, the bit line coupled to the selected memory cell (C1) can be determined as the first bit line. In this way, the peripheral circuit can determine all the first bit lines, and determine the other selected bit lines in the selected bit lines except the first bit line as the second bit lines. The peripheral circuit can apply a bit line compensation read voltage to the first bit line in response to the read command, and apply a bit line read voltage to the second bit line in response to the read command, and the bit line compensation read voltage is greater than the bit line read voltage. In other words, the peripheral circuit can perform a compensation read on the first bit line that is affected by the larger threshold voltage of the adjacent selected memory cell and the bit line coupling effect during the read operation, so that the final read result is more accurate to improve the read margin. Here, the bit line compensation read voltage can be determined based on the bit line read voltage, such as the bit line compensation read voltage can be obtained by adding the compensation voltage to the bit line read voltage, and the specific compensation voltage value can be adjusted according to actual conditions.

[0128] It is understood that because the threshold voltage of at least one selected memory cell adjacent to the selected memory cell coupled to the first bit line is greater than a preset voltage, the coupling effect between the bit line coupled to the at least one adjacent selected memory cell and the first bit line may cause an error in the read result of the selected memory cell coupled to the first bit line. In this case, the peripheral circuit can apply a bit line compensation read voltage to a first bit line among the multiple selected bit lines, and apply a bit line read voltage to a second bit line among the multiple selected bit lines, where the bit line compensation read voltage is greater than the bit line read voltage. In this way, during a read operation, although the higher threshold voltage of the adjacent selected memory cell will result in a higher voltage on the adjacent selected bit line, the bit line compensation read voltage applied to the first bit line can reduce the impact of the coupling effect caused by the higher voltage on the adjacent selected bit line, thereby improving the read margin and enhancing the reliability of the memory read operation.

[0129] In some embodiments, the method further includes determining the first bit line and the second bit line of the plurality of selected bit lines in response to the read command.

[0130] In some embodiments, determining the first bit line and the second bit line among the multiple selected bit lines includes: applying the preset voltage to the selected word line to obtain a pre-read result of the multiple selected memory cells; wherein the pre-read result includes a first logic value, and the first logic value is used to indicate that the threshold voltage of the memory cell is greater than the preset voltage; in response to the pre-read result, determining the first bit line and the second bit line among the multiple selected bit lines.

[0131] In some embodiments, in response to the pre-read result, determining the first bit line among the multiple selected bit lines includes: performing a logical operation on the pre-read result to generate an operation result; wherein the operation result includes first identification information, and the first identification information is used to indicate that the number of the selected storage cells adjacent to one of the selected storage cells and whose threshold voltage is greater than the preset voltage is greater than or equal to a preset value; in response to the first identification information, determining that a selected bit line coupled to the selected storage cell is the first bit line.

[0132] In some embodiments, performing a logical operation on the pre-read result to generate an operation result includes: determining the number of first logic values ​​corresponding to multiple selected storage cells adjacent to one selected storage cell in response to the pre-read result; and generating the first identification information in response to the number of first logic values ​​corresponding to multiple selected storage cells adjacent to one selected storage cell being greater than or equal to the preset value.

[0133] In some embodiments, the operation result also includes second identification information, and the second identification information is used to indicate that the number of the selected storage cells adjacent to another selected storage cell and having a threshold voltage greater than the preset voltage is less than the preset value; the method also includes: in response to the second identification information, determining that the selected bit line coupled to the other selected storage cell is the second bit line.

[0134] In some embodiments, performing a logical operation on the pre-read result to generate an operation result also includes: determining the number of first logic values ​​corresponding to multiple selected storage cells adjacent to another selected storage cell in response to the pre-read result; and generating the second identification information in response to the number of first logic values ​​corresponding to multiple selected storage cells adjacent to another selected storage cell being less than the preset value.

[0135] In some embodiments, the method further includes: latching the operation result.

[0136] In some embodiments, the method further includes: determining the number of the selected memory cells adjacent to one of the selected memory cells and having a threshold voltage greater than the preset voltage; and determining the bit line compensation read voltage of the first bit line coupled to one of the selected memory cells in response to the number of the selected memory cells adjacent to one of the selected memory cells and having a threshold voltage greater than the preset voltage.

[0137] In some embodiments, the pre-read result also includes a second logic value; obtaining the pre-read result of the multiple selected memory cells includes: generating the first logic value in response to the threshold voltage of the selected memory cell being greater than the preset voltage; or generating the second logic value in response to the threshold voltage of the selected memory cell being less than the preset voltage.

[0138] In some embodiments, applying the preset voltage to the selected word line to obtain the pre-read results of the multiple selected memory cells includes: applying the preset voltage to the selected word line, and applying the bit line read voltage to all the multiple selected bit lines to obtain the pre-read results.

[0139] In some embodiments, the method further includes: in response to the read command, applying a word line read voltage to the selected word line, and applying the bit line compensation read voltage and the bit line read voltage to the first bit line and the second bit line, respectively, to obtain a read result; wherein the word line read voltage is less than the preset voltage.

[0140] The present disclosure provides a memory system, comprising:

[0141] The memory according to any one of the above embodiments; a memory controller coupled to the memory.

[0142] In the embodiment of the present disclosure, the memory system may correspond to the reference Figure 1 In the embodiment shown in FIG. 1 , the memory system 102 may correspond to the memory system 102 of FIG. Figure 1 The memory 104 in the embodiment shown, and the memory controller may correspond to the reference Figure 1 The memory controller 106 in the illustrated embodiment is configured to control a memory, and the specific functions, applications, and interactions between the memory and the memory controller are not described in detail herein.

[0143] In the memory, memory operation method, and memory system provided by the present disclosure, because the threshold voltage of at least one selected memory cell adjacent to a selected memory cell coupled to a first bit line is greater than a preset voltage, a coupling effect between the selected bit line coupled to the at least one adjacent selected memory cell and the first bit line may cause an error in the read result of the selected memory cell coupled to the first bit line. In this case, the peripheral circuit can apply a bit line compensation read voltage to a first bit line among a plurality of selected bit lines, and apply a bit line read voltage to a second bit line among the plurality of selected bit lines, wherein the bit line compensation read voltage is greater than the bit line read voltage. In this way, during a read operation, although the higher threshold voltage of the adjacent selected memory cell causes a higher voltage on the adjacent selected bit line, the bit line compensation read voltage applied to the first bit line can reduce the impact of the coupling effect caused by the higher voltage on the adjacent selected bit line, thereby improving the read margin and enhancing the reliability of the memory in performing a read operation.

[0144] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0145] The above description is only a preferred embodiment of the present disclosure and does not limit the patent scope of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A memory, characterized in that: The memory includes: A memory cell array, comprising: a plurality of memory cells; A peripheral circuit is coupled to the memory cell array via a plurality of bit lines and a plurality of word lines; the peripheral circuit is configured as follows: In response to a read command, applying a bit line compensation read voltage to a first bit line among a plurality of selected bit lines; wherein, among a plurality of selected memory cells coupled to a selected word line, a threshold voltage of at least one of the selected memory cells adjacent to the selected memory cell coupled to the first bit line is greater than a predetermined voltage; In response to the read command, a bit line read voltage is applied to a second bit line; wherein the second bit line is a bit line other than the first bit line among the plurality of selected bit lines; and the bit line compensation read voltage is greater than the bit line read voltage.

2. The memory according to claim 1, wherein: The peripheral circuit is further configured to: In response to the read command, the first bit line and the second bit line of the plurality of selected bit lines are determined.

3. The memory according to claim 2, wherein: The peripheral circuit is specifically configured as follows: Applying the preset voltage to the selected word line to obtain pre-read results of the plurality of selected memory cells; wherein the pre-read results include a first logic value, the first logic value being used to indicate that a threshold voltage of the memory cell is greater than the preset voltage; In response to the pre-read result, the first bit line and the second bit line among the plurality of selected bit lines are determined.

4. The memory according to claim 3, wherein: The peripheral circuit includes a control logic circuit; the control logic circuit is configured to: Performing a logical operation on the pre-read result to generate an operation result; wherein the operation result includes first identification information, the first identification information being used to indicate that the number of the selected memory cells adjacent to the selected memory cell and having a threshold voltage greater than the preset voltage is greater than or equal to a preset value; In response to the first identification information, a selected bit line coupled to the selected memory cell is determined to be the first bit line.

5. The memory according to claim 4, wherein: The control logic circuit is specifically configured as follows: In response to the pre-read result, determining the number of first logic values ​​corresponding to a plurality of the selected memory cells adjacent to the selected memory cell; In response to the number of first logic values ​​corresponding to a plurality of the selected memory cells adjacent to one of the selected memory cells being greater than or equal to the preset value, the first identification information is generated.

6. The memory according to claim 4, wherein: The operation result further includes second identification information, where the second identification information is used to indicate that the number of the selected memory cells adjacent to another selected memory cell and having a threshold voltage greater than the preset voltage is less than the preset value; and the control logic circuit is further configured to: In response to the second identification information, a selected bit line coupled to another selected memory cell is determined to be the second bit line.

7. The memory according to claim 6, wherein: The control logic circuit is specifically configured as follows: In response to the pre-read result, determining the number of first logic values ​​corresponding to a plurality of the selected memory cells adjacent to another selected memory cell; The second identification information is generated in response to the number of first logic values ​​corresponding to a plurality of the selected memory cells adjacent to another selected memory cell being smaller than the preset value.

8. The memory according to claim 4, wherein: The peripheral circuit further includes: A latch circuit is coupled to the control logic circuit; the latch circuit is configured to latch the operation result.

9. The memory according to claim 4, wherein: The control logic circuit is further configured to: determining the number of the selected memory cells adjacent to the selected memory cell and having a threshold voltage greater than the preset voltage; The bit line compensation read voltage of the first bit line coupled to the selected memory cell is determined in response to the number of the selected memory cells adjacent to the selected memory cell and having a threshold voltage greater than the preset voltage.

10. The memory according to claim 3, wherein: The pre-read result further includes a second logic value; and the peripheral circuit is specifically configured as follows: generating the first logic value in response to a threshold voltage of the selected memory cell being greater than the preset voltage; or, In response to a threshold voltage of the selected memory cell being lower than the preset voltage, the second logic value is generated.

11. The memory according to claim 3, wherein: The peripheral circuit is specifically configured as follows: The preset voltage is applied to the selected word line, and the bit line read voltage is applied to the plurality of selected bit lines to obtain the pre-read result.

12. The memory according to claim 1, wherein: The peripheral circuit is further configured to: In response to the read command, a word line read voltage is applied to the selected word line, and the bit line compensation read voltage and the bit line read voltage are applied to the first bit line and the second bit line, respectively, to obtain a read result; wherein the word line read voltage is less than the preset voltage.

13. A method for operating a memory, characterized in that: The memory includes a memory cell array and a peripheral circuit coupled to the memory cell array, wherein the memory cell array includes a plurality of memory cells; and the operating method includes: In response to a read command, applying a bit line compensation read voltage to a first bit line among a plurality of selected bit lines; wherein, among a plurality of selected memory cells coupled to a selected word line, a threshold voltage of at least one of the selected memory cells adjacent to the selected memory cell coupled to the first bit line is greater than a predetermined voltage; In response to the read command, a bit line read voltage is applied to a second bit line; wherein the second bit line is a bit line other than the first bit line among the plurality of selected bit lines; and the bit line compensation read voltage is greater than the bit line read voltage.

14. The operating method according to claim 13, characterized in that: The method further comprises: In response to the read command, the first bit line and the second bit line of the plurality of selected bit lines are determined.

15. The operating method according to claim 14, characterized in that: The determining the first bit line and the second bit line among the plurality of selected bit lines comprises: Applying the preset voltage to the selected word line to obtain pre-read results of the plurality of selected memory cells; wherein the pre-read results include a first logic value, the first logic value being used to indicate that a threshold voltage of the memory cell is greater than the preset voltage; In response to the pre-read result, the first bit line and the second bit line among the plurality of selected bit lines are determined.

16. The operating method according to claim 15, characterized in that: The step of determining the first bit line among the plurality of selected bit lines in response to the pre-read result comprises: Performing a logical operation on the pre-read result to generate an operation result; wherein the operation result includes first identification information, the first identification information being used to indicate that the number of the selected memory cells adjacent to the selected memory cell and having a threshold voltage greater than the preset voltage is greater than or equal to a preset value; In response to the first identification information, a selected bit line coupled to the selected memory cell is determined to be the first bit line.

17. The operating method according to claim 16, characterized in that: The performing a logical operation on the pre-read result to generate an operation result includes: In response to the pre-read result, determining the number of first logic values ​​corresponding to a plurality of the selected memory cells adjacent to the selected memory cell; In response to the number of first logic values ​​corresponding to a plurality of the selected memory cells adjacent to one of the selected memory cells being greater than or equal to the preset value, the first identification information is generated.

18. The operating method according to claim 16, characterized in that: The operation result further includes second identification information, where the second identification information is used to indicate that the number of the selected memory cells adjacent to another selected memory cell and having a threshold voltage greater than the preset voltage is less than the preset value; the method further includes: In response to the second identification information, a selected bit line coupled to another selected memory cell is determined to be the second bit line.

19. The operating method according to claim 18, characterized in that: The performing a logical operation on the pre-read result to generate an operation result further includes: In response to the pre-read result, determining the number of first logic values ​​corresponding to a plurality of the selected memory cells adjacent to another selected memory cell; The second identification information is generated in response to the number of first logic values ​​corresponding to a plurality of the selected memory cells adjacent to another selected memory cell being smaller than the preset value.

20. The operating method according to claim 16, characterized in that: The method further comprises: The operation result is latched.

21. The operating method according to claim 16, characterized in that: The method further comprises: determining the number of the selected memory cells adjacent to the selected memory cell and having a threshold voltage greater than the preset voltage; The bit line compensation read voltage of the first bit line coupled to the selected memory cell is determined in response to the number of the selected memory cells adjacent to the selected memory cell and having a threshold voltage greater than the preset voltage.

22. The operating method according to claim 15, characterized in that: The pre-read result further includes a second logic value; and obtaining the pre-read results of the plurality of selected memory cells includes: generating the first logic value in response to a threshold voltage of the selected memory cell being greater than the preset voltage; or, In response to a threshold voltage of the selected memory cell being lower than the preset voltage, the second logic value is generated.

23. The operating method according to claim 15, characterized in that: Applying the preset voltage to the selected word line to obtain pre-read results of the plurality of selected memory cells includes: The preset voltage is applied to the selected word line, and the bit line read voltage is applied to the plurality of selected bit lines to obtain the pre-read result.

24. The operating method according to claim 13, characterized in that: The method further comprises: In response to the read command, a word line read voltage is applied to the selected word line, and the bit line compensation read voltage and the bit line read voltage are applied to the first bit line and the second bit line, respectively, to obtain a read result; wherein the word line read voltage is less than the preset voltage.

25. A memory system, characterized in that: include: The memory according to any one of claims 1 to 12; A memory controller is coupled to the memory.

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