FPGA-based least square method clock synchronization precision compensation method and system

Abstract

The invention relates to the technical field of time sensitive networks, and provides a least square method clock synchronization precision compensation method and system based on an FPGA, and the method comprises the steps: responding to a starting signal of an operation enabling controller; analyzing timestamp data of the master clock device and the slave clock device through a clock data analysis module, caching the timestamp data into a corresponding dual-port RAM (Random Access Memory), and triggering a pulse signal until the cache number reaches a preset timestamp sampling threshold N; the FPGA control processor responds to the pulse signal, the data reading module reads timestamp data from the dual-port RAM and inputs the timestamp data to the least square processing module to calculate a time deviation value of the master clock device and the slave clock device; and the clock deviation compensation and correction module compensates the timestamp of the slave clock equipment according to the time deviation value. The dynamic compensation of the master clock and the slave clock is realized in combination with the least square method and FPGA hardware calculation, the clock synchronization precision is improved, and compared with a traditional software-based method, higher calculation efficiency and real-time performance are provided, and the problem of network congestion caused by frequent synchronization in the prior art is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of time-sensitive networks, and in particular to a least squares clock synchronization accuracy compensation method and system based on FPGA. Background Art

[0002] With the continuous advancement of network technology, the IEEE 1588 Precision Time Protocol (PTP) has gained widespread adoption in industrial control, test and measurement, and network communications due to its high synchronization accuracy, low-cost implementation, and ease of installation and maintenance. In distributed test systems, the IEEE 1588 protocol achieves high-precision clock synchronization through timestamp exchange between master and slave clock devices, ensuring consistent time across all nodes. However, in practice, variations in the crystal stability of local clocks significantly impact the synchronization accuracy of the PTP system. The inherent stability differences between the crystal oscillators (crystal oscillators) of master and slave clock devices lead to frequency errors between the crystal oscillators. Furthermore, external factors such as temperature, pressure, power supply voltage fluctuations, and crystal oscillator aging can cause the slave clock frequency to drift relative to the master clock frequency. This drift accumulates over time, causing the slave clock's timing to deviate from the master clock. This deviation typically requires waiting for the next synchronization moment to fully correct.

[0003] Therefore, during PTP clock synchronization, frequency drift between the master and slave clocks must be continuously suppressed. Master-slave clock deviations must be corrected during each synchronization cycle to minimize the impact of these deviations on synchronization accuracy. Traditional solutions typically increase the frequency of synchronization messages, hoping to correct clock deviations promptly through more frequent synchronization operations. While this approach can mitigate the impact of frequency drift to some extent, frequent synchronization message exchanges significantly increase network load, leading to excessive bandwidth consumption and, in turn, network congestion, impacting overall system performance. Summary of the Invention

[0004] To address the above issues, the present invention proposes a least squares clock synchronization accuracy compensation method and system based on FPGA, which effectively improves the accuracy of master-slave clock synchronization. While ensuring real-time performance and high efficiency, it solves the problem of low accuracy of existing clock synchronization methods and achieves more accurate clock synchronization compensation. The above-mentioned invention objectives are achieved through the following technical solutions: The present invention provides a least squares clock synchronization accuracy compensation method based on FPGA, comprising: Responding to a start signal from an operation enable controller; The clock data parsing module parses the timestamp data of the master and slave clock devices and caches them in the corresponding dual-port RAM until the cached number reaches a preset timestamp sampling threshold N, triggering a pulse signal, where N is a natural number greater than 0; The FPGA control processor responds to the pulse signal, and the data reading module reads the timestamp data from the dual-port RAM and inputs the timestamp data into the least squares processing module to calculate the time deviation value of the master and slave clock devices. In the least squares processing module, based on the read timestamp data, a corresponding fitting curve is calculated by the least squares method, and the slave timestamp data of the slave clock device (N+1) is substituted into the fitting curve to calculate the predicted master timestamp data of the corresponding master clock device, and determine the time deviation value between the master timestamp data and the predicted master timestamp data. The clock deviation compensation correction module compensates the timestamp of the slave clock device according to the time deviation value, so that the timestamp data of the master and slave clock devices are synchronized.

[0005] Furthermore, responding to the start signal of the operation enable controller includes: Setting a fixed macrocycle in the operation enable controller to limit the working time window of the FPGA control processor; Whenever a macrocycle begins, the operation enable controller generates a start signal; The FPGA control processor responds to the start signal and starts running within the working time window.

[0006] Furthermore, the timestamp data of the master and slave clock devices are parsed by the clock data parsing module and cached in the corresponding dual-port RAM until the cache quantity reaches a preset timestamp sampling threshold N and then a pulse signal is triggered, where N is a natural number greater than 0 including: The clock data parsing module receives the message containing the timestamp information sent by the master and slave clock devices through the Ethernet interface, extracts and converts it into the timestamp data of the corresponding format, the timestamp data includes the master timestamp data and the slave timestamp data; The timestamp data is cached in the corresponding dual-port RAM, and a pulse signal is sent when the cached timestamp data reaches the preset timestamp sampling threshold to trigger the data reading module to read the timestamp data from the dual-port RAM and send it to the least squares processing module for calculation.

[0007] Furthermore, based on the read timestamp data, calculating the corresponding fitting curve by the least squares method includes: Based on the read timestamp data, calculate the slope and intercept of the fitting curve; the slope k and intercept b are calculated as follows: ; ; Where X is the timestamp data of the slave clock device, Y is the timestamp data of the master clock device, i ranges from 1 to N, and n is the number of sampling times N; According to the calculated slope and intercept, the corresponding fitting curve equation is constructed.

[0008] Furthermore, the slope k and intercept b are calculated using the lower 32 bits of the timestamp data.

[0009] Further, substituting the slave timestamp data of the slave clock device of the N+1th time into the fitting curve, calculating the predicted master timestamp data of the corresponding master clock device, and determining the time deviation value between the master timestamp data and the predicted master timestamp data includes: Get the N+1th timestamp data; Use the fitting curve equation to substitute the N+1th slave timestamp data and calculate the corresponding predicted master timestamp data; Obtain the (N+1)th primary timestamp data and calculate the time deviation between the primary timestamp data and the predicted primary timestamp data.

[0010] Furthermore, it also includes deploying a clock synchronization protocol on the communication nodes of the master and slave clock devices, and the clock synchronization protocol includes IEEE 1588, IEEE 1588v2, and IEEE 802.1AS.

[0011] Based on the same inventive concept, the present invention also provides a least squares clock synchronization accuracy compensation system based on FPGA, which adopts the least squares clock synchronization accuracy compensation method as described above, including: The clock data parsing module parses the timestamp data of the master and slave clock devices and caches them in the corresponding dual-port RAM until the cached number reaches a preset timestamp sampling threshold N, triggering a pulse signal, where N is a natural number greater than 0; and responding to the pulse signal; The data reading module is used to read the timestamp data from the dual-port RAM and input it into the least squares processing module to calculate the time deviation value of the master and slave clock devices; A least squares processing module is used to calculate a corresponding fitting curve based on the read timestamp data by the least squares method, and substitute the slave timestamp data of the slave clock device (N+1) into the fitting curve to calculate the predicted master timestamp data of the corresponding master clock device, and determine the time deviation value between the master timestamp data and the predicted master timestamp data; The clock deviation compensation and correction module is used to compensate the timestamp of the slave clock device according to the time deviation value to synchronize the timestamp data of the master and slave clock devices.

[0012] Furthermore, it also includes an operation enable control module, which is used to set a fixed macro cycle in the operation enable controller to limit the working time window of the FPGA control processor. Whenever the macro cycle starts, the operation enable controller generates a start signal, and the FPGA control processor responds to the start signal and starts running within the working time window.

[0013] Furthermore, the least squares processing module includes, The fitting curve calculation unit is used to calculate the slope and intercept of the fitting curve according to the read timestamp data; wherein, the slope k and intercept b are calculated as follows: ; ; Where X is the timestamp data of the slave clock device, Y is the timestamp data of the master clock device, i ranges from 1 to N, and n is the number of sampling times N. Based on the calculated slope and intercept, the corresponding fitting curve equation is constructed; A master clock prediction value calculation unit is used to obtain the N+1th slave timestamp data, substitute the N+1th slave timestamp data into the fitting curve equation, and calculate the corresponding predicted master timestamp data; The master-slave clock deviation value calculation unit is used to obtain the (N+1)th master timestamp data and calculate the time deviation value between the master timestamp data and the predicted master timestamp data.

[0014] Compared with the prior art, the present invention has at least one of the following beneficial effects: This invention combines the least squares method with FPGA hardware calculations to achieve dynamic compensation of master and slave clocks, significantly improving clock synchronization accuracy and offering higher computational efficiency and real-time performance compared to traditional software-based methods. Furthermore, by optimizing the frequency of synchronization message transmission, it effectively reduces network load and avoids the network congestion caused by frequent synchronization in existing technologies. Furthermore, the modular design offers strong scalability and maintainability, allowing the functions of each module to be flexibly adjusted as needed. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a flowchart of the steps of the least squares clock synchronization accuracy compensation method based on FPGA of the present invention; Figure 2 A system block diagram of clock synchronization accuracy compensation according to an embodiment of the present invention; Figure 3 This is a flowchart for implementing clock synchronization accuracy compensation in an embodiment of the present invention. DETAILED DESCRIPTION

[0016] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0017] Those skilled in the art will appreciate that, unless otherwise stated, the singular forms "a," "an," "said," and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present invention refers to the presence of the stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0018] First embodiment Currently, the IEEE 1588 protocol standard only defines methods for clock synchronization and timestamp marking, but does not provide a compensation method for slave clocks. However, accurate compensation for slave clocks directly affects the overall accuracy of clock synchronization. To improve the system's clock synchronization accuracy and address the frequency drift problem between the master and slave clocks, existing technologies typically increase the frequency of synchronization message transmission to improve clock synchronization accuracy. Specifically, increasing the number of synchronization messages can, to a certain extent, promptly correct clock deviations, thereby improving synchronization accuracy. However, this method also has obvious disadvantages: increasing the frequency of synchronization messages will significantly increase the network burden, leading to network congestion and seriously affecting the real-time performance and stability of the system. Therefore, although increasing the frequency of synchronization messages can improve clock synchronization accuracy, it does not solve other problems caused by excessive network load.

[0019] To address the aforementioned issues, the prior art proposes a clock adjustment method based on a least-squares model. This method utilizes a program written in C language and executed within a clock synchronization device. By dividing the frequency of a high-precision crystal oscillator, a pulse-per-second clock signal is generated. This signal is then compared in phase with the GPS pulse-per-second signal to calculate the clock deviation. A mathematical regression method is then used to estimate the deviation, thereby correcting the accumulated error of the crystal oscillator and improving clock synchronization accuracy. In its specific implementation, a frequency-dividing circuit divides the frequency of the high-precision clock signal to generate a pulse-per-second signal. This signal is then passed through a digital phase-detection filter and compared in phase with the GPS signal to obtain a sequence of phase deviation samples. A linear regression algorithm, combined with historical data, is then used to estimate and correct the compensation value, with adjustments made once per second to reduce the clock deviation. However, this method relies on software calculations, limiting its clock synchronization accuracy due to computational resources. Furthermore, it cannot effectively address the network load and real-time performance issues associated with the increased frequency of synchronization messages.

[0020] To overcome these problems, the inventors, based on their reflections, proposed a clock synchronization solution based on FPGA hardware. Unlike traditional software-based solutions, FPGAs (field programmable gate arrays) are hardware accelerators capable of processing large amounts of data in parallel, with computational speeds far exceeding those of standard software processing. This application, based on a specific FPGA implementation, divides the least squares algorithm clock synchronization accuracy compensation into modules and functions. A specific implementation scheme is provided for the hardware deployment of this algorithm and the optimization of time synchronization accuracy in the hardware circuit, enabling faster, real-time clock synchronization adjustment. The specific implementation scheme is as follows: like Figure 1 、 2 , 3, the present invention provides a least squares clock synchronization accuracy compensation method based on FPGA, including: Responding to a start signal from an operation enable controller; The clock data parsing module parses the timestamp data of the master and slave clock devices and caches them in the corresponding dual-port RAM until the cached number reaches a preset timestamp sampling threshold N, triggering a pulse signal, where N is a natural number greater than 0; The FPGA control processor responds to the pulse signal, and the data reading module reads the timestamp data from the dual-port RAM and inputs the timestamp data into the least squares processing module to calculate the time deviation value of the master and slave clock devices. In the least squares processing module, based on the read timestamp data, a corresponding fitting curve is calculated by the least squares method, and the slave timestamp data of the slave clock device (N+1) is substituted into the fitting curve to calculate the predicted master timestamp data of the corresponding master clock device, and determine the time deviation value between the master timestamp data and the predicted master timestamp data. The clock deviation compensation correction module compensates the timestamp of the slave clock device according to the time deviation value, so that the timestamp data of the master and slave clock devices are synchronized.

[0021] Furthermore, responding to the start signal of the operation enable controller includes: Setting a fixed macrocycle in the operation enable controller to limit the working time window of the FPGA control processor; Whenever a macrocycle begins, the operation enable controller generates a start signal; The FPGA control processor responds to the start signal and starts running within the working time window.

[0022] Specifically, the least-squares clock compensation algorithm typically uses a continuous operation approach, with the computational task performed uninterrupted. While this approach can continuously correct for frequency drift between the master and slave clocks, it can also present several issues: 1. Continuous algorithm operation requires constant synchronization messages, which consumes significant network bandwidth. Particularly in large-scale distributed systems, frequent synchronization message transmission can lead to network congestion, reducing overall system efficiency and stability. 2. Continuous operation can make the system overly dependent on network synchronization, resulting in delayed system response time and an inability to meet high real-time requirements. Therefore, to effectively address the aforementioned issues in the prior art, the present invention proposes setting a fixed macrocycle in the operation enable controller to define the operating time window of the FPGA control processor. The specific operation is as follows: The macrocycle is set, and at the beginning of each macrocycle, the operation enable controller generates a start signal, instructing the FPGA control processor to begin operation. In response to the start signal, the FPGA control processor begins executing the least-squares clock compensation algorithm within the specified operating time window. Setting the macrocycle ensures that computations are performed only within each specific time window, thereby avoiding bandwidth usage and network congestion caused by the algorithm's continuous operation.

[0023] Furthermore, the timestamp data of the master and slave clock devices are parsed by the clock data parsing module and cached in the corresponding dual-port RAM until the cache quantity reaches a preset timestamp sampling threshold N and then a pulse signal is triggered, where N is a natural number greater than 0 including: The clock data parsing module receives the message containing the timestamp information sent by the master and slave clock devices through the Ethernet interface, extracts and converts it into the timestamp data of the corresponding format, the timestamp data includes the master timestamp data and the slave timestamp data; The timestamp data is cached in the corresponding dual-port RAM, and a pulse signal is sent when the cached timestamp data reaches the preset timestamp sampling threshold to trigger the data reading module to read the timestamp data from the dual-port RAM and send it to the least squares processing module for calculation.

[0024] Furthermore, based on the read timestamp data, calculating the corresponding fitting curve by the least squares method includes: Based on the read timestamp data, calculate the slope and intercept of the fitting curve; the slope k and intercept b are calculated as follows: ; ; Where X is the timestamp data of the slave clock device, Y is the timestamp data of the master clock device, i ranges from 1 to N, and n is the number of sampling times N; According to the calculated slope and intercept, the corresponding fitting curve equation is constructed.

[0025] When calculating the slope and intercept, timestamp data is calculated using data less than 32 bits. Specifically, both the master and slave timestamps are 64 bits, with the upper 32 bits representing seconds and the lower 32 bits representing nanoseconds. Because the system's clock synchronization accuracy error typically does not reach the second level, only the lower 32 bits of data are processed for calculations during this process. This avoids the waste of high-precision data while improving computational efficiency. When performing these mathematical operations in the FPGA, the official FPGA IP core is used to perform data addition, subtraction, multiplication, and division. To ensure efficiency and accuracy, the FPGA performs these operations through hardware acceleration. In particular, when floating-point operations are involved, a single-precision floating-point operation module is used to ensure the real-time performance of the system.

[0026] Further, substituting the slave timestamp data of the slave clock device of the N+1th time into the fitting curve, calculating the predicted master timestamp data of the corresponding master clock device, and determining the time deviation value between the master timestamp data and the predicted master timestamp data includes: Get the N+1th timestamp data; Use the fitting curve equation to substitute the N+1th slave timestamp data and calculate the corresponding predicted master timestamp data; Obtain the (N+1)th primary timestamp data and calculate the time deviation between the primary timestamp data and the predicted primary timestamp data.

[0027] Specifically, both the master and slave timestamps are 64-bit data, with the upper 32 bits representing seconds and the lower 32 bits representing nanoseconds. Because the system clock synchronization accuracy does not reach the second level, only the lower 32 bits are used for mathematical operations. Data processing for mathematical operations is performed in the FPGA. Calculating this formula involves addition, subtraction, multiplication, and division. This is accomplished using the official FPGA IP core and single-precision floating-point operations. If a negative value is generated during a subtraction operation, the value is represented using the two's complement. When performing division operations, the dividend can be appropriately amplified to avoid a zero result. The result can then be restored after the calculation is complete. Finally, the accuracy of the final calculated data can be determined based on system requirements.

[0028] The clock deviation compensation module compensates the timestamps of slave clock devices based on the time deviation value, synchronizing the timestamp data of the master and slave clock devices. Specifically, if the calculated time deviation is not zero, synchronization compensation is required. Synchronization compensation corrects the system's clock synchronization error by adjusting the frequency and phase of the master or slave clock, thereby achieving higher-precision synchronization. It is important to note that if a subtraction operation results in a negative value, the data processing in the FPGA uses two's complement representation to ensure accuracy. During division operations, to avoid zero division, the system can appropriately scale the dividend and restore the result after the calculation is complete. Finally, hardware acceleration of the mathematical calculations in the above steps using the FPGA can effectively improve the accuracy and efficiency of the calculations. Based on system requirements, developers can further adjust the calculation accuracy to meet the clock synchronization accuracy requirements of different application scenarios.

[0029] Furthermore, it also includes deploying a clock synchronization protocol on the communication nodes of the master and slave clock devices to achieve time synchronization of each communication node, wherein the clock synchronization protocol includes IEEE 1588, IEEE 1588v2, IEEE 802.1AS, etc.

[0030] Second embodiment Based on the same inventive concept, the present invention also provides a least squares clock synchronization accuracy compensation system based on FPGA, which adopts the least squares clock synchronization accuracy compensation method as described above, including: The clock data parsing module parses the timestamp data of the master and slave clock devices and caches them in the corresponding dual-port RAM until the cached number reaches a preset timestamp sampling threshold N, triggering a pulse signal, where N is a natural number greater than 0; and responding to the pulse signal; The data reading module is used to read the timestamp data from the dual-port RAM and input it into the least squares processing module to calculate the time deviation value of the master and slave clock devices; A least squares processing module is used to calculate a corresponding fitting curve based on the read timestamp data by the least squares method, and substitute the slave timestamp data of the slave clock device (N+1) into the fitting curve to calculate the predicted master timestamp data of the corresponding master clock device, and determine the time deviation value between the master timestamp data and the predicted master timestamp data; The clock deviation compensation and correction module is used to compensate the timestamp of the slave clock device according to the time deviation value to synchronize the timestamp data of the master and slave clock devices.

[0031] Furthermore, it also includes an operation enable control module, which is used to set a fixed macro cycle in the operation enable controller to limit the working time window of the FPGA control processor. Whenever the macro cycle starts, the operation enable controller generates a start signal, and the FPGA control processor responds to the start signal and starts running within the working time window.

[0032] Furthermore, the least squares processing module includes, The fitting curve calculation unit is used to calculate the slope and intercept of the fitting curve according to the read timestamp data; wherein, the slope k and intercept b are calculated as follows: ; ; Where X is the timestamp data of the slave clock device, Y is the timestamp data of the master clock device, i ranges from 1 to N, and n is the number of sampling times N. Based on the calculated slope and intercept, the corresponding fitting curve equation is constructed; A master clock prediction value calculation unit is used to obtain the N+1th slave timestamp data, substitute the N+1th slave timestamp data into the fitting curve equation, and calculate the corresponding predicted master timestamp data; The master-slave clock deviation value calculation unit is used to obtain the (N+1)th master timestamp data and calculate the time deviation value between the master timestamp data and the predicted master timestamp data.

[0033] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

[0034] It should be noted that the above embodiments can be freely combined as needed. The above description is only a preferred embodiment of the present invention. It should be pointed out that those skilled in the art can make several improvements and modifications without departing from the principles of the present invention, and such improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A least squares clock synchronization accuracy compensation method based on FPGA, characterized in that: include, Responding to a start signal from an operation enable controller; The clock data parsing module parses the timestamp data of the master and slave clock devices and caches them in the corresponding dual-port RAM until the cached amount reaches a preset timestamp sampling threshold N, triggering a pulse signal, where N is a natural number greater than 0; The FPGA control processor responds to the pulse signal, and the data reading module reads the timestamp data from the dual-port RAM and inputs the timestamp data into the least squares processing module to calculate the time deviation value of the master-slave clock device; wherein, in the least squares processing module, based on the read timestamp data, a corresponding fitting curve is calculated by the least squares method, and the slave timestamp data of the slave clock device (N+1) is substituted into the fitting curve to calculate the predicted master timestamp data of the corresponding master clock device, and the time deviation value between the master timestamp data and the predicted master timestamp data is determined; The clock deviation compensation and correction module compensates the timestamp of the slave clock device according to the time deviation value, so as to synchronize the timestamp data of the master and slave clock devices.

2. The least squares clock synchronization accuracy compensation method according to claim 1, characterized in that: The start signal of the response operation enable controller includes: Setting a fixed macrocycle in the operation enable controller to limit the working time window of the FPGA control processor; The operation enable controller generates the start signal each time the macro cycle starts; The FPGA control processor responds to the start signal and starts running within the working time window.

3. The least squares clock synchronization accuracy compensation method according to claim 1, characterized in that: The clock data parsing module parses the timestamp data of the master and slave clock devices and caches them in the corresponding dual-port RAM until the cached amount reaches a preset timestamp sampling threshold N, after which a pulse signal is triggered, where N is a natural number greater than 0, including: The clock data parsing module receives the message containing timestamp information sent by the master and slave clock devices through the Ethernet interface, extracts and converts the timestamp data into the corresponding format, the timestamp data including the master timestamp data and the slave timestamp data; The timestamp data is cached in the corresponding dual-port RAM, and the pulse signal is sent when the cached timestamp data reaches the preset timestamp sampling threshold to trigger the data reading module to read the timestamp data from the dual-port RAM and send it to the least squares processing module for calculation.

4. The least squares clock synchronization accuracy compensation method according to claim 1, characterized in that: Calculating a corresponding fitting curve based on the read timestamp data by the least squares method includes: Based on the read timestamp data, the slope and intercept of the fitting curve are calculated; wherein the slope k and the intercept b are calculated using the following formulas: ； ； Wherein, X is the timestamp data of the slave clock device, Y is the timestamp data of the master clock device, the value range of i is 1 to N, and n is the number of sampling times N; The corresponding fitting curve equation is constructed according to the calculated slope and intercept.

5. The least squares clock synchronization accuracy compensation method according to claim 4, characterized in that: The slope k and the intercept b are calculated using the lower 32 bits of the timestamp data.

6. The least squares clock synchronization accuracy compensation method according to claim 4, characterized in that: Substituting the slave timestamp data of the slave clock device of the N+1th time into the fitting curve, calculating the predicted master timestamp data of the corresponding master clock device, and determining the time deviation value between the master timestamp data and the predicted master timestamp data includes: Obtain the N+1th slave timestamp data; Substituting the N+1th slave timestamp data into the fitting curve equation to calculate the corresponding predicted master timestamp data; The primary timestamp data of the N+1th time is obtained, and the time deviation value between the primary timestamp data and the predicted primary timestamp data is calculated.

7. The least squares clock synchronization accuracy compensation method according to claim 1, characterized in that: It also includes deploying a clock synchronization protocol on the communication nodes of the master-slave clock devices, and the clock synchronization protocol includes IEEE 1588, IEEE1588v2, and IEEE 802.1AS.

8. A least squares clock synchronization accuracy compensation system based on FPGA, adopting the least squares clock synchronization accuracy compensation method according to any one of claims 1 to 7, characterized in that: include, A clock data parsing module parses the timestamp data of the master and slave clock devices and caches them in the corresponding dual-port RAM until the cached number reaches a preset timestamp sampling threshold N, where N is a natural number greater than 0, and triggers a pulse signal; A data reading module, configured to read the timestamp data from the dual-port RAM and input the timestamp data into a least squares processing module to calculate the time deviation value of the master-slave clock device; The least squares processing module is configured to calculate a corresponding fitting curve using a least squares method based on the read timestamp data, substitute the slave timestamp data of the slave clock device (N+1) for the fitting curve, calculate the predicted master timestamp data of the corresponding master clock device, and determine the time deviation value between the master timestamp data and the predicted master timestamp data; The clock deviation compensation and correction module is used to compensate the timestamp of the slave clock device according to the time deviation value to synchronize the timestamp data of the master and slave clock devices.

9. The least squares clock synchronization accuracy compensation system according to claim 8, characterized in that: It also includes an operation enable control module, which is used to set a fixed macro cycle in the operation enable controller to limit the working time window of the FPGA control processor. Whenever the macro cycle starts, the operation enable controller generates the start signal, and the FPGA control processor responds to the start signal and starts running within the working time window.

10. The least squares clock synchronization accuracy compensation system according to claim 8, characterized in that: The least squares processing module includes: The fitting curve calculation unit is used to calculate the slope and intercept of the fitting curve according to the read timestamp data; wherein the slope k and the intercept b are calculated using the following formulas: ； ； Wherein, X is the timestamp data of the slave clock device, Y is the timestamp data of the master clock device, the value range of i is 1 to N, n is the number of sampling times N, and the corresponding fitting curve equation is constructed according to the calculated slope and intercept; a master clock prediction value calculation unit, configured to obtain the N+1th slave timestamp data, substitute the N+1th slave timestamp data into the fitting curve equation, and calculate the corresponding predicted master timestamp data; The master-slave clock deviation value calculation unit is used to obtain the (N+1)th master timestamp data and calculate the time deviation value between the master timestamp data and the predicted master timestamp data.

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