Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a display area and a non-display area surrounding the display area. A plurality of data signal lines; the data signal lines in the first display area are electrically connected with the fan-out lines through the corresponding auxiliary lines, and the data signal lines in the second display area are electrically connected with the fan-out lines; in the second display area, along the first direction, two first auxiliary wires are arranged between each group of data signal wires; wherein in the n groups of data signal lines in the second display area, each group comprises two adjacent data signal lines; the two first auxiliary lines between one group of data signal lines are electrically connected with the first pixel column or the second pixel column; in the first direction, the distance between the first data signal line and the first target auxiliary line is larger than the distance L2 between the first data signal line and the second target auxiliary line. According to the display panel, the coupling influence between the data signal lines and the auxiliary wires can be reduced, and the brightness uniformity of the display panel can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Currently, display panels typically consist of multiple light-emitting sub-pixels arranged in an array. These sub-pixels are composed of pixel circuits and light-emitting elements. The pixel circuits are typically composed of thin-film transistors (TFTs) and capacitors. The light-emitting elements can typically include organic light-emitting diodes (OLEDs) or other light-emitting devices.

[0003] When optimizing narrow-bezel designs for OLED display products, FIAA (Fanout In AA) is typically used. This means that data signal lines near the edge of the display area are not directly extended out of the display area to connect to the fanout lines in the non-display area. Instead, they are routed through auxiliary lines within the display area to a location near the center, where they are then extended out of the display area to connect to the driver chip. The FIAA approach reduces the space occupied by fanout lines in the lower bezel, thereby reducing the width of the lower bezel.

[0004] In the display area, since the sub-pixels in the part of the area using the FIAA method need to receive data signals through auxiliary wiring, when the auxiliary wiring extends to another part of the area where the FIAA method is not used, it will couple signals with the data signal lines in the non-FIAA area, resulting in a brighter or darker color cast in the displayed image. Summary of the Invention

[0005] Embodiments of the present application provide a display panel and a display device, which can improve the technical problem of poor display uniformity of the display panel when using the FIAA method.

[0006] In a first aspect, an embodiment of the present application provides a display panel, comprising:

[0007] a display area and a non-display area surrounding the display area; the display area includes a first display area and a second display area, the first display area is located on at least one side of the second display area along a first direction; the first direction intersects the second direction;

[0008] a plurality of data signal lines, the plurality of data signal lines being arranged in the first display area and the second display area, the plurality of data signal lines extending along the second direction and the plurality of data signal lines being arranged sequentially along the first direction;

[0009] a plurality of auxiliary lines, the auxiliary lines comprising a first auxiliary line and a second auxiliary line; in the second display area, the first auxiliary line extends along the second direction; in the first display area and the second display area, the second auxiliary line extends along the first direction;

[0010] The data signal lines in the first display area are electrically connected to the fan-out lines through corresponding auxiliary lines, and the data signal lines in the second display area are electrically connected to the fan-out lines;

[0011] In the second display area, along the first direction, each group of data signal lines includes two first auxiliary lines; wherein the 2n data signal lines in the second display area are divided into n groups of data signal lines, and a group of data signal lines includes two adjacent data signal lines.

[0012] Optionally, the display area includes a first pixel column and a second pixel column alternately arranged along a first direction, the first pixel column includes a first color sub-pixel and a second color sub-pixel alternately arranged along a second direction, and the second pixel column includes a third color sub-pixel arranged along the second direction;

[0013] In the second display area, two first auxiliary wirings located between a group of data signal lines are both electrically connected to the first pixel column in the first display area, or are both electrically connected to the second pixel column in the first display area.

[0014] Optionally, the colors of two sub-pixels in the same row of any two adjacent first pixel columns are different;

[0015] In the second display area, when two first auxiliary routing lines located between a group of data signal lines are both electrically connected to the first pixel column in the first display area, the group of data signal lines includes a first data signal line electrically connected to the first pixel column in the second display area and a second data signal line electrically connected to the second pixel column in the second display area, and the two first auxiliary routing lines are respectively a first target auxiliary routing line and a second target auxiliary routing line;

[0016] In the first pixel column corresponding to the first data signal line and the first pixel column corresponding to the first target auxiliary wiring, sub-pixels located in the same row have the same color; in the first pixel column corresponding to the first data signal line and the first pixel column corresponding to the second target auxiliary wiring, sub-pixels located in the same row have different colors;

[0017] Along the first direction, the distance between the first data signal line and the first target auxiliary wiring is L1, and the distance between the first data signal line and the second target auxiliary wiring is L2; ​​wherein,

[0018] L1>L2.

[0019] In a second aspect, an embodiment of the present application provides a display device comprising the display panel of the first aspect.

[0020] Compared with the prior art, the display panel and display device provided by the embodiments of the present application are characterized in that each group of data signal lines in the second display area includes adjacent first data signal lines and second data signal lines, which are electrically connected to adjacent first pixel columns and second pixel columns in the second display area, respectively. Two first auxiliary routing lines are arranged between the first data signal line and the second data signal line, and both first auxiliary routing lines are electrically connected to the first pixel column in the first display area, or both first auxiliary routing lines are connected to the second pixel column in the first display area. When both first auxiliary routing lines are connected to the first pixel column, the two first auxiliary routing lines are respectively a first target auxiliary routing line and a second target auxiliary routing line. For sub-pixels in the same row, the first target auxiliary routing line has the same color as the sub-pixel corresponding to the first data signal line, and the second target auxiliary routing line has a different color from the sub-pixel corresponding to the first data signal line. The first target auxiliary routing line is farther away from the first data signal line than the second target auxiliary routing line. When both the first data signal line and the two auxiliary lines are transmitting data signals, the second target auxiliary line, which is closer to the first data signal line, corresponds to sub-pixels of different colors, and therefore provides a certain difference in data voltage. In this case, the coupling effect between the two signal lines is relatively weak. However, since the first data signal line and the first target auxiliary line, which correspond to the same color, are farther apart, the coupling effect between the two signal lines is also relatively weak. This design reduces the coupling effect between the existing data signal line and the newly added auxiliary lines in the second display area using the FIAA routing scheme, improving the brightness uniformity and stability of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 is a schematic structural diagram of a display panel in related art;

[0023] Figure 2 is a structural diagram of a display panel provided in one embodiment of the present application;

[0024] Figure 3 is a structural diagram of a display panel provided by another embodiment of the present application;

[0025] Figure 4This is a schematic structural diagram of a sub-pixel array arrangement provided in one embodiment of the present application;

[0026] Figure 5 is a structural diagram of a sub-pixel array arrangement provided by another embodiment of the present application;

[0027] Figure 6 This is a schematic structural diagram of auxiliary wiring of a display panel provided in one embodiment of the present application;

[0028] Figure 7 This is a schematic structural diagram of a data signal line of a display panel provided by an embodiment of the present application;

[0029] Figure 8 This is a schematic structural diagram of a signal gating circuit for a display panel provided in one embodiment of the present application;

[0030] Figure 9 is a structural diagram of a signal gating circuit for a display panel provided by another embodiment of the present application;

[0031] Figure 10 1 is a schematic structural diagram of a signal gating circuit for a display panel provided in another embodiment of the present application;

[0032] Figure 11 This is a timing diagram of the row scanning phase provided by an embodiment of the present application;

[0033] Figure 12 is a structural diagram of a display panel provided in another embodiment of the present application;

[0034] Figure 13 This is one of the structural diagrams of a display panel provided in yet another embodiment of the present application;

[0035] Figure 14 This is a second structural diagram of a display panel provided in yet another embodiment of the present application;

[0036] Figure 15 This is a schematic diagram of the structure of the signal routing of the display panel provided by an embodiment of the present application;

[0037] Figure 16 This is a schematic structural diagram of signal routing of a display panel provided by another embodiment of the present application;

[0038] Figure 17 This is a third structural diagram of a display panel provided in yet another embodiment of the present application;

[0039] Figure 18 A schematic structural diagram of a display device provided in an embodiment of the present application.

[0040] In the attached figure:

[0041] AA, display area; NA, non-display area; AA1, first display area; AA, second display area; X, first direction; Y, second direction; 10, data signal line; 11, first data signal line; 12, second data signal line; 20, auxiliary routing; 21, first auxiliary routing; 22, second auxiliary routing; 30, fan-out routing; FA, fan-out area; 41, first pixel column; 42, second pixel column; 211, first target auxiliary routing; 212, second target auxiliary routing; 51, first color sub-pixel; 52, second color sub-pixel; 53, third color sub-pixel; 60, signal selection circuit; Source, source routing; Q1, first selection unit; Q2, second selection unit. DETAILED DESCRIPTION

[0042] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0043] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0044] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The embodiments will be described in detail below with reference to the accompanying drawings.

[0045] Currently, display panels are typically composed of multiple light-emitting sub-pixels arranged in an array. Each sub-pixel consists of a pixel circuit and a light-emitting element. The pixel circuit is typically composed of a TFT and a capacitor. The light-emitting element can typically include an OLED or other light-emitting device.

[0046] When optimizing narrow-border designs for OLED display products, FIAA is usually used. Figure 1 As shown, data signal lines 10 near the edge of display area AA do not extend directly downward from display area AA to electrically connect to the fan-out lines in non-display area NA. Instead, they are routed through auxiliary lines 20 within display area AA to a location near the center before extending downward from display area AA to electrically connect to the driver chip. This FIAA approach reduces the space occupied by fan-out lines in the lower bezel, thereby reducing the width of the lower bezel.

[0047] In the display area, since the sub-pixels in the part of the area using the FIAA method need to receive data signals through auxiliary wiring, when the auxiliary wiring extends to another part of the area where the FIAA method is not used, it will couple signals with the data signal lines in the non-FIAA area, resulting in a brighter or darker color cast in the displayed image.

[0048] In order to solve the above technical problems, the embodiments of the present application provide a display panel and a display device. The display panel provided by the embodiments of the present application is first introduced below.

[0049] Figure 2 The structure diagram of a display panel provided by one embodiment of the present application is shown. The display panel includes a display area AA, a non-display area NA, a plurality of data signal lines 10 and a plurality of auxiliary lines 20.

[0050] The non-display area NA is arranged around the display area AA. The display area AA may include a first display area AA1 and a second display area AA2. The first display area AA1 is located on at least one side of the second display area AA2 along the first direction X.

[0051] A plurality of data signal lines 10 are respectively disposed in the first display area AA1 and the second display area AA2 and are sequentially spaced apart along a first direction X. Each data signal line 10 extends along a second direction Y. The first direction X and the second direction Y intersect.

[0052] Each auxiliary trace 20 includes a first auxiliary trace 21 and a second auxiliary trace 22. In the second display area AA2, the first auxiliary trace 21 extends along the second direction Y; in the first display area AA1 and the second display area AA2, the second auxiliary trace 22 extends along the first direction X.

[0053] In one embodiment, the first auxiliary routing line 21 extends upward along the second direction Y from the boundary between the non-display area NA and the display area AA, and when extending to a certain position, overlaps with the second auxiliary routing line 22 extending along the first direction X. The first auxiliary routing line 21 and the second auxiliary routing line 22 can be electrically connected through a via at the overlapping position.

[0054] It can be understood that since the first display area AA1 is located on one side of the second display area AA2 along the first direction X, the first auxiliary trace 21 can extend only in the second display area AA2 when extending along the second direction Y, and the second auxiliary trace 22 connected to the first auxiliary trace 21, when extending along the first direction X, a portion of the second auxiliary trace 22 is located in the second display area AA2, and the other portion of the second auxiliary trace 22 is located in the first display area AA1.

[0055] Please refer to Figure 3 The first display area AA1 and the second display area AA2 each include multiple data signal lines 10. Each data signal line 10 can provide data signals for the sub-pixels in the same column. The data signal lines 10 in the first display area AA1 can be electrically connected to the fan-out lines 30 in the non-display area NA via corresponding auxiliary lines 20. The data signals provided by the fan-out lines 30 can be transmitted to the data signal lines 10 via the auxiliary lines 20, so that the data signals are written into the sub-pixels via the data signal lines 10.

[0056] The data signal lines 10 located in the second display area AA2 may directly extend along the second direction Y, and after extending out of the second display area AA2 , are connected to the fan-out lines 30 of the non-display area NA.

[0057] In the second display area AA2, the signal lines extending along the second direction Y include the first auxiliary lines 21 and the data signal lines 10 located in the second display area AA2. Along the first direction X, the first auxiliary lines 21 and the data signal lines 10 may be arranged in the following manner:

[0058] Taking the second display area AA2 including 2n data signal lines 10 as an example, the 2n data signal lines 10 can be divided into n groups of data signal lines 10 , and each group of data signal lines 10 includes two adjacent data signal lines 10 .

[0059] Please continue to refer to Figure 3 Two first auxiliary traces 21 are included between each group of data signal lines 10. For example, if the second display area AA2 includes four data signal lines 10, and they are numbered ①②③④ in arrangement order, two first auxiliary traces 21 are provided between ① and ②. ①, ②, and the first auxiliary traces 21 all extend along the second direction Y. Therefore, ①, ②, and the first auxiliary traces 21 do not overlap during the extension process.

[0060] Similarly, two first auxiliary traces 21 are respectively provided between ③ and ④, and ③, ④ and the first auxiliary traces 21 will not overlap during the extension process.

[0061] It can be understood that, for two adjacent data signal lines that do not belong to the same group, for example, ② and ③, no first auxiliary trace 21 is provided between ② and ③.

[0062] Please refer to Figure 4 In the above embodiment, the display area AA may include first pixel columns 41 and second pixel columns 42 alternately arranged along the first direction X. The first pixel columns 41 may include first color sub-pixels 51 and second color sub-pixels 52 alternately arranged along the second direction Y, and the second pixel columns 42 may include third color sub-pixels 53 arranged along the second direction Y.

[0063] Please refer to Figure 3 and Figure 4 In the second display area AA2, the two first auxiliary lines 21 arranged between a group of data signal lines 10 are both electrically connected to the first pixel column 41 in the first display area AA1, or the two first auxiliary lines 21 are both electrically connected to the second pixel column 42 in the first display area AA1.

[0064] As an optional implementation, taking the second display area AA2 including four data signal lines 10 as an example, Figure 3 As shown, the four data signal lines are ①②③④.

[0065] The two first auxiliary traces 21 disposed between the data signal line ① and the data signal line ② can be respectively extended to the first display area AA1 through the corresponding two second auxiliary traces 22 and electrically connected to the two first pixel columns 41 in the first display area AA1.

[0066] The two first auxiliary traces 21 disposed between the data signal line ③ and the data signal line ④ may be respectively extended to the first display area AA1 through the corresponding two second auxiliary traces 22 and electrically connected to the two second pixel columns 42 in the first display area AA1.

[0067] By analogy, in the second display area AA2, after the 2n data signal lines 10 are divided into n groups of data signal lines 10, the two data signal lines 10 in each group of data signal lines 10 are respectively connected to the first pixel column 41 and the second pixel column 42 in the second display area AA2, and the two first auxiliary lines 21 sandwiched between the two data signal lines 10 are both electrically connected to the first pixel column 41 in the first display area AA1, or, are both electrically connected to the second pixel column 42 in the first display area AA1.

[0068] In the above embodiment, the sub-pixels of the first pixel column 41 are arranged in such a manner that the two sub-pixels in the same row of any two adjacent first pixel columns 41 have different colors. Figure 4 and Figure 5In the display area AA, the first pixel columns 41 and the second pixel columns 42 are alternately arranged along the first direction X. Taking the first and third columns as two adjacent first pixel columns 41 as an example, in the same row of sub-pixels, if the sub-pixel corresponding to the first column is the first color sub-pixel 51, then the sub-pixel corresponding to the third column is the second color sub-pixel 52.

[0069] Please refer to Figure 6 In the second display area AA2, when the two first auxiliary routing lines 21 located between a group of data signal lines 10 are both electrically connected to the first pixel column 41 in the first display area AA1, the two first auxiliary routing lines 21 are respectively a first target auxiliary routing line 211 and a second target auxiliary routing line 212. The group of data signal lines 10 may include a first data signal line 11 electrically connected to the first pixel column 41 in the second display area AA2 and a second data signal line 12 electrically connected to the second pixel column 42 in the second display area AA2, and the first pixel column 41 and the second pixel column 42 connected by the group of data signal lines 10 are two adjacent pixel columns.

[0070] like Figure 6 As shown, taking the first data signal line 11 and the second data signal line 12 in a group of data signal lines 10, and the first target auxiliary routing line 211 and the second target auxiliary routing line 212 sandwiched between the first data signal line 11 and the second data signal line 12 as examples, the sub-pixels located in the same row of the first pixel column 41 in the second display area AA2 corresponding to the first data signal line 11 and the first pixel column 41 in the first display area AA1 corresponding to the first target auxiliary routing line 211 have the same color. For example, if the sub-pixels in the first row of the two first pixel columns 41 corresponding to the first data signal line 11 and the first target auxiliary routing line 211 are P1 and P2, respectively, then the sub-pixels P1 and P2 have the same color.

[0071] In the second display area AA2, the sub-pixels in the same row of the first pixel column 41 corresponding to the first data signal line 11 and the first pixel column 41 corresponding to the second target auxiliary routing line 212 have different colors. That is, when two first auxiliary routing lines 21 between a set of data signal lines 10 are both electrically connected to a first pixel column 41 containing sub-pixels of two colors, the two first auxiliary routing lines 21 correspond to sub-pixels of two different colors in the same row. For example, if the sub-pixels in the first row of the two first pixel columns 41 corresponding to the first data signal line 11 and the second target auxiliary routing line 212 in the second display area AA2 are P3 and P2, respectively, then sub-pixels P3 and P2 have different colors.

[0072] Along the first direction X, the distance between the first data signal line 11 and the first target auxiliary trace 211 is L1 , the distance between the first data signal line 11 and the second target auxiliary trace 212 is L2 , and L1 > L2 .

[0073] In the same row, the color of the subpixel corresponding to the first target auxiliary trace 211 is the same as that of the subpixel corresponding to the first data signal line 11 , and the color of the subpixel corresponding to the second target auxiliary trace 212 is different from that of the subpixel corresponding to the first data signal line 11 .

[0074] Taking the first row as an example, the sub-pixel corresponding to the first data signal line 11 is P2, and the sub-pixel P2 is the first color sub-pixel 51; the sub-pixel corresponding to the first target auxiliary routing 211 is P1, and the sub-pixel P1 is also the first color sub-pixel 51; the sub-pixel corresponding to the second target auxiliary routing 212 is P3, and the sub-pixel P3 is the second color sub-pixel 52. Then, the distance L1 between the first target auxiliary routing 211 and the first data signal line 11 in the first direction X is greater than the distance L2 between the second target auxiliary routing 212 and the first data signal line 11 in the first direction X. That is, the first target auxiliary routing 211 is farther away from the first data signal line 11 than the second target auxiliary routing 212.

[0075] It should be noted that if the two first auxiliary lines 21 between a group of data signal lines 10 are both electrically connected to the second pixel columns 42, since the two second pixel columns 42 are both third color sub-pixels 53, the distance between the two first auxiliary lines 21 and the first data signal line 11 in the group of data signal lines 10 is not limited.

[0076] In this embodiment, each group of data signal lines 10 in the second display area AA2 includes adjacent first and second data signal lines 11, 12. The first and second data signal lines 11, 12 are electrically connected to adjacent first and second pixel columns 41, 42 in the second display area AA2, respectively. Two first auxiliary lines 21 are disposed between the first and second data signal lines 11, 12. Both first auxiliary lines 21 are electrically connected to the first pixel column 41 in the first display area AA1, or both first auxiliary lines 21 are connected to the second pixel column 42 in the first display area AA1. When both first auxiliary lines 21 are connected to the first pixel column 41, the two first auxiliary lines 21 are respectively a first target auxiliary line 211 and a second target auxiliary line 212. Because the first data signal line 11 is connected to the first pixel column 41, in the same row, the sub-pixels corresponding to the first data signal line 11, the first target auxiliary routing 211, and the second target auxiliary routing 212 are first color sub-pixels 51 and second color sub-pixels 52, while the sub-pixels corresponding to the second data signal line 12 are third color sub-pixels 53. For the sub-pixels in the same row, the sub-pixels corresponding to the first target auxiliary routing 211 and the first data signal line 11 have the same color, while the sub-pixels corresponding to the second target auxiliary routing 212 and the first data signal line 11 have different colors. The first target auxiliary routing 211 and the second target auxiliary routing 212 are respectively distances L1 and L2 from the first data signal line 11 along the first direction X. In the signal routing layout design, L1>L2 can be set, i.e., the first target auxiliary routing 211 is farther from the first data signal line 11 than the second target auxiliary routing 212. When both the first data signal line 11 and the two auxiliary lines 20 are transmitting data signals, the second target auxiliary line 212, which is closer to the first data signal line 11, corresponds to sub-pixels of different colors, and therefore provides a certain difference in data voltage. In this case, the coupling effect between the two signal lines is relatively weak. However, since the first data signal line 11 and the first target auxiliary line 211, which correspond to the same color, are farther apart, the coupling effect between the two signal lines is also relatively weak. This design reduces the coupling effect between the existing data signal line 10 and the newly added auxiliary lines 20 in the second display area AA2 in the FIAA routing scheme, improving the brightness uniformity and stability of the display panel.

[0077] Please refer to Figure 7In some embodiments, in the second display area AA2, along the first direction X, any two adjacent data signal lines 10 may be two data signal lines 10 in the same group of data signal lines 10, or may belong to two separate groups of data signal lines 10. If the two adjacent data signal lines 10 are two data signal lines 10 in the same group of data signal lines 10, the distance between the two data signal lines 10 is L3; if the two adjacent data signal lines 10 belong to two separate groups of data signal lines 10, the distance between the two data signal lines 10 is L4. L3 and L4 satisfy the following relationship:

[0078] L3>L4.

[0079] When the data signal lines 10 are arranged sequentially along the first direction X, each data signal line 10 needs to be electrically connected to the sub-pixels in the same column to provide data signals to the sub-pixels. However, the orthographic projections of the data signal lines 10 on the substrate of the display panel are generally not arranged to overlap with the orthographic projections of the sub-pixels on the substrate of the display panel. Therefore, the data signal lines 10 can be arranged on both sides of a corresponding column of sub-pixels. For example, the data signal lines 10 can be arranged on the left or right side of a column of sub-pixels.

[0080] like Figure 7 As shown, in the above embodiment, for two data signal lines 10 in the same group of data signal lines 10, the signal routing arrangement can be such that two columns of sub-pixels are disposed between the two data signal lines 10, with each data signal line 10 electrically connected to the column of sub-pixels that is closer to the other of the two columns of sub-pixels. That is, the two data signal lines 10 in the same group are disposed on either side of the corresponding two columns of sub-pixels. Therefore, a width of at least two columns of sub-pixels must be retained between the two data signal lines 10 in the same group. In this case, the distance L3 between the two data signal lines 10 should be set to be at least greater than the width of the two columns of sub-pixels.

[0081] Accordingly, if two adjacent data signal lines 10 belong to two groups of data signal lines 10, one or more columns of sub-pixels are not disposed between the two data signal lines 10. Therefore, the distance L4 between the two data signal lines 10 can be set to a smaller width. That is, L3>L4.

[0082] like Figure 7 As shown, in the first display area AA1, the arrangement of the data signal lines 10 can be the same as the arrangement of the data signal lines 10 in the second display area AA2, that is, if two adjacent data signal lines 10 belong to the same group of data signal lines, the distance between the two data signal lines 10 is wider to be used for arranging two columns of sub-pixels; if two adjacent data signal lines 10 do not belong to the same group of data signal lines, the distance between the two data signal lines 10 is narrower.

[0083] As another optional embodiment, in the first display area AA1, the data signal lines 10 can be arranged such that each data signal line 10 is disposed on the same side of the corresponding sub-pixel column, for example, on the left or right side of the sub-pixel column. In this case, the multiple data signal lines do not need to be grouped in pairs, and the distance between any two adjacent data signal lines 10 only needs to be greater than the width of a single column of sub-pixels.

[0084] In some embodiments, the display panel may further include a plurality of signal gating circuits 60. The input end of the signal gating circuit 60 may be electrically connected to a driver chip (not shown) via a source line Source. The signal gating circuit 60 may include at least two output ends, each of which is electrically connected to a corresponding fan-out line 30. Each fan-out line 30 may be electrically connected to a corresponding data signal line 10 or auxiliary line 20. The signal gating circuit 60 may output a data signal on the source line Source to the fan-out line 30 via one of the output ends, and transmit the data signal to the corresponding data signal line 10 via the fan-out line 30 to implement data signal writing for the sub-pixel.

[0085] It should be noted that the plurality of fan-out traces 30 are respectively electrically connected to the plurality of data signal lines 10. With respect to the data signal lines 10 in the first display area AA1, the fan-out traces 30 can extend into the fan-out area FA of the non-display area NA between the signal selection circuit 60 and the display area AA, and electrically connect to the corresponding first auxiliary traces 21 at the junction of the display area AA and the fan-out area FA. The data signals are transmitted to the data signal lines 10 in the first display area AA1 via the corresponding first auxiliary traces 21 and second auxiliary traces 22, i.e., an FIAA routing scheme.

[0086] For the data signal line 10 in the second display area AA2, the fan-out line 30 can be extended in the fan-out area FA of the non-display area NA between the signal selection circuit 60 and the display area AA, and electrically connected to the corresponding data signal line 10 at the junction of the display area AA and the fan-out area FA.

[0087] Please refer to Figure 8 In some embodiments, the signal gating circuit 60 may include a first gating unit Q1 and a second gating unit Q2.

[0088] A first end of the first gating unit Q1 may be connected to the source wiring Source, and a second end of the first gating unit Q1 may be connected to the first fan-out wiring 31 .

[0089] A first end of the second gating unit Q2 is connected to the source wiring Source, and a second end of the first gating unit Q1 is connected to the second fan-out wiring 32 .

[0090] The data signal line 10 corresponding to the first fan-out routing 31 is electrically connected to the first pixel column 41, and the data signal line 10 corresponding to the second fan-out routing 32 is electrically connected to the second pixel column 42. That is, a single signal gating circuit 60 can sequentially provide data signals to two sub-pixels in the same row, where the two sub-pixels belong to the first pixel column 41 and the second pixel column 42, respectively.

[0091] As another optional implementation, please refer to Figure 9 When the signal gating circuit 60 is electrically connected to the data signal lines 10 of the first display area AA1, the first gating unit Q1 and the second gating unit Q2 included in the signal gating circuit 60 are respectively connected to the two first auxiliary traces 21 sandwiched between the same group of data signal lines 10. Since the two first auxiliary traces 21 sandwiched between the same group of data signal lines 10 are either connected to the first pixel column 41 or to the second pixel column 42, in this embodiment, the signal gating circuit 60 can sequentially provide data signals to two sub-pixels in the same row in the first display area AA1, and both sub-pixels belong to the first pixel column 41 or the second pixel column 42.

[0092] It is understandable that in the above embodiment, Figure 10 As shown, when the signal gating circuit 60 is electrically connected to the data signal lines 10 of the second display area AA2, the first gating unit Q1 and the second gating unit Q2 can be respectively connected to two data signal lines in the same group of data signal lines 10. That is, when the signal gating circuit 60 successively provides data signals to two sub-pixels in the same row in the second display area AA2, the two sub-pixels belong to the first pixel column 41 and the second pixel column 42, respectively.

[0093] Please refer to Figure 11 In some embodiments, the above-mentioned single row scanning phase may include a first selection phase t1, a second selection phase t2, and a scanning signal valid phase t3.

[0094] Refer to Figure 9 and Figure 11 In the first gating stage t1, the first gating unit Q1 receives a valid turn-on signal and turns on. At this time, the first data voltage provided by the source line Source can be transmitted to the data signal line 10 corresponding to the first pixel column 41 through the first gating unit Q1.

[0095] In the second gating stage t2 , the second gating unit Q2 receives a valid turn-on signal and turns on. At this time, the second data voltage provided by the source line Source can be transmitted to the data signal line 10 corresponding to the second pixel column 42 through the second gating unit Q2 .

[0096] It should be noted that the source line Source can perform voltage jump between the first gating stage t1 and the second gating stage t2 to jump the first data voltage to the second data voltage.

[0097] In the scan signal valid phase t3, the sub-pixels in the pixel row corresponding to the row scan phase receive the Scan valid signal. At this time, the data writing transistor in the pixel circuit of the sub-pixel is turned on, and the data signal line 10 corresponding to the first pixel column 41 can transmit the first data voltage written in the first selection phase t1 to the first color sub-pixel 51 or the second color sub-pixel 52, and the data signal line 10 corresponding to the second pixel column 42 can transmit the second data voltage written in the second selection phase t2 to the third color sub-pixel 53.

[0098] In the above embodiment, in a single row scanning phase, the first selection phase t1 may precede the second selection phase t2, and the first selection phase t1 and the second selection phase t2 do not overlap, so that the source line Source can perform a voltage jump between the first selection phase t1 and the second selection phase t2. The second selection phase t2 may precede the scanning signal valid phase t3, and the second selection phase t2 may or may not overlap with the scanning signal valid phase t3.

[0099] Because the first selection phase t1 does not overlap with the scan signal valid phase t3, the first data voltage can only reach the data signal line 10 corresponding to the first pixel column 41 during the first selection phase t1. The first data voltage stored on the data signal line 10 can only be written into the sub-pixel during the scan signal valid phase t3. In other words, the data signal writing method for the first pixel column 41 is the line charging method.

[0100] For the second pixel column 42 , when the second selection phase t2 does not coincide with the scanning signal valid phase t3 , the data signal writing method for the second pixel column 42 is also the line charging method.

[0101] like Figure 11 As shown, when the second selection phase t2 at least partially overlaps with the scanning signal valid phase t3, within the overlapping interval, the second data voltage provided by the source wiring Source can be directly written into the sub-pixel of the second pixel column 42 through the turned-on second selection unit Q2. At this time, the data signal writing method of the second pixel column 42 is a hybrid charging method of direct charging first and then line charging.

[0102] As another optional embodiment, a second strobe stage t2 may be provided before the first strobe stage t1 in a single row scanning phase. In this case, the data signal writing method for the second pixel column 42 is the line charging method. Depending on whether there is a partial overlap between the first strobe stage t1 and the scanning signal valid phase t3, the data signal writing method for the first pixel column 41 may be the line charging method or the hybrid charging method.

[0103] Please refer to Figure 3 In some embodiments, the non-display area NA may further include a fan-out area FA located on one side of the display area AA along the second direction Y. The fan-out area FA may include a plurality of fan-out traces 30. The number of fan-out traces 30 is a, and the total number of data signal lines 10 in the first display area AA1 and the second display area AA2 is b. A and b satisfy the following relationship:

[0104] a≥b;

[0105] In the display area AA of the display panel, the data signal lines 10 in the first display area AA1 do not extend directly along the second direction Y to the non-display area NA to connect with the fan-out lines 30. Instead, they extend to the first display area AA1 via the first auxiliary lines 21 and the second auxiliary lines 22, and connect with the fan-out lines 30 at the boundary between the first display area AA1 and the non-display area NA. Therefore, no fan-out lines 30 are provided at the boundary between the first display area AA1 and the non-display area NA, thereby reducing the border area around the first display area AA1 and achieving a narrow border.

[0106] In the second display area AA2, in addition to the multiple data signal lines 10 corresponding to the sub-pixels in the second display area AA2, it also includes the first auxiliary wiring 21 and the second auxiliary wiring 22 corresponding to the first display area AA1. Therefore, the number and density of signal wiring in the second display area AA2 exceed those in the normal display area.

[0107] Please refer to Figure 12 In addition to the first display area AA1 and the second display area AA2, the display panel may also include a third display area AA3. The data signal lines 10 in the third display area AA3 are not connected to the fan-out lines 30 via the auxiliary lines 20. The third display area AA3 also lacks the first auxiliary lines 21 and the second auxiliary lines 22 corresponding to the first display area AA1. Therefore, the only signal lines that need to provide data signals in the third display area AA3 are the data signal lines 10 corresponding to the sub-pixel columns within the third display area AA3.

[0108] It is understandable that when the display area AA includes only the first display area AA1 and the second display area AA2 , the number a of the fan-out lines 30 is consistent with the total number b of the data signal lines 10 in the first display area AA1 and the second display area AA2 , ie a=b.

[0109] When the display area AA includes the first display area AA1, the second display area AA2, and the third display area AA3, a portion of the fan-out traces 30 are connected to the data signal lines 10 in the third display area AA3. Therefore, the number a of the fan-out traces 30 should be greater than the total number b of the data signal lines 10 in the first display area AA1 and the second display area AA2, that is, a>b.

[0110] In some embodiments, when the display area AA further includes the third display area AA3 , the first display area AA1 and the third display area AA3 may be located along the first direction X on both sides of the second display area AA2 , respectively.

[0111] like Figure 12 As shown, when the auxiliary trace 20 corresponding to the data signal line 10 of the first display area AA1 extends from the first display area AA1 to the adjacent display area AA, the display area AA to which the auxiliary trace 20 extends is the second display area AA2, and the display area AA to which the auxiliary trace 20 does not extend is the third display area AA3. Therefore, the second display area AA2 is adjacent to the first display area AA1, and the third display area AA3 can be separated from the first display area AA1 by the second display area AA2.

[0112] In some embodiments, the data signal lines 10 in the first display area AA1 are electrically connected to the corresponding fan-out lines 30 through the corresponding second auxiliary lines 22 and first auxiliary lines 21 .

[0113] In the first display area AA1, the data signal lines 10 do not extend directly to the non-display area NA. Instead, they extend through the second auxiliary lines 22 and the first auxiliary lines 21 in the display area AA to the second display area AA2, and are electrically connected to the corresponding fan-out lines 30 at the boundary between the second display area AA2 and the non-display area NA. Therefore, the data signal lines 10 in the first display area AA1 are electrically connected to the corresponding fan-out lines 30 at the boundary between the second display area AA2 and the non-display area NA; the data signal lines 10 in the second display area AA2 can be directly extended to the boundary between the second display area AA2 and the non-display area NA, and electrically connected to the corresponding fan-out lines 30. In other words, the fan-out lines 30 corresponding to the first display area AA1 and the second display area AA2 can both be disposed at the boundary between the second display area AA2 and the non-display area NA. In this case, no fan-out lines 30 are required at the boundary between the first display area AA1 and the non-display area NA, which can reduce the size of the border area of ​​this portion of the non-display area NA and achieve a narrow border effect.

[0114] Please refer to Figure 3In some embodiments, among the two second auxiliary routing lines 22 corresponding to any two pixel columns, the distance L5 between the second auxiliary routing line 22 corresponding to the pixel column close to the non-display area NA along the first direction X and the fan-out area FA is greater than the distance L6 between the other second auxiliary routing line 22 and the fan-out area FA, that is, L5>L6.

[0115] As an exemplary embodiment, the two pixel columns mentioned above may be any two pixel columns in the first display area AA1. Since the plurality of pixel columns in the first display area AA1 are arranged along the first direction X, one of the two pixel columns must be closer to the non-display area NA along the first direction X. For example Figure 13 As shown, if the first display area AA1 is the left area of ​​the display area AA, and the pixel columns in the first display area AA1 extend in the up-down direction and are arranged in the left-right direction, then one of the two pixel columns must be closer to the edge of the display area AA.

[0116] The two second auxiliary traces 22 corresponding to the two pixel columns are both signal traces extending in the first direction X. The second auxiliary traces 22 corresponding to the pixel columns closer to the edge are farther away from the fan-out area FA. The fan-out area FA can be the non-display area NA located to one side of the display area AA along the second direction Y and where the fan-out traces 30 are arranged.

[0117] Taking the fan-out area FA as an example, if one of the two pixel columns in the first display area AA1 is closer to the edge, the second auxiliary trace 22 corresponding to that pixel column will be farther from the fan-out area FA. That is, when the second auxiliary trace 22 is closer to the fan-out area FA, it will be connected to the pixel column farther from the left edge of the display area AA. When the second auxiliary trace 22 is farther from the fan-out area FA, it will be connected to the pixel column closer to the left edge of the display area AA.

[0118] In some embodiments, among the two second auxiliary routing lines 22 corresponding to any two pixel columns, the routing length L7 of the second auxiliary routing line 22 corresponding to the pixel column close to the non-display area NA along the first direction X is greater than the routing length L8 of the other second auxiliary routing line 22, that is, L7>L8.

[0119] like Figure 14 As shown, taking the first display area AA1 as the left area of ​​the display area AA, and the pixel columns in the first display area AA1 extending in the up-down direction and arranged in the left-right direction as an example, for two pixel columns in the first display area AA1, if one pixel column is closer to the left edge of the display area AA, the corresponding second auxiliary trace 22 has a longer routing length.

[0120] As an optional implementation, based on the combination of the above two embodiments, in any two pixel columns of the first display area AA1, the second auxiliary trace 22 corresponding to the pixel column closer to the edge of the display area AA is longer and farther away from the fan-out area FA. Figure 15 As shown, after routing based on the above embodiment, a rough inverted eight design can be formed. That is, the lengths of the plurality of second auxiliary traces 22 decrease gradually as the distance from the fan-out area FA below decreases.

[0121] As an optional implementation, please refer to Figure 15 , Figure 15 1 shows a portion of the display area of ​​the display panel corresponding to 960 data signal lines 10. The 960 data signal lines 10 are numbered D1 to D960. D1 to D480 are data signal lines 10 in the first display area AA1, and D481 to D960 are data signal lines in the second display area AA2.

[0122] like Figure 15 As shown, D481 to D960 serve as data signal lines in the second display area AA2 and can directly extend out of the display area AA to be electrically connected to the fan-out wiring, while D1 to D480 serve as data signal lines 10 in the first display area AA1 and need to be electrically connected to the fan-out wiring through the first auxiliary wiring and the second auxiliary wiring.

[0123] exist Figure 15 In the illustrated embodiment, data signal lines D1 and D3 provide data signals for the first pixel column, while D2 and D4 provide signals for the second pixel column. Therefore, the two first auxiliary traces corresponding to data signal lines D1 and D3 are sandwiched between D959 and D960, and the two first auxiliary traces corresponding to data signal lines D2 and D4 are sandwiched between D957 and D958. In other words, D481 to D960 serve as data signal lines in the second display area AA2, with two first auxiliary traces disposed between every two data signal lines.

[0124] It can be understood that, in the above embodiment, the display area widths of the first display area AA1 and the second display area AA2 are consistent, both having a width of 480 pixel columns.

[0125] As another optional implementation, please combine Figure 15 and Figure 16 When the two first auxiliary traces corresponding to the data signal lines D1 and D3 are sandwiched between D959 and D960, they can be as follows: Figure 15 As shown, the first auxiliary trace corresponding to the data signal line D1 is closer to D959; it can also be as follows Figure 16 As shown, the first auxiliary trace corresponding to the data signal line D3 is closer to D959.

[0126] according to Figure 15 and Figure 16 As shown below, the light-emitting colors of the same row of luminous sub-pixels indicate that, for a certain pixel row, the sub-pixel corresponding to the data signal line D1 is a red sub-pixel R, the sub-pixel corresponding to the data signal line D3 is a blue sub-pixel B, the sub-pixel corresponding to the data signal line D959 is a blue sub-pixel B, and the sub-pixel corresponding to the data signal line 960 is a green sub-pixel G. If the implementation in the above embodiment of the present application is adopted, in the two first auxiliary lines, the corresponding sub-pixel color is the same as the sub-pixel color corresponding to the first data signal line. The first auxiliary line is farther away from the first data signal line, then the method can be used. Figure 16 In a corresponding design, the sub-pixels corresponding to the data signal line D1 and the data signal line D959 have different colors, so the first auxiliary trace corresponding to the data signal line D1 is closer to the data signal line D959.

[0127] Please refer to Figure 17 In some embodiments, based on the above implementation, among any two second auxiliary routing lines 22, the signal routing width of the second auxiliary routing line 22 with a longer routing length can be set to be greater than or equal to the routing width of the other second auxiliary routing line 22 with a shorter routing length.

[0128] It is understandable that the second auxiliary lines 22 have a certain amount of line resistance. As the length of the second auxiliary lines 22 increases, the line resistance will gradually increase, resulting in a higher voltage drop on the longer second auxiliary lines 22, causing a large deviation in the data voltage received by the corresponding pixel columns. To address the difference in data voltage drop caused by the length differences of the second auxiliary lines 22 corresponding to different pixel columns, the longer second auxiliary lines 22 can be configured with a wider line width. By increasing the line width of the second auxiliary lines 22, the line resistance of the second auxiliary lines 22 per unit length can be reduced, thereby achieving line resistance balance for second auxiliary lines 22 of different lengths, avoiding excessive line resistance in longer second auxiliary lines 22, and reducing the impact of line resistance on the data voltage received by each pixel column.

[0129] In some embodiments, the display area AA may include a plurality of sub-pixels arranged in an array. The sub-pixels include a pixel circuit and a light-emitting unit. The pixel circuit may include a driving transistor, which may be an LTPS (Low Temperature Poly-Silicon) transistor. The LTPS transistor is turned on when it receives a low-level signal and turned off when it receives a high-level signal.

[0130] The driving transistor being an LTPS transistor is only an example. The driving transistor may also be an IGZO (Indium Gallium Zinc Oxide) transistor, which is not limited here.

[0131] The present application also provides a display device 1000, see Figure 18 The display device 1000 can be a PC, a television, a monitor, a mobile terminal, a tablet computer, a wearable device, etc. The display device can include the display panel 100 provided in the embodiment of the present application.

[0132] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium that can store or transmit information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROMs, flash memories, erasable ROMs (EROMs), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0133] It should be noted that, in this article, the terms "comprises", "includes" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements that are inherent to such process, method, article or apparatus.

[0134] This article uses specific examples to illustrate the principles and implementation methods of this application. The above examples are only used to help understand the method and core ideas of this application. The above are only preferred implementation methods of this application. It should be pointed out that due to the limitations of textual expression, there are objectively infinite specific structures. For ordinary technicians in this technical field, without departing from the principles of this application, they can make several improvements, modifications or changes, and can also combine the above technical features in an appropriate manner; these improvements, modifications, changes or combinations, or the direct application of the concept and technical solution of this application to other occasions without improvement, should be regarded as the scope of protection of this application.

Claims

1. A display panel, characterized in that: The display panel includes: a display area and a non-display area surrounding the display area; the display area includes a first display area and a second display area, the first display area is located on at least one side of the second display area along a first direction; the first direction intersects the second direction; a plurality of data signal lines, the plurality of data signal lines being arranged in the first display area and the second display area, the plurality of data signal lines extending along the second direction and the plurality of data signal lines being arranged sequentially along the first direction; a plurality of auxiliary lines, the auxiliary lines comprising a first auxiliary line and a second auxiliary line; in the second display area, the first auxiliary line extends along the second direction; in the first display area and the second display area, the second auxiliary line extends along the first direction; The data signal lines in the first display area are electrically connected to the fan-out lines through corresponding auxiliary lines, and the data signal lines in the second display area are electrically connected to the fan-out lines; In the second display area, along the first direction, each group of data signal lines includes two first auxiliary lines; wherein the 2n data signal lines in the second display area are divided into n groups of data signal lines, and a group of data signal lines includes two adjacent data signal lines.

2. The display panel according to claim 1, wherein: The display area includes a first pixel column and a second pixel column alternately arranged along a first direction, the first pixel column includes first color sub-pixels and second color sub-pixels alternately arranged along a second direction, and the second pixel column includes third color sub-pixels arranged along the second direction; In the second display area, two first auxiliary wirings located between a group of data signal lines are both electrically connected to the first pixel column in the first display area, or are both electrically connected to the second pixel column in the first display area.

3. The display panel according to claim 2, wherein: The colors of the two sub-pixels in the same row of any two adjacent first pixel columns are different; In the second display area, when two first auxiliary routing lines located between a group of data signal lines are both electrically connected to the first pixel column in the first display area, the group of data signal lines includes a first data signal line electrically connected to the first pixel column in the second display area and a second data signal line electrically connected to the second pixel column in the second display area, and the two first auxiliary routing lines are respectively a first target auxiliary routing line and a second target auxiliary routing line; In the first pixel column corresponding to the first data signal line and the first pixel column corresponding to the first target auxiliary wiring, sub-pixels located in the same row have the same color; in the first pixel column corresponding to the first data signal line and the first pixel column corresponding to the second target auxiliary wiring, sub-pixels located in the same row have different colors; Along the first direction, the distance between the first data signal line and the first target auxiliary wiring is L1, and the distance between the first data signal line and the second target auxiliary wiring is L2; ​​wherein, L1>L2.

4. The display panel according to claim 2, wherein: In the second display area, along the first direction, the distance between two adjacent data signal lines in the same group of data signal lines is L3, and the distance between two adjacent data signal lines in different groups of data signal lines is L4; wherein, L3>L4.

5. The display panel according to claim 1, wherein: The display panel further includes: Multiple signal gating circuits, wherein the input end of the signal gating circuit is connected to the driver chip through the source line, and at least two output ends of the signal gating circuit are connected to the fan-out line; the signal gating circuit is configured to transmit the data signal on the source line to the corresponding data signal line through the fan-out line.

6. The display panel according to claim 5, wherein: The signal gating circuit comprises: a first gating unit, wherein a first end of the first gating unit is connected to the source wiring, and a second end of the first gating unit is connected to a first fan-out wiring; wherein a data signal line corresponding to the first fan-out wiring is electrically connected to a first pixel column; A second gating unit, wherein a first end of the second gating unit is connected to the source wiring, and a second end of the first gating unit is connected to a second fan-out wiring; wherein a data signal line corresponding to the second fan-out wiring is electrically connected to a second pixel column.

7. The display panel according to claim 6, wherein: A single row scanning phase includes a first gating phase, a second gating phase, and a scanning signal valid phase; In the first gating stage, the first gating unit is used to transmit the first data voltage provided by the source wiring to the data signal line corresponding to the first pixel column; In the second gating stage, the second gating unit is used to transmit the second data voltage provided by the source wiring to the data signal line corresponding to the second pixel column; During the effective scanning signal phase, the data signal line corresponding to the first pixel column is used to transmit the data voltage to the first color sub-pixel or the second color sub-pixel, and the data signal line corresponding to the second pixel column is used to transmit the data voltage to the third color sub-pixel.

8. The display panel according to claim 7, wherein: In a single row scanning phase, the second gating phase at least partially overlaps with the scanning signal valid phase.

9. The display panel according to claim 1, wherein: The non-display area includes a fan-out area located on one side of the display area along the second direction, and the fan-out area includes a plurality of fan-out lines; The number of the fan-out lines is a, and the total number of the data signal lines of the first display area and the second display area is b, wherein, a≥b.

10. The display panel according to claim 9, wherein: The display area further includes a third display area, and the first display area and the third display area are respectively located on both sides of the second display area along a first direction.

11. The display panel according to claim 1, wherein The data signal lines in the first display area are electrically connected to the corresponding fan-out lines through the corresponding second auxiliary lines and the first auxiliary lines.

12. The display panel according to claim 11, wherein: Among the two second auxiliary lines corresponding to any two pixel columns, the distance between the second auxiliary line corresponding to the pixel column close to the non-display area along the first direction and the fan-out area is greater than the distance between the other second auxiliary line and the fan-out area.

13. The display panel according to claim 11, wherein: Among the two second auxiliary routing lines corresponding to any two pixel columns, the routing length of the second auxiliary routing line corresponding to the pixel column close to the non-display area along the first direction is greater than the routing length of the other second auxiliary routing line.

14. The display panel according to claim 13, wherein: Of any two second auxiliary routing lines, the routing width of the second auxiliary routing line with a longer routing length is greater than or equal to the routing width of the other second auxiliary routing line.

15. The display panel according to claim 1, wherein The display area includes sub-pixels arranged in an array, and the pixel circuits of the sub-pixels include driving transistors, which are LTPS transistors.

16. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 15.

Images