Power conversion device

Abstract

The control unit (50) controls the plurality of switching elements (31a, 32a, 33a, 34a, 35a, 36a) to control the output voltage of the inverter circuit (30) so as to reduce the peak value of the maximum phase current by superimposing harmonics when the electrical angular frequency of the motor (2) is set as the fundamental frequency (omega) near the voltage peak time when the voltage of the capacitor (40) reaches the peak value, and to reduce the peak value of the maximum phase current by superimposing the harmonics when the electrical angular frequency of the motor (2) is set as the fundamental frequency (omega) near the voltage peak time when the voltage of the capacitor (40) reaches the peak value. The maximum phase current is the maximum value among absolute values of a plurality of phase currents (iv, iw) of the motor (2). The capacitance value of the capacitor (40) is set such that the voltage of the capacitor (40) is allowed to pulse at half a cycle of the single-phase AC power supply (1), such that the maximum value of the voltage is at least twice the minimum value of the voltage.

Description

Technical Field

[0001] The present disclosure relates to a power conversion device for supplying power to an electric motor. Background Art

[0002] There is a type of power conversion device that can convert power from an AC power source into any AC power. Some of these power conversion devices include a capacitor with a small capacitance in the DC link to improve the power factor (see, for example, Patent Document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2002-51589 Summary of the Invention

[0006] -Technical problem to be solved by the invention-

[0007] However, when the power conversion device of Patent Document 1 is used to supply power to a motor, the peak current in the motor tends to increase, resulting in a reduction in the operating range. One possible solution to this problem is to increase the size of the motor or the capacitance of the switching elements that make up the inverter circuit. However, this would increase the size of the device and increase its cost. Therefore, other solutions are needed.

[0008] The present disclosure is made to solve the above-mentioned problem, and its purpose is to reduce the current peak value of the motor in the power conversion device.

[0009] -Technical solutions for solving technical problems-

[0010] A first aspect of the present disclosure relates to a power conversion device 10 that supplies power to a motor 2, characterized in that the power conversion device 10 includes a conversion circuit 20, an inverter circuit 30, a capacitor 40, and a control unit 50, wherein the conversion circuit 20 rectifies an AC voltage supplied from a single-phase AC power supply 1, the inverter circuit 30 includes a plurality of switching elements 31a, 32a, 33a, 34a, 35a, and 36a, and through the operation of the plurality of switching elements 31a, 32a, 33a, 34a, 35a, and 36a, the DC power output by the conversion circuit 20 is converted into AC power and supplied to the motor 2, the capacitor 40 is connected between input nodes of the inverter circuit 30, and the control unit 50. The output voltage of the inverter circuit 30 is controlled by controlling the plurality of switching elements 31a, 32a, 33a, 34a, 35a, and 36a so that higher harmonics generated when the electrical angular frequency of the motor 2 is set to the fundamental frequency ω are superimposed near a peak voltage moment when the voltage of the capacitor 40 reaches a peak value, thereby reducing a peak value of the maximum phase current imax, which is the maximum value among the absolute values ​​of the plurality of phase currents iu, iv, and iw of the motor 2. The capacitance value of the capacitor 40 is set so that the voltage of the capacitor 40 is allowed to pulsate with a period of half a cycle of the single-phase AC power supply 1 and the maximum value of the voltage is at least twice the minimum value of the voltage.

[0011] In the first aspect, by superimposing harmonics on the phase currents iu, iv, iw of the motor 2 , the peak value of the maximum value among the absolute values ​​of the plurality of phase currents iu, iv, iw of the motor 2 can be reduced.

[0012] A second aspect of the present disclosure is based on the first aspect and is characterized in that the higher harmonics are odd harmonics relative to the fundamental frequency ω.

[0013] In the second aspect, the peak value of the maximum value of the absolute value waveform of the phase currents iu, iv, iw of the motor 2 can be reliably reduced compared to the case where higher harmonics including even harmonics with respect to the fundamental frequency ω are superimposed.

[0014] The third aspect of the present disclosure is based on the second aspect and is characterized in that the higher harmonic is at least one of the (6n+1)th harmonic and the (6n-1)th harmonic relative to the fundamental frequency ω, where n is a natural number.

[0015] The fourth aspect of the present disclosure is based on any one of the first to third aspects and is characterized in that: the control unit 50 controls the output voltage of the inverter circuit 30 so that the period other than the voltage peak moment includes a period in which the superposition is not performed.

[0016] In the fourth aspect, by not performing the superposition during the period when the voltage of capacitor 40 is low, the increase in the current and effective current value for weakening the magnetic flux can be suppressed during the period when the voltage is low. Therefore, the loss caused by the increase in the current of motor 2 can be reduced.

[0017] The fifth aspect of the present disclosure is based on any one of the first to third aspects and is characterized in that: when the waveform of the phase current after removing the higher harmonics from the phase current iu, iv, iw of the motor 2 is set as the phase current before superposition, and the maximum phase current before superposition is set to the maximum value among the absolute values ​​of the multiple phase currents before superposition corresponding to the multiple phase currents iu, iv, iw of the motor 2, the control unit 50 controls the output voltage of the inverter circuit 30 so that the peak value of the maximum phase current imax is smaller than the peak value of the maximum phase current before superposition.

[0018] In the fifth aspect, the peak value of the maximum phase current imax can be made lower than the peak value of the maximum phase current before superposition.

[0019] The sixth aspect of the present disclosure is based on the fifth aspect and is characterized in that the superposition performed by the control unit 50 is performed at least near the current peak moment when the maximum phase current reaches the peak value before the superposition, and the period other than the current peak moment includes a period when the superposition is not performed.

[0020] In the sixth aspect, by setting the period during which the current peak value is relatively low as a period during which the superposition is not performed, it is possible to suppress the loss caused by the superposition during the period.

[0021] The seventh aspect of the present disclosure is based on the fifth aspect and is characterized in that the superposition performed by the control unit 50 is performed during at least a portion of the period during which the maximum phase current before the superposition is greater than 75% of the peak value.

[0022] In the seventh aspect, the peak value of the maximum value of the absolute value waveform of the phase currents iu, iv, and iw of the electric motor 2 can be reliably reduced.

[0023] The eighth aspect of the present disclosure is based on the fifth aspect and is characterized in that: the higher harmonic is at least one of the odd harmonics relative to the fundamental frequency ω, and the amplitude of the higher harmonic is less than 20% of the amplitude |Ia| of the current vector of the superimposed front phase current.

[0024] In the eighth aspect, by setting the amplitude of the harmonics to less than 20% of the amplitude |Ia| of the current vector before superposition, the loss due to superposition of the harmonics can be reduced compared to the case where the amplitude is set to 20% or more.

[0025] The ninth aspect of the present disclosure is based on any one of the first to third aspects and is characterized in that: when the waveform of the phase current obtained by synthesizing the frequency components after removing the odd multiples of the fundamental frequency ω and the frequencies obtained by odd multiples of the fundamental frequency ω ± 2m times the power supply frequency from the multiple phase currents iu, iw, iv of the motor 2 is set as the phase current after removal, where m is a natural number, and the maximum phase current after removal is set as the maximum value among the absolute values ​​of the multiple phase currents after removal corresponding to the multiple phase currents iu, iw, iv of the motor 2, the control unit 50 controls the output voltage of the inverter circuit 30 so that the peak value of the maximum phase current imax is smaller than the peak value of the maximum phase current after removal.

[0026] In the ninth aspect, the peak value of the maximum phase current imax can be made lower than the peak value of the post-removal maximum phase current.

[0027] The tenth aspect of the present disclosure is based on the ninth aspect and is characterized in that the superposition performed by the control unit 50 is performed at least near the current peak moment when the maximum phase current reaches the peak value after the removal, and the period other than the current peak moment includes a period when the superposition is not performed.

[0028] In the tenth aspect, by setting the period during which the current peak value is relatively low as a period during which the superposition is not performed, it is possible to suppress the loss caused by the superposition during the period.

[0029] The eleventh aspect of the present disclosure is characterized in that, based on the ninth aspect, the superposition performed by the control unit 50 is performed during at least a portion of the period during which the maximum phase current after removal is greater than 75% of the peak value.

[0030] In the eleventh aspect, the peak value of the maximum value of the absolute value waveform of the phase currents iu, iv, and iw of the motor 2 can be reliably reduced.

[0031] The twelfth aspect of the present disclosure is based on the ninth aspect and is characterized in that: the higher harmonics are odd harmonics relative to the fundamental frequency ω, and the amplitude of the higher harmonics is less than 20% of the amplitude of the current vector of the phase current after removal.

[0032] In the twelfth aspect, by setting the amplitude of the higher harmonics to less than 20% of the amplitude of the current vector of the phase current after removal, the loss due to superposition of the higher harmonics can be reduced compared to the case where the amplitude is set to 20% or more.

[0033] The thirteenth aspect of the present disclosure is based on any one of the first to twelfth aspects and is characterized in that: the phase shift between the higher harmonics and the component of the fundamental frequency ω is set to: when the higher harmonics include the third harmonic, the phase shift between the third harmonic and the component of the fundamental frequency ω is -10° to 10°, and the phase shift of the fifth harmonic and the seventh harmonic contained in the higher harmonic relative to the component of the fundamental frequency ω is -5° to 5°; when the higher harmonics do not include the third harmonic, the phase shift of the fifth harmonic and the seventh harmonic contained in the higher harmonic relative to the component of the fundamental frequency ω is 176° to 184°.

[0034] In the thirteenth aspect, when the higher harmonics include the third harmonic, the current peak of the motor 2 can be effectively reduced by setting the phase offset between the third harmonic and the component of the fundamental frequency ω to -10°~10°, and setting the phase offset between the fifth harmonic and the seventh harmonic relative to the component of the fundamental frequency ω to -5°~5°.

[0035] When the higher harmonics do not include the third harmonic, the current peak of the motor 2 can be effectively reduced by setting the phase shift of the fifth and seventh harmonics relative to the component of the fundamental frequency ω to 176° to 184°.

[0036] The fourteenth aspect of the present disclosure is based on any one of the first to thirteenth aspects, and is characterized in that: the control unit 50 is based on the input current i flowing from the single-phase AC power supply 1 to the conversion circuit 20 in , the voltage V of the capacitor 40 dc , the input current I of the inverter circuit 30 dc and at least one of the output power of the inverter circuit 30 to control at least one of the amplitude and phase of the higher harmonics.

[0037] In the fourteenth aspect, higher harmonics can be controlled based on at least one of the input current flowing from the single-phase AC power supply 1 to the conversion circuit 20, the voltage of the capacitor 40, the input current of the inverter circuit 30, and the output power of the inverter circuit 30, thereby simultaneously achieving the reduction of the current peak of the motor 2 and the suppression of the higher harmonics of the input current generated by the superposition of higher harmonics.

[0038] A fifteenth aspect of the present disclosure relates to a power conversion device that supplies power to an electric motor 2, and is characterized in that: the power conversion device includes a conversion circuit 20, an inverter circuit 30, a capacitor 40 and a control unit 50, the conversion circuit 20 rectifies the AC voltage supplied from the single-phase AC power supply 1, the inverter circuit 30 has a plurality of switching elements 31a, 32a, 33a, 34a, 35a, 36a, and through the operation of the plurality of switching elements 31a, 32a, 33a, 34a, 35a, 36a, the DC power output by the conversion circuit 20 is converted into AC power and supplied to the electric motor 2, the capacitor 40 is connected between the input nodes of the inverter circuit 30, and the control unit 50 controls the plurality of The switching elements 31a, 32a, 33a, 34a, 35a, and 36a are controlled to control the output voltage of the inverter circuit 30, so that when the electrical angular frequency of the motor 2 is set to the fundamental frequency ω and the maximum phase current imax is set to the maximum value among the absolute values ​​of the multiple phase currents iu, iv, and iw of the motor 2, higher harmonics relative to the fundamental frequency ω are superimposed, thereby reducing the peak value of the maximum phase current imax. The capacitance value of the capacitor 40 is set to allow the voltage of the capacitor 40 to pulsate with a period of half a cycle of the single-phase AC power supply 1, so that the maximum value of the voltage becomes more than twice the minimum value of the voltage, and the higher harmonics are odd harmonics relative to the fundamental frequency ω.

[0039] In the fifteenth aspect, by controlling the inverter circuit 30 , the peak value of the maximum value among the absolute values ​​of the plurality of phase currents iu, iv, and iw of the electric motor 2 can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a block diagram showing the configuration of a power conversion device according to the first embodiment;

[0041] Figure 2 This is a block diagram of the current command generating unit;

[0042] Figure 3 This is a timing chart illustrating the waveforms of the power supply voltage, phase current, and maximum phase current when no higher harmonics are superimposed;

[0043] Figure 4 This is equivalent to always superimposing higher harmonics. Figure 3 's picture;

[0044] Figure 5 It is a timing diagram of the output voltage of the inverter circuit and its limit value;

[0045] Figure 6This is a time series diagram showing the fundamental wave, the composite wave formed by superimposing the fifth and seventh harmonics on the fundamental wave, and the ratio of the fifth and seventh harmonics.

[0046] Figure 7 The following diagram shows the equations for the d-axis current and q-axis current when the fifth and seventh harmonics are superimposed on the motor phase current, and the equation for deriving the current vector.

[0047] Figure 8 This is a time series diagram of the amplitude of the current vector before the (6n-1)th harmonic, (6n+1)th harmonic, and higher harmonics of the motor phase current are superimposed;

[0048] Figure 9 This is a time chart showing the ratio of the (6n-1)th harmonic and (6n+1)th harmonic of the motor phase current to the amplitude of the current vector;

[0049] Figure 10 is a graph showing the relationship between the ratio of the amplitude of the current vector of the higher harmonics to the amplitude of the current vector of the phase current before superposition and the reduction rate of the peak value of the maximum phase current;

[0050] Figure 11 This graph shows the relationship between the phase shift of the fifth harmonic component contained in the higher harmonics with respect to the fundamental frequency component and the reduction rate of the peak value of the maximum phase current when the phase shift of the fifth harmonic component contained in the higher harmonics with respect to the fundamental frequency component is set to +180°, +175°, and +185°, when the higher harmonics do not include the third harmonic.

[0051] Figure 12 The following formula clearly expresses the frequency component of five times the fundamental frequency and the frequency component obtained by five times the fundamental frequency ± 2m times the power supply frequency (m is a natural number) contained in the phase current of the motor.

[0052] Figure 13 A graph showing the relationship between the phase shifts of the fifth and seventh harmonic components included in the higher harmonics relative to the fundamental frequency and the reduction rate of the peak value of the maximum phase current, when the phase shift of the third harmonic component included in the higher harmonics relative to the fundamental frequency is set to 0°;

[0053] Figure 14 This is equivalent to setting the phase shift of the third harmonic component contained in the higher harmonics relative to the fundamental frequency component to -10 degrees. Figure 13 's picture;

[0054] Figure 15 This is equivalent to setting the phase shift of the third harmonic component contained in the higher harmonics relative to the fundamental frequency component to +10°. Figure 13 's picture;

[0055] Figure 16 This is a modification of the first embodiment, equivalent to Figure 6 's picture;

[0056] Figure 17 The second embodiment is equivalent to Figure 1 's picture;

[0057] Figure 18 The second embodiment is equivalent to Figure 2 's picture;

[0058] Figure 19 It is a timing diagram of the motor phase currents and their current vectors, as well as the current vectors before the superposition of higher harmonics;

[0059] Figure 20 This is a timing chart illustrating the waveforms of the power supply voltage, maximum phase current, and phase current when harmonics are superimposed only during a period in which the maximum phase current before superimposition is 91.5% or more of the peak value;

[0060] Figure 21 The third embodiment is equivalent to Figure 2 Picture. DETAILED DESCRIPTION

[0061] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the following embodiments are merely preferred examples in nature and are not intended to limit the scope of the present invention, its applications, or its uses.

[0062] (First embodiment)

[0063] Figure 1 1 is a block diagram showing the structure of a power conversion device 10 according to the first embodiment of the present disclosure. The power conversion device 10 converts the AC power supplied from the single-phase AC power supply 1 into a predetermined output AC power and supplies it to the motor 2. Figure 1 As shown, the power conversion device 10 includes a conversion circuit 20, an inverter circuit 30, a capacitor 40, and a control unit 50. The motor 2 is constituted by, for example, an IPM motor (Interior Permanent Magnet Motor), and drives a compressor (not shown) of an air conditioner.

[0064] The conversion circuit 20 is connected to the single-phase AC power supply 1 via a reactor L and performs full-wave rectification on the AC voltage supplied from the single-phase AC power supply 1. In this example, the conversion circuit 20 includes four diodes 21, 22, 23, and 24 connected in a bridge configuration. In other words, the conversion circuit 20 is composed of a diode bridge circuit.

[0065] The inverter circuit 30 includes six switching elements 31a, 32a, 33a, 34a, 35a, and 36a connected in a bridge configuration. The inverter circuit 30 converts the DC power output by the conversion circuit 20 into AC power through the operation of the switching elements 31a, 32a, 33a, 34a, 35a, and 36a, and supplies the AC power to the motor 2. Specifically, in this example, the inverter circuit 30 includes three switching legs, each consisting of two switching elements 31a, 32a, 33a, 34a, 35a, and 36a connected in series. In each of the three switching legs, the midpoints of the switching elements 31a, 32a, and 33a in the upper arm and the switching elements 34a, 35a, and 36a in the lower arm are connected to the coils of each phase (u-phase, v-phase, and w-phase) of the motor 2. Six freewheeling diodes 31b, 32b, 33b, 34b, 35b, 36b are connected in antiparallel to the six switching elements 31a, 32a, 33a, 34a, 35a, and 36a, respectively.

[0066] Capacitor 40 is connected between the input nodes of inverter circuit 30. The capacitance of capacitor 40 is set to minimize smoothing of the output of conversion circuit 20 while suppressing ripple voltage (voltage fluctuations corresponding to the switching frequency) caused by the switching operation (described later) of inverter circuit 30. Specifically, capacitor 40 is comprised of a film capacitor with a capacitance of, for example, tens of μF. Specifically, the capacitance of capacitor 40 is set to allow the voltage across capacitor 40 to pulsate with a half-cycle of the single-phase AC power supply 1, with the maximum value of the voltage being at least twice the minimum value of the voltage.

[0067] <Control Department>

[0068] The control unit 50 is composed of a microcomputer and a memory. The memory stores software for controlling the microcomputer. The control unit 50 controls the output (output AC voltage) of the inverter circuit 30 by controlling the switching operation of the six switching elements 31a, 32a, 33a, 34a, 35a, and 36a so that the electrical angular frequency of the motor 2 reaches the given command value (hereinafter referred to as the speed command value ω). m *). In this way, the motor 2 can be controlled to work.

[0069] Here, the electrical angular frequency of the motor 2 is set to the fundamental frequency ω, and the maximum value among the absolute values ​​of the multiple phase currents iu, iv, and iw of the motor 2 is set to the maximum phase current imax. The control unit 50 controls the output voltage of the inverter circuit 30 by controlling the six switching elements 31a, 32a, 33a, 34a, 35a, and 36a so that higher harmonics are superimposed on the phase currents iu, iv, and iw near the voltage peak moment when the voltage of the capacitor 40 reaches its peak, thereby reducing the peak value of the maximum phase current imax. In this first embodiment, the higher harmonics are (6n±1) (n is a natural number) harmonics. In other words, the higher harmonics are odd harmonics with respect to the fundamental frequency ω. Specifically, the higher harmonics are the 5th harmonic and the 7th harmonic. The higher harmonics do not include the 3rd harmonic. In addition, if the 5th harmonic and the 7th harmonic are transformed into dq-axis coordinates, they appear as the 6th harmonic.

[0070] In order to achieve the control, Figure 1 As shown, the control unit 50 includes a speed control unit 51 , a current command generating unit 60 , a coordinate conversion unit 52 , a current control unit 53 , and a PWM calculation unit 54 .

[0071] The speed control unit 51 is based on the rotation speed command value ω of the motor 2. m *, calculate the first d-axis current command value i d * and the first q-axis current command value i q *.

[0072] The current command generating unit 60 generates a first d-axis current command value i calculated by the speed control unit 51. d * and the first q-axis current command value i q *, input current i flowing from the single-phase AC power supply 1 to the conversion circuit 20 in , the phase angle of the power supply voltage of the single-phase AC power supply 1 (hereinafter referred to as the power supply phase θ in ), the voltage V of capacitor 40 dc , d-axis voltage command value v d And the q-axis voltage command value v q , calculate the second d-axis current command value i d ** and the second q-axis current command value i q **.

[0073] Specifically, if Figure 2 As shown, the current command generating unit 60 includes a 6nth harmonic command generating unit 61, a first multiplying unit 62, a second multiplying unit 63, a first adding unit 64, a square root calculating unit 65, a third multiplying unit 66, a peak holding unit 67, a fourth multiplying unit 68, a peak judging unit 69, a selecting unit 70, a power supply current command generating unit 71, a second adding unit 72, and a third adding unit 73.

[0074] The 6nth order harmonic command generating unit 61 generates a first d-axis current command value i d * and the first q-axis current command value i q * is the 6nth harmonic (n is a natural number) of the fundamental frequency ω. The 6nth harmonic (n is a natural number) is a frequency component that is 6n times the fundamental frequency ω. Specifically, in the first embodiment, the 6nth harmonic command generator 61 generates only the 6th harmonic.

[0075] In the first embodiment, the 6nth harmonic command generating unit 61 outputs the 6nth harmonic so that the 5th and 7th harmonics superimposed on the phase currents iu, iv, and iw generate a 180° phase shift θ with respect to the component of the fundamental frequency ω. e In addition, the amplitude of the fifth harmonic superimposed on the phase currents iu, iv, iw is set to 12.3% of the component of the fundamental frequency ω, and the amplitude of the seventh harmonic superimposed on the phase currents iu, iv, iw is set to 5.1% of the component of the fundamental frequency ω.

[0076] The first multiplication unit 62 calculates the d-axis voltage command value v d The square of .

[0077] The second multiplication unit 63 calculates the q-axis voltage command value v q The square of .

[0078] The first adding section 64 adds the calculation results of the first multiplying section 62 and the second multiplying section 63 .

[0079] The square root calculation unit 65 calculates the square root of the calculation result of the first addition unit 64 and uses the calculation result as the output voltage v of the inverter circuit 30. INV Output.

[0080] The third multiplication unit 66 multiplies the voltage V of the capacitor 40 by dc Multiply by 1 / √2 and use it as the output voltage v of the inverter circuit 30 INV The limit value v lim Output. The limit value v lim The pulsation is performed with a period of half the period of the power supply voltage of the single-phase AC power supply 1 .

[0081] The peak holding section 67 holds the limit value v outputted from the third multiplication section 66. lim The peak value v of the waveform MAX .

[0082] The fourth multiplication unit 68 outputs the peak value v held by the peak holding unit 67. MAX 1 / 2(v MAX / 2).

[0083] The peak value determination unit 69 determines whether the output voltage v INV Less than the limit value v lim And the limit value v lim Greater than peak v MAX 1 / 2(v MAX / 2) Such superposition conditions.

[0084] If the peak determination unit 69 determines that the superposition condition is satisfied, the selection unit 70 selects and outputs the output of the 6nth harmonic command generation unit 61. On the other hand, if the peak determination unit 69 determines that the superposition condition is not satisfied, the selection unit 70 selects and outputs 0.

[0085] The power supply current command generating unit 71 is based on the power supply phase θ in Generates a command value that pulsates according to the frequency of the power supply voltage so that the command value is consistent with the input current i from the single-phase AC power supply 1. in The compensation amount i is calculated and output in a manner that the deviation between the absolute values ​​of comp *. The power supply current command generating unit 71 performs a PI operation (proportional and integral) based on the deviation to obtain the compensation amount i comp *.

[0086] The second adding unit 72 adds the output of the selecting unit 70 to the compensation amount i calculated by the power supply current command generating unit 71. comp *Add and output.

[0087] The third adding unit 73 adds the output of the second adding unit 72 to the first d-axis current command value i d * and the first q-axis current command value i q * Add and output the second d-axis current command value i d ** and the second q-axis current command value i q **.

[0088] The coordinate conversion unit 52 is based on the u-phase current i of the motor 2. u 、W phase current i w The electrical angle of the rotor (not shown) in the motor 2 is converted into a so-called dq conversion, thereby deriving the d-axis current i of the motor 2. d and q-axis current i q It should be noted that, for example, a current sensor can be set to directly detect the u-phase current i u And w phase current i w value.

[0089] The current control unit 53 is based on the second d-axis current command value i d **, the second q-axis current command value i q **、d-axis current i dAnd the q-axis current i q , derive the d-axis voltage command value v d And the q-axis voltage command value v q Specifically, the current control unit 53 derives the d-axis voltage command value v d and q-axis voltage command value v q , so that the second d-axis current command value i d **With d-axis current i d The deviation between the second q-axis current command value i q **With q-axis current i q The deviations between them are reduced.

[0090] The PWM operation unit 54 generates a control signal G for controlling the on / off switching of the switching elements 31a, 32a, 33a, 34a, 35a, and 36a in the inverter circuit 30. Specifically, the PWM operation unit 54 generates a control signal G based on the motor phase and the voltage V dc , d-axis voltage command value v d And the q-axis voltage command value v q , sets the duty ratio of the control signal G supplied to each of the switching elements 31a, 32a, 33a, 34a, 35a, and 36a. When the control signal G is output, each of the switching elements 31a, 32a, 33a, 34a, 35a, and 36a switches (turns on and off) at the duty ratio set by the PWM calculation unit 54. This control signal G is periodically updated, and the switching operation in the inverter circuit 30 can be controlled by the control signal G.

[0091] <Operation of a power conversion device>

[0092] When the power conversion device 10 starts working, the conversion circuit 20 performs full-wave rectification on the power supply voltage. The voltage V dc The pulsation frequency is twice that of the power supply voltage. The inverter circuit 30 supplies a predetermined AC power to the motor 2 by performing a switching operation according to the control signal G. As a result, the motor 2 is operated.

[0093] The output voltage v of the inverter circuit 30 INV is less than the voltage V of capacitor 40 dc 1 / √2 times the limit value v lim , and the limit value v lim Greater than the limit value v lim When the first d-axis current command value i d * and the first q-axis current command value i q*Add its 6nth harmonic (n is a natural number). As a result, the control unit 50 controls the output voltage of the inverter circuit 30 by controlling the multiple switching elements 31a, 32a, 33a, 34a, 35a, and 36a so that the higher harmonics when the electrical angular frequency of the motor 2 is the fundamental frequency ω are superimposed on the phase currents iu, iw, and iv of the motor 2 near the voltage peak moment when the voltage of the capacitor 40 reaches its peak. In this first embodiment, the higher harmonics are the fifth and seventh harmonics. The higher harmonics do not include the third harmonic. The 6nth harmonic command generation unit 61 generates the 6nth harmonics so that the phase shift of these fifth and seventh harmonics relative to the components of the fundamental frequency ω reaches 180°. Here, the waveform of the phase current after removing the higher harmonics from the phase currents iu, iv, and iw of the motor 2 is referred to as the phase current before superposition. The 6nth order harmonic command generating unit 61 generates the 6nth order harmonic so that the amplitudes of the fifth order harmonic and the seventh order harmonic are smaller than 20% of the current vector of the preceding phase current to which the current is superimposed.

[0094] Figure 3 The waveforms of the power supply voltage, phase current, and maximum phase current when no harmonics are superimposed are shown as examples.

[0095] Figure 4 The waveforms of the power supply voltage, phase current, and maximum phase current when higher harmonics, namely, the fifth harmonic and the seventh harmonic, are always superimposed are shown as examples.

[0096] like Figure 3 and Figure 4 As shown, superposition of higher harmonics can reduce the peak value of the maximum phase current imax, which is the maximum value among the absolute values ​​of the multiple phase currents iu, iv, and iw of the motor 2. If the maximum phase current before superposition is set to the maximum value among the absolute values ​​of the multiple phase currents before superposition corresponding to the multiple phase currents iu, iv, and iw of the motor 2, it can be said that the control unit 50 controls the output voltage of the inverter circuit 30 so that the peak value of the maximum phase current imax is smaller than the peak value of the maximum phase current before superposition.

[0097] As described above, in the first embodiment, the peak value of the maximum value among the absolute values ​​of the plurality of phase currents iu, iv, and iw of the electric motor 2 can be reduced.

[0098] Figure 5 The output voltage v of the inverter circuit 30 is shown INV and its limit value v lim .exist Figure 5 In the example, the symbol Tp represents the period during which the superposition condition is satisfied, that is, the output voltage v of the inverter circuit 30 INV Less than the limit value v lim And the limit value v limGreater than peak v MAX 1 / 2(v MAX / 2). This period Tp corresponds to the time near the voltage peak. In the first embodiment, higher harmonics are superimposed on the phase currents iu, iv, and iw of the motor 2 during this period Tp. However, higher harmonics are not superimposed on the phase currents iu, iv, and iw of the motor 2 during periods other than this period Tp. In other words, the control unit 50 controls the output voltage of the inverter circuit 30 so that the period other than the voltage peak includes a period in which higher harmonics are not superimposed.

[0099] In this way, by setting the period during which the voltage of the capacitor 40 is low as a period during which harmonics are not superimposed, it is possible to suppress an increase in the current and the effective value of the current for weakening the magnetic flux during the period during which the voltage is low.

[0100] In the first embodiment, in order to improve the power factor, the capacitance value of the capacitor 40 is set to a small value to allow the voltage of the capacitor 40 to pulsate with a half cycle of the single-phase AC power supply 1, so that the maximum value of the voltage is more than twice the minimum value of the voltage. In addition, the output voltage of the inverter circuit 30 is controlled to improve the power factor. Therefore, near the time when the maximum phase current imax reaches its peak, the DC voltage of the capacitor 40 is large. Therefore, even in the high speed range, the output voltage v of the inverter circuit 30 is INV It will not exceed the limit value v lim , which enables the superposition of higher harmonics as described above.

[0101] Figure 6 Shows the phase current i u 、i w 、i v The fundamental frequency ω component (fundamental wave), the composite wave formed by superimposing the fifth and seventh harmonics on the fundamental wave, and the ratio of the fifth and seventh harmonics. The amplitude of the fifth harmonic is set to 12.3% of the fundamental frequency ω component, and the amplitude of the seventh harmonic is set to 5.1% of the fundamental frequency ω component. The peak value of the composite wave is 7.2% lower than the peak value of the fundamental frequency ω component.

[0102] Here, the d-axis current i of the motor 2 is d Set to i d , the q-axis current i q Set to i q When the fundamental frequency ω is set to ω, the d-axis current i when the fifth and seventh harmonics are superimposed on the phase currents iu, iv, and iw of the motor 2 is d and q-axis current i q like Figure 7As shown in Equation 1. In addition, when the current vector of the phase current iu, iv, iw of the motor 2 is set to Ia, the current vector is as follows Figure 7 As shown in formula 2.

[0103] exist Figure 8 In , w(6n-1) represents the (6n-1)th harmonic of any phase current iu, iv, iw of the motor 2, and w(6n+1) represents the (6n+1)th harmonic of the phase current iu, iv, iw. Figure 8 In , |Ia| represents the amplitude (absolute value) of the current vector of the superimposed previous phase current. Figure 9 In the equation (6n-1), w(6n-1) represents the ratio of the (6n-1)th harmonic of any phase current iu, iv, iw of the motor 2 to the amplitude |Ia| of the current vector, and w(6n+1) represents the ratio of the (6n+1)th harmonic of the phase current iu, iv, iw to the amplitude |Ia| of the current vector.

[0104] like Figure 9 As shown, the amplitudes of the (6n-1)th harmonic and the (6n+1)th harmonic superimposed on the phase currents iu, iv, iw of the motor 2 are set to be smaller than 20% of the amplitude |Ia| of the current vector of the phase current before superposition.

[0105] Figure 10 The relationship between the ratio of the amplitude of the current vector of the higher harmonics superimposed on the phase currents iu, iv, iw of the motor 2 to the amplitude |Ia| of the current vector of the phase current before superposition and the reduction rate of the peak value of the maximum phase current imax is shown.

[0106] As shown in the figure, by setting the ratio of the amplitude of the higher harmonics to the amplitude |Ia| of the current vector of the phase current before superposition to 15% or more and less than 20%, the reduction rate of the peak value of the maximum phase current imax can be improved compared to the case of setting it to 20% or more.

[0107] By setting the ratio of the amplitude of the harmonics to the amplitude |Ia| of the current vector before superposition to less than 20%, the loss caused by superposition of the harmonics can be reduced compared to the case where it is set to 20% or more.

[0108] Figure 11The figure shows the relationship between the phase shift of the fifth harmonic component with respect to the fundamental frequency ω and the reduction rate of the peak value of the maximum phase current imax, when the phase shift of the fifth harmonic component with respect to the fundamental frequency ω is set to +180°, +175°, and +185°, assuming the third harmonic is not included in the higher harmonics. As shown in the figure, setting the phase shift of the fifth and seventh harmonics with respect to the fundamental frequency ω to 180° maximizes the reduction rate of the peak value of the maximum phase current imax.

[0109] By setting the phase shift of the fifth harmonic component with respect to the fundamental frequency ω to 176° to 184°, the reduction rate of the peak value of the maximum phase current imax can be increased compared to the case where the phase shift is set to a value less than 176° or greater than 184°.

[0110] By setting the phase shift of the seventh harmonic component with respect to the fundamental frequency ω to 176° to 184°, the reduction rate of the peak value of the maximum phase current imax can be increased compared to the case where the phase shift is set to a value less than 176° or greater than 184°.

[0111] It should be noted that the fundamental frequency ω component i of the phase current iu, iv, iw is u1 When expressed as the following formula 3, the fifth harmonic i superimposed on the phase current iu, iv, iw is u5 and 7th harmonic i u7 As shown in the following formulas 4 and 5.

[0112] i u1 =Imsin(ωt+φ1)···(3)

[0113] i u5 = ImA5s in5(ωt+φ5+180) · · · (4)

[0114] i u7 = ImA7s in7(ωt+φ7+180) · · · (5)

[0115] φ5 and φ7 are φ1±4°.

[0116] Figure 12 The waveforms of the phase currents iu, iv, and iw are expressed by the equations when (n-1)th harmonics, specifically, 5th harmonics, are superimposed on the phase current pulsating at a frequency twice the power supply frequency (half the power supply cycle). Figure 12 In the formula, i u1 Assume that the component of fundamental frequency ω, and i u5 Assuming it is the 5th harmonic, ω e Set as fundamental frequency, and ωg Set to the power frequency. Figure 12 In the equation, boxes are used to enclose terms that may appear in the phase currents iu, iv, and iw due to the superposition of the fifth harmonic. The boxed terms are frequency components that are odd-order multiples of the fundamental frequency ω (odd-order harmonics) and frequency components that are odd-order multiples of the fundamental frequency ω ± 2m times the power supply frequency (where m is a natural number).

[0117] In the first embodiment, the control unit 50 reduces the peak value of the maximum phase current imax, which is a plurality of phase currents i of the motor 2, by superimposing higher harmonics. u 、i w 、i v Therefore, when the multiple phase currents i from the motor 2 are u 、i w 、i v The waveform of the phase current obtained by removing the odd multiple frequencies of the fundamental frequency ω and the frequency components obtained by removing the odd multiple frequencies of the fundamental frequency ω ± 2m times the power supply frequency (m is a natural number) is set as the phase current after removal, and the maximum phase current after removal is set as the phase current after removal with the multiple phase currents i of the motor 2. u 、i w 、i v When the absolute values ​​of the corresponding plurality of phase currents after removal are the maximum, the peak value of the maximum phase current imax is less than the peak value of the maximum phase current after removal. Furthermore, the ratio of the amplitude of the higher harmonics superimposed on the phase currents iu, iv, and iw to the amplitude of the current vector of the phase current after removal may be set to be greater than 15% and less than 20%.

[0118] (Modification 1 of the first embodiment)

[0119] In Modification 1 of the first embodiment, a motor structure, such as a delta connection, is employed that allows the superposition of third harmonics on the phase currents iu, iv, and iw of the motor 2. Furthermore, the higher harmonics include the third harmonic. The phase offset between the third harmonic and the component of the fundamental frequency ω is set to -10° to 10°, and the phase offset between the fifth and seventh harmonics included in the higher harmonics and the component of the fundamental frequency ω is set to -5° to 5°.

[0120] Figure 13 The figure shows the relationship between the fifth and seventh harmonics included in the harmonics and the reduction rate of the peak value of the maximum phase current imax when the phase shift of the third harmonic included in the harmonics with respect to the component of the fundamental frequency ω is set to 0°. Figure 14 The phase shift of the third harmonic component included in the higher harmonics relative to the fundamental frequency ω is -10°, which is equivalent to Figure 13 Picture. Figure 15 The phase shift of the third harmonic component included in the higher harmonics relative to the fundamental frequency ω is +10°, which is equivalent to Figure 13 Picture.

[0121] Reference Figures 13 to 15 It can be seen that by setting the phase offset between the 3rd harmonic and the component of the fundamental frequency ω to -10°~10°, and setting the phase offset of the 5th harmonic and the 7th harmonic contained in the higher harmonics relative to the component of the fundamental frequency ω to -5°~5°, the reduction rate of the peak value of the maximum phase current imax can be made greater than 0%.

[0122] (Variation 2 of the First Embodiment)

[0123] Figure 16 This is a modification of the first embodiment, equivalent to Figure 6 . In this modification example 2, the higher harmonics superimposed on the phase currents iu, iv, and iw of the motor 2 also include (6n±1) (n is an even number) harmonics. Specifically, the higher harmonics are the 5th harmonic, the 7th harmonic, the 11th harmonic, and the 13th harmonic. The amplitude of the 5th harmonic is set to 16.4% of the component of the fundamental frequency ω, the amplitude of the 7th harmonic is set to 9.7% of the component of the fundamental frequency ω, the amplitude of the 11th harmonic is set to 3.4% of the component of the fundamental frequency ω, and the amplitude of the 13th harmonic is set to 1.6% of the component of the fundamental frequency ω. In addition, the phase offset of the (6n±1) harmonics with n being an odd number relative to the component of the fundamental frequency ω is set to 176°~184°, and the phase offset of the (6n±1) harmonics with n being an even number relative to the component of the fundamental frequency ω is set to -6°~+4°.

[0124] The component i of the fundamental frequency ω of the phase current iu, iv, iw is u1 When expressed as the above formula 3, the 11th harmonic i superimposed on the phase current iu, iv, iw u11 and 13th harmonic i u13 As shown in the following formulas 6 and 7.

[0125] i u11 = ImA 11 s in11 (ωt+φ 11 ) · · · (6)

[0126] i u13 = ImA 13 s in13(ωt+φ 13 ) · · · (7)

[0127] φ 11 and φ13 It is φ1±4°.

[0128] (Second embodiment)

[0129] Figure 17 The second embodiment is equivalent to Figure 1 In the second embodiment, the current command generating unit 60 generates a first d-axis current command value i calculated by the speed control unit 51. d * and the first q-axis current command value i q *, input current i flowing from the single-phase AC power supply 1 to the conversion circuit 20 in , the phase angle of the power supply voltage of the single-phase AC power supply 1 (hereinafter referred to as the power supply phase θ in ), the voltage V of capacitor 40 dc , d-axis current i of motor 2 d And the q-axis current i q , calculate the second d-axis current command value i d ** and the second q-axis current command value i q **.

[0130] Specifically, if Figure 18 As shown, the current command generating unit 60 includes a first square calculating unit 74, a second square calculating unit 75, a square adding unit 76, a current vector calculating unit 77, a 6nth-order harmonic removing unit 78, a peak holding unit 79, and a peak determining unit 80, instead of the first multiplying unit 62, the second multiplying unit 63, the first adding unit 64, the square root calculating unit 65, the third multiplying unit 66, the peak holding unit 67, the fourth multiplying unit 68, and the peak determining unit 69 of the first embodiment.

[0131] The first square calculation unit 74 calculates the d-axis current i of the motor 2. d The square of .

[0132] The second square calculation unit 75 calculates the q-axis current i of the motor 2. q The square of .

[0133] The square addition unit 76 adds the calculation results of the first square calculation unit 74 and the second square calculation unit 75 .

[0134] The current vector calculation unit 77 calculates the square root of the calculation result of the square addition unit 76 and outputs the calculation result as the current vector Ia.

[0135] The 6nth harmonic removal unit 78 is a filter that removes the 6nth harmonic, or 6nth frequency component of the fundamental frequency ω, from the current vector Ia. The 6nth harmonic removal unit 78 outputs the current vector after removing the 6nth harmonic as the current vector Iaf before superposition of higher harmonics.

[0136] The peak holding unit 79 holds the peak value Ipeak of the current vector Iaf before the superposition of higher harmonics output from the 6nth-order harmonic removing unit 78 .

[0137] The peak determination unit 80 determines whether a superimposition condition is satisfied, namely, that the current vector Iaf before superimposition outputted from the 6nth harmonic removal unit 78 is greater than 0.915 times the peak value Ipeak held by the peak holding unit 79 .

[0138] Figure 19 The phase currents iu, iv, and iw of the motor 2 and their current vectors Ia and a current vector Iaf before superposition of higher harmonics are shown.

[0139] As shown in the figure, the control unit 50 superimposes harmonics only while the current vector Iaf before superimposition is greater than 91.5% of the peak value Ipeak of the current vector Iaf before superimposition.

[0140] The other structures are the same as those of the first embodiment, and therefore the same structures are denoted by the same reference numerals and detailed description thereof will be omitted.

[0141] (Modification of the Second Embodiment)

[0142] In the second embodiment described above, the superposition condition is set to the condition that the current vector Iaf before superposition is greater than 0.915 times its peak value Ipeak. In a modified example of the second embodiment, the superposition condition is set to the condition that the maximum phase current before superposition is at least 91.5% of its peak value. Therefore, in this modified example, superposition of higher harmonics on the phase currents iu, iv, and iw is performed near the current peak moment, when the maximum phase current before superposition reaches its peak value. Furthermore, higher harmonics are superimposed on the phase currents iu, iv, and iw during a portion of the period during which the maximum phase current before superposition is at least 75% of its peak value. In other words, the control unit 50 can control the output voltage of the inverter circuit 30 so that the period other than the current peak moment includes a period during which higher harmonics are not superimposed.

[0143] like Figure 20 As shown, in this modification, the control unit 50 superimposes harmonics on the phase currents iu, iv, and iw only during the period when the maximum phase current before superimposition is at least 91.5% of its peak value. This reduces the peak value of the maximum phase current after superimposition compared to the peak value of the maximum phase current before superimposition.

[0144] Note that, in this variation, the superposition condition is set to be 91.5% or more of the peak value of the maximum phase current before superposition. However, it may be set to be 75% or more of the peak value.

[0145] Alternatively, the superposition condition may be set to a condition where the maximum phase current after removal is at least 91.5% of its peak value, or a condition where the maximum phase current after removal is at least 75% of its peak value. This allows superposition of higher harmonics onto the phase currents iu, iv, and iw near the peak point where the maximum phase current after removal reaches its peak value. Furthermore, higher harmonics can be superimposed onto the phase currents iu, iv, and iw during a portion of the period during which the maximum phase current after removal is at least 75% of its peak value.

[0146] (Third embodiment)

[0147] Figure 21 The third embodiment is equivalent to Figure 2 In the third embodiment, the current command generating unit 60 generates a first d-axis current command value i calculated by the speed control unit 51. d * and the first q-axis current command value i q *, input current i flowing from the single-phase AC power supply 1 to the conversion circuit 20 in , and the phase angle of the power supply voltage of the single-phase AC power supply 1 (hereinafter referred to as the power supply phase θ in ), calculate the second d-axis current command value i d ** and the second q-axis current command value i q **.

[0148] Specifically, in the third embodiment, the current command generating unit 60 does not include the 6nth order harmonic command generating unit 61, the first multiplication unit 62, the second multiplication unit 63, the first addition unit 64, the square root calculation unit 65, the third multiplication unit 66, the peak hold unit 67, the fourth multiplication unit 68, the peak determination unit 69, and the selection unit 70 of the first embodiment. In the third embodiment, the current command generating unit 60 includes a high-pass filter 81, a Fourier transform unit 82, an excess amount calculation unit 83, a gain multiplication unit 84, a limiter 85, a reduction ratio calculation unit 86, a fifth harmonic multiplication unit 87, a seventh harmonic multiplication unit 88, and a 6nth order harmonic command generating unit 89 instead of the aforementioned components.

[0149] The high-pass filter 81 removes the input current i from the single-phase AC power supply 1. in The DC component is output and the high frequency component is output.

[0150] The Fourier transform unit 82 extracts the 6n-order component i by performing Fourier transform on the output of the high-pass filter 81. in6 .

[0151] The excess amount calculation unit 83 calculates the 6n-order component i extracted by the Fourier transform unit 82. in6 Subtract the specified 6n times input current threshold i in6_th .

[0152] The gain multiplication unit 84 multiplies the subtraction result of the excess amount calculation unit 83 by the gain K p Multiply.

[0153] When the output of the gain multiplier 84 exceeds 1, the limiter 85 outputs 1. On the other hand, when the output of the gain multiplier 84 does not exceed 1, the limiter 85 outputs the output of the gain multiplier 84 as it is.

[0154] The reduction ratio calculation unit 86 calculates the reduction ratio by subtracting the output of the limiter 85 from 1.

[0155] The fifth harmonic multiplication unit 87 calculates the amplitude A5′ by multiplying the fifth harmonic amplitude A5 by the reduction ratio calculated by the reduction ratio calculation unit 86. The original fifth harmonic amplitude A5 can be calculated based on the first d-axis current command value i d * and the first q-axis current command value i q * to calculate.

[0156] The seventh harmonic multiplication unit 88 calculates the amplitude A7′ by multiplying the seventh harmonic amplitude A7 by the reduction ratio calculated by the reduction ratio calculation unit 86. The original seventh harmonic amplitude A7 can be calculated based on the first d-axis current command value i d * and the first q-axis current command value i q * to calculate.

[0157] The 6nth harmonic command generator 89 generates 6nth harmonics (n is a natural number) so that the amplitude of the fifth harmonic becomes the amplitude A5′ calculated by the fifth harmonic multiplier 87 and the amplitude of the seventh harmonic becomes the amplitude A7′ calculated by the seventh harmonic multiplier 88 .

[0158] As described above, in the third embodiment, the control unit 50 controls the amplitude of the harmonics superimposed on the phase currents iu, iv, and iw based on the input current flowing from the single-phase AC power supply 1 to the conversion circuit 20 .

[0159] (Modification of the Third Embodiment)

[0160] It should be noted that, in the third embodiment, the control unit 50 controls the input current i flowing from the single-phase AC power source 1 to the conversion circuit 20. in , to control the amplitude of the higher harmonics superimposed on the phase currents iu, iv, iw. However, the control unit 50 may also control the voltage V dc , the input current I of the inverter circuit 30 dc, or the output power of the inverter circuit 30, to control the amplitude of the higher harmonics superimposed on the phase currents iu, iv, iw. In addition, the control unit 50 can also control the amplitude of the higher harmonics superimposed on the phase currents iu, iv, iw according to the input current i flowing from the single-phase AC power supply 1 to the conversion circuit 20. in , the voltage V of capacitor 40 dc , the input current I of the inverter circuit 30 dc and two or more values ​​of the output power of the inverter circuit 30 to control the amplitude of the higher harmonics superimposed on the phase currents iu, iv, iw.

[0161] In addition, the control unit 50 may also be configured to control the input current i flowing from the single-phase AC power supply 1 to the conversion circuit 20. in , the voltage V of capacitor 40 dc , the input current I of the inverter circuit 30 dc and two or more values ​​of the output power of the inverter circuit 30 to control the phases of the higher harmonics superimposed on the phase currents iu, iv, iw.

[0162] It should be noted that in the above-mentioned first to third embodiments and their modifications, an inverter circuit having six switching elements 31a, 32a, 33a, 34a, 35a, and 36a is used as the inverter circuit 30, but an inverter circuit having a plurality of switching elements 31a, 32a, 33a, 34a, 35a, and 36a other than six may also be used.

[0163] In the above-mentioned first to third embodiments and their modifications, the higher harmonics are set to the (6n+1)th harmonic (n is a natural number) and the (6n-1)th harmonic (n is a natural number) relative to the fundamental frequency, but can also be set to only one of the (6n+1)th harmonic (n is a natural number) and the (6n-1)th harmonic (n is a natural number).

[0164] While the embodiments are described above, it should be understood that various modifications may be made to the embodiments and specific circumstances without departing from the spirit and scope of the claims. The embodiments and modifications described above may be appropriately combined or replaced as long as they do not affect the functionality of the disclosed object.

[0165] Industrial Applicability

[0166] The present disclosure is useful as a power conversion device for supplying power to an electric motor.

[0167] - Explanation of symbols -

[0168] 1 single-phase AC power supply

[0169] 2 Electric motors

[0170] 10 Power conversion device

[0171] 20 Conversion circuit

[0172] 30 Inverter Circuit

[0173] 31a, 32a, 33a, 34a, 35a, 36a switching elements

[0174] 40 capacitors

[0175] 50 Control Department

[0176] ω fundamental frequency

[0177] imax maximum phase current

[0178] i in Input current

[0179] V dc Voltage

[0180] I dc Input current

[0181] iu, iv, iw phase current

[0182] |Ia|Amplitude of the current vector

Claims

1. A power conversion device, which is a power conversion device (10) for supplying power to an electric motor (2), characterized in that: The power conversion device (10) includes a conversion circuit (20), an inverter circuit (30), a capacitor (40), and a control unit (50). The conversion circuit (20) rectifies the AC voltage supplied from the single-phase AC power supply (1). The inverter circuit (30) has a plurality of switching elements (31a, 32a, 33a, 34a, 35a, 36a), and through the operation of the plurality of switching elements (31a, 32a, 33a, 34a, 35a, 36a), the DC power output by the conversion circuit (20) is converted into AC power and supplied to the motor (2). The capacitor (40) is connected between the input nodes of the inverter circuit (30), The control unit (50) controls the output voltage of the inverter circuit (30) by controlling the plurality of switching elements (31a, 32a, 33a, 34a, 35a, 36a) so that near the voltage peak moment when the voltage of the capacitor (40) reaches a peak value, higher harmonics when the electrical angular frequency of the motor (2) is set to the fundamental frequency (ω) are superimposed, thereby reducing the peak value of the maximum phase current (imax), which is the maximum value among the absolute values ​​of the plurality of phase currents (iu, iv, iw) of the motor (2). The capacitance value of the capacitor (40) is set to allow the voltage of the capacitor (40) to pulsate with a half cycle of the single-phase AC power supply (1) as a cycle, so that the maximum value of the voltage becomes more than twice the minimum value of the voltage.

2. The power conversion device according to claim 1, wherein: The higher harmonics are odd harmonics relative to the fundamental wave frequency (ω).

3. The power conversion device according to claim 2, wherein: The higher harmonic is at least one of a (6n+1)th harmonic and a (6n-1)th harmonic with respect to the fundamental frequency (ω), where n is a natural number.

4. The power conversion device according to any one of claims 1 to 3, characterized in that: The control unit (50) controls the output voltage of the inverter circuit (30) so that a period other than the voltage peak time includes a period in which the superposition is not performed.

5. The power conversion device according to any one of claims 1 to 3, characterized in that: When the waveform of the phase current after removing the higher harmonics from the phase current (iu, iv, iw) of the motor (2) is set as the phase current before superposition, and the maximum phase current before superposition is set as the maximum value among the absolute values ​​of the multiple phase currents before superposition corresponding to the multiple phase currents (iu, iv, iw) of the motor (2), the control unit (50) controls the output voltage of the inverter circuit (30) so that the peak value of the maximum phase current (imax) is smaller than the peak value of the maximum phase current before superposition.

6. The power conversion device according to claim 5, wherein: The superposition performed by the control unit (50) is performed at least near the current peak time when the maximum phase current reaches the peak value before the superposition. The period other than the current peak time includes a period during which the superposition is not performed.

7. The power conversion device according to claim 5, wherein: The superposition performed by the control unit (50) is performed during at least a portion of a period during which the maximum phase current before superposition is 75% or more of the peak value.

8. The power conversion device according to claim 5, wherein: The higher harmonic is at least one of odd harmonics relative to the fundamental frequency (ω), The amplitude of the higher harmonics is less than 20% of the amplitude (|Ia|) of the current vector of the superimposed front-phase current.

9. The power conversion device according to any one of claims 1 to 3, characterized in that: When the waveform of the phase current obtained by synthesizing the frequency components obtained by removing the odd multiple frequencies of the fundamental frequency (ω) and the frequencies obtained by removing the odd multiple frequencies of the fundamental frequency (ω) ± 2m times the power supply frequency from the multiple phase currents (iu, iw, iv) of the motor (2) is set as the phase current after removal, where m is a natural number, and the maximum phase current after removal is set as the maximum value among the absolute values ​​of the multiple phase currents after removal corresponding to the multiple phase currents (iu, iw, iv) of the motor (2), the control unit (50) controls the output voltage of the inverter circuit (30) so that the peak value of the maximum phase current (imax) is smaller than the peak value of the maximum phase current after removal.

10. The power conversion device according to claim 9, characterized in that: The superposition performed by the control unit (50) is performed at least near the current peak time when the maximum phase current after the removal reaches the peak value, The period other than the current peak time includes a period during which the superposition is not performed.

11. The power conversion device according to claim 9, wherein: The superposition performed by the control unit (50) is performed during at least a portion of a period during which the maximum phase current after removal is 75% or more of the peak value.

12. The power conversion device according to claim 9, wherein: The higher harmonics are odd harmonics relative to the fundamental frequency (ω), The amplitude of the higher harmonics is less than 20% of the amplitude of the current vector of the phase current after removal.

13. The power conversion device according to any one of claims 1 to 12, characterized in that: The phase shift between the higher harmonics and the components of the fundamental frequency (ω) is set as follows: when the higher harmonics include the third harmonic, the phase shift between the third harmonic and the components of the fundamental frequency (ω) is -10° to 10°, and the phase shift of the fifth harmonic and the seventh harmonic contained in the higher harmonics relative to the components of the fundamental frequency (ω) is -5° to 5°; when the higher harmonics do not include the third harmonic, the phase shift of the fifth harmonic and the seventh harmonic contained in the higher harmonics relative to the components of the fundamental frequency (ω) is 176° to 184°.

14. The power conversion device according to any one of claims 1 to 13, characterized in that: The control unit (50) controls the input current (i in ), the voltage of the capacitor (40) (V dc ), the input current (I dc ) and at least one of the output power of the inverter circuit (30) to control at least one of the amplitude and phase of the higher harmonics.

15. A power conversion device for supplying power to an electric motor (2), characterized in that: The power conversion device includes a conversion circuit (20), an inverter circuit (30), a capacitor (40) and a control unit (50). The conversion circuit (20) rectifies the AC voltage supplied from the single-phase AC power supply (1). The inverter circuit (30) has a plurality of switching elements (31a, 32a, 33a, 34a, 35a, 36a), and through the operation of the plurality of switching elements (31a, 32a, 33a, 34a, 35a, 36a), the DC power output by the conversion circuit (20) is converted into AC power and supplied to the motor (2). The capacitor (40) is connected between the input nodes of the inverter circuit (30), The control unit (50) controls the output voltage of the inverter circuit (30) by controlling the plurality of switching elements (31a, 32a, 33a, 34a, 35a, 36a) so that when the electrical angular frequency of the motor (2) is set to the fundamental frequency (ω) and the maximum phase current (imax) is set to the maximum value among the absolute values ​​of the plurality of phase currents (iu, iv, iw) of the motor (2), the peak value of the maximum phase current (imax) is reduced by superimposing higher harmonics with respect to the fundamental frequency (ω). The capacitance value of the capacitor (40) is set to allow the voltage of the capacitor (40) to pulsate with a half cycle of the single-phase AC power supply (1) as a period, so that the maximum value of the voltage is more than twice the minimum value of the voltage. The higher harmonics are odd harmonics relative to the fundamental wave frequency (ω).

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