Control method and device of flash memory equipment, electronic equipment and storage medium

Abstract

The invention discloses a control method and device of flash memory equipment, electronic equipment and a storage medium, and belongs to the technical field of flash memory control. The control method comprises the following steps: acquiring an interface rate corresponding to a data operation under the condition that the flash memory equipment executes the data operation; controlling the flash memory device to switch between an activated state and a sub-activated state according to the interface rate; wherein in the activated state, the at least two flash memory controllers are started; in the sub-activation state, at least one flash memory controller in the at least two flash memory controllers is turned off, and at least one flash memory controller in the at least two flash memory controllers is turned on; or, under the condition that the flash memory equipment does not execute the data operation, obtaining the idle duration of the flash memory equipment; under the condition that the idle duration is greater than the duration threshold value, controlling the flash memory device to be switched from the idle state to the idle dormant state; wherein in the idle dormant state, at least one flash memory controller in the at least two flash memory controllers is turned off.

Description

Technical Field

[0001] The present application belongs to the field of flash memory control technology, and specifically relates to a flash memory device control method and device, an electronic device, and a storage medium. Background Art

[0002] In related technologies, Universal Flash Storage (UFS) in electronic devices serves as a data storage device and is the repository for all data. Its data is crucial to the responsiveness of front-end applications. Flash device performance is influenced by a combination of factors: interface speed, the number of UFS lanes, framework (FW) scheduling, the NAND Flash Interface IO speed of the nonlinear macro-unit mode memory, and the basic data read and write (Tread / Twrite) performance of the nonlinear macro-unit mode memory (NAND Flash).

[0003] To improve the performance of flash memory devices, the current UFS device architecture, where one controller controls two data channels, is enhanced to an architecture where two controllers each control two data channels. By forming a redundant array of independent disks level 0 (RAID 0), it is ultimately formed into a UFS with four data channels, namely 4Lane UFS, doubling the performance.

[0004] However, the performance and power consumption of flash memory devices are often negatively correlated. When the number of controllers is increased, the overall power consumption of UFS will also increase significantly, resulting in high power consumption of flash memory devices. Summary of the Invention

[0005] The purpose of the embodiments of the present application is to provide a control method and apparatus for a flash memory device, an electronic device, and a storage medium, which can solve the problem of high power consumption of the flash memory device.

[0006] In a first aspect, an embodiment of the present application provides a method for controlling a flash memory device, wherein the flash memory device includes at least two flash memory controllers, and the control method includes:

[0007] When the flash memory device performs a data operation, obtaining an interface rate corresponding to the data operation;

[0008] Controlling the flash memory device to switch between an active state and a sub-active state according to an interface rate; wherein, in the active state, both of the at least two flash memory controllers are enabled; and in the sub-active state, at least one of the at least two flash memory controllers is disabled, and at least one of the at least two flash memory controllers is enabled;

[0009] Alternatively, when the flash memory device does not perform any data operation, obtaining the idle time of the flash memory device;

[0010] When the idle time is longer than the time threshold, the flash memory device is controlled to switch from the idle state to the idle sleep state; wherein, in the idle sleep state, at least one of the at least two flash memory controllers is shut down.

[0011] In a second aspect, an embodiment of the present application provides a control device for a flash memory device, wherein the flash memory device includes at least two flash memory controllers, and the control device includes:

[0012] An acquisition module, configured to acquire an interface rate corresponding to a data operation when the flash memory device performs a data operation;

[0013] a control module configured to control the flash memory device to switch between an active state and a sub-active state according to an interface rate; wherein, in the active state, both of the at least two flash memory controllers are enabled; and in the sub-active state, at least one of the at least two flash memory controllers is disabled and at least one of the at least two flash memory controllers is enabled;

[0014] The acquisition module is further used to obtain the idle time of the flash memory device when the flash memory device does not perform any data operation;

[0015] The control module is further used to control the flash memory device to switch from the idle state to the idle sleep state when the idle time is greater than the time threshold; wherein, in the idle sleep state, at least one of the at least two flash memory controllers is shut down.

[0016] In a third aspect, an embodiment of the present application provides an electronic device comprising a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the method of the first aspect are implemented.

[0017] In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the steps of the method of the first aspect are implemented.

[0018] In a fifth aspect, an embodiment of the present application provides a chip, which includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the steps of the method of the first aspect.

[0019] In a sixth aspect, an embodiment of the present application provides a computer program product, which is stored in a storage medium and executed by at least one processor to implement the method of the first aspect.

[0020] In an embodiment of the present application, in addition to the active and idle states of the flash memory device, a sub-active state and an idle dormant state are added. When the flash memory device is under a low load, the flash memory device is controlled to enter the sub-active state from the active state, or when the flash memory device is in the idle state for a long time, the flash memory device is controlled to enter the idle dormant state from the idle state. By shutting down at least one flash memory controller when entering the sub-active or idle state, power consumption in low-load or idle conditions is reduced, thereby reducing the overall power consumption of the flash memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A flowchart showing a method for controlling a flash memory device according to some embodiments of the present application is shown;

[0022] Figure 2 A schematic diagram showing state switching of a flash memory device according to some embodiments of the present application is shown;

[0023] Figure 3 A schematic diagram showing state switching of a flash memory device according to some embodiments of the present application is shown;

[0024] Figure 4 A schematic diagram showing the architecture of a flash memory device according to some embodiments of the present application is shown;

[0025] Figure 5 A flowchart showing switching to a low power consumption mode in some embodiments of the present application is shown;

[0026] Figure 6 A schematic diagram showing module data addressing of a flash memory device according to some embodiments of the present application is shown;

[0027] Figure 7 A schematic diagram of system data access under dual controllers in some embodiments of the present application is shown;

[0028] Figure 8 A schematic diagram of system data access under a single controller in some embodiments of the present application is shown;

[0029] Figure 9 A structural block diagram showing a control device for a flash memory device according to some embodiments of the present application is shown;

[0030] Figure 10 shows a structural block diagram of an electronic device according to an embodiment of the present application;

[0031] Figure 11 A schematic diagram of the hardware structure of an electronic device implementing an embodiment of the present application. DETAILED DESCRIPTION

[0032] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0033] The terms "first," "second," and the like in the specification of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of the same type, and do not limit the number of objects. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship.

[0034] The control method and apparatus for the flash memory device, the electronic device, and the storage medium provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings through specific embodiments and their application scenarios.

[0035] Conventional UFS4.x device designs have two external power supplies: a 2.5V VCC (Volt Current Condenser) that powers the NAND media inside the device, and a 1.2V VCCQ signal that powers the controller and NAND's IO (Input Output) interface.

[0036] UFS4.x has multiple device states, which are typically switched using the SSU (Start Stop Unit) command. When the device is operating, UFS is in high-performance mode, in the Active state, which consumes the highest power. After a period of I / O inactivity, it automatically switches to the Idle state, which consumes relatively low power.

[0037] In the Active state, the VCC current is in the hundreds of mA range, and the VCCQ current is generally around 1 A. In the Idle state, the UFS device shuts down some of its internal power supplies to reduce power consumption. The VCCQ current is only around 1 mA, and because the NAND media is not in any operation, the VCC current is even lower, at just hundreds of uA, a difference of 3 to 4 orders of magnitude from the Active mode.

[0038] The 4Lane UFS design adds a controller module compared to the native two data lanes. In Active mode, while delivering high performance, power consumption increases by approximately 50%. In Idle mode, since the controller consumes the majority of power, power consumption essentially doubles.

[0039] In response to the above problems, in some embodiments of the present application, a method for controlling a flash memory device is provided, where the flash memory device includes at least two flash memory controllers.

[0040] Figure 1 A flow chart showing a method for controlling a flash memory device according to some embodiments of the present application is shown in FIG. Figure 1 As shown, the control method includes:

[0041] Step 102: When the flash memory device performs a data operation, obtain an interface rate corresponding to the data operation.

[0042] In the embodiments of the present application, the flash memory device is illustratively a UFS device. Data operations include data write operations, data read operations, and data erase operations. The interface rate is also the UFS IO interface rate, which can reflect the current load of the flash memory device.

[0043] Step 104: Control the flash memory device to switch between an active state and a sub-active state according to the interface rate; wherein, in the active state, at least two flash memory controllers are both turned on; in the sub-active state, at least one of the at least two flash memory controllers is turned off, and at least one of the at least two flash memory controllers is turned on.

[0044] In the embodiment of the present application, the rate threshold is used to measure whether the current flash memory device is in a light load state or a heavy load state. It can be understood that the higher the current interface rate, the heavier the load on the flash memory device.

[0045] Based on the traditional active state (Active state) and idle state (Idle state), the embodiment of the present application adds a sub-active state, which is recorded as the Sub-Active state. The sub-active state is a low-power intermediate state between the active state and the idle state.

[0046] The flash memory device responds to data requests from upper-layer applications and executes corresponding data operations. When the upper-layer data volume is large, the interface rate requirement is higher. When the upper-layer data volume is small, the interface rate requirement is lower. Therefore, when the upper-layer data volume is small, power consumption can be reduced by shutting down at least one of the at least two flash memory controllers. When the upper-layer data volume is large, the shut-down flash memory controller is re-enabled, and the performance of data operations such as data read, write, and erase on the flash memory device is improved by having multiple flash memory controllers operate simultaneously.

[0047] Taking the 4Lane UFS design as an example, after shutting down one of the two flash memory controllers, the 4LaneUFS becomes equivalent to a 2Lane UFS, and its power consumption performance is the same as that of the 2Lane UFS, which can significantly reduce power consumption.

[0048] Step 106 : When the flash memory device does not perform any data operation, obtain the idle time of the flash memory device.

[0049] In the embodiment of the present application, when no data is accessed from the upper layer, the flash memory device automatically switches to an idle state (Idle state) after a period of I / O inactivity, thereby reducing power consumption. In the idle state, the flash memory device partially shuts down its internal power supply while retaining the power supply signal to the flash memory controller, which is in the on state. At this point, the primary source of power consumption for the flash memory device is the power supply signal VCCQ that powers the flash memory controller.

[0050] After entering the idle state, the flash memory device continuously obtains the idle time, where the idle time is the time during which the flash memory device enters the idle state and no data is accessed from the upper layer.

[0051] Step 108 : When the idle time is longer than the time threshold, control the flash memory device to switch from the idle state to the idle sleep state; wherein, in the idle sleep state, at least one of the at least two flash memory controllers is shut down.

[0052] In an embodiment of the present application, when the flash memory device is in an idle state and the idle duration exceeds a threshold, the flash memory device is controlled to enter an idle dormant state. At this point, at least one of the at least two flash memory controllers is controlled to shut down, thereby reducing the power supply signal VCCQ that supplies power to the flash memory controller, thereby reducing power consumption during idle standby.

[0053] Taking a flash memory device including two flash memory controllers as an example, the idle standby power consumption of each flash memory controller is Q. After shutting down one of the flash memory controllers, the total idle standby power consumption of the flash memory controllers of the flash memory device is reduced from 2Q to Q, that is, the power consumption is reduced by 50%.

[0054] For example, after entering the idle state, some circuits can be shut down, such as circuits that have little impact on the responsiveness of the flash memory device, thereby reducing standby power consumption. After entering the idle hibernation state, based on the idle state, some flash memory controllers can be further shut down to further reduce standby power consumption.

[0055] In addition to the active and idle states of a flash memory device, this application adds a sub-active state and an idle dormant state. When the flash memory device is under a low load, the flash memory device is controlled to enter the sub-active state from the active state, or when the flash memory device is in an idle state for a long time, the flash memory device is controlled to enter the idle dormant state from the idle state. By shutting down at least one flash memory controller when entering the sub-active or idle state, power consumption in low-load or idle conditions is reduced, thereby reducing the overall power consumption of the flash memory device.

[0056] In some embodiments of the present application, controlling a flash memory device to switch between an active state and a subactive state according to an interface rate includes:

[0057] When the interface rate is less than or equal to the rate threshold and the flash memory device is in the active state, the flash memory device is controlled to switch from the active state to the sub-active state; or, when the interface rate is greater than the rate threshold and the flash memory device is in the sub-active state, the flash memory device is controlled to switch from the sub-active state to the active state.

[0058] In an embodiment of the present application, if the interface rate of the flash memory device is less than or equal to a rate threshold, the flash memory device is determined to be in a lightly loaded state. In this case, the flash memory device is controlled to switch from an active state to a sub-active state, and at least one of the at least two flash memory controllers is shut down, thereby reducing energy consumption.

[0059] If the interface rate of the flash memory device is greater than the rate threshold, the flash memory device is determined to be in a heavy load state. In this case, the flash memory device is controlled to switch from a sub-active state to an active state, and all flash memory controllers are turned on to improve data operation performance.

[0060] For example, Figure 2 and Figure 3 Schematic diagram showing the state switching of the flash memory device in some embodiments of the present application is shown in FIG. Figure 2 As shown, the flash memory device includes an active state, a sub-active state, an idle state, and an idle sleep state.

[0061] In the active state, the system determines whether there is a data request. If there is no data request, the system enters the idle state. If there is a data request, the system obtains the interface rate. If there is a data request, and the interface rate is less than or equal to the rate threshold, the system enters the sub-active state. If the interface rate is greater than the rate threshold, the system enters the active state. If there is no data request, the system enters the idle state and begins counting. If the idle duration exceeds the duration threshold, the system enters the idle sleep state. If a data request is detected in the idle or idle sleep state, the system immediately enters the active state.

[0062] like Figure 3 As shown, the active state and the subactive state can switch between each other. The active state and the idle state can switch between each other. The subactive state and the active state can both enter the idle state. The idle state can enter the idle sleep state. The idle state and the idle sleep state can both enter the active state.

[0063] For example, a new flag can be added to the UFS's inherent flag function to specifically characterize the interface rate. When the interface rate exceeds the rate threshold, the flag is set to notify the host. The host can then issue the following command to control both parties to enter the sub-active state.

[0064] Exemplarily, the rate threshold ranges from 2 GB / s to 10 GB / s. Exemplarily, the rate threshold is 4 GB / s.

[0065] This application determines the load status of the flash memory device by comparing the interface rate with the rate threshold, and dynamically switches between the activation state and the sub-activation state according to the judgment result. It can dynamically adjust the performance and power consumption of the flash memory device based on the actual load, and reduce power consumption in low-load scenarios.

[0066] In some embodiments of the present application, at least two flash memory controllers include a first flash memory controller and a second flash memory controller, the first flash memory controller includes a first flash translation layer mapping table, and the second flash memory controller includes a second flash translation layer mapping table; the flash memory device also includes a first flash memory unit and a second flash memory unit. When the flash memory device is in an activated state, the first flash memory controller is used to perform data operations on the first flash memory unit through the first flash translation layer mapping table, and the second flash memory controller is used to perform data operations on the second flash memory unit through the second flash translation layer mapping table.

[0067] Controlling the flash memory device to switch from an active state to a sub-active state includes: controlling the second flash memory controller to write a second flash memory translation layer mapping table into the second flash memory unit; controlling the first flash memory controller to obtain the second flash memory translation layer mapping table in the second flash memory unit; controlling the second flash memory controller to shut down; controlling the first flash memory controller to perform data operations on the first flash memory unit through the first flash memory translation layer mapping table, and to perform data operations on the second flash memory unit through the second flash memory translation layer mapping table.

[0068] In the embodiments of the present application, for example, Figure 4 Schematic diagram of the architecture of the flash memory device of some embodiments of the present application is shown as follows: Figure 4 As shown, the flash memory device is a 4-Lane UFS design. It includes two flash memory controllers, designated as the first flash memory controller Controller0 and the second flash memory controller Controller1. It also includes two flash memory units, designated as the first flash memory unit NAND Flash0 and the second flash memory unit NAND Flash1. The flash memory device communicates with the host.

[0069] Through the RAID 0 mechanism, in both active and idle states, the first flash memory controller Controller0 accesses the first flash memory unit NAND Flash0, and the second flash memory controller Controller1 accesses the second flash memory unit NAND Flash1 in parallel. By switching the state machine, when switching to the sub-active state or idle sleep state, the second flash memory controller Controller1 is automatically shut down to reduce power consumption.

[0070] When the second flash memory controller Controller1 is turned off and the first flash memory controller Controller 0 is kept in single controller mode, in order to access the data in the two arrays of the first flash memory unit NAND Flash0 and the second flash memory unit NAND Flash1, it is necessary to enable the first flash memory controller Controller0 to access the address mapping tables of NAND Flash0 and NAND Flash1 respectively, that is, the above-mentioned first flash translation layer mapping table FTL0 and second flash translation layer mapping table FTL1.

[0071] Among them, the Flash Translation Layer (FTL) mapping table mainly converts the host's logical block address (LBA) access to the storage device into the physical block address (PBA) access of the flash memory chip, that is, forming a one-to-one correspondence between LBA and PBA.

[0072] Since the first flash memory controller Controller0 and the second flash memory controller Controller1 respectively hold the first flash translation layer mapping table FTL0 and the second flash translation layer mapping table FTL1 in the active state, in order for the first flash memory controller Controller0 to also access the data in the second flash memory unit NAND Flash1, the second flash translation layer mapping table FTL1 held by the second flash memory controller Controller1 needs to be transferred to the first flash memory controller Controller0 before shutting down the second flash memory controller Controller1.

[0073] Figure 4 The arrows in FIG. 1 show the data transfer path of the second flash translation layer mapping table FTL1. Figure 4 As shown, the flash memory device first flushes the second flash translation layer mapping table FTL1 in the second flash memory controller Controller1 to the second flash memory unit NAND Flash1. Then the first flash memory controller Controller0 loads the second flash translation layer mapping table FTL1 in the second flash memory unit NAND Flash1 to the first flash memory controller Controller0.

[0074] In this way, the first flash controller Controller0 holds both the first flash translation layer mapping table FTL0 and the second flash translation layer mapping table FTL1, and can access the physical space of the first flash memory unit NAND Flash0 and the second flash memory unit NAND Flash1 and perform data operations.

[0075] For example, Figure 5 The switching flow chart of the low power consumption mode of some embodiments of the present application is shown as follows: Figure 5 As shown, including:

[0076] Step 502: The flash memory device enters a sub-active state or an idle dormant state;

[0077] Step 504: close the UFS host controller interface of the second flash memory controller;

[0078] Among them, the UFS host controller interface is Universal Flash Storage Host Controller Interface (UFSHCI).

[0079] Step 506: The second flash memory controller flushes the second flash translation layer mapping table to the second flash memory unit.

[0080] Step 508, switching the flash memory unit;

[0081] Among them, according to the host's address resolution, the corresponding flash memory unit is accessed. Figure 4 As shown, the Control line and the Data line on the NandInterface are switched between NAND Flash0 and NAND Flash1 through a switch circuit.

[0082] Step 510: The first flash memory controller loads a second flash translation layer mapping table;

[0083] Step 512: shut down the second flash memory controller.

[0084] For example, Figure 6 Schematic diagram of module data addressing of flash memory devices in some embodiments of the present application is shown. Figure 6 As shown, for data reading and writing between the host Host and the flash memory device UFS, correct data interaction is achieved through the mapping of logical addresses and physical addresses.

[0085] For example, Figure 7 Schematic diagram of system data access under dual controllers in some embodiments of the present application is shown. Figure 7 As shown, A1 to A8 are physical addresses in the flash memory unit. In the activated state, both the first flash memory controller and the second flash memory controller are working. At this time, the first flash memory controller controls the data addressing in the first flash memory unit, and the second flash memory controller controls the data addressing in the second flash memory unit.

[0086] For example, Figure 8 Schematic diagram of system data access under a single controller in some embodiments of the present application is shown. Figure 8 As shown, A1 to A8 are physical addresses in the flash memory unit. In the sub-activation state, the second flash memory controller is turned off, and the first flash memory controller performs mapping conversion of the physical address according to the logical address of the host, and serially accesses the first flash memory unit and the second flash memory unit according to the physical address to realize normal data reading operation, data writing operation and data erasing operation.

[0087] The present application can implement data reading operations, data writing operations, and data erasing operations on data in two flash memory units through a single flash memory controller, thereby reducing the power consumption of the flash memory device under low-load conditions.

[0088] In some embodiments of the present application, controlling the flash memory device to switch from a sub-activation state to an activation state includes: controlling the second flash memory controller to turn on; controlling the first flash memory controller to perform data operations on the first flash memory unit through the first flash memory translation layer mapping table, and controlling the second flash memory controller to perform data operations on the second flash memory unit through the second flash memory translation layer mapping table.

[0089] In an embodiment of the present application, when the flash memory device is in a sub-active state and detects that the interface rate exceeds a rate threshold, the flash memory device is controlled to switch from the sub-active state to the active state. When switching to the active state, the first flash memory controller activates and turns on the second flash memory controller.

[0090] After the second flash controller is enabled, the first flash controller performs data operations on the first flash memory unit using the first flash translation layer mapping table, and the second flash controller performs data operations on the second flash memory unit using the second flash translation layer mapping table. Using the RAID 0 mechanism, in both active and idle states, the first flash controller Controller0 accesses the first flash memory unit NAND Flash0, and the second flash controller Controller1 accesses the second flash memory unit NAND Flash1 in parallel, thereby increasing the data operation rate.

[0091] The present application improves the data operation performance of the flash memory device by enabling multiple flash memory controllers under high load conditions, allowing the multiple flash memory controllers to access multiple flash memory units in parallel.

[0092] In some embodiments of the present application, at least two flash memory controllers include a first flash memory controller and a second flash memory controller; controlling the flash memory device to switch from an idle state to an idle sleep state includes: when both the first flash memory controller and the second flash memory controller are in the turned-on state, controlling the second flash memory controller to turn off.

[0093] In the embodiment of the present application, after the flash memory device enters the idle state, the idle time of the flash memory device is recorded. When the idle time exceeds a time threshold, the flash memory device switches to the idle dormant state.

[0094] At this time, if both the first flash memory controller and the second flash memory controller are in the on state, the second flash memory controller is controlled to be turned off. If the second flash memory controller is already in the off state, the current state is maintained unchanged.

[0095] Exemplarily, the flash memory controller directly enters the idle state from the active state. At this time, the first flash memory controller and the second flash memory controller are both in the on state, and when switching to the idle dormant state, the second flash memory controller is controlled to be turned off.

[0096] Exemplarily, the flash memory controller enters the idle state from the sub-active state. At this time, the second flash memory controller has been turned off, and the current state is maintained unchanged when switching to the idle dormant state.

[0097] The present application reduces idle standby energy consumption by shutting down the second flash memory controller after entering the idle dormant state.

[0098] In some embodiments of the present application, after controlling the flash memory device to switch from an idle state to an idle sleep state, the control method further includes: upon receiving a data operation instruction, controlling the second flash memory controller to turn on, and controlling the second flash memory controller to switch to an active state.

[0099] In an embodiment of the present application, when the flash memory device is in an idle state or an idle sleep state, if a data operation instruction is received, the flash memory device is immediately controlled to enter an active state, the second flash memory controller is turned on, and the second flash memory controller is controlled to switch to an active state, so that the flash memory device is capable of coping with possible high-load scenarios.

[0100] The flash memory device control method provided in the embodiment of the present application can be executed by a flash memory device control device. In the embodiment of the present application, the flash memory device control method executed by the flash memory device control device is used as an example to illustrate the flash memory device control device provided in the embodiment of the present application.

[0101] In some embodiments of the present application, a control device for a flash memory device is provided. The flash memory device includes at least two flash memory controllers. Figure 9 The structure block diagram of the control device of the flash memory device in some embodiments of the present application is shown. The control device 900 includes:

[0102] An acquisition module 902 is configured to acquire an interface rate corresponding to a data operation when the flash memory device performs a data operation;

[0103] a control module 904 configured to control the flash memory device to switch between an active state and a sub-active state according to an interface rate; wherein, in the active state, both of the at least two flash memory controllers are enabled; and in the sub-active state, at least one of the at least two flash memory controllers is disabled and at least one of the at least two flash memory controllers is enabled;

[0104] The acquisition module 902 is further configured to acquire the idle time of the flash memory device when the flash memory device does not perform any data operation;

[0105] The control module 904 is further configured to control the flash memory device to switch from an idle state to an idle sleep state when the idle time is greater than a time threshold; wherein, in the idle sleep state, at least one of the at least two flash memory controllers is shut down.

[0106] In addition to the active and idle states of a flash memory device, this application adds a sub-active state and an idle dormant state. When the flash memory device is under a low load, the flash memory device is controlled to enter the sub-active state from the active state, or when the flash memory device is in an idle state for a long time, the flash memory device is controlled to enter the idle dormant state from the idle state. By shutting down at least one flash memory controller when entering the sub-active or idle state, power consumption in low-load or idle conditions is reduced, thereby reducing the overall power consumption of the flash memory device.

[0107] In some embodiments of the present application, the control module 904 is also used to control the flash memory device to switch from the active state to the sub-active state when the interface rate is less than or equal to the rate threshold and the flash memory device is in the active state; or to control the flash memory device to switch from the sub-active state to the active state when the interface rate is greater than the rate threshold and the flash memory device is in the sub-active state.

[0108] This application determines the load status of the flash memory device by comparing the interface rate with the rate threshold, and dynamically switches between the activation state and the sub-activation state according to the judgment result. It can dynamically adjust the performance and power consumption of the flash memory device based on the actual load, and reduce power consumption in low-load scenarios.

[0109] In some embodiments of the present application, at least two flash memory controllers include a first flash memory controller and a second flash memory controller, the first flash memory controller includes a first flash translation layer mapping table, and the second flash memory controller includes a second flash translation layer mapping table; the flash memory device also includes a first flash memory unit and a second flash memory unit. When the flash memory device is in an activated state, the first flash memory controller is used to perform data operations on the first flash memory unit through the first flash translation layer mapping table, and the second flash memory controller is used to perform data operations on the second flash memory unit through the second flash translation layer mapping table.

[0110] The control module 904 is also used to: control the second flash memory controller to write the second flash memory translation layer mapping table into the second flash memory unit; control the first flash memory controller to obtain the second flash memory translation layer mapping table in the second flash memory unit; control the second flash memory controller to shut down; control the first flash memory controller to perform data operations on the first flash memory unit through the first flash memory translation layer mapping table, and to perform data operations on the second flash memory unit through the second flash memory translation layer mapping table.

[0111] The present application can implement data reading operations, data writing operations, and data erasing operations on data in two flash memory units through a single flash memory controller, thereby reducing the power consumption of the flash memory device under low-load conditions.

[0112] In some embodiments of the present application, the control module 904 is also used to: control the second flash memory controller to start up; control the first flash memory controller to perform data operations on the first flash memory unit through the first flash memory translation layer mapping table, and control the second flash memory controller to perform data operations on the second flash memory unit through the second flash memory translation layer mapping table.

[0113] The present application improves the data operation performance of the flash memory device by enabling multiple flash memory controllers under high load conditions, allowing the multiple flash memory controllers to access multiple flash memory units in parallel.

[0114] In some embodiments of the present application, the at least two flash memory controllers include a first flash memory controller and a second flash memory controller; the control module 904 is further configured to control the second flash memory controller to shut down when both the first flash memory controller and the second flash memory controller are in the on state.

[0115] The present application reduces idle standby energy consumption by shutting down the second flash memory controller after entering the idle dormant state.

[0116] In some embodiments of the present application, the control module 904 is further configured to control the second flash memory controller to start up and switch to an active state upon receiving a data operation instruction.

[0117] In an embodiment of the present application, when the flash memory device is in an idle state or an idle sleep state, if a data operation instruction is received, the flash memory device is immediately controlled to enter an activated state and the second flash memory controller is turned on, so that the flash memory device is capable of coping with possible high-load scenarios.

[0118] The control device of the flash memory device in the embodiment of the present application can be an electronic device or a component in the electronic device, such as an integrated circuit or chip. The electronic device can be a terminal or other device other than a terminal. For example, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, an in-vehicle electronic device, a mobile internet device (MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a personal digital assistant (PDA), etc. It can also be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), a teller machine or a self-service machine, etc., and the embodiment of the present application does not specifically limit it.

[0119] The control device of the flash memory device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0120] The control device of the flash memory device provided in the embodiment of the present application can implement each process implemented in the above method embodiment. To avoid repetition, it will not be described here.

[0121] Optionally, an embodiment of the present application further provides an electronic device, Figure 10 FIG. 1 shows a structural block diagram of an electronic device according to an embodiment of the present application. Figure 10 As shown, the electronic device 1000 includes a processor 1002, a memory 1004, and a program or instruction stored in the memory 1004 and executable on the processor 1002. When the program or instruction is executed by the processor 1002, the various processes of the above-mentioned method embodiment are implemented and the same technical effect can be achieved. To avoid repetition, they will not be described here.

[0122] It should be noted that the electronic devices in the embodiments of the present application include the above-mentioned mobile electronic devices and non-mobile electronic devices.

[0123] Figure 11 A schematic diagram of the hardware structure of an electronic device implementing an embodiment of the present application.

[0124] The electronic device 1100 includes but is not limited to: a radio frequency unit 1101, a network module 1102, an audio output unit 1103, an input unit 1104, a sensor 1105, a display unit 1106, a user input unit 1107, an interface unit 1108, a memory 1109 and a processor 1110.

[0125] Those skilled in the art will understand that the electronic device 1100 may also include a power source (such as a battery) to power each component, and the power source may be logically connected to the processor 1110 through a power management system, thereby implementing functions such as charging, discharging, and power consumption management through the power management system. Figure 11 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be repeated here.

[0126] Among them, the processor 1110 is used to obtain the interface rate corresponding to the data operation when the flash memory device performs data operations; control the flash memory device to switch between the active state and the sub-active state according to the interface rate; wherein, in the active state, at least two flash memory controllers are turned on; in the sub-active state, at least one of the at least two flash memory controllers is turned off, and at least one of the at least two flash memory controllers is turned on; when the flash memory device does not perform data operations, obtain the idle time of the flash memory device; when the idle time is greater than the time threshold, control the flash memory device to switch from the idle state to the idle sleep state; wherein, in the idle sleep state, at least one of the at least two flash memory controllers is turned off.

[0127] In addition to the active and idle states of a flash memory device, this application adds a sub-active state and an idle dormant state. When the flash memory device is under a low load, the flash memory device is controlled to enter the sub-active state from the active state, or when the flash memory device is in an idle state for a long time, the flash memory device is controlled to enter the idle dormant state from the idle state. By shutting down at least one flash memory controller when entering the sub-active or idle state, power consumption in low-load or idle conditions is reduced, thereby reducing the overall power consumption of the flash memory device.

[0128] Optionally, processor 1110 is further used to control the flash memory device to switch from an active state to a sub-active state when the interface rate is less than or equal to a rate threshold and the flash memory device is in an active state; or to control the flash memory device to switch from a sub-active state to an active state when the interface rate is greater than a rate threshold and the flash memory device is in a sub-active state.

[0129] This application determines the load status of the flash memory device by comparing the interface rate with the rate threshold, and dynamically switches between the activation state and the sub-activation state according to the judgment result. It can dynamically adjust the performance and power consumption of the flash memory device based on the actual load, and reduce power consumption in low-load scenarios.

[0130] Optionally, at least two flash memory controllers include a first flash memory controller and a second flash memory controller, the first flash memory controller includes a first flash translation layer mapping table, and the second flash memory controller includes a second flash translation layer mapping table; the flash memory device also includes a first flash memory unit and a second flash memory unit, and when the flash memory device is in an activated state, the first flash memory controller is used to perform data operations on the first flash memory unit through the first flash translation layer mapping table, and the second flash memory controller is used to perform data operations on the second flash memory unit through the second flash translation layer mapping table.

[0131] Processor 1110 is also used to control the second flash memory controller to write the second flash memory translation layer mapping table into the second flash memory unit; control the first flash memory controller to obtain the second flash memory translation layer mapping table in the second flash memory unit; control the second flash memory controller to shut down; control the first flash memory controller to perform data operations on the first flash memory unit through the first flash memory translation layer mapping table, and to perform data operations on the second flash memory unit through the second flash memory translation layer mapping table.

[0132] The present application can implement data reading operations, data writing operations, and data erasing operations on data in two flash memory units through a single flash memory controller, thereby reducing the power consumption of the flash memory device under low-load conditions.

[0133] Optionally, the processor 1110 is also used to control the second flash memory controller to start up; control the first flash memory controller to perform data operations on the first flash memory unit through the first flash memory translation layer mapping table, and control the second flash memory controller to perform data operations on the second flash memory unit through the second flash memory translation layer mapping table.

[0134] The present application improves the data operation performance of the flash memory device by enabling multiple flash memory controllers under high load conditions, allowing the multiple flash memory controllers to access multiple flash memory units in parallel.

[0135] Optionally, the at least two flash memory controllers include a first flash memory controller and a second flash memory controller; the processor 1110 is further configured to control the second flash memory controller to be turned off when both the first flash memory controller and the second flash memory controller are in an on state.

[0136] The present application reduces idle standby energy consumption by shutting down the second flash memory controller after entering the idle dormant state.

[0137] Optionally, the processor 1110 is further configured to control the second flash memory controller to start up and switch to an active state when a data operation instruction is received.

[0138] In an embodiment of the present application, when the flash memory device is in an idle state or an idle sleep state, if a data operation instruction is received, the flash memory device is immediately controlled to enter an activated state and the second flash memory controller is turned on, so that the flash memory device is capable of coping with possible high-load scenarios.

[0139] It should be understood that in an embodiment of the present application, the input unit 1104 may include a graphics processing unit (GPU) 11041 and a microphone 11042, and the graphics processor 11041 processes the image data of a static picture or video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The display unit 1106 may include a display panel 11061, and the display panel 11061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 1107 includes a touch panel 11071 and at least one of other input devices 11072. The touch panel 11071 is also called a touch screen. The touch panel 11071 may include two parts: a touch detection device and a touch controller. Other input devices 11072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and an operating stick, which will not be repeated here.

[0140] The memory 1109 can be used to store software programs and various data. The memory 1109 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, applications or instructions required for at least one function (such as a sound playback function, an image playback function, etc.). In addition, the memory 1109 may include a volatile memory or a non-volatile memory, or the memory 1109 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct RAM bus random access memory (DRRAM). The memory 1109 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0141] Processor 1110 may include one or more processing units. Optionally, processor 1110 integrates an application processor and a modem processor. The application processor primarily handles operations related to the operating system, user interface, and application programs, while the modem processor primarily processes wireless communication signals, such as a baseband processor. It is understood that the modem processor may not be integrated into processor 1110.

[0142] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the various processes of the above-mentioned method embodiment are implemented and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0143] The processor is the processor in the electronic device in the above embodiment. The readable storage medium includes a computer-readable storage medium, such as a computer read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0144] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, the communication interface and the processor are coupled, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0145] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0146] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the above-mentioned method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0147] It should be noted that, in this article, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, it should be noted that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the opposite order according to the functions involved. For example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0148] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0149] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A method for controlling a flash memory device, characterized in that: The flash memory device includes at least two flash memory controllers, and the control method includes: When the flash memory device performs a data operation, obtaining an interface rate corresponding to the data operation; Controlling the flash memory device to switch between an active state and a sub-active state according to the interface rate; wherein, in the active state, both of the at least two flash memory controllers are turned on; and in the sub-active state, at least one of the at least two flash memory controllers is turned off, and at least one of the at least two flash memory controllers is turned on; Alternatively, when the flash memory device does not perform any data operation, obtaining the idle time of the flash memory device; When the idle time is longer than a time threshold, the flash memory device is controlled to switch from an idle state to an idle sleep state; wherein, in the idle sleep state, at least one of the at least two flash memory controllers is shut down.

2. The control method according to claim 1, characterized in that: The step of controlling the flash memory device to switch between the active state and the sub-active state according to the interface rate includes: When the interface rate is less than or equal to the rate threshold and the flash memory device is in the active state, controlling the flash memory device to switch from the active state to the sub-active state; or When the interface rate is greater than the rate threshold and the flash memory device is in the sub-active state, the flash memory device is controlled to switch from the sub-active state to the active state.

3. The control method according to claim 2, characterized in that: The at least two flash memory controllers include a first flash memory controller and a second flash memory controller, the first flash memory controller includes a first flash translation layer mapping table, and the second flash memory controller includes a second flash translation layer mapping table; The flash memory device further includes a first flash memory unit and a second flash memory unit. When the flash memory device is in the activated state, the first flash memory controller is used to perform data operations on the first flash memory unit through the first flash translation layer mapping table, and the second flash memory controller is used to perform data operations on the second flash memory unit through the second flash translation layer mapping table. The controlling the flash memory device to switch from the active state to the sub-active state includes: Controlling the second flash memory controller to write the second flash translation layer mapping table into the second flash memory unit; Controlling the first flash memory controller to obtain the second flash translation layer mapping table in the second flash memory unit; controlling the second flash memory controller to shut down; The first flash memory controller is controlled to perform data operations on the first flash memory unit through the first flash translation layer mapping table, and to perform data operations on the second flash memory unit through the second flash translation layer mapping table.

4. The control method according to claim 3, characterized in that: The controlling the flash memory device to switch from the sub-active state to the active state includes: Controlling the second flash memory controller to start; The first flash memory controller is controlled to perform data operations on the first flash memory unit through the first flash translation layer mapping table, and the second flash memory controller is controlled to perform data operations on the second flash memory unit through the second flash translation layer mapping table.

5. The control method according to claim 1, characterized in that: The at least two flash memory controllers include a first flash memory controller and a second flash memory controller; and controlling the flash memory device to switch from an idle state to an idle dormant state includes: When both the first flash memory controller and the second flash memory controller are in an on state, the second flash memory controller is controlled to be off.

6. The control method according to claim 5, characterized in that: After controlling the flash memory device to switch from the idle state to the idle dormant state, the control method further includes: When a data operation instruction is received, the second flash memory controller is controlled to be turned on, and the second flash memory controller is controlled to switch to the active state.

7. A control device for a flash memory device, characterized in that: The flash memory device includes at least two flash memory controllers, and the control device includes: an acquisition module, configured to acquire an interface rate corresponding to a data operation when the flash memory device performs the data operation; a control module, configured to control the flash memory device to switch between an active state and a sub-active state according to the interface rate; wherein, in the active state, both of the at least two flash memory controllers are enabled; and in the sub-active state, at least one of the at least two flash memory controllers is disabled and at least one of the at least two flash memory controllers is enabled; The acquisition module is further configured to acquire an idle time length of the flash memory device when the flash memory device does not perform any data operation; The control module is further configured to control the flash memory device to switch from an idle state to an idle sleep state when the idle time is greater than a time threshold; wherein, in the idle sleep state, at least one of the at least two flash memory controllers is shut down.

8. The control device according to claim 7, characterized in that: The control module is further configured to control the flash memory device to switch from the active state to the sub-active state when the interface rate is less than or equal to the rate threshold and the flash memory device is in the active state; or, When the interface rate is greater than the rate threshold and the flash memory device is in the sub-active state, the flash memory device is controlled to switch from the sub-active state to the active state.

9. The control device according to claim 8, characterized in that The at least two flash memory controllers include a first flash memory controller and a second flash memory controller, the first flash memory controller includes a first flash translation layer mapping table, and the second flash memory controller includes a second flash translation layer mapping table; The flash memory device further includes a first flash memory unit and a second flash memory unit. When the flash memory device is in the activated state, the first flash memory controller is used to perform data operations on the first flash memory unit through the first flash translation layer mapping table, and the second flash memory controller is used to perform data operations on the second flash memory unit through the second flash translation layer mapping table. The control module is further configured to: Controlling the second flash memory controller to write the second flash translation layer mapping table into the second flash memory unit; Controlling the first flash memory controller to obtain the second flash translation layer mapping table in the second flash memory unit; controlling the second flash memory controller to shut down; The first flash memory controller is controlled to perform data operations on the first flash memory unit through the first flash translation layer mapping table, and to perform data operations on the second flash memory unit through the second flash translation layer mapping table.

10. The control device according to claim 9, characterized in that: The control module is further configured to: Controlling the second flash memory controller to start; The first flash memory controller is controlled to perform data operations on the first flash memory unit through the first flash translation layer mapping table, and the second flash memory controller is controlled to perform data operations on the second flash memory unit through the second flash translation layer mapping table.

11. The control device according to claim 7, characterized in that: The at least two flash memory controllers include a first flash memory controller and a second flash memory controller; The control module is further configured to control the second flash memory controller to be turned off when both the first flash memory controller and the second flash memory controller are in the turned on state.

12. The control device according to claim 11, characterized in that The control module is further configured to control the second flash memory controller to start up and switch to the active state when a data operation instruction is received.

13. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores a program or instruction that can be run on the processor, and when the program or instruction is executed by the processor, the steps of the method according to any one of claims 1 to 6 are implemented.

14. A readable storage medium, characterized in that The readable storage medium stores a program or instruction, and when the program or instruction is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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