Superconducting quantum chip graphical design system
Through the superconducting quantum chip graphical design system, which adopts modular architecture and full-process graphical design, the problems of insufficient visualization and versatility of existing software are solved, efficient quantum chip design is achieved, and multiple design requirements and rapid verification are supported.
Patent Information
- Application Number
- CN202510816606.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-18
- Publication Date
- 2025-09-26
AI Technical Summary
Existing superconducting quantum chip design software lacks a visual design environment, versatility and scalability. The design process is complex and relies on manual intervention. It lacks quantum property verification and simulation capabilities, making it difficult to meet the needs of efficient and precise design, and faces performance bottlenecks when working with large-scale quantum bit arrays.
Provides a graphical design system for superconducting quantum chips with a modular architecture, including a component library, global object module, rendering engine, control center, shortcut manager and menu generator. It integrates quantum circuit simulation and physical property verification functions, supports various design requirements, and realizes full-process graphical design.
Significantly improve design efficiency, shorten R&D cycle, enhance software practicality, reduce resource waste and time loss, support rapid prototyping and iteration, and adapt to different research directions.
Smart Images
Figure CN120706349A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present disclosure relate to the field of superconducting quantum chip graphical design, and particularly to a superconducting quantum chip graphical design system. Background Art
[0002] Currently, the design of superconducting quantum chips primarily relies on traditional electronic design tools (such as Klayout and Ledit) and specialized software. These tools often suffer from the following limitations: Existing quantum chip design software is mostly code-based or uses simple graphical user interfaces, lacking a complete visual design environment; software architectures are often customized for specific quantum computing platforms, lacking versatility and scalability; the mapping of quantum circuits to physical implementations in the design process is complex and relies on manual intervention; and existing tool chains lack effective quantum property verification and simulation capabilities, resulting in extended design cycles. Furthermore, quantum chip design requires consideration of factors such as the unique physical properties of superconductors, coupling effects between qubits, and precise transmission of microwave control signals. Existing software architectures struggle to effectively integrate this specialized domain knowledge, failing to meet the demands of efficient and accurate quantum chip design. Furthermore, as quantum computing scales up, traditional software architectures face performance bottlenecks and user experience issues when handling large-scale qubit arrays. Summary of the Invention
[0003] The content of this disclosure is used to briefly introduce concepts that will be described in detail in the detailed description section below. The content of this disclosure is not intended to identify key features or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.
[0004] Some embodiments of the present disclosure propose a superconducting quantum chip graphical design system to solve the technical problems mentioned in the above background technology section.
[0005] In a first aspect, some embodiments of the present disclosure provide a superconducting quantum chip graphical design system, which includes: a core module, including: a component library, a global object module, a rendering engine, a control center, a shortcut key manager and a menu generator; an icon management module, including: an identification storage module, an icon component library, a tool icon library, and a component graphic management module; a test module is used for sorting initialization, completing module registration, global configuration loading and display channel establishment; in a working state, the system starts the test module to trigger topological sorting initialization, and sequentially completes module registration, global configuration loading and display channel establishment; during operation, a processing pipeline is formed in which user events are captured by program functions, distributed by global object modules, component library status is updated, and the rendering engine outputs, and the icon management module is synchronously triggered to be loaded on demand.
[0006] In a second aspect, some embodiments of the present disclosure provide an electronic device comprising: one or more processors; a storage device on which one or more programs are stored, and when the one or more programs are executed by one or more processors, the one or more processors implement the system described in any implementation method of the above-mentioned first aspect.
[0007] In a third aspect, some embodiments of the present disclosure provide a computer-readable medium having a computer program stored thereon, wherein when the program is executed by a processor, the system described in any implementation of the first aspect is implemented.
[0008] The above-mentioned embodiments of the present disclosure have the following beneficial effects: through the superconducting quantum chip graphical design system of some embodiments of the present disclosure, the full-process graphics of superconducting quantum chip design can be realized, which significantly improves design efficiency, shortens the R&D cycle, and enables researchers to more quickly perform prototype verification and iteration of quantum chips; through a modular and scalable architecture, it supports various superconducting quantum chip design requirements, can flexibly adapt to different research directions and application scenarios, and enhances the practicality of the software; the integration of quantum circuit simulation and physical property verification functions makes error detection and optimization in the design process possible, reducing resource waste and time loss caused by design defects. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The above and other features, advantages, and aspects of the various embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that components and elements are not necessarily drawn to scale.
[0010] Figure 1 is a structural flow chart of a superconducting quantum chip graphical design system according to some embodiments of the present disclosure; Figure 2 This is a scene display diagram of the superconducting quantum chip graphical design system disclosed in the present invention; Figure 3 This is a basic architecture diagram of the superconducting quantum chip graphical design system disclosed in the present invention; Figure 4 It is a structural diagram of an electronic device suitable for implementing some embodiments of the present disclosure. DETAILED DESCRIPTION
[0011] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure.
[0012] It should also be noted that, for ease of description, only the parts related to the invention are shown in the drawings. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.
[0013] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.
[0014] It should be noted that the modifications of "one" and "multiple" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, they should be understood as "one or more".
[0015] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.
[0016] The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.
[0017] Figure 1 This is a structural flow chart of some embodiments of the superconducting quantum chip graphical design system of some embodiments of the present disclosure. The superconducting quantum chip graphical design system includes: a core module 1, an icon management module 2 and a test module 3.
[0018] In some embodiments, the core module includes: a component library, a global object module, a rendering engine, a control center, a shortcut key manager, and a menu generator. The component library may refer to the Component component library. The global object module may refer to the Global module. The rendering engine may refer to the Display rendering engine. The control center may refer to the Manager control center. The shortcut key manager may refer to the Tool toolbar. The menu generator may refer to the Menu menu generator. The core module 1, the icon management module 2, and the test module 3 are interconnected and communicated with each other.
[0019] Optionally, in the above core modules, the component library builds a hierarchical component tree structure based on the inheritance mechanism to realize independent components that can be customized and extended, including layout architecture, style definition and tool call; when the component library is updated, the observer mode of the global object module is used to trigger real-time synchronization of global data; the rendering engine integrates a programming interface to realize dual-mode display of circuit layout and topology diagram, and the built-in dynamic ruler system realizes nanometer-level dimension annotation; the global object module maintains system-level parameters and runtime status through the key-value storage engine, and uses the event bus mechanism to broadcast status changes; the control center provides design operations such as creating, deleting and renaming design files, and integrates version control and transaction rollback functions; the shortcut key manager and menu generator are used to bind dynamic resources with toolbar icons.
[0020] In the core functional modules, the Component library builds a hierarchical component tree structure based on the inheritance mechanism to implement customizable and extensible independent components, including layout architecture, style definition and L-edit tool calling functions. When the components are updated, the observer mode of the Global module is used to trigger real-time synchronization of global data; the Display rendering engine integrates the gdspy interface to realize dual-mode display of GDS layout and topology diagram, and the built-in dynamic ruler system realizes nanometer-level dimensioning; the Global global configuration module maintains system-level parameters and runtime status through the key-value storage engine, and uses the event bus mechanism to broadcast status changes; the Manager control center provides design file creation, deletion and renaming Design operations, and integrates version control and transaction rollback functions; the Tool toolbar has a built-in shortcut manager and context menu generator to realize dynamic resource binding with toolbar icons.
[0021] In some embodiments, the icon management module includes: an identification storage module, an icon component library, a tool icon library, and a component graphics management module. The identification storage module may refer to the logo layer. The icon component library may refer to the title management component library. The tool icon library may refer to the toolbar layer tool icon library. The component graphics management module may refer to the type layer.
[0022] Optionally, in the above-mentioned icon management module, the logo storage module stores multi-resolution brand logos; the icon component library manages component library-associated icons; the tool icon library deploys three-state-aware tool icons; the component graphic management module maintains SVG format type graphics; and the path_manager.py path manager is used to realize intelligent addressing and dynamic loading of icon resources.
[0023] In some embodiments, the test module (testcode) is used to sort initialization, complete module registration, global configuration loading and display channel establishment.
[0024] In the working state, the system starts the test module to trigger the topological sorting initialization, and completes the module registration, global configuration loading and display channel establishment in sequence; during the operation, a processing pipeline is formed in which user events are captured by program functions, distributed by global object modules, component library status is updated, and the rendering engine outputs, and the icon management module is synchronously triggered to be loaded on demand.
[0025] The module collaboration process includes three major mechanisms: initialization, operation, and exception handling: when the system starts, the main function triggers the topological sorting initialization through __init__.py, and completes the module registration, global configuration loading, and display channel establishment in sequence; during operation, a processing pipeline is formed in which user events are captured by the main function, distributed globally, updated in component status, and rendered and output on display, and icon resources are simultaneously triggered to be loaded on demand; the exception handling link is closed by component self-inspection, global status monitoring, abnormal graphics rendering, and test log recording. The technical innovation of this system is reflected in the modular communication architecture and self-healing initialization mechanism, which realizes efficient interaction through the triple communication protocols of message bus, data binding, and observer mode. After each module declares its dependencies in __init__.py, the system automatically parses the dependency tree and performs topological sorting initialization, and has the self-healing ability of dynamic isolation of missing modules. Appendix Figure 2 The effect diagram shown intuitively demonstrates the implementation effect of the above technical solution.
[0026] It should be further explained that the design scheme of the superconducting quantum chip graphical design system is as follows: First, we designed the main interface framework, employing a modular architecture to divide functional areas, including the component library panel, design canvas, and property editor. We also defined a global configuration class to manage basic software parameters, created a component base class to implement common interaction logic, and supported adaptive scaling of interface elements and dynamic multilingual switching.
[0027] Subsequently, we developed subcomponent functional modules, linking user input with global state through a data binding mechanism. When users modify component parameters, global update events are triggered to drive real-time interface refreshes. Asynchronous threads are used to separate computational tasks from interface rendering, ensuring smooth operation.
[0028] Refine toolbar functionality, store sub-window components by module type, and establish a dynamic loading mechanism to call tool modules on demand. Support third-party plug-in extensions, provide standardized interfaces for accessing external tools, and automatically record the layout preferences of users' frequently used tools.
[0029] Establish a global signal management system and define a unified communication protocol to enable cross-component data transmission. Signal queues notify associated modules of component status changes, implement flow control for high-frequency events, prioritize critical operations, and ensure system stability.
[0030] Finally, the main interface startup process is optimized, a hierarchical loading strategy is adopted to shorten the initialization time, the property panel synchronously displays parameters and supports one-click simulation, and outputs layout files that meet the lithography process standards.
[0031] Further references Figure 3 , which illustrates the basic architecture of the superconducting quantum chip graphical design system: First, a global variable container is initialized at the program entry point to centrally manage design parameters and interface state. The main function is then constructed as the execution entry point. This function creates a main window instance and mounts core functional modules, including menu bar event handlers, toolbar shortcuts, the Design Manager for data persistence, the component library for draggable quantum component collections, and the image display interface for real-time layout rendering. Each module is instantiated and initialized in the main function. Data is transferred between them through global variable containers, sharing state. Direct signal connections are also established. For example, selecting a component in the component library triggers an add operation in the Design Manager, and changes to Design data immediately notify the image display interface to redraw the canvas. Finally, a simulated user operation chain is used to verify the complete process, from component selection and parameter adjustment to layout rendering, ensuring that all modules work together correctly. The system adopts a tree-like hierarchical modular architecture consisting of three major components: the core functional module (gui_modules), the icon management module (icons), and the test module (testcode). Each module establishes hierarchical dependencies through the initialization file __init__.py. A loosely coupled interface-oriented design pattern is employed to achieve functional decoupling and data communication.
[0032] Reference below Figure 4 , which shows a schematic structural diagram of an electronic device (such as a computing device) suitable for implementing some embodiments of the present disclosure. Figure 4 The electronic device shown is only an example and should not limit the functions and scope of use of the embodiments of the present disclosure. Figure 4 As shown, the computer device includes a processor, a memory and a network interface connected via a system bus, wherein the memory may include a non-volatile storage medium and an internal memory. The non-volatile storage medium can store an operating system and a computer program. The computer program includes program instructions, which, when executed, can enable the processor to execute any superconducting quantum chip graphical design system. The processor is used to provide computing and control capabilities to support the operation of the entire computer device. The internal memory provides an environment for the operation of the computer program in the non-volatile storage medium, which, when executed by the processor, can enable the processor to execute any superconducting quantum chip graphical design system. The network interface is used for network communication, such as sending assigned tasks, etc. Those skilled in the art will understand that Figure 4The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present disclosure, and does not constitute a limitation on the computer device to which the solution of the present disclosure is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.
[0033] It should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.
[0034] Among them, in one embodiment, the above-mentioned processor is used to run a computer program stored in the memory to implement the following steps: a core module, including: a component library, a global object module, a rendering engine, a control center shortcut key manager and a menu generator; an icon management module, including: an identification storage module, an icon component library, a tool icon library, and a component graphic management module; a test module is used for sorting initialization, completing module registration, global configuration loading and display channel establishment; in a working state, the system starts the test module to trigger topological sorting initialization, and completes module registration, global configuration loading and display channel establishment in sequence; during operation, a processing pipeline is formed in which user events are captured by program functions, distributed by global object modules, component library status is updated, and the rendering engine outputs, and the icon management module is synchronously triggered to be loaded on demand.
[0035] The embodiments of the present disclosure further provide a computer-readable storage medium, on which a computer program is stored. The computer program includes program instructions. The system implemented when the program instructions are executed can refer to the various embodiments of the superconducting quantum chip graphical design system disclosed in the present disclosure.
[0036] The computer-readable storage medium may be an internal storage unit of the computer device described in the aforementioned embodiment, such as a hard disk or memory of the computer device. The computer-readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, a SmartMedia Card (SMC), a Secure Digital (SD) card, a flash memory card, etc., provided on the computer device.
[0037] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, system, article, or system comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, system, article, or system. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, system, article, or system comprising the element.
[0038] The above descriptions are merely some preferred embodiments of the present disclosure and illustrate the underlying technical principles. Those skilled in the art should understand that the scope of the invention encompassed by the embodiments of the present disclosure is not limited to technical solutions formed by specific combinations of the aforementioned technical features. It also encompasses other technical solutions formed by any combination of the aforementioned technical features or their equivalents, without departing from the aforementioned inventive concept. For example, a technical solution formed by replacing the aforementioned features with (but not limited to) technical features with similar functions disclosed in the embodiments of the present disclosure.
Claims
1. A superconducting quantum chip graphical design system, characterized in that: include: Core modules, including: component library, global object module, rendering engine, control center, shortcut manager and menu generator; Icon management module, including: logo storage module, icon component library, tool icon library, component graphic management module; The test module is used for sorting initialization, completing module registration, global configuration loading and display channel establishment; In the working state, the system starts the test module to trigger the topological sorting initialization, and completes the module registration, global configuration loading and display channel establishment in sequence; during the operation, a processing pipeline is formed in which user events are captured by program functions, distributed by global object modules, component library status is updated, and the rendering engine outputs, and the icon management module is synchronously triggered to be loaded on demand.
2. The superconducting quantum chip graphical design system according to claim 1, characterized in that: In the core module, the component library builds a hierarchical component tree structure based on the inheritance mechanism to implement independent components that can be customized and extended, including layout architecture, style definition and tool calls; When the component library is updated, the observer mode of the global object module is used to trigger real-time synchronization of global data; The rendering engine integrates a programming interface to achieve dual-mode display of circuit layout and topology diagram, and a built-in dynamic ruler system enables nanometer-level dimensioning; The global object module maintains system-level parameters and runtime status through a key-value storage engine and uses an event bus mechanism to broadcast state changes; The control center provides operations for creating, deleting, and renaming design files, and integrates version control and transaction rollback functions; The shortcut key manager and menu generator are used to bind with the dynamic resources of the toolbar icon.
3. The superconducting quantum chip graphical design system according to claim 2, characterized in that: In the icon management module, the logo storage module stores multi-resolution brand logos; Icon component library manages component library associated icons; The tool icon library deploys tri-state aware tool icons; The component graphics management module maintains SVG format type graphics; Intelligent addressing and dynamic loading of icon resources are achieved through the path manager.
4. An electronic device, characterized in that: include: one or more processors; a storage device having one or more programs stored thereon; When the one or more programs are executed by the one or more processors, the one or more processors implement the superconducting quantum chip graphical design system according to claims 1-3.
5. A computer-readable medium, characterized in that A computer program is stored thereon, wherein when the computer program is executed by a processor, the superconducting quantum chip graphical design system according to claims 1 to 3 is implemented.