A novel wafer layout and cutting calculation method

Abstract

The application provides a novel wafer layout and cutting calculation method, relates to the technical field of semiconductor chip manufacturing, and optimizes wafer layout by distinguishing between Shot pitch and Die pitch and combining a graphic periodic layout tree structure, significantly improves the number of chips (DPW), effectively improves wafer utilization, breaks through the limitations of traditional methods, inputs independent pitch constraints in Sp1, constructs a periodic tree structure in Sp2, and searches for an optimal layout through iteration and traversal in Sp3 and Sp4, so that the DPW is increased from 624 to 637, and the increase is about 2.1%, thanks to the innovative application of adaptive step length and pruning algorithm, not only the edge space is accurately captured, but also the waste is eliminated through secondary fine adjustment, the geometric conversion of non-rectangular Die shape is supported, the wafer area potential is further released, the breakthrough pitch optimization capability provides a more efficient solution for semiconductor manufacturing, and has remarkable creative significance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor chip manufacturing, in particular to a novel wafer layout and cutting calculation method. BACKGROUND

[0002] According to the semiconductor chip cutting method disclosed in Chinese Patent No. "CN118943068A", which relates to the technical field of semiconductors, the method comprises: placing a target semiconductor wafer on a cutting machine to obtain a positioning authentication result; when the positioning authentication result is authentication passed, activating a high-speed camera to obtain a wafer surface image; performing mountain simulation to determine a plurality of shape features and a plurality of warping features of a plurality of division regions; performing cutting path identification to determine a first cutting path; determining a plurality of key cutting parameters at a plurality of key cutting points to obtain a plurality of key cutting parameter sets, and performing chip cutting of the target semiconductor wafer. The present application solves the technical problems of low cutting accuracy and efficiency when processing irregular or warped semiconductor chips in the prior art, and achieves the technical effect of significantly improving the accuracy and efficiency of cutting through accurate positioning and feature recognition.

[0003] According to the wafer cutting method disclosed in Chinese Patent No. "CN119036656A", a wafer is provided, the wafer has a plurality of die regions and a cutting lane region between adjacent die regions; a first cutting path is cut in the cutting lane region; and an additional cutting path is cut in the cutting lane region on at least one side of the first cutting path; wherein the first cutting path and the additional cutting path overlap each other to form a combined cutting path.

[0004] The above patent documents and prior art have the following technical problems when used:

[0005] Problem one, the traditional wafer cutting algorithm usually uses a unified spacing calculation, which cannot adapt to the reality that the Shot spacing (such as 50μm) and the Die spacing (such as 10μm) are different in the step-and-repeat photolithography machine, resulting in space waste;

[0006] Problem two, the prior art lacks efficiency and dynamics in layout calculation, serial calculation is time-consuming and cannot adapt to real-time parameter changes, for example, after adjusting the Die size, the entire layout needs to be recalculated, which is not conducive to actual use and affects calculation efficiency. SUMMARY

[0007] Technical problems solved

[0008] In view of the deficiencies of the prior art, the present application provides a novel wafer layout and cutting calculation method, which solves the following problems:

[0009] 1. The traditional method leads to area waste due to incorrect spacing assumptions and shape limitations;

[0010] 2. The traditional method has low computational efficiency and poor dynamic adaptability.

[0011] Technical scheme

[0012] To achieve the above object, the present application is realized by the following technical scheme: a novel wafer layout and cutting calculation method, the method comprising the following steps:

[0013] Sp1: input wafer size, Shot size, Die size, and Shot space periodicity parameters Px and Py in X and Y directions, wherein Px and Py reflect the periodic arrangement of Shot and mechanical equipment constraints, and support the input of non-rectangular Die shape;

[0014] Sp2: establish a graph periodic layout tree structure based on the input parameters, which maps the periodic distribution of Shot on the wafer surface, and supports subsequent layout optimization through tree search algorithm;

[0015] Sp3: use an iterator to adjust the wafer center position in the spatial periodic grid of Shot, calculate the periodic arrangement of Shot and the distribution of Die in Shot for each position, and generate multiple candidate layout schemes;

[0016] Sp4: search all candidate layout schemes by traversing the graph periodic layout tree structure, calculate the chip quantity (DPW) of each scheme, and select the layout with the maximum DPW as the optimal scheme;

[0017] Sp5: output the optimal layout scheme, including wafer center position, periodic arrangement of Shot, distribution of Die, and final DPW value, and generate a visual result.

[0018] Preferably, the parameters input in step Sp1 further include independent constraint conditions of Shot spacing and Die spacing, and a pre-processing module is used to perform geometric conversion on non-rectangular Die to generate a minimum enclosing rectangle suitable for periodic calculation, thereby improving the accuracy of layout calculation.

[0019] Preferably, the construction of the graph periodic layout tree structure in step Sp2 includes defining the periodic boundary conditions of Shot, and introducing a weight factor to balance the difference between Shot spacing and Die spacing, and optimizing the search efficiency of the tree structure.

[0020] Preferably, the iterator in step Sp3 adopts an adaptive step adjustment strategy to dynamically adjust the moving step of the wafer center position according to the wafer size and Shot periodicity parameters, so as to reduce redundant calculation and improve iteration efficiency.

[0021] Preferably, the traversal search in step Sp4 further combines a pruning algorithm to eliminate branches with a DPW lower than a preset threshold in the periodic graph layout tree, so as to reduce calculation complexity and speed up the screening of the optimal scheme.

[0022] Preferably, the output of the optimal layout scheme in step Sp5 includes generating multi-dimensional comparison data, specifically including comparison with the results of existing online calculation methods, quantifying the DPW gain and displaying the spatial distribution of layout optimization in the form of a heat map.

[0023] Preferably, the method further comprises an adaptive optimization step of fine-tuning the optimal layout scheme to eliminate edge waste by locally adjusting the Shot boundary and Die arrangement, so as to maximize the DPW gain.

[0024] Preferably, the method is executed by a computer system, which includes an input module, a tree construction module, a parallel calculation module, an iterative optimization module, and a search module. The tree construction module and the iterative optimization module are connected by bidirectional data flow, supporting dynamic updating of the layout tree structure to adapt to real-time parameter changes. The parallel calculation module uses multi-threading technology to simultaneously process layout calculation of multiple wafer center positions, and integrates a priority queue in the search module to accelerate the convergence of the optimal scheme.

[0025] Advantages

[0026] The present application provides a novel wafer layout and cutting calculation method, which has the following advantages:

[0027] 1. The present application optimizes wafer layout by distinguishing between Shot spacing and Die spacing and combining a periodic graph layout tree structure, significantly improving the number of chips (DPW) and effectively improving wafer utilization, breaking through the limitations of traditional methods. In Sp1, independent spacing constraints are input, Sp2 constructs a periodic tree structure, and Sp3 and Sp4 iteratively search for the optimal layout, increasing the DPW from 624 to 637, an increase of about 2.1%. Thanks to the innovative application of adaptive step and pruning algorithms, not only is the edge space accurately captured, but also waste is eliminated through secondary fine-tuning, supporting geometric conversion of non-rectangular Die shapes, further releasing wafer area potential, and providing a more efficient solution for semiconductor manufacturing with breakthrough spacing optimization capabilities, which has significant creative significance.

[0028] 2. This invention employs modular design and parallel computing optimization of the computer system to achieve efficient dynamic adjustment of wafer layout, greatly improving computing performance. In Sp2 and Sp4, bidirectional data flow between the tree construction module and the iterative optimization module supports dynamic updates of the layout tree. The tree structure is reconstructed in real time when the die size is adjusted. The parallel computing module utilizes multi-threading and priority queues to process multiple center positions simultaneously in Sp3 and Sp4, reducing the computation time from 10 seconds to 2 seconds and accelerating the convergence of the optimal solution (e.g., increasing DPW from 612 to 616). The innovative combination of pruning algorithms and GPU acceleration reduces redundant computation and optimizes the search path. The multi-dimensional comparison and heat map output in Sp5 provide users with intuitive decision-making basis. This breakthrough not only improves the real-time performance of layout calculations but also provides scalability for large-scale wafer design, demonstrating creative technological progress. Attached Figure Description

[0029] Figure 1 This is a diagram illustrating the method steps of the present invention;

[0030] Figure 2 This is a system composition diagram of the present invention;

[0031] Figure 3 This is a system hardware diagram of the present invention;

[0032] Figure 4 This is a layout calculation diagram for the present invention;

[0033] Figure 5 This invention calculates the optimal layout scheme when the shot and die spacing are different.

[0034] Figure 6 The algorithm results for improving DPW in this invention Figure 1 ;

[0035] Figure 7 The algorithm results for DPW enhancement in this invention Figure 2 . Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Specific Implementation Example 1:

[0038] like Figures 1 to 7 As shown, a novel wafer layout and dicing calculation method includes the following steps:

[0039] Sp1: Input wafer, Shot and Die parameters and preprocessing: Collect and standardize all parameters needed for wafer layout calculation, and lay the foundation for subsequent optimization, starting from the user or system interface, the user inputs the wafer size (usually diameter, such as 300mm), Shot size (length and width of single exposure area), Die size (length and width of a single chip) and spatial periodicity parameters Px and Py of Shot in X and Y directions, where Px and Py not only reflect the periodic arrangement of Shot, but also directly affected by the mechanical constraints of the stepper photolithography machine, embodying the device characteristics, in addition, the input parameters further include independent constraint conditions of Shot pitch and Die pitch, for example, Shot pitch may be 50μm and Die pitch is 10μm, which solves the defect of uniform pitch in the prior art, supports the input of non-rectangular Die shape (such as hexagonal or L-shaped chip), through the preprocessing module, the non-rectangular Die is geometrically converted to generate a minimum enclosing rectangle suitable for periodicity calculation, for example, the circumscribed rectangle size of a non-rectangular Die is calculated as the length and width boundary to ensure the compatibility of subsequent calculation. In terms of workflow, the input data is first checked for reasonableness (such as size), then the geometric conversion and parameter standardization are completed by the preprocessing module, and a structured parameter set (such as JSON format) is output, which is directly passed to Sp2. This step not only collects basic data, but also improves the accuracy and flexibility of layout calculation by distinguishing pitch and handling non-rectangular shapes, providing high-quality input for subsequent optimization;

[0040] Sp2: Establishing periodic layout tree structure: This is the core modeling stage, which abstracts the wafer surface into an optimized data structure through mathematical and algorithmic means to support subsequent layout search. Based on the parameter set output by Sp1, the system first defines the periodic boundary conditions of the shot, such as determining the grid distribution of the shot on the wafer according to Px and Py (e.g., every Px shot in the X direction and every Py shot in the Y direction), forming a two-dimensional periodic grid. Then, a periodic layout tree structure is constructed, which maps the periodic distribution of the shot to a tree hierarchy. Each node represents a shot position, the child nodes reflect the die arrangement possibilities within the shot, and the root node corresponds to the initial state of the entire wafer layout. To optimize the search efficiency of the tree structure, a weight factor is introduced to balance the differences between the shot spacing and the die spacing. For example, if the shot spacing is much larger than the die spacing, the weight factor adjusts the tree depth to prioritize the exploration of shot distribution schemes. The total number of shots that can be accommodated on the wafer surface is calculated (e.g., 300mm wafer estimated shot grid according to Px=50mm, Py=40mm), and then a tree structure is initialized through a tree search algorithm (e.g., pre-processing of depth-first search) to generate a model containing all possible shot distributions. Functionally, this step converts the complex spatial periodicity problem into a computable tree structure, not only mapping the distribution relationship between the shot and the die, but also improving the relevance and efficiency of subsequent searches through weight optimization, laying the foundation for efficient iteration of Sp3 and Sp4;

[0041] Sp3: Iterative adjustment of wafer center position and generation of candidate layout: This is a dynamic process of layout generation, which explores different positions of the wafer center through an iterator and calculates multiple layout schemes to provide a candidate set for optimal solution screening. Starting from the tree structure of Sp2, the iterator adjusts the wafer center position in the spatial periodic grid of the shot, such as setting the initial position as the grid origin (0, 0) and then moving step by step along the X and Y directions according to the periodicity of Px and Py (e.g., (0, Py), (Px, 0)). To improve efficiency, the iterator uses an adaptive step size adjustment strategy, dynamically adjusting the moving step size based on the wafer size and shot periodicity parameters, such as reducing the step size (e.g., Px / 2) when approaching the wafer edge to capture edge layout changes. For each center position, the system calculates the periodic arrangement of the shot (e.g., filling the grid based on Px and Py) and determines the distribution of the die within each shot (considering die spacing and boundary constraints) to generate a candidate layout scheme, record its DPW value, and the iterator first initializes the position list, then iterates through each position, each time calling the layout calculation function to generate the coordinate set of the shot and die, checking whether it exceeds the wafer boundary (through the circular boundary formula x 2 +y 2 ≤r 2verification), the final output candidate layout set (e.g. 10 positions corresponding to 10 layouts), through adaptive iteration and accurate calculation, not only generates diversified layout options, but also reduces redundant calculation (avoiding invalid positions), providing rich candidate data for Sp4 optimization.

[0042] Sp4: Iterative search and optimization of optimal layout scheme: Find the optimal scheme from the candidate layout of Sp3 through iteration and screening, and further improve the results through secondary fine-tuning. The running scheme is based on the graph periodic layout tree structure of Sp2 and the candidate layout set of Sp3. The system starts the iterative search, first calculates the DPW for each candidate layout, for example, the total sum is obtained by multiplying the number of shots by the number of dies in each shot. To speed up the screening, combined with the pruning algorithm, branches with DPW lower than the preset threshold (e.g. lower than 90% of the existing online calculator result) are removed in the tree, reducing the calculation complexity, for example, if the preliminary DPW of a branch is only 500 and the target is 600, the child nodes are directly skipped. After the search is completed, the layout with the largest DPW is selected as the preliminary optimal scheme, and further adaptive optimization steps are integrated to fine-tune the preliminary optimal scheme, for example, by adjusting the shot boundary (e.g. moving 0.1mm) or die arrangement (e.g. rotating non-rectangular die angle), eliminating edge waste (e.g. the blank area not fully utilized at the wafer edge), and finally maximizing the DPW gain. The system first traverses the tree structure to calculate the DPW, applies pruning to lock the preliminary scheme, and then outputs the final layout through fine-tuning iteration (e.g. 10 times of local adjustment). Through efficient screening of the optimal solution through iteration and pruning, and breaking through the limitations of the preliminary scheme through fine-tuning, the number of chips is significantly increased (e.g. from 624 to 637) compared to existing technologies;

[0043] Sp5: output the optimal layout scheme and generate a visualization result: integrate and present the optimization results to the user, support subsequent manufacturing applications. Run the scheme based on the optimal layout scheme of Sp4, the system outputs detailed results, including wafer center position coordinates (such as (x0, y0)), periodic arrangement of shots (such as grid coordinate list), distribution of dies in shots (such as the number and position of dies in each shot), and the final DPW value (such as 637), in addition, generate multi-dimensional comparison data, compare with existing online calculation methods (such as the results of silicon-edge.co.uk), quantify the DPW gain (such as an increase of 2.1%), and show the spatial distribution of layout optimization in the form of a heat map, for example, use color depth to represent die density, highlight the effect of edge optimization, the system first integrates the calculation results of Sp4, calls the visualization module to generate graphics (such as SVG or PNG format), and then encapsulates the data and graphics into a report file (such as PDF), outputs through the user interface, not only provides accurate layout parameters, but also visually demonstrates the superiority of the method (such as DPW gain 0% to 3%) through comparison and visualization, providing comprehensive support for user decision-making and process implementation.

[0044] The entire method is implemented by a computer program, forming a closed-loop optimization process from the input of Sp1 to the output of Sp5, the running scheme is oriented to the needs of semiconductor manufacturing, aiming at the pain point of the difference between Shot and Die spacing in wafer cutting, and innovatively improving the layout efficiency through periodic tree structure and iterative search. The workflow is executed in order: Sp1 collects and preprocesses data, Sp2 constructs an optimization model, Sp3 generates candidate schemes, Sp4 filters and fine-tunes the optimal solution, and Sp5 outputs results and verifies the effect. Each step functions closely, Sp1 ensures data quality, Sp2 provides a calculation framework, Sp3 and Sp4 optimize the layout cooperatively, and Sp5 presents the results. The overall process runs on standard computer hardware (such as equipped with CPU and optional GPU), realizes DPW improvement through algorithm innovation (such as pruning and fine-tuning), and solves the defect of wasting wafer area in existing technology. Specific embodiment two:

[0046] As Figures 1 to 7 shown, according to the content in the above specific embodiments, the following content is further disclosed:

[0047] The method of the entire specific embodiment one is executed by a computer system, which includes an input module, a tree construction module, a parallel computing module, an iterative optimization module, and a search module, which work cooperatively to optimize wafer layout and cutting calculation, significantly improving the number of chips (Dies Per Wafer, DPW), and further including the following content:

[0048] Input module: is the starting point of the whole system, responsible for receiving, verifying and standardizing the wafer layout parameters provided by the user, providing high-quality data basis for subsequent calculation, starting from the user interaction interface, the user inputs wafer size (such as diameter 300mm), Shot size (such as 50mm x 40mm), Die size (such as 5mm x 4mm), Shot spatial periodicity parameters Px and Py in X and Y directions (such as Px = 50mm, Py = 40mm), and independent constraint conditions of Shot pitch and Die pitch (such as Shot pitch 50um, Die pitch 10um) through graphical interface or command line, supporting the input of non-rectangular Die shape (such as the vertex coordinates of hexagonal Die), first verifying the integrity and reasonableness of the input data, such as checking whether the wafer diameter is a positive value, whether the Shot size is smaller than the wafer size, then geometrically preprocessing the non-rectangular Die, calculating its minimum enclosing rectangle (such as circumscribing the hexagonal shape as a 5.2mm x 4.5mm rectangle) through algorithm, and standardizing all parameters into unified format (such as floating point array or JSON object). The process involves data parsing and conversion, such as parsing the user input string "300mm" into numerical value 300.0, and recording logs to track input history, not only collecting basic parameters, but also improving data adaptability through preprocessing, such as explicitly encoding the difference between Shot and Die pitch as constraint conditions, outputting structured parameter set directly to tree construction module, ensuring that subsequent modules can seamlessly use these data, thus laying a precise foundation for the whole optimization process.

[0049] Tree construction module: is the core modeling unit of the system, responsible for converting input parameters into an optimizable periodic layout tree structure, providing a mathematical framework for layout calculation. Based on the parameter set passed by the input module, the module first calculates the periodic grid of shots on the wafer surface, for example, according to Px=50mm and Py=40mm, determine the maximum number of shots that can be accommodated on a 300mm wafer (about 6x7 shots), then define the periodic boundary conditions (such as the shot coordinates of the grid boundary), then build a tree structure, the root node represents the entire wafer layout, the next layer of nodes represents the possible shot distribution (such as grid filling starting from the upper left corner), and the child nodes further reflect the possibility of die arrangement within each shot (such as arranging 4x5 dies based on die spacing), generate the tree through initialization algorithm, for example, use depth-first search preprocessing to generate all combinations of shot positions, then introduce weight factors (such as shot spacing weight 0.7, die spacing weight 0.3) to balance the spacing difference, optimize the search efficiency of the tree structure, the process involves dynamic updating mechanism, connected with the iterative optimization module through bidirectional data flow, for example, if the iterative optimization module feedbacks wafer center position adjustment (such as offset Px / 2), the tree construction module updates the tree nodes in real time (such as adding branches or adjusting the depth of child nodes), ensures that the tree structure adapts to parameter changes, abstracts the complex periodic layout problem into a tree data structure, not only maps the spatial relationship between shots and dies, but also supports real-time optimization through dynamic updating, provides an efficient and scalable model foundation for subsequent parallel calculation and search;

[0050] Parallel computing module: is the performance acceleration unit of the system, which uses multi-threading technology to process multiple wafer center position layout calculations simultaneously, improving computing efficiency and supporting large-scale optimization. Based on the tree structure of the tree construction module and the center position list of the iterative optimization module, the module divides the wafer surface into multiple partitions (e.g. divided into 4 sub-regions according to the grid), and each partition is assigned a thread. The thread parallelly calculates the Shot and Die layout of different wafer center positions. For example, one thread handles the center position (0, 0) and another thread handles (Px, Py). Each thread calls the layout algorithm to generate candidate solutions (such as Shot coordinates and Die number). First, initialize the thread pool (e.g. 8 threads based on CPU core number), then receive the position task queue from the iterative optimization module, distribute tasks to each thread, and aggregate the results (e.g. DPW value of each position) after calculation. The process involves multi-thread synchronization, such as using mutex to ensure data consistency between threads, and integrating a priority queue in the search module, such as sorting candidate solutions according to preliminary DPW values (e.g. higher priority for DPW > 600) to accelerate the convergence of the optimal solution. Functionally, this module significantly reduces computation time by parallelizing, for example, reducing 10 seconds of single-threaded computation to 2 seconds, while optimizing search order through a priority queue to ensure that high-potential layouts are evaluated first, thereby improving the overall system's throughput and response speed, providing fast and reliable data support for the iterative optimization and search modules.

[0051] Iterative optimization module: is the dynamic adjustment unit of the system, responsible for generating diverse candidate layout solutions and supporting real-time updates of the tree structure, providing rich options for final optimization. The running scheme is based on the initial tree structure of the tree construction module. The module uses an iterator to adjust the wafer center position in the Shot periodic grid, for example, starting from (0, 0), moving to (Px, Py), (2Px, 0), etc. in steps of Px and Py (e.g. Px / 2 = 25mm). In terms of workflow, the module first initializes the position list (e.g. 100 candidate center points), then calls the parallel computing module to generate layout solutions for each position, calculates Shot arrangement (e.g. 6x7 grid) and Die distribution (e.g. 20 Dies per Shot), and records DPW values (e.g. 620). The process involves an adaptive step strategy, such as reducing the step size (e.g. edge area step size is Px / 4) based on wafer edge proximity to reduce redundant calculations, while interacting with the tree construction module through a bidirectional data stream, such as feeding the calculation results of the new position (Px / 2, Py / 2) back to the tree structure to trigger node updates (e.g. adding branches to reflect offset layout). Functionally, this module ensures coverage of all potential optimization spaces through iterative exploration, such as generating multiple solutions from DPW = 600 to 637, and adapting to parameter changes (e.g. Die size adjustment) through dynamic tree structure updates, providing a comprehensive and high-quality candidate layout set for the search module, thereby driving the entire system towards the optimal solution.

[0052] The search module is the core of the system's decision-making process. It determines the optimal solution from candidate layouts through traversal and filtering, accelerating convergence to the maximum DPW result. The solution is based on the candidate layout set from the iterative optimization module and the tree structure from the tree construction module. The module initiates a traversal search, such as a depth-first traversal of the tree nodes, calculating the DPW value for each layout (e.g., root node DPW = 600, child node DPW = 620). In terms of workflow, the module first receives candidate solutions (e.g., a list of 10 layouts' DPWs) from the parallel computing module. Then, it uses a pruning algorithm to remove inefficient branches. For example, if a node's DPW = 550 is lower than a threshold (e.g., 90% of the existing method's DPW = 624), its subtree exploration is skipped. The process integrates a priority queue. For example, based on the initial DPW value fed back from the parallel computing module (e.g., 637 > 620), high-potential solutions are prioritized to accelerate convergence. For instance, the layout with DPW = 637 can be locked in within 10 iterations out of 100 candidates. Ultimately, the module outputs the optimal solution, including the wafer center position (e.g., (Px / 2, Py / 2)), shot arrangement (e.g., 6×7 grid), die distribution (e.g., 20 dies / shots), and DPW value (e.g., 637). Functionally, this module quickly filters for the optimal solution through efficient traversal and priority optimization, for example, reducing the search time from 30 seconds in a single thread to 5 seconds, while ensuring that the results maximize wafer utilization (e.g., an improvement of 2.1%), providing the final high-precision output for the entire system.

[0053] The entire computer system achieves wafer layout optimization through modular design. Starting with the input module receiving parameters, the tree construction module creates a periodic tree structure, the parallel computing module accelerates layout calculations, the iterative optimization module generates candidate solutions and dynamically updates the tree structure, and the search module ultimately selects the optimal solution. The execution is pipelined, with each module collaborating closely through data flow. For example, the input module outputs parameters to the tree construction module, the iterative optimization module interacts bidirectionally with the tree construction module, and the parallel computing module accelerates iteration and search. In terms of workflow, the system first initializes (input and tree construction), then iteratively generates the layout in parallel (computation and optimization), and finally searches and outputs the results. The entire process runs on standard hardware (such as a multi-core CPU), typically taking only seconds (e.g., 5-10 seconds). Functionally, the system supports real-time adjustments (e.g., updating the tree when parameters change) through bidirectional data flow, and parallel computing and priority queues ensure efficient convergence, resulting in an overall improvement in DPW (e.g., 0% to 3%), significantly outperforming existing technologies. Specific Implementation Example 3:

[0055] like Figures 1 to 7 As shown, based on the content of the above specific embodiments, the following content is further disclosed:

[0056] To further verify the feasibility and effectiveness of the method, a comparison with existing technology is designed, which further includes the following content:

[0057] The existing technology (such as the online calculator of sil icon-edge.co.uk and anysi l icon.com) adopts uniform spacing assumption and serial calculation, ignores the spacing difference between Shot and Die, only supports rectangular Die, and has low calculation efficiency. The technical solution solves these problems through the steps of Sp1 to Sp5 and the modular system. The experiment compares the DPW (Dies Per Wafer) and the calculation time through specific cases to verify the technical breakthrough:

[0058] Experimental equipment and environment:

[0059] Hardware: equipped with 8-core CPU (Intel i 7-9700), 16GB RAM, NVIDIA GTX1660 GPU (used for parallel calculation of this solution);

[0060] Software: this technical solution is implemented in Python (including NumPy, multiprocessing library), and the existing technology uses the sil icon-edge.co.uk online tool;

[0061] Wafer parameters: diameter 300mm, Shot size 50mm×40mm, Die size 5mm×4mm (rectangular) and hexagonal (edge length 2.5mm, enclosing rectangle about 5.2mm×4.5mm);

[0062] Spacing settings: Shot spacing 50μm, Die spacing 10μm (this solution distinguishes, and the existing technology is uniformly 50μm);

[0063] Experimental content:

[0064] Experimental group and control group setting:

[0065] Experimental group: use this technical solution, execute Sp1 input parameters (including independent spacing and non-rectangular Die support), Sp2 construct tree structure, Sp3 iterate center position (adaptive step size), Sp4 traversal search (pruning + parallel calculation), Sp5 output results;

[0066] Control group: use existing technology (sil icon-edge.co.uk calculator), input the same wafer, Shot and Die size, uniform spacing 50μm, only support rectangular Die, serial calculation layout;

[0067] Experimental steps are as follows:

[0068] Step 1: Parameter input and preprocessing: The experimental group inputs wafer parameters, Shot and Die spacing, and non-rectangular Die shape (hexagonal), and performs geometric conversion; the control group inputs the same parameters, but uniform spacing and only rectangular Die;

[0069] Step 2: Layout calculation: The experimental group constructs a tree structure and iterates 100 center positions (8 threads in parallel), and traverses to search for the optimal layout; the control group calculates a single layout according to a fixed formula;

[0070] Step 3: Performance recording: Record the DPW values and calculation time of the two methods, and take the average of 5 repeated experiments;

[0071] Step 4: Non-rectangular Die test: The experimental group calculates the hexagonal Die layout, and the control group calculates the approximate surrounding rectangle, and compares the DPW difference;

[0072] Verification indicators: Wafer utilization rate: measured by DPW value, to verify the effect of spacing differentiation and non-rectangular support; calculation efficiency: measured by calculation time (seconds), to verify the advantages of parallel calculation and dynamic optimization;

[0073] The experimental results are shown in Table 1 below:

[0074]

[0075] Table 1

[0076] Result analysis:

[0077] Wafer utilization rate improvement: In the rectangular Die scenario, the DPW of the technical solution is 637, and that of the control group is 624, with a gain of 2.1%. This is due to Sp1 distinguishing between Shot and Die spacing (50 μm vs. 10 μm), and Sp4's secondary fine-tuning further optimizing the edge space. In the non-rectangular Die scenario, the DPW of the technical solution is 615, and that of the control group is only 596, with a gain of 3.2%. This is because Sp1 supports geometric conversion to accurately calculate the hexagonal layout, while the control group uses the surrounding rectangle approximation, resulting in waste. This verifies that the technical solution has broken through the traditional spacing limitations and shape support deficiencies.

[0078] Calculation efficiency improvement: In the rectangular Die scenario, the calculation time of the technical solution is 2.1 seconds, and that of the control group is 10.0 seconds, with a reduction of 79.0%. This is due to Sp3 parallel calculation (8 threads) and Sp4 pruning + priority queue accelerating convergence. In the non-rectangular Die scenario, the calculation time of the technical solution is 2.3 seconds, and that of the control group is 9.8 seconds, with a reduction of 76.5%. Dynamic tree updating and GPU acceleration further optimize performance. This verifies the innovation of the technical solution in dynamic optimization and calculation performance.

[0079] Experiments show that the technical scheme significantly improves wafer utilization (DPW gain 0%-3.2%) and computing efficiency (time reduction 76.5%-79.0%) by distinguishing the spacing, supporting non-rectangular Die and parallel optimization, which is in sharp contrast with the prior art, and the distinguishing features (such as the processes of Sp1-Sp5 and the modular system) effectively solve the problems of space waste and low efficiency in the background technology.

[0080] As the chip manufacturing process continues to improve, the area of the chip is gradually reduced, resulting in multiple dies arranged in a single shot area. Due to the influence of hardware equipment in different process flows, the distances between shots and the distances between dies contained therein are often different. The present method can adapt to this requirement and calculate the optimal layout that meets this condition, such as Figure 5 As shown, the optimal layout scheme of our product under the condition that the distances between shots and dies are different is shown;

[0081] The present method establishes a periodic layout tree structure according to the given conditions, and searches the wafer surface according to the structure to find the optimal scheme. By comparing the calculation results of our algorithm with the results of the online calculator, the number of dies in our results will be 0%-3% higher;

[0082] As shown in Figures 6 to 7 In the two examples, the number of dies obtained by our algorithm is better than that obtained by the online algorithm.

[0083] As shown in Figure 4 The arrangement of shots in space has spatial periodicity, and the periods in the X and Y directions are denoted as Px and Py, respectively. The center of the wafer must be located somewhere in the spatial period. We designed an effective iterator to iterate the position of the center in the spatial period and calculate the layout results formed under each position, thereby obtaining the optimal layout scheme.

[0084] It should be noted that in this paper, relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitations, the element defined by the statement "including a reference structure" does not exclude the presence of another identical element in the process, method, article or equipment including the element.

[0085] While embodiments of the application have been shown and described, it is to be understood that the application is not limited to the details of the embodiments described, since numerous changes, modifications, substitutions and variations can be made thereto without departing from the spirit and scope of the application as defined by the appended claims and their equivalents.

Claims

1. A novel wafer layout and dicing calculation method, characterized in that: The method includes the following steps: Sp1: Input wafer size, shot size, die size = spatial periodicity parameters Px and Py of the shot in the X and Y directions, as well as independent constraints of shot spacing and die spacing, where Px and Py reflect the periodic arrangement of the shot and mechanical constraints. The preprocessing module performs geometric transformation on non-rectangular dies to generate a minimum bounding rectangle adapted to periodic calculations to support input of non-rectangular die shapes. Sp2: Based on the input parameters, a periodic layout tree structure is established. This structure maps the periodic distribution of the shot on the wafer surface and supports subsequent layout optimization through a tree search algorithm. Sp3: Use an iterator to adjust the wafer center position in the spatial periodic grid of the Shot, calculate the periodic arrangement of the Shot and the distribution of the Die within the Shot for each position, and generate multiple candidate layout schemes. Sp4: By traversing the periodic layout tree structure of the graph, all candidate layout schemes are searched, the chip count (DPW) of each scheme is calculated, and the layout scheme with the largest chip count (DPW) is selected as the optimal scheme. Sp5: Outputs the optimal layout scheme, including the wafer center position, the periodic arrangement of shots, the distribution of dies, and the final chip count (DPW) value, and generates visualization results.

2. The novel wafer layout and dicing calculation method according to claim 1, characterized in that: The construction of the periodic layout tree structure in Sp2 includes defining periodic boundary conditions for Shots and introducing weight factors to balance the difference between Shot spacing and Die spacing, thereby optimizing the search efficiency of the tree structure.

3. The novel wafer layout and dicing calculation method according to claim 1, characterized in that: The iterator in Sp3 employs an adaptive step size adjustment strategy, dynamically adjusting the moving step size of the wafer center position based on the wafer size and the Shot periodicity parameter to reduce redundant calculations and improve iteration efficiency.

4. The novel wafer layout and dicing calculation method according to claim 1, characterized in that: The traversal search in Sp4 is further combined with a pruning algorithm to remove branches in the periodic layout tree structure of the graph where the number of chips (DPW) is lower than a preset threshold, thereby reducing computational complexity and accelerating the selection of the optimal solution.

5. The novel wafer layout and dicing calculation method according to claim 1, characterized in that: The optimal output scheme in Sp5 includes generating multidimensional comparison data, quantifying the chip quantity (DPW) gain, and displaying the spatial distribution of layout optimization in the form of a heatmap.

6. The novel wafer layout and dicing calculation method according to claim 1, characterized in that: The method further includes an adaptive optimization step, which performs a second fine-tuning of the optimal solution after Sp4, eliminating edge waste by locally adjusting the Shot boundary and Die arrangement.

7. The novel wafer layout and dicing calculation method according to claim 1, characterized in that: The method is executed by a computer system, which includes an input module, a tree construction module, a parallel computing module, an iterative optimization module, and a search module. The tree construction module and the iterative optimization module are connected through a bidirectional data stream, supporting dynamic updates of the periodic layout tree structure to adapt to real-time parameter changes. The parallel computing module uses multi-threading technology to process layout calculations at multiple wafer center locations simultaneously, and integrates a priority queue in the search module to accelerate the convergence of the optimal solution.

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